Single-chip integrated 3D hall device and preparation method therefor

Abstract

A single-chip integrated 3D Hall device and a preparation method therefor. The single-chip integrated 3D Hall device is provided with an STI isolation trench, a first P-type buried layer, a second P-type buried layer, N-type electrodes, an oxide layer, a third P-type well and a metal layer. The single-chip integrated 3D Hall device comprises four first N-type electrodes and one second N-type electrode, wherein when the device detects a vertical magnetic field, mutually perpendicular electrodes among the four first N-type electrodes are respectively bias electrodes and Hall voltage detection electrodes; when the device detects a horizontal magnetic field, the four first N-type electrodes represent a current in an X or Y direction; and when a parallel magnetic field perpendicular to an electric current direction passes through the device, an induced electric potential is generated in another perpendicular direction, and is concentrated at the second N-type electrode, thus detecting a Hall voltage which is induced by a magnetic field in the Y or X direction. The device is formed in a P-type silicon wafer substrate, and the maximum size of a Hall active function area of the device is merely within the range of 30 μm to 50 μm; thus, the device has an extremely small size.

Description

Single-chip integrated 3D Hall device and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of Hall devices, in particular to a single-chip integrated 3D Hall device and a preparation method thereof. BACKGROUND

[0002] A Hall device for current magnetic field detection is a magnetic sensor based on the Hall effect, wherein the Hall effect refers to that when a conductor or semiconductor material is in a magnetic field and current passes through, an electric field will be generated in the direction perpendicular to the magnetic field and the current, and a Hall electromotive force will be generated. The magnetic sensor composed of Hall elements plays an important role in many fields, such as consumer electronics, industrial automation, automotive electronics, medical health systems, etc. With the development of application technology, the requirements for Hall magnetic sensors are getting higher and higher, and they are no longer limited to detecting magnetic fields in one-dimensional direction, but are required to detect magnetic fields in three-dimensional direction, wherein the three-dimensional direction refers to detecting magnetic fields in three mutually orthogonal directions in space at the same time.

[0003] Currently, 3D Hall devices for detecting magnetic fields in three-dimensional direction mainly include the following two types: the first type is to place multiple horizontal devices in X / Y / Z three directions by adjustment and integrate them in one package, and each device detects the magnetic field in the corresponding direction; the second type is to integrate multiple magnetic concentrator structures on the surface of a horizontal Hall device, so that the horizontal magnetic field is deflected to a vertical magnetic field under the action of the magnetic concentrator for detection. However, the above-mentioned 3D Hall devices have the disadvantages of low integration and large device size, which limit their application.

[0004] Therefore, in view of the deficiencies of the prior art, it is very necessary to provide a single-chip integrated 3D Hall device and a preparation method thereof to solve the deficiencies of the prior art. SUMMARY

[0005] A first object of the present application is to provide a single-chip integrated 3D Hall device to avoid the deficiencies of the prior art. The single-chip integrated 3D Hall device has the advantages of high integration and small size.

[0006] The above object of the present application is achieved by the following technical measures:

[0007] The present application provides a single-chip integrated 3D Hall device, which is provided with:

[0008] An STI isolation groove is arranged around the inner side wall of a P-type silicon wafer substrate;

[0009] A first N-type deep well is arranged at the bottom of the P-type silicon wafer substrate and is in close contact with the STI isolation groove;

[0010] The first P-type buried layer is arranged at the center of the upper surface of the first N-type deep well and has a gap with the STI isolation groove.

[0011] The second N-type well is arranged on the upper surface of the first P-type buried layer and has five vertical structures and a cross-beam structure, wherein four vertical structures are integrally connected to four ends of the cross-beam structure respectively, and the four vertical structures are defined as first vertical structures; and another vertical structure is located at the midpoint of the cross-beam structure and is defined as a second vertical structure.

[0012] The second P-type buried layer is arranged on the upper surface region of the first P-type buried layer and around and on the upper surface of the second N-type well.

[0013] The N-type electrode is arranged on the upper part of the first vertical structure and the upper part of the second vertical structure, and the N-type electrode located on the first vertical structure is defined as a first N-type electrode, and the N-type electrode located on the second vertical structure is defined as a second N-type electrode.

[0014] The oxide layer is arranged on the upper surface of the second P-type buried layer.

[0015] The third P-type well is arranged in the gap between the STI isolation groove and the first P-type buried layer and is in contact with the sidewall of the second N-type well, the sidewall of the second P-type buried layer, the sidewall of the N-type electrode and the sidewall of the oxide layer.

[0016] The metal layer is arranged on the upper surface of the N-type electrode.

[0017] The second N-type well is used as a Hall active functional area.

[0018] Preferably, the cross-beam structure is provided with four beam bodies and a connecting body, each of the beam bodies is integrally connected to the connecting body, each beam body is perpendicular to the adjacent beam body, and the four beam bodies are in the same plane; each of the first vertical structures is correspondingly connected to the end of a beam body, and the second vertical structure is integrally connected to the upper surface of the connecting body.

[0019] Preferably, the cross-beam structure is a central symmetric structure.

[0020] The four first vertical structures are sequentially connected into a closed area by using a virtual straight line, and the closed area is used as a Hall active functional area.

[0021] The depth of the Hall active functional area is defined as D, and D is 4-8 μm.

[0022] The maximum length of the Hall active functional area is defined as L1, and L1 is 30-50 μm.

[0023] Preferably, the first P-type buried layer, the P-type silicon wafer substrate and the second P-type buried layer are all grounded.

[0024] Preferably, the second P-type buried layer forms a reverse PN junction with the second N-type well.

[0025] Preferably, the depth of the STI isolation groove is 5500 Å to 6000 Å.

[0026] Preferably, the material of the STI isolation groove is silicon dioxide.

[0027] The thickness of the cross-beam structure is defined as H, and H is 0.5 μm to 2 μm.

[0028] The width of each beam in the cross-beam structure is defined as W, and W is 6 μm to 8 μm.

[0029] The length of each beam in the cross-beam structure is defined as L2, and L2 is 15 μm to 20 μm.

[0030] The thickness of the N-type electrode is 0.1 μm to 0.5 μm.

[0031] Preferably, the upper surface of the N-type electrode is flush with the upper surface of the oxide layer.

[0032] Preferably, the N-type electrode is located between the oxide layer and the second P-type buried layer.

[0033] Preferably, the depth of the third P-type well is equal to the sum of the thickness of the first P-type buried layer, the thickness of the second N-type well and the thickness of the N-type electrode.

[0034] The second object of the present application is to provide a preparation method of a single-chip integrated 3D Hall device to avoid the shortcomings of the prior art. The preparation method of the single-chip integrated 3D Hall device can prepare a single-chip integrated 3D Hall device with high integration and small size through a simple preparation method.

[0035] The above objects of the present application are achieved by the following technical measures:

[0036] The present application provides a preparation method of a single-chip integrated 3D Hall device, characterized by the following steps:

[0037] S1, forming the STI isolation groove on the inner side wall of the P-type silicon wafer substrate;

[0038] S2, implanting N-type ions at the bottom of the P-type silicon wafer substrate, and then annealing to form the first N-type deep well;

[0039] S3, implanting P-type ions in the epitaxial layer of the first N-type deep well to obtain the first P-type buried layer;

[0040] S4, implanting N-type ions on the upper surface of the first P-type buried layer to obtain the second N-type well with cross-beam structure and five vertical structures;

[0041] S5, implanting P-type ions in the upper surface region of the first P-type buried layer and around and on the upper surface of the second N-type well, and then annealing to obtain the second P-type buried layer;

[0042] S6, depositing an oxide layer on the upper surface of the second P-type buried layer;

[0043] S7, implanting P-type ions in the gap between the STI isolation groove and the first P-type buried layer, so that the P-type ions fill the second N-type well, the second P-type buried layer, the N-type electrode, and the gap between the oxide layer and the STI isolation groove, and then annealing to obtain the third P-type well;

[0044] S8, implanting N-type ions on the upper part of the five vertical structures to form the N-type electrode;

[0045] S9, patterning a metal layer directly above the N-type electrode.

[0046] Preferably, the above S2 is specifically performed by the following steps:

[0047] S2.1, implanting N-type ions at the bottom of the P-type silicon wafer substrate to form an NBL layer with moderate doping, which is the first N-type deep well;

[0048] S2.2, continuing to implant N-type ions in the epitaxial layer of the NBL layer to grow an N-EPI layer with shallow doping;

[0049] Preferably, the above S3 is specifically implanting P-type ions in the N-EPI layer with shallow doping to obtain the first P-type buried layer.

[0050] Preferably, the above P-type ions are boron ions;

[0051] Preferably, the above N-type ions are phosphorus ions or arsenic ions.

[0052] The application discloses a single-chip integrated 3D Hall device and a preparation method thereof. The single-chip integrated 3D Hall device is provided with an STI isolation groove which is arranged on the inner side wall of a P-type silicon wafer substrate; a first N-type deep well which is arranged at the bottom of the P-type silicon wafer substrate and is attached to the STI isolation groove; a first P-type buried layer which is arranged at the center of the upper surface of the first N-type deep well and has a gap between the first P-type buried layer and the STI isolation groove; a second N-type well which is arranged on the upper surface of the first P-type buried layer and has five vertical structures and a cross beam structure, wherein four vertical structures are integrally connected to four ends of the cross beam structure respectively, and the four vertical structures are defined as first vertical structures; another vertical structure is located at the midpoint of the cross beam structure and is defined as a second vertical structure; a second P-type buried layer which is arranged on the upper surface region of the first P-type buried layer and around and on the upper surface of the second N-type well; an N-type electrode which is arranged on the upper part of the first vertical structure and the upper part of the second vertical structure, and the N-type electrode located on the first vertical structure is defined as a first N-type electrode, and the N-type electrode located on the second vertical structure is defined as a second N-type electrode; an oxide layer which is arranged on the upper surface of the second P-type buried layer; a third P-type well which is arranged in the gap between the STI isolation groove and the first P-type buried layer and is attached to the side wall of the second N-type well, the side wall of the second P-type buried layer, the side wall of the N-type electrode and the side wall of the oxide layer; and a metal layer which is arranged on the upper surface of the N-type electrode. The single-chip integrated 3D Hall device comprises four first N-type electrodes and one second N-type electrode, wherein the electrodes which are perpendicular to each other among the four first N-type electrodes are bias electrodes and Hall voltage detection electrodes when detecting a vertical magnetic field, and the four first N-type electrodes represent X or Y direction currents when detecting a horizontal magnetic field, and when a parallel magnetic field which is perpendicular to the current direction passes through, an induced potential is generated along another perpendicular direction, is concentrated on the second N-type electrode, and a Hall voltage generated by Y or X direction magnetic field induction is detected. The single-chip integrated 3D Hall device is formed in a P-type silicon wafer substrate, and the maximum size of a Hall active functional area thereof is only in the range of 30-50 mu m, so that the size thereof is very small. BRIEF DESCRIPTION OF DRAWINGS

[0053] The application is further described with reference to the drawings, but the content in the drawings does not constitute any limitation on the application.

[0054] Fig. 1 is a schematic diagram of a single-chip integrated 3D Hall device.

[0055] Fig. 2 is a schematic diagram of a cross section in the "X-X'" direction or the "Y-Y'" direction in Fig. 1.

[0056] Fig. 3 is a schematic diagram of a cross section in the "Z1-Z1'" direction in Fig. 2.

[0057] Fig. 4 is a schematic cross-sectional view of the direction "Z2-Z2'" in Fig. 2.

[0058] Fig. 5 is a schematic perspective view of a second N-type well.

[0059] Fig. 6 is another angle view of Fig. 5.

[0060] Fig. 7 is a schematic view of a structure prepared in Example 2, S1.

[0061] Fig. 8 is a schematic view of a structure prepared in Example 2, S2.

[0062] Fig. 9 is a schematic view of a structure prepared in Example 2, S3.

[0063] Fig. 10 is a schematic view of a structure prepared in Example 2, S4.

[0064] Fig. 11 is a schematic view of a structure prepared in Example 2, S5.

[0065] Fig. 12 is a schematic view of a structure prepared in Example 2, S6.

[0066] Fig. 13 is a schematic view of a structure prepared in Example 2, S7.

[0067] Fig. 14 is a schematic view of a structure prepared in Example 2, S8.

[0068] Fig. 15 is a schematic view of a structure prepared in Example 2, S9.

[0069] In Figs. 1-15, there are included:

[0070] a P-type silicon wafer substrate 100, a first N-type deep well 200, a first P-type buried layer 300, a third P-type well 400, an STI isolation trench 500,

[0071] a second N-type well 600, a first vertical structure 610, a second vertical structure 620, a cross-beam structure 630, a Hall active functional area 640,

[0072] a second P-type buried layer 700, an oxide layer 800, an N-type electrode 900, a metal layer 1000. DETAILED DESCRIPTION

[0073] The technical solutions of the present application are further described in connection with the following examples.

[0074] Example 1

[0075] A single-chip integrated 3D Hall device, as shown in Figs. 1-2, is provided with:

[0076] STI isolation groove 500 - set around the inner sidewall of the P-type silicon wafer substrate 100; wherein the material of the STI isolation groove 500 is silicon dioxide.

[0077] First N-type deep well 200 - set at the bottom of the P-type silicon wafer substrate 100 and in contact with the STI isolation groove 500.

[0078] First P-type buried layer 300 - set at the center of the upper surface of the first N-type deep well 200, and there is a gap between the first P-type buried layer 300 and the STI isolation groove 500.

[0079] Second N-type well 600 - set in the upper surface region of the first P-type buried layer 300, and has 5 vertical structures and a cross-beam structure 630, wherein 4 vertical structures are integrally connected to the 4 ends of the cross-beam structure 630, and the 4 vertical structures are defined as the first vertical structure 610; another vertical structure is located at the midpoint of the cross-beam structure 630 and is defined as the second vertical structure 620; wherein the 4 first vertical structures 610 of the second N-type well 600 are symmetrically distributed with the second vertical structure 620 as the center.

[0080] Second P-type buried layer 700 - set in the upper surface region of the first P-type buried layer 300, and around and on the upper surface of the second N-type well 600, as shown in Figures 3 and 4.

[0081] N-type electrode 900 - set on the upper part of the first vertical structure 610 and the upper part of the second vertical structure 620, the N-type electrode 900 located in the first vertical structure 610 is defined as the first N-type electrode 900, and the N-type electrode 900 located in the second vertical structure 620 is defined as the second N-type electrode 900.

[0082] Oxide layer 800 - set on the upper surface of the second P-type buried layer 700, as shown in Figure 1.

[0083] Third P-type well 400 - set in the gap between the STI isolation groove 500 and the first P-type buried layer 300, and in contact with the sidewall of the second N-type well 600, the sidewall of the second P-type buried layer 700, the sidewall of the N-type electrode 900, and the sidewall of the oxide layer 800.

[0084] Metal layer 1000 - set on the upper surface of the N-type electrode 900.

[0085] It should be noted that the STI isolation trench 500 surrounds the Hall active functional area 640 and the outer periphery of the third P-type well 400 as a physical isolation structure. The first N-type deep well 200 plays an electrical isolation role to further enhance the isolation of the Hall active area and the P-type silicon wafer substrate 100. The oxide layer 800 serves to isolate different N-type electrodes 900 and protect the underlying doped regions from contamination. The N-type electrode 900 is used to apply a bias current or detect a magnetic field-induced potential.

[0086] The second P-type buried layer 700 of the present application forms a reverse PN junction with the second N-type well 600 to achieve isolation of the P-type silicon wafer substrate 100. It should also be noted that the second N-type well 600 of the Hall active functional area 640 partially overlaps the first P-type buried layer 300 and the second P-type buried layer 700, which limits the vertical migration of electrons in the Hall active functional area 640 and maintains good lateral diffusion of the bias current.

[0087] The first P-type buried layer 300, the P-type silicon wafer substrate 100, and the second P-type buried layer 700 are all grounded.

[0088] It should be noted that the grounding of the second P-type buried layer 700 and the grounding of the P-type silicon wafer substrate 100 effectively improve the surface effect caused by the direct contact of the active layer with the oxide layer 800. The grounding of the first P-type buried layer 300 enhances the isolation of the device active area and the substrate.

[0089] The cross-beam structure of the present application is provided with four beam bodies and a connecting body, each beam body is integrally connected to the connecting body, each beam body is perpendicular to the adjacent beam body, and the four beam bodies are in the same plane; each first vertical structure is respectively connected to the end of a beam body, and the second vertical structure is integrally connected to the upper surface of the connecting body; the cross-beam structure is a central symmetric structure, as shown in FIG. 5, the shaded area in FIG. 5 is the vertical structure, and the hollow area is the cross-beam structure.

[0090] The present application uses a virtual straight line to sequentially connect a closed area of four first vertical structures 610, and the closed area serves as the Hall active functional area 640, as shown in FIG. 6. The dashed line in FIG. 6 is a virtual straight line, and the closed area formed by the virtual straight line and the edges of the first vertical structure 610 is the Hall active functional area 640.

[0091] The depth of the Hall active functional area 640 of the application is defined as D, and D is 4-8 μm; the maximum length of the Hall active functional area 640 is defined as L1, and L1 is 30-50 μm; the thickness of the cross-beam structure 630 is defined as H, and H is 0.5-2 μm; the width of each beam body in the cross-beam structure 630 is defined as W, and W is 6-8 μm; the length of each beam body in the cross-beam structure 630 is defined as L2, and L2 is 15-20 μm. The thickness of the N-type electrode 900 is 0.1-0.5 μm.

[0092] The upper surface of the N-type electrode 900 is flush with the upper surface of the oxide layer 800; the N-type electrode 900 is located between the oxide layer 800 and the second P-type buried layer 700; the depth of the third P-type well 400 is equal to the sum of the thickness of the first P-type buried layer 300, the thickness of the second N-type deep well 600 and the thickness of the N-type electrode 900.

[0093] The magnetic field detection working principle of the single-chip integrated 3D Hall device of the application is as follows:

[0094] 1. When detecting a vertical magnetic field, the metal layer 1000 above a pair of opposite first N-type electrodes is marked as V1 and V2, and the metal layer 1000 above another pair of opposite first N-type electrodes 900 is marked as V3 and V4, as shown in Fig. 1. A pair of mutually perpendicular first N-type electrodes are bias electrodes and Hall voltage detection electrodes, and when any one group is powered as a bias electrode, the other group can be used to detect the magnetic field induced Hall voltage.

[0095] 2. When detecting a horizontal magnetic field, the metal layer 1000 above the second N-type electrode is marked as V0, as shown in Fig. 1. V1 / V2 and V3 / V4 represent X or Y direction current, respectively. When a parallel magnetic field perpendicular to the current direction passes through, an induced potential is generated along the other perpendicular direction, which is concentrated in the V0 electrode. Since the P-type buried layer potential is zero, the detected V0 voltage is the Hall voltage induced by the Y or X direction magnetic field.

[0096] The single-chip integrated 3D Hall device includes four first N-type electrodes and one second N-type electrode. In the detection of a vertical magnetic field, the mutually perpendicular electrodes of the four first N-type electrodes are bias electrodes and Hall voltage detection electrodes. In the detection of a horizontal magnetic field, the four first N-type electrodes represent X or Y direction current. When a parallel magnetic field perpendicular to the current direction passes through, an induced potential is generated along the other perpendicular direction, which is concentrated in the second N-type electrode, so as to detect the Hall voltage induced by the Y or X direction magnetic field. The single-chip integrated 3D Hall device of the application is formed in a P-type silicon wafer substrate 100, and the maximum size of the Hall active functional area 640 thereof is only in the range of 30-50 μm, so the size thereof is very small.

[0097] Embodiment 2

[0098] A method for preparing a single-chip integrated 3D Hall device as in Embodiment 1 is performed by the following steps:

[0099] S1, forming an STI isolation groove 500 on the inner sidewall of a P-type silicon wafer substrate 100, as shown in FIG. 7;

[0100] S2, implanting N-type ions at the bottom of the P-type silicon wafer substrate 100, and then annealing to form a first N-type deep well 200, as shown in FIG. 8;

[0101] S3, implanting P-type ions in the epitaxial layer of the first N-type deep well 200 to obtain a first P-type buried layer 300, as shown in FIG. 9;

[0102] S4, implanting N-type ions on the upper surface of the first P-type buried layer 300 to obtain a second N-type well 600 with a cross-beam structure 630 and five vertical structures, as shown in FIG. 10;

[0103] S5, implanting P-type ions in the upper surface region of the first P-type buried layer 300 and around and on the upper surface of the second N-type well 600, and then annealing to obtain a second P-type buried layer 700, as shown in FIG. 11;

[0104] S6, depositing an oxide layer 800 on the upper surface of the second P-type buried layer 700, as shown in FIG. 12;

[0105] S7, implanting P-type ions in the gap between the STI isolation groove 500 and the first P-type buried layer 300, so that the P-type ions fill the gap between the second N-type well 600, the second P-type buried layer 700, the N-type electrode 900, and the oxide layer 800 and the STI isolation groove 500, and then annealing to obtain a third P-type well 400, as shown in FIG. 13;

[0106] S8, implanting N-type ions at the upper part of the five vertical structures to form an N-type electrode 900, as shown in FIG. 14;

[0107] S9, patterning a metal layer 1000 directly above the N-type electrode 900, as shown in FIG. 15.

[0108] Wherein S2 is specifically performed by the following steps:

[0109] S2.1, doping N-type ions at the bottom of the P-type silicon wafer substrate 100 to form a moderately doped NBL layer, which is the first N-type deep well 200;

[0110] S2.2, continuing to implant N-type ions in the epitaxial layer of the NBL layer to grow a shallowly doped N-EPI layer.

[0111] Wherein, S3 is specifically doping P-type ions in the shallow doped N-EPI layer to obtain the first P-type buried layer 300.

[0112] The P-type ions of the application are boron ions, and the N-type ions are phosphorus ions or arsenic ions. The ion source of the boron ions, the phosphorus ions or the arsenic ions in the application can be various, as long as the corresponding ions of the application can be provided to serve as the ion source of the application.

[0113] It should be further pointed out that the annealing conditions in the steps S2, S5, S7 and the like of the application are related to the equipment, and can be determined according to the actual conditions of the equipment.

[0114] The preparation method of the single-chip integrated 3D Hall device can prepare the single-chip integrated 3D Hall device through a simple preparation method, and the maximum size of the Hall active functional area 640 of the single-chip integrated 3D Hall device is only in the range of 30 μm to 50 μm, so the size is very small.

[0115] Example 3

[0116] A preparation method of a single-chip integrated 3D Hall device, other features are the same as example 1, is carried out by the following steps:

[0117] S1, forming an STI isolation groove 500 on the inner side wall of the P-type silicon wafer substrate 100;

[0118] S2, injecting phosphine at the bottom of the P-type silicon wafer substrate 100 to form a moderately doped NBL layer, the NBL layer is the first P-type buried layer 300, wherein the moderately doped concentration is 1014cm-3, and the injection energy is 20KEV~30KEV; using an annealing process, an epitaxial layer of a shallow doped N-EPI layer is continuously injected and grown on the NBL layer, wherein the shallow doped concentration is 1013cm-3, and the injection energy is 1KEV~10KEV;

[0119] S3, injecting BF3 in the shallow doped N-EPI layer to obtain the first P-type buried layer 300; phosphine

[0120] S4, injecting phosphorus ions on the upper surface of the first P-type buried layer 300, and the concentration of BF3 is 1.5x1016cm-3, to form a second N-type well 600 with a cross-beam structure 630 and 5 vertical structures;

[0121] S5, injecting BF3 in the upper surface region of the first P-type buried layer 300 and around and on the upper surface of the second N-type well 600, and the concentration of BF3 is 1016cm-3, and then annealing to obtain a second P-type buried layer 700;

[0122] S6, depositing silicon dioxide on the upper surface of the second P-type buried layer 700 to obtain an oxide layer 800;

[0123] S7, BF3 is injected into the gap between the STI isolation groove 500 and the first P-type buried layer 300, the concentration of the BF3 is 1016cm-3, so that boron ions fill the second N-type well 600, the second P-type buried layer 700, the N-type electrode 900 and the gap between the oxide layer 800 and the STI isolation groove 500, and then annealing is performed to obtain the third P-type well 400;

[0124] S8, phosphine is doped at the upper part of the five vertical structures, the doping depth is 0.4 μm, the concentration of the phosphine is 1x1020cm-3, and the N-type electrode 900 is formed;

[0125] S9, a metal layer 1000 is formed on the N-type electrode 900.

[0126] It is verified by experiments that the single-chip integrated 3D Hall device prepared by the preparation method of the embodiment can simultaneously realize the detection of three-dimensional magnetic field, has high integration degree and small size.

[0127] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the protection scope of the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A single-chip integrated 3D Hall device, characterized by, The application relates to a Hall sensor structure. STI isolation groove - arranged around the inner side wall of a P-type silicon wafer substrate; First N-type deep well - arranged at the bottom of the P-type silicon wafer substrate and matched with the STI isolation groove; First P-type buried layer - arranged at the center of the upper surface of the first N-type deep well, and a gap exists between the first P-type buried layer and the STI isolation groove; Second N-type well - arranged on the upper surface of the first P-type buried layer, and having five vertical structures and a cross-beam structure, wherein four vertical structures are integrally connected to four ends of the cross-beam structure respectively, and the four vertical structures are defined as first vertical structures; and another vertical structure is located at the midpoint of the cross-beam structure and is defined as a second vertical structure; Second P-type buried layer - arranged on the upper surface region of the first P-type buried layer, and around and on the upper surface of the second N-type well; N-type electrode - arranged on the upper part of the first vertical structure and the upper part of the second vertical structure, and the N-type electrode located on the first vertical structure is defined as a first N-type electrode, and the N-type electrode located on the second vertical structure is defined as a second N-type electrode; Oxidation layer - arranged on the upper surface of the second P-type buried layer; Third P-type well - arranged in the gap between the STI isolation groove and the first P-type buried layer, and matched with the side wall of the second N-type well, the side wall of the second P-type buried layer, the side wall of the N-type electrode and the side wall of the oxidation layer; Metal layer - arranged on the upper surface of the N-type electrode.

2. The single-chip integrated 3D Hall device according to claim 1, characterized in that: The cross-beam structure is provided with four beam bodies and a connecting body, each beam body is integrally connected to the connecting body, each beam body is perpendicular to the adjacent beam body, and the four beam bodies are in the same plane; Each first vertical structure is integrally connected to the end of a beam body, and the second vertical structure is integrally connected to the upper surface of the connecting body; The cross-beam structure is a central symmetric structure.

3. The single-chip integrated 3D Hall device according to claim 1, characterized in that: Four first vertical structures are sequentially connected into a closed area by using a virtual straight line, and the closed area is used as a Hall active functional area; The depth of the Hall active functional area is defined as D, and D is 4-8 mu m; The maximum length of the Hall active functional area is defined as L1, and L1 is 30-50 mu m.

4. The single-chip integrated 3D Hall device according to claim 1, characterized in that: The first P-type buried layer, the P-type silicon wafer substrate and the second P-type buried layer are grounded; The second P-type buried layer and the second N-type well form a reverse PN junction.

5. The single-chip integrated 3D Hall device according to claim 1, characterized in that: The depth of the STI isolation groove is 5500-6000 angstroms; The material of the STI isolation groove is silicon dioxide.

6. The single-chip integrated 3D Hall device according to claim 2, characterized in that: The thickness of the cross-beam structure is defined as H, and H is 0.5-2 mu m; The width of each beam body in the cross-beam structure is defined as W, and W is 6-8 mu m; The length of each beam body in the cross-beam structure is defined as L2, and L2 is 15-20 mu m; The thickness of the N-type electrode is 0.1-0.5 mu m.

7. The single-chip integrated 3D Hall device according to claim 1, characterized in that: The upper surface of the N-type electrode is flush with the upper surface of the oxidation layer; The N-type electrode is located between the oxidation layer and the second P-type buried layer; The third P-type well has a depth equal to the sum of the thickness of the first P-type buried layer, the thickness of the second N-type well and the thickness of the N-type electrode.

8. A method for manufacturing a single-chip integrated 3D Hall device according to any one of claims 1 to 7, characterized in that, The method comprises the following steps: S1, forming the STI isolation groove on the inner sidewall of the P-type silicon wafer substrate; S2, implanting N-type ions on the bottom of the P-type silicon wafer substrate and then annealing to form the first N-type deep well; S3, implanting P-type ions on the epitaxial layer of the first N-type deep well to obtain the first P-type buried layer; S4, implanting N-type ions on the upper surface of the first P-type buried layer to obtain the second N-type well with a cross-beam structure and five vertical structures; S5, implanting P-type ions in the upper surface region of the first P-type buried layer and around and on the upper surface of the second N-type well and then annealing to obtain the second P-type buried layer; S6, depositing an oxide layer on the upper surface of the second P-type buried layer; S7, implanting P-type ions in the gap between the STI isolation groove and the first P-type buried layer, so that the P-type ions fill the second N-type well, the second P-type buried layer, the N-type electrode and the gap between the oxide layer and the STI isolation groove, and then annealing to obtain the third P-type well; S8, implanting N-type ions on the upper part of the five vertical structures to form the N-type electrode; S9, patterning a metal layer on the top of the N-type electrode.

9. The method for fabricating a single-chip integrated 3D Hall device according to claim 8, wherein, The S2 specifically comprises the following steps: S2.1, implanting N-type ions on the bottom of the P-type silicon wafer substrate to form an NBL layer with moderate doping, which is the first N-type deep well; S2.2, continuing to implant N-type ions on the epitaxial layer of the NBL layer to grow an N-EPI layer with shallow doping; The S3 specifically comprises implanting P-type ions in the N-EPI layer with shallow doping to obtain the first P-type buried layer.

10. The method for fabricating a single-chip integrated 3D Hall device according to claim 9, characterized in that: The P-type ions are boron ions, and the N-type ions are phosphorus ions or arsenic ions.

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