Code error correction method for successive-approximation register analog-to-digital converter, and successive-approximation register analog-to-digital converter

Abstract

A code error correction method for a successive-approximation register analog-to-digital converter, and a successive-approximation register analog-to-digital converter, relating to the technical field of integrated circuits. The code error correction method for a successive-approximation register analog-to-digital converter of the present invention comprises the following steps: a, detecting whether a comparator completes data comparison within specified time, if yes, executing step b, and if not, executing step c; b, the comparator outputting data, starting the next data comparison process, and returning to step a; and c, interrupting a conversion cycle, waiting for a signal to start the next conversion, initiating the next data comparison process, and returning to step a. The present invention can effectively prevent the speed of a comparator from slowing down due to dead-time voltage.

Description

Method for correcting error code of successive approximation analog-to-digital converter and successive approximation analog-to-digital converter TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a successive approximation analog-to-digital converter (SAR ADC), and more particularly to a method for correcting error code of a successive approximation analog-to-digital converter and a successive approximation analog-to-digital converter. BACKGROUND

[0002] A successive approximation analog-to-digital converter (SAR ADC) includes a synchronous SAR ADC and an asynchronous SAR ADC.

[0003] The clock signal of the synchronous SAR ADC is externally input, and the comparison period of each bit of data is equal. In order to ensure the resolution accuracy of the comparator, each comparison period needs to be long enough, and the synchronous SAR ADC is generally used in a low-speed analog-to-digital converter.

[0004] The asynchronous SAR ADC automatically generates a clock signal by automatically judging the state of the comparator, and the comparison period of each bit of data can be unequal. In addition to avoiding the external input of a high-speed clock signal, the asynchronous SAR ADC can also improve the speed, and the asynchronous SAR ADC is generally used in a high-speed analog-to-digital converter.

[0005] The SAR ADC inevitably has an error code problem. The main causes of the error code problem are the dead-zone voltage of the comparator in the asynchronous logic and the glitch interference when the dynamic latch is flipped.

[0006] In order to facilitate the description, a 10-bit SAR ADC is taken as an example to describe the working process of a conventional asynchronous SAR ADC.

[0007] FIG. 1 is a block diagram of the asynchronous structure of a conventional asynchronous SAR ADC. When the external CLK_ST signal is “0”, the asynchronous logic does not work, the comparator Comp outputs OUTN and OUTP are both “0”, the dynamic latch Dynamic Latch is in a reset state, the decision module Comp Finish outputs “0”, the clock signal generator CLK_GEN does not flip, and the SAR Logic count value is “0”.

[0008] When the external CLK_ST signal is "1", the clock signal generator generates the first pulse, and the comparator performs the first comparison after receiving the first pulse. After the comparison result is obtained, "01" or "10" is output. The output data is given to the dynamic latch for latching on one side, and the SAR Logic module reads the latch for processing and output and counts as "1" on the other side. The output data is given to the decision module on the other side, and the decision module detects that the comparator output is no longer the initial all "0" to decide that the comparison is completed, and controls the clock signal generator to generate the next pulse. The comparator resets the output to all "0" after receiving the second pulse and starts the second comparison, and after the comparison result is obtained, "01" or "10" is output. The output data is given to the dynamic latch for latching on one side, and the SAR Logic module reads the latch for processing and output and counts as "2" on the other side. The output data is given to the decision module on the other side, and the decision module detects that the comparator output is no longer the initial all "0" to decide that the comparison is completed, and controls the clock signal generator to generate the next pulse. By analogy, until the tenth comparison, the comparator resets the output to all "0" after receiving the tenth pulse and starts the tenth comparison, and after the comparison result is obtained, "01" or "10" is output. The output data is given to the dynamic latch for latching on one side, and the SAR Logic module reads the latch for processing and output and counts as "10" on the other side, and the output Count signal terminates the CLK_GEN module to generate the clock pulse. The loop ends, and the data is output.

[0009] Error code caused by dead zone voltage.

[0010] As described above, the logic of the asynchronous SARADC, whether it can enter the next cycle (generate the next clock pulse) from the current working cycle depends on when the comparator completes the comparison output "01" or "10". However, the speed of the comparator is limited, and there is always a dead zone voltage. When the input DACN and DACP are very small or even completely consistent, the comparator will not be able to complete the comparison output "01" or "10" within the specified time. This makes the subsequent conversion cycle unable to proceed, so that the correct number cannot be output, resulting in an error code, as shown in FIG. 2.

[0011] Another source of SARADC error code is the glitch interference when the dynamic latch flips.

[0012] As shown in FIG. 3, when the comparator does not completely compare the result, at this time the output comparison is close, if there is a glitch interference that makes the output result simultaneously "1" for a short time. At this time, the dynamic latch will lock the result and cannot be restored. The reason is that the dynamic latch uses semi-dynamic logic in order to pursue speed, and once the result is locked, it cannot be restored.

[0013] Or in the comparator does not complete the comparison results, at this time output comparison close, if there are burr interference so that the output results in a short time for the threshold voltage, the decision circuit has been flip and output results are not really high, dynamic latch will read the wrong results "0", as shown in Figure 4.

[0014] Obviously these two cases from the circuit interference, and the comparator dead zone voltage has nothing to do with, no matter how fast the comparator, the dead zone voltage is small, still can produce this situation. SUMMARY

[0015] The main purpose of the present application is to provide a kind of successive approximation analog-digital converter error correction method and successive approximation analog-digital converter, in the asynchronous logic of comparator dead zone voltage and / or burr interference generated by dynamic latch flip error code correction is corrected without affecting the main circuit speed.

[0016] In order to achieve the above purpose, according to one aspect of the specific embodiments of the present application, a kind of successive approximation analog-digital converter error correction method is provided, comprising the following steps:

[0017] a, detect whether the comparator completes data comparison within a specified time, if yes, execute step b, if no, execute step c;

[0018] b, comparator output data, start next data comparison process, return to step a;

[0019] c, interrupt conversion period, wait for the signal of starting next conversion, start next data comparison process, return to step a.

[0020] In some embodiments, in step c, the clock signal generator is turned off, and a forced interruption signal is output, and the SAR Logic module sends an error signal.

[0021] In some embodiments, the error signal is consistent with the information output when the comparator input signal is the same.

[0022] In some embodiments, further comprising the steps of:

[0023] d, read the final output data of each positive and negative terminal of the comparator stored in the latch and store it;

[0024] e, compare before output data, judge whether the positive and negative terminal data of a bit are both "1" or "0", if yes, execute step f, if no, execute step g;

[0025] f、correcting the output from the current bit to an error code, outputting a forced interrupt signal, the SAR Logic module outputs an error code signal and interrupts the current conversion, waiting for the next conversion start signal, starting the next conversion data comparison process, and returning to step d to read the next bit of data;

[0026] g、outputting the data and returning to step d to read the next bit of data.

[0027] In order to achieve the above-mentioned purpose, according to another aspect of the embodiment of the present application, a successive approximation analog-to-digital converter is provided, comprising a comparator, a clock signal generator, a SAR Logic module, characterized in that further comprising a time decision module, the input end of the time decision module being connected to the output end of the comparator, the output end of the time decision module being connected to the clock signal generator and the SAR Logic module respectively, and the timing end of the time decision module being connected to the trigger signal of the clock signal generator.

[0028] In some embodiments, the time decision module is used to detect whether the comparator completes the data comparison within a specified time; if yes, the comparator outputs the data and starts the next data comparison process; if no, the time decision module outputs a forced interrupt signal to make the SAR Logic module output an error code signal to interrupt the conversion period, and the comparator waits for the signal to start the next conversion and starts the next data comparison process.

[0029] In some embodiments, the error code signal is consistent with the information output when the input signal of the comparator is the same.

[0030] In some embodiments, further comprising a memory and a data comparator, the memory being connected to the SAR Logic module, and the data comparator being connected to the memory.

[0031] In some embodiments, the memory is used to store the data output from the positive and negative ends of the comparator output by the SAR Logic module; and the data comparator is used to compare whether the data of a certain bit output from the positive and negative ends of the comparator stored in the memory are both "1" or "0".

[0032] Once it is found that the data of a certain bit at the positive and negative ends are both "1" or "0", it is determined that there is an error code; the output from the current bit is corrected to an error code signal, the data comparator outputs a forced interrupt signal, the SAR Logic module outputs an error code signal, and the data comparator reads the next bit of data for comparison.

[0033] In some embodiments, the memory is a DFF memory.

[0034] According to the technical solution of the present application and the further improved technical solution in some exemplary embodiments, the present application has the following beneficial effects:

[0035] The comparator speed slowing problem caused by dead zone voltage can be effectively prevented. The time decision module is parallel to the main circuit and does not occupy the time of the main loop, so the overall conversion rate is not reduced.

[0036] Further, the application can effectively prevent the error code caused by glitch interference, and use the result in the latch to judge and handle the error code in the process of preventing the error code caused by glitch interference. This is a digital way of processing, and the whole process is not in the conversion period and does not occupy the time of the conversion period. Therefore, the speed of the converter is not reduced, which is very suitable for the needs of high-speed asynchronous SARADC.

[0037] The application will be further described below in combination with the drawings and specific embodiments. The additional aspects and advantages of the application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0038] The drawings constituting a part of the application are used to provide further understanding of the application, and the specific embodiments, schematic embodiments and their descriptions of the application are used to explain the application and do not constitute an improper limitation on the application. In the drawings:

[0039] Fig. 1 is a schematic diagram of the structure of an asynchronous SARADC of the prior art;

[0040] Fig. 2 is a schematic diagram of signal levels that cannot complete comparison under the action of dead zone voltage;

[0041] Fig. 3 is a schematic diagram of signal levels when the output is “1” due to glitch interference;

[0042] Fig. 4 is a schematic diagram of signal levels when the output is “0” due to glitch interference;

[0043] Fig. 5 is a schematic diagram of the structure of the time detection circuit of embodiment 1;

[0044] Fig. 6 is a flow chart of the error code correction method of the analog-digital converter of embodiment 1;

[0045] Fig. 7 is a schematic diagram of the signal timing relationship of the time detection circuit of embodiment 1;

[0046] Fig. a is a schematic diagram of the signal timing relationship in a normal state, and Fig. b is a schematic diagram of the signal timing relationship in an abnormal state;

[0047] Fig. 8 is a flow chart of the error code correction method of the analog-digital converter of embodiment 2;

[0048] Fig. 9 is a schematic diagram of the logic circuit of the error code correction method of embodiment 2;

[0049] FIG. 10 is a schematic diagram of an asynchronous SAR ADC structure of Example 3. DETAILED DESCRIPTION

[0050] It should be noted that the specific implementations, exemplary embodiments and features in the present application can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the following contents.

[0051] In order for those skilled in the art to better understand the present application, the technical solutions in the specific implementations and exemplary embodiments of the present application will be described clearly and completely below in combination with the drawings in the specific implementations and exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the specific implementations and exemplary embodiments in the present application, all other implementations and embodiments obtained by those skilled in the art without making creative efforts should belong to the protection scope of the present application.

[0052] Example 1

[0053] As shown in FIG. 1, whether the working logic of the asynchronous SAR ADC can enter the next cycle (generate the next clock pulse) from the current working cycle depends on when the comparator Comp completes the comparison output "01" or "10". However, the speed of the comparator Comp is limited, and there is always a dead zone voltage. When the input difference is very small or even completely consistent, the comparator Comp will not be able to complete the comparison output "01" or "10" within the specified time, at which time the SAR Logic module will send the error code signal "1000000000" (10-bit ADC as an example), which makes the subsequent conversion cycle unable to proceed, and the asynchronous SAR ADC generates an error code.

[0054] In view of this situation, the present example adopts a time decision module Time_MAX to judge the output of the comparator, as shown in FIG. 5. Not only is it judged whether the output of the comparator Comp is "10" or "01", but also the comparison time of the comparator is detected, and the comparison time is timed using the signal CLK_ST as the starting signal. If the comparison time of the comparator exceeds a certain threshold, the conversion cycle is interrupted, the clock signal generator CLK_GEN is turned off, the forced interruption signal Force_out is output, and the SAR Logic module outputs the error code signal "1000000000" to wait for the arrival of the next start conversion signal. The error code correction method flow is shown in FIG. 6. This time detection method can effectively prevent the problem of slow speed of the comparator caused by the dead zone voltage. Moreover, the time decision module is parallel to the main circuit and does not occupy the time of the main loop, so it will not reduce the overall conversion rate.

[0055] The time decision module is shown in Fig. 5, which is composed of logic gates, delay unit DEL, selector DFF and SAR_LOGIC module. DACP, DATAN and OUTP, OUTN are the inputs and outputs of the comparator, COV_EN is the end signal of conversion, COV_END is the forced interruption signal, VLD is the conversion process (representing the time of each comparison in the conversion period), DATA_OK is the data completion signal, COV_OK is the conversion completion signal, CLK_ST is the start signal of conversion, Cout_over is the detection result, Force_out is the forced interruption signal. Signal flow: the comparator decision results OUTP, OUTN, through the or gate and the not gate, get the conversion process VLD, which is ended by COV_EN if it is completed normally. When the comparator is too slow to result in the results not coming out all the time, VLD will also not produce results for a long time, and then and CLK_ST delay get the detection result Cout_over (normal case is 0, error case will produce a pulse signal). The results are given to the SAR_LOGIC module by the selector, and the DATA_OK signal and the COV_OK signal are generated, the conversion is ended, and feedback to the time decision module, reset the detection result to prevent affecting the next conversion.

[0056] Fig. 7 shows the timing relationship of the signals of the time decision module. As shown in Fig. 7a, in the normal conversion case, the overlapping time of VLD and CLK_ST is too short to produce a pulse signal, so Cout_over and Force_out are always 0, which will not interrupt the conversion.

[0057] In the error case, as shown in Fig. 7b, OUTP and OUTN do not produce results for a long time, VLD will also not produce falling edge for a long time, and and CLK_ST will produce a pulse signal Cout_over, thereby interrupting the conversion.

[0058] Example 2

[0059] Another source of error of the asynchronous SARADC is the glitch interference when the dynamic latch flips. The traditional solution is to use XOR to judge whether the comparator has completed the comparison. This method has two obvious problems: 1. As a digital circuit, the decision of the XOR logic circuit still has the problem of intermediate state, that is, when the two inputs are near the threshold value, the decision of the XOR gate cannot be guaranteed to be correct. More generally, any decision gate will have its own threshold voltage, and when the input is near this voltage, it may appear to be misjudged. 2. The XOR gate greatly increases the circuit delay compared with the simple or gate, which is very disadvantageous for high-speed asynchronous SARADC.

[0060] The error correction method of the example analog-to-digital converter uses a posteriori method, directly storing the final output OUTP and OUTN of each positive and negative terminal of the comparator (using DFF as the storage). The comparison is performed before the output, and once it is found that there is a bit with both positive and negative terminals being "1" or "0", it is determined that there is an error code. The output from the current bit is immediately corrected to 1000000000 (10-bit ADC as an example). The correction method flow of the example is shown in FIG. 8. Since the output result in the latch is read, not the direct output of the comparator, there is no intermediate state problem near the threshold. Thus, the intermediate state problem of the error code decision is avoided. Another advantage of the example is that the result in the latch is used to process the error code, which is processed by a digital method. The entire process is not within the ADC conversion period, and does not occupy the conversion period time, so it will not reduce the speed of the converter, and is very suitable for the requirements of high-speed asynchronous SAR ADC.

[0061] As shown in FIG. 9, the logic circuit of the error correction method of the example is shown. The signal processing flow of the logic circuit is as follows:

[0062] a. Read the comparator decision result Latch_data in the latch <n>and the result data <n>A reference data for a comparison process is generated by an OR gate to obtain the start and finish times of each comparison.

[0063] b, en enable, output the nth decision result data_out <n>;

[0064] c. Based on the comparator completion time obtained in a, shorten the enable range of en to obtain en_next;

[0065] d. Pass en_next to the (n-1)th logic circuit to enable it (ensure that the previous comparison result has been read before proceeding to prevent data conflicts).

[0066] Example 3

[0067] The error correction circuit shown in Figure 10 operates as follows:

[0068] a. The comparator Comp compares the inputs DCN and DAP to obtain the results OUTP and OUTN, which are then given to the time decision module Time_MAX and stored in the latch Dynamic Latch.

[0069] b. The Time_MAX module determines whether a comparison has not been completed for an extended period. If so, proceed to step c; otherwise, proceed to step d.

[0070] c. If the comparison time is too long, a Force_out interrupt signal is generated and sent to the SAR LOGIC module and the CLK_GEN module. The SAR LOGIC module then stops the subsequent process of this conversion. Proceed to step e.

[0071] d. SAR LOGIC determines that the comparison is complete, outputs the comparison data, and simultaneously sends a comparison completion signal to the CLK_GEN module until the conversion is complete and all final data is output. Proceed to step e;

[0072] e. Control the start and interruption of the comparator based on the results of the SAR LOGIC module and the time decision module. Proceed to step f after conversion is complete / interrupted;

[0073] f. The final SAR LOGIC data, Datap and Datan, are given to DFF;

[0074] g. Determine the data Datap <n>and Datan <n>If yes, it means that there is an error code, and the selection is generated by the data_cal module 1000000000 (for example, 10-bit ADC). Otherwise, it means normal, and the data Out_data is directly output.

[0075] As shown in FIG. 10, the SAR ADC in the example includes a comparator, a clock signal generator, a SAR Logic module, a time decision module, a memory, and a data comparator (shown in the dashed box in FIG. 10).

[0076] The input end of the time decision module is connected to the output end of the comparator, the output end of the time decision module is connected to the clock signal generator and the SAR Logic module respectively, and the timing end of the time decision module is connected to the trigger signal CLK_ST of the clock signal generator.

[0077] The memory is connected to the SAR Logic module, and the data comparator is connected to the memory.

[0078] The memory is used to store the data output by the comparator positive and negative ends output by the SAR Logic module; the data comparator is used to compare whether the data of a certain bit output by the comparator positive and negative ends is "1" or "0".

[0079] Once it is found that the positive and negative ends of a certain bit are "1" or "0", it is determined that there is an error code; the output from the current bit is corrected as an error code signal, and the data comparator outputs a forced interruption signal (Force_out), so that the SAR Logic module sends an error code signal (1000000000), and the data comparator reads the next bit data for comparison.

[0080] The memory in the example uses a DFF memory, which is actually a D-type flip-flop, which can store the data output by the comparator positive and negative ends output by the SAR Logic module.< / n> < / n> < / n> < / n> < / n>

Claims

1. A method of error correction for a successive approximation analog-to-digital converter, characterized in that, The method comprises the following steps: a. detecting whether the comparator completes data comparison within a specified time, if yes, executing step b, if no, executing step c; b. outputting data of the comparator, starting a next data comparison process, and returning to step a; c. interrupting a conversion period, waiting for a signal for starting a next conversion, starting a next data comparison process, and returning to step a.

2. The method of claim 1, wherein, In step c, a clock signal generator is turned off, a forced interrupt signal is outputted, and the SAR Logic module sends an error code signal.

3. The method of claim 2, wherein, The error code signal is consistent with information outputted when the comparator input signal is the same.

4. The method of claim 1, wherein, The method further comprises the following steps: d. reading and storing final output data of the comparator at positive and negative terminals each time in a latch; e. comparing before outputting the data, judging whether the data at positive and negative terminals of a bit are both "1" or "0", if yes, executing step f, if no, executing step g; f. correcting output from the current bit as an error code, outputting a forced interrupt signal, the SAR Logic module sending an error code signal and interrupting the current conversion, waiting for a signal for starting a next conversion, starting a data comparison process of the next conversion, and returning to step d to read data of a next bit; g. outputting the data and returning to step d to read data of a next bit.

5. A successive approximation analog-to-digital converter comprising a comparator, a clock signal generator, a SAR Logic module, characterized in that, The method further comprises a time decision module, an output end of the time decision module is connected with an output end of the comparator, an output end of the time decision module is connected with the clock signal generator and the SAR Logic module respectively, and a trigger signal of the clock signal generator is connected with a timing end of the time decision module.

6. The successive approximation analog-to-digital converter of claim 5, wherein, The time decision module is used for detecting whether the comparator completes data comparison within a specified time, if yes, the comparator outputs data, a next data comparison process is started, if no, the time decision module outputs a forced interrupt signal, the SAR Logic module sends an error code signal to interrupt a conversion period, the comparator waits for a signal for starting a next conversion, and a next data comparison process is started.

7. The successive approximation analog-to-digital converter of claim 5, wherein, The error code signal is consistent with information outputted when the comparator input signal is the same.

8. The successive approximation analog-to-digital converter of claim 5, wherein, The method further comprises a memory and a data comparator, the memory is connected with the SAR Logic module, and the data comparator is connected with the memory.

9. The successive approximation analog-to-digital converter of claim 8, wherein, The memory is used for storing data outputted by the SAR Logic module at positive and negative terminals of the comparator, and the data comparator is used for comparing whether data of a bit at positive and negative terminals of the comparator are both "1" or "0". Once it is found that the data at positive and negative terminals of a bit are both "1" or "0", it is judged that there is an error code, output from the current bit is corrected as an error code signal, the data comparator outputs a forced interrupt signal, the SAR Logic module sends an error code signal, and the data comparator reads data of a next bit for comparison.

10. The successive approximation analog-to-digital converter of claim 5, wherein, The memory adopts a DFF memory.

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