Optoelectronic interconnection packaging structure and preparation method therefor

Abstract

Provided are an optoelectronic interconnection packaging structure and a preparation method therefor. A TGV metal pillar, an optical waveguide layer, and a bonded TSV bridge plate are prepared in a glass substrate. A transmission path of an optical chip is provided by means of the optical waveguide layer, and an electrical chip and the optical chip are interconnected by means of the TSV bridge plate. In this way, high-density and high-performance integration of an electrical chip and an optical chip can be achieved, reducing packaging size, decreasing power consumption, improving reliability, and achieving good optoelectronic signal transmission.

Description

Optoelectronic interconnection packaging structure and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and relates to an optoelectronic interconnection packaging structure and a preparation method thereof. BACKGROUND

[0002] Optics has excellent performances such as small signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS. It is generally believed that the introduction of optical technology into semiconductor processes can not only reduce chip size, cost and power consumption, but also improve reliability, so that functional chips can be connected by optical fibers in an edge coupling manner.

[0003] In semiconductor 2.5D / 3D packaging, organic adapter plates, through-silicon via (TSV) adapter plates and through-glass via (TGV) adapter plates are the mainstream adapter plate materials. The main purpose of setting the adapter plate is to solve some challenges in semiconductor packaging, such as improving integration, reducing cost and improving electrical performance.

[0004] Most of the existing optoelectronic interconnection packaging structures directly bond optical chips and electrical chips on a substrate and are electrically connected with the substrate by wire-bonds or Flip-Chip, but the existing optoelectronic interconnection packaging structures are difficult to meet the needs of high-density and high-performance product packaging. Since glass is an insulating material, it has a low dielectric constant (about 1 / 3 of silicon) and a small loss factor (about 2-3 orders of magnitude smaller than silicon), and excellent high-frequency performance, which enables glass to significantly reduce insertion loss and crosstalk at high frequencies.

[0005] Therefore, it is necessary to provide an optoelectronic interconnection packaging structure and a preparation method thereof. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an optoelectronic interconnection packaging structure and a preparation method thereof, which can solve the problem that the optoelectronic interconnection packaging structure in the prior art is difficult to meet the needs of high-density and high-performance products.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of an optoelectronic interconnection packaging structure, comprising the following steps:

[0008] providing a glass substrate, the glass substrate comprising a first surface and a second surface arranged oppositely;

[0009] patterning the glass substrate to form a blind hole with a bottom in the glass substrate from the first surface of the glass substrate;

[0010] forming a TGV metal column in the blind hole;

[0011] graphically patterning the glass substrate, forming a first recess and a second recess in the glass substrate from the second surface of the glass substrate, and the second recess exposing a second end of the TGV metal post;

[0012] forming an optical waveguide layer in the first recess, and providing a TSV bridge plate and bonding the TSV bridge plate in the second recess, and the TSV bridge plate being electrically connected with the second end of the TGV metal post;

[0013] forming a rewiring layer on the first surface of the glass substrate, and the rewiring layer being electrically connected with the first end of the TGV metal post;

[0014] providing an electrical chip and an optical chip with a photosensitive region, bonding the electrical chip and the optical chip on the TSV bridge plate, the electrical chip and the optical chip being electrically connected with the TSV bridge plate, and the photosensitive region of the optical chip being arranged corresponding to the optical waveguide layer.

[0015] Optionally, the method for patterning the glass substrate to form the blind hole, the first recess and the second recess comprises a laser method, and the laser method comprises a laser ablation method or a laser-induced denaturation etching method; and the method for forming the TGV metal post comprises chemical plating or electroplating.

[0016] Optionally, the method for forming the rewiring layer on the first surface of the glass substrate comprises a semiconductor process method or a substrate bonding method.

[0017] Optionally, the optical interconnection package structure comprises 2≤N optical chips, wherein N is an integer, and each of the optical chips is interconnected through the optical waveguide layer.

[0018] Optionally, after the TSV bridge plate is bonded, the method further comprises a step of forming a passivation filling layer in the second recess to fill a gap.

[0019] Optionally, the method further comprises a step of forming a metal mirror on a sidewall of the first recess; a step of forming a convex lens on the optical waveguide layer; and a step of forming a metal bump on the rewiring layer.

[0020] Optionally, the thickness of the glass substrate is 100-300 μm.

[0021] The application further provides an optical-electrical interconnection package structure, which comprises:

[0022] a glass substrate, the glass substrate comprising a first surface and a second surface arranged oppositely;

[0023] a blind hole, the blind hole extending from the first surface of the glass substrate into the glass substrate;

[0024] a TGV metal pillar located in the blind hole;

[0025] a first groove and a second groove, both extending into the glass substrate from the second surface of the glass substrate, and the second groove exposing a second end of the TGV metal pillar;

[0026] an optical waveguide layer located in the first groove;

[0027] a TSV bridge plate bonded in the second groove and electrically connected with the second end of the TGV metal pillar;

[0028] a rewiring layer located on the first surface of the glass substrate and electrically connected with the first end of the TGV metal pillar;

[0029] an electrical chip and an optical chip with a light sensing region, both bonded on the TSV bridge plate, both electrically connected with the TSV bridge plate, and the light sensing region of the optical chip corresponding to the optical waveguide layer.

[0030] Optionally, 2≤N optical chips are included, where N is an integer, and each of the optical chips is interconnected through the optical waveguide layer.

[0031] Optionally, a metal mirror located on the sidewall of the first groove, a convex lens located on the optical waveguide layer, and a metal bump located on the rewiring layer are further included.

[0032] As described above, the optoelectronic interconnection packaging structure and the preparation method thereof, the TGV metal pillar, the optical waveguide layer and the bonded TSV bridge plate are prepared in the glass substrate, the transmission path of the optical chip is provided through the optical waveguide layer, and the interconnection of the electrical chip and the optical chip is realized through the TSV bridge plate, thereby realizing the high-density and high-performance integration of the electrical chip and the optical chip, reducing the packaging size, reducing the power consumption, improving the reliability, and realizing good optical and electrical signal transmission. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 shows a flowchart of preparing the optoelectronic interconnection packaging structure in the embodiment of the present application.

[0034] FIG. 2 shows a structure schematic diagram after forming a blind hole in the embodiment of the present application.

[0035] FIG. 3 shows a structure schematic diagram after forming a TGV metal pillar in the embodiment of the present application.

[0036] Figure 4 shows a structure schematic diagram after forming the first recess and the second recess in an embodiment of the present application.

[0037] Figure 5 shows a structure schematic diagram after forming the optical waveguide layer and bonding the TSV bridge plate in an embodiment of the present application.

[0038] Figure 6 shows a structure schematic diagram after forming the passivation filling layer and the convex lens in an embodiment of the present application.

[0039] Figure 7 shows a structure schematic diagram after forming the re-wiring layer in an embodiment of the present application.

[0040] Figure 8 shows a structure schematic diagram after bonding the electrical chip, the optical chip and forming the metal bump in an embodiment of the present application.

[0041] Figure 9 shows a top view structure schematic diagram of Figure 8.

[0042] Figure 10 shows an enlarged structure schematic diagram of the area A in Figure 9.

[0043] Reference sign explanation 100 glass substrate 101 blind hole 102 first recess 103 second recess 200 TGV metal column 300 optical waveguide layer 400 TSV bridge plate 500 passivation filling layer 600 convex lens 700 re-wiring layer 801 electrical chip 802 optical chip 812 photosensitive region 900 metal bump 110 metal mirror DETAILED DESCRIPTION

[0044] Following, the advantages and effects of the present application will be easily understood by those skilled in the art from the description of the present application. The present application can also be implemented or applied by different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0045] As described in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general proportion for the convenience of description, and the schematic view is only an example which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0046] For the convenience of description, spatial relationship words such as "under", "below", "lower", "under", "above", "upper" and the like can be used to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include the device in use or operation in other directions than the direction depicted in the drawings, which can include the embodiment that the first and second features are formed in direct contact, and can also include the embodiment that the additional features are formed between the first and second features, so that the first and second features can not be in direct contact, and in addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0047] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed, and the component layout pattern can be more complex.

[0048] Referring to FIG. 1, the present embodiment provides a preparation method of an optoelectronic interconnection packaging structure, a TGV metal column, an optical waveguide layer and a bonding TSV bridge plate are prepared in a glass substrate, the transmission path of an optical chip is provided through the optical waveguide layer, and the interconnection of an electrical chip and an optical chip is realized through the TSV bridge plate, thereby realizing high-density and high-performance integration of the electrical chip and the optical chip, reducing the packaging size, reducing the power consumption, improving the reliability, and realizing good optical and electrical signal transmission.

[0049] The preparation of the optoelectronic interconnection packaging structure will be further described below in conjunction with FIGS. 2-10, which specifically includes:

[0050] First, referring to FIGS. 1 and 2, step S1 is performed to provide a glass substrate 100, the glass substrate 100 including a first surface and a second surface disposed opposite to each other.

[0051] Specifically, the glass substrate 100 can include a wafer-level glass substrate, such as a 4-inch, 6-inch, 8-inch, 12-inch, etc., and the thickness of the glass substrate 100 can be 100-300 μm, such as 100 μm, 200 μm, 300 μm, etc., but the size of the glass substrate 100 is not limited thereto and can be set as needed, which is not excessively limited herein.

[0052] Next, referring to FIGS. 1 and 2, step S2 is performed to pattern the glass substrate 100 to form a blind hole 101 in the glass substrate 100 from a first surface of the glass substrate 100.

[0053] Specifically, the method of patterning the glass substrate 100 to form the blind hole 101 can include a laser method, which can include, for example, a laser ablation method or a laser-induced phase-change etching method, and the specific operations of the laser ablation method or the laser-induced phase-change etching method are not described herein and can be referred to existing preparation methods.

[0054] The blind hole 101 is formed by the laser method, and thus the opening width of the blind hole 101 is greater than the bottom width, and the specific size of the blind hole 101 is not excessively limited herein.

[0055] Further, after forming the blind hole 101, the glass substrate 100 can also be subjected to a thinning process, such as chemical mechanical polishing (CMP), etc., to further thin the thickness of the glass substrate 100, reduce the size of the packaging structure, and by thinning, the area of the blind hole 101 with a greater width can be removed, and the critical dimension (CD) of the blind hole 101 can be further reduced. The thickness of the glass substrate 100 after thinning can be 100-200 μm, such as 100 μm, 150 μm, 200 μm, etc., and the critical dimension of the blind hole 101 after thinning can be 40-50 μm, such as 40 μm, 45 μm, 50 μm, etc.

[0056] Next, referring to FIGS. 1 and 3, step S3 is performed to form a TGV metal pillar 200 in the blind hole 101.

[0057] The method of forming the TGV metal pillar 200 can include, for example, electroless plating or electroplating, and the specific operations of the electroless plating or electroplating are not described herein and can be referred to existing preparation methods.

[0058] In this embodiment, the material of the TGV metal pillar 200 is selected to be copper metal, but the material of the TGV metal pillar 200 is not limited thereto and can also be other conductive metal materials.

[0059] Further, after the blind hole 101 is prepared by the laser method, in order to facilitate the formation of the TGV metal column 200 filling the blind hole 101, the blind hole 101 can be surface treated, such as wet etching, so that the blind hole 101 has a smooth inner surface. The method of surface treatment is not limited here.

[0060] Further, after the TGV metal column 200 is formed, in order to facilitate the preparation of the subsequent rewiring layer, the glass substrate 100 can be surface treated, such as grinding, wet etching, etc., to obtain a flat surface.

[0061] Next, referring to FIGS. 1 and 4, step S4 is performed to pattern the glass substrate 100 to form a first groove 102 and a second groove 103, both of which have bottoms located in the glass substrate 100, from the second surface of the glass substrate 100, and the second groove 103 exposes the second end of the TGV metal column 200.

[0062] The method of patterning the glass substrate 100 to form the first groove 102 and the second groove 103 can include a laser method, which can include, for example, a laser ablation method or a laser-induced phase-change etching method. Preferably, the method of forming the first groove 102 and the second groove 103 is the same as the method of forming the blind hole 101, so as to reduce the process complexity and facilitate the management and operation of the process. However, the method is not limited to this, and different preparation methods can also be used according to needs.

[0063] Since the first groove 102 and the second groove 103 are prepared by the laser method, the opening width of the first groove 102 and the second groove 103 is greater than the bottom width. In particular, the sidewall of the first groove 102 has an inclined surface, which is beneficial to the subsequent transmission of optical signals. The inclination angle of the inclined surface can be set according to specific needs, and is not limited here.

[0064] Next, referring to FIGS. 1 and 5, step S5 is performed to form an optical waveguide layer 300 in the first groove 102, and to provide a TSV bridge plate 400 and bond the TSV bridge plate 400 in the second groove 103, and the TSV bridge plate 400 is electrically connected to the second end of the TGV metal column 200.

[0065] Referring to FIG. 10, which is a partial enlarged view of region A in FIG. 9, in order to reduce optical loss and improve optical transmission efficiency, in the present embodiment, a metal mirror 110 is preferably formed on the sidewall of the first groove 102, such as a titanium metal mirror prepared by sputtering and etching. The metal mirror 110 can also cover the bottom of the first groove 102, and is not limited here.

[0066] The semiconductor process method can be used to prepare the optical waveguide layer 300, i.e. through coating, exposure, development, etching and other steps, and the optical waveguide layer 300 can include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer, etc.

[0067] The specific structure, preparation and bonding method of the TSV bridge plate 400 are not limited here and can be selected as needed. The order of forming the optical waveguide layer 300 in the first groove 102 and bonding the TSV bridge plate 400 in the second groove 103 can be selected as needed and is not limited here.

[0068] Further, referring to FIG. 6, after bonding the TSV bridge plate 400, a step of forming a passivation filling layer 500 to fill the gap in the second groove 103 can be further included to improve the bonding stability through the passivation filling layer 500. The material of the passivation filling layer 500 can be, for example, an organic plastic packaging material, and the specific material and filling method of the passivation filling layer 500 are not limited here.

[0069] Further, referring to FIG. 6, a convex lens 600 is preferably formed on the optical waveguide layer 300 to play a role of light condensation through the convex lens 600 to further reduce light loss. The preparation method of the convex lens 600 is not limited here and can be bonding, but is not limited thereto.

[0070] Next, referring to FIGS. 1 and 7, step S6 is performed to form a rewiring layer 700 on the first surface of the glass substrate 100, and the rewiring layer 700 is electrically connected to the first end of the TGV metal pillar 200.

[0071] Specifically, the method of forming the rewiring layer 700 on the first surface of the glass substrate 100 can include a semiconductor process method or a substrate bonding method, which is not limited here. The semiconductor process method is to prepare the rewiring layer 700 on the glass substrate 100 through coating, exposure, development, deposition, etching and other steps, and the substrate bonding method is to prepare the required rewiring layer 700 in advance and then directly bond the rewiring layer 700 to the glass substrate 100.

[0072] The specific preparation of the rewiring layer 700 is not limited here, and the specific material and structure of the rewiring layer 700 are not limited here and can be selected as needed.

[0073] Then, referring to FIG. 1, FIG. 8 and FIG. 9, wherein FIG. 8 is a sectional structural schematic view of FIG. 9 along C-C', a step S7 is performed to provide an electric chip 801 and a light chip 802 with a light sensitive region 812, and the electric chip 801 and the light chip 802 are bonded on the TSV bridge plate 400, the electric chip 801 and the light chip 802 are both electrically connected with the TSV bridge plate 400, and the light sensitive region 812 of the light chip 802 is arranged corresponding to the optical waveguide layer 300.

[0074] As an example, 2≤N light chips 802 are included, wherein N is an integer, and each of the light chips 802 is interconnected through the optical waveguide layer 300.

[0075] Specifically, referring to FIG. 8 and FIG. 9, in the embodiment, the value of N is 2, that is, 2 light chips 802 are bonded on the TSV bridge plate 400, and the electrically leading ends of the electric chip 801 and the light chip 802 are electrically connected with the TSV bridge plate 400 through metal bumps, and the light sensitive region 812 of the 2 light chips 802 is arranged corresponding to the optical waveguide layer 300 to form an optical transmission path together with the optical waveguide layer 300, as shown by the dashed line with arrow in FIG. 9, but the optical transmission path is not limited to this. The value of N of the light chip 802 can also be, for example, 1, 3, 5, etc., and the distribution of the light chip 802 is not limited here.

[0076] Similarly, the number of the electric chip 801 bonded on the TSV bridge plate 400 is not limited to 1, and can also be 2, 3, etc. The specific number and distribution of the electric chip 801 are not limited here.

[0077] Further, referring to FIG. 8, a step of forming a metal bump 900 on the re-distribution layer 700 can also be included to facilitate subsequent electrical connection.

[0078] It can be understood that, in order to improve productivity, the optoelectronic interconnection packaging structure in FIG. 8 can be regarded as a single structure formed after a cutting process, of course, according to needs, the optoelectronic interconnection packaging structure in FIG. 8 can also be a single structure directly prepared without a cutting process, which is not limited here.

[0079] Referring to FIG. 2-FIG. 10, the embodiment also provides an optoelectronic interconnection packaging structure, wherein the optoelectronic interconnection packaging structure can be directly prepared by using the above preparation process, so the material, structure, etc. of the optoelectronic interconnection packaging structure can be referred to the above content, of course, according to needs, the optoelectronic interconnection packaging structure can also be prepared by using other preparation processes.

[0080] In the embodiment, the optoelectronic interconnection packaging structure includes:

[0081] a glass substrate 100 comprising a first surface and a second surface arranged oppositely;

[0082] a blind hole 101 extending into the glass substrate 100 from the first surface of the glass substrate 100;

[0083] a TGV metal pillar 200 located in the blind hole 101;

[0084] a first groove 102 and a second groove 103 both extending into the glass substrate 100 from the second surface of the glass substrate 100, and the second groove 102 exposing a second end of the TGV metal pillar 200;

[0085] an optical waveguide layer 300 located in the first groove 102;

[0086] a TSV bridge plate 400 bonded in the second groove 102, and the TSV bridge plate 400 being electrically connected with the second end of the TGV metal pillar 200;

[0087] a rewiring layer 700 located on the first surface of the glass substrate 100, and the rewiring layer 700 being electrically connected with a first end of the TGV metal pillar 200;

[0088] an electrical chip 801 and an optical chip 802 with a photosensitive region 812, the electrical chip 801 and the optical chip 802 being bonded on the TSV bridge plate 400, the electrical chip 801 and the optical chip 802 both being electrically connected with the TSV bridge plate 400, and the photosensitive region 812 of the optical chip 802 being arranged correspondingly with the optical waveguide layer 300.

[0089] The glass substrate 100 can comprise a wafer-level glass substrate, such as 4 inches, 6 inches, 8 inches, 12 inches, etc., and the thickness of the glass substrate 100 can be 100-300 μm, such as 100 μm, 200 μm, 300 μm, etc., but the size of the glass substrate 100 is not limited thereto, and can be set as needed, which is not limited herein.

[0090] The TGV metal pillar 200 and the optical waveguide layer 300 can have a tapered morphology with the upper part being wide and the lower part being narrow, which is not limited thereto, and the morphology and size of the TGV metal pillar 200 are not limited herein.

[0091] As an example, 2≤N optical chips 802 are included, where N is an integer, and each of the optical chips 802 is interconnected by the optical waveguide layer 300.

[0092] Specifically, referring to FIGS. 8 and 9, in the embodiment, the value of N is 2, that is, 2 optical chips 802 are bonded on the TSV bridge plate 400, and the electrical leads of the electrical chip 801 and the optical chip 802 are electrically connected to the TSV bridge plate 400 through metal bumps, and the light-sensitive regions 812 of the 2 optical chips 802 are correspondingly arranged with the optical waveguide layer 300 to form an optical transmission path in combination with the optical waveguide layer 300, as shown by the dashed line with arrows in FIG. 9, but the optical transmission path is not limited thereto. The value of N for the optical chip 802 can also be, for example, 1, 3, 5, etc., and the distribution of the optical chip 802 is not limited herein.

[0093] Similarly, the number of the electrical chip 801 bonded on the TSV bridge plate 400 is not limited to 1, but can also be 2, 3, etc. The specific number and distribution of the electrical chip 801 are not limited herein.

[0094] Referring to FIG. 10, which is a partial enlarged view of region A in FIG. 9. In order to reduce light loss and improve optical transmission efficiency, in the embodiment, a metal mirror 110 is preferably formed on the sidewall of the first groove 102, such as a titanium metal mirror prepared by sputtering and etching, and the metal mirror 110 can also cover the bottom of the first groove 102, which is not limited herein.

[0095] Further, referring to FIG. 8, a step of forming a metal bump 900 on the re-wiring layer 700 can also be included to facilitate subsequent electrical connection.

[0096] It can be understood that, in order to improve productivity, the optoelectronic interconnection packaging structure in FIG. 8 can be considered as a single structure formed after a cutting process, and of course, according to needs, the optoelectronic interconnection packaging structure in FIG. 8 can also be a single structure directly prepared without a cutting process, which is not limited herein.

[0097] In summary, the optoelectronic interconnection packaging structure and the preparation method thereof of the present application prepare a TGV metal column, an optical waveguide layer, and a bonded TSV bridge plate in a glass substrate, provide a transmission path for an optical chip through the optical waveguide layer, and realize the interconnection of an electrical chip and an optical chip through the TSV bridge plate, thereby realizing high-density and high-performance integration of the electrical chip and the optical chip, reducing the packaging size, reducing power consumption, improving reliability, and achieving good optical and electrical signal transmission.

[0098] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method of fabricating an optoelectronic interconnect package structure, comprising: The method comprises the following steps: ​ providing a glass substrate comprising a first surface and a second surface arranged oppositely; patterning the glass substrate to form a blind hole with a bottom in the glass substrate from the first surface of the glass substrate; forming a TGV metal column in the blind hole; patterning the glass substrate to form a first groove and a second groove with bottoms in the glass substrate from the second surface of the glass substrate, and the second groove exposes a second end of the TGV metal column; forming an optical waveguide layer in the first groove, and providing a TSV bridge plate and bonding the TSV bridge plate in the second groove, and the TSV bridge plate is electrically connected with the second end of the TGV metal column; forming a rewiring layer on the first surface of the glass substrate, and the rewiring layer is electrically connected with a first end of the TGV metal column; providing an electrical chip and an optical chip with a photosensitive region, and bonding the electrical chip and the optical chip on the TSV bridge plate, the electrical chip and the optical chip are electrically connected with the TSV bridge plate, and the photosensitive region of the optical chip is arranged correspondingly with the optical waveguide layer.

2. The method of claim 1, wherein: The method for patterning the glass substrate to form the blind hole, the first groove and the second groove comprises a laser method, and the laser method comprises a laser ablation method or a laser-induced denaturation etching method; the method for forming the TGV metal column comprises chemical plating or electroplating.

3. The method of claim 1, wherein: The method for forming the rewiring layer on the first surface of the glass substrate comprises a semiconductor process method or a substrate bonding method.

4. The method of claim 1, wherein: The optical interconnection package structure comprises 2≤N optical chips, wherein N is an integer, and each optical chip is interconnected through the optical waveguide layer.

5. The method of claim 1, wherein: After bonding the TSV bridge plate, the method further comprises a step of forming a passivation filling layer to fill a gap in the second groove.

6. The method of claim 1, wherein: The method further comprises a step of forming a metal mirror on a sidewall of the first groove, a step of forming a convex lens on the optical waveguide layer, and a step of forming a metal bump on the rewiring layer.

7. The method of claim 1, wherein: The thickness of the glass substrate is 100-300 μm.

8. An optoelectronic interconnect package structure, comprising: The optoelectronic interconnection package structure comprises: a glass substrate comprising a first surface and a second surface arranged oppositely; a blind hole extending into the glass substrate from the first surface of the glass substrate; a TGV metal column in the blind hole; a first groove and a second groove both extending into the glass substrate from the second surface of the glass substrate, and the second groove exposes a second end of the TGV metal column; an optical waveguide layer in the first groove; a TSV bridge plate bonded in the second groove, and the TSV bridge plate is electrically connected with the second end of the TGV metal column; a rewiring layer on the first surface of the glass substrate, and the rewiring layer is electrically connected with a first end of the TGV metal column; An electrical chip and a light chip with a light sensing area are bonded on the TSV bridge plate, the electrical chip and the light chip are electrically connected with the TSV bridge plate, and the light sensing area of the light chip is arranged corresponding to the light waveguide layer.

9. The optoelectronic interconnect package structure of claim 8, wherein: The light chip includes 2≤N light chips, where N is an integer, and each light chip is interconnected through the light waveguide layer.

10. The optoelectronic interconnect package structure of claim 8, wherein: A metal mirror is further arranged on the sidewall of the first groove, a convex lens is further arranged on the light waveguide layer, and a metal bump is further arranged on the re-wiring layer.

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