Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a base substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer, and a pixel layer that are sequentially stacked. The display panel comprises circuit areas arranged in an array, and the circuit areas are provided with pixel driving circuits for driving sub-pixels. The display panel is provided with first connection lines and data signal wires, and each circuit area column comprises a plurality of circuit areas sequentially arranged in a column direction; each first connection line comprises first sub-lines sequentially and alternately arranged in the first source-drain metal layer and second sub-lines arranged in the second source-drain metal layer, and a first sub-line and a second sub-line adjacent thereto are electrically connected by means of a via hole. The display panel further comprises second connection lines; at least some of the first connection lines are electrically connected to the data signal wires by means of the second connection lines. The display panel and the display device using the display panel have the effects of reducing the processing costs and improving the display quality.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410876680.7, filed on July 01, 2024, entitled “Display panel and display device”, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a display panel and a display device. BACKGROUND

[0004] FIP (Fan-shaped Integrated in Display) technology can integrate the diagonal wires of the fan-shaped area in the display area, which can significantly reduce the lower frame space of the display panel, realize the extreme narrow frame of the product, and improve the visual experience, and has been widely applied in the design of display panels. In the prior art, the fan-shaped lines are wired by using 3 layers of source-drain metal layers, i.e., the third source-drain metal layer is used for the longitudinal fan-shaped lines, and the second source-drain metal layer is used for the transverse fan-shaped lines, but there are problems of low integration and high cost.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel and a display device applying the same. The display quality of the display panel and the display device applying the same is improved, and the processing cost thereof is reduced.

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising a substrate substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer which are sequentially stacked; wherein the display panel comprises circuit areas arranged in an array along a row direction and a column direction, and the circuit areas are provided with a pixel driving circuit for driving a sub-pixel;

[0008] The display panel is provided with a data signal wire corresponding to each circuit area column and extending along the column direction, and is also provided with a first connection line corresponding to at least part of the circuit area columns and extending along the column direction, wherein the circuit area columns comprise a plurality of circuit areas arranged in sequence along the column direction.

[0009] The first connection line comprises first sub-lines arranged alternately in sequence in the first source-drain metal layer and second sub-lines arranged in the second source-drain metal layer, and adjacent first sub-lines and second sub-lines are electrically connected through a via hole.

[0010] The display panel further comprises a second connection line extending along the row direction; at least part of the first connection line is electrically connected to the data signal trace through the second connection line.

[0011] According to an embodiment of the present disclosure, the first connection line comprises connection leads and initialization voltage auxiliary traces arranged alternately in sequence along the row direction.

[0012] The connection leads are electrically connected to the data signal trace through the second connection line.

[0013] The initialization voltage auxiliary traces are used to be electrically connected to initialization voltage traces located in the first source-drain metal layer or the transistor layer.

[0014] According to an embodiment of the present disclosure, the initialization voltage traces comprise a first initialization voltage trace used to load a first initialization voltage and extending along the row direction, a second initialization voltage trace used to load a second initialization voltage and extending along the row direction, and a third initialization voltage trace used to load a third initialization voltage and extending along the row direction.

[0015] The initialization voltage auxiliary traces comprise a first initialization voltage auxiliary trace used to be electrically connected to the first initialization voltage trace, a second initialization voltage auxiliary trace used to be electrically connected to the second initialization voltage trace, and a third initialization voltage auxiliary trace used to be electrically connected to the third initialization voltage trace.

[0016] According to an embodiment of the present disclosure, among the initialization voltage auxiliary traces arranged along the row direction, the first initialization voltage auxiliary trace, the second initialization voltage auxiliary trace, and the third initialization voltage auxiliary trace are arranged periodically in sequence.

[0017] According to an embodiment of the present disclosure, the second connection line is arranged in the first source-drain metal layer and extends along the row direction.

[0018] The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with a first initialization voltage trace used to load a first initialization voltage, and the first initialization voltage trace is used to reset a gate of a driving transistor of the pixel driving circuit.

[0019] The extension track of the second connection line is consistent with the extension track of the adjacent first initialization voltage trace.

[0020] According to an embodiment of the present disclosure, the first connection line is arranged between two adjacent circuit area columns.

[0021] According to an embodiment of the present disclosure, the pixel driving circuit has a storage capacitor.

[0022] The transistor layer comprises a first gate layer and a second gate layer arranged in sequence.

[0023] The storage capacitor comprises a first electrode plate located at the first gate layer and a second electrode plate located at the second gate layer.

[0024] The connection position of the first sub-line and the second sub-line on the substrate substrate has a projection that partially overlaps with the projection of the second electrode plate on the substrate substrate.

[0025] According to an embodiment of the present disclosure, the transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with a first initialization voltage trace for loading a first initialization voltage, and the first initialization voltage trace is used for resetting the gate of a driving transistor of the pixel driving circuit.

[0026] The first connection line comprises a first initialization voltage auxiliary trace connected with the first initialization voltage trace.

[0027] The first source-drain metal layer has a first initialization voltage switching structure, one end of the first initialization voltage switching structure is electrically connected with the first initialization voltage auxiliary trace, and the other end is connected with the first initialization voltage trace through a via hole.

[0028] According to an embodiment of the present disclosure, the pixel driving circuit has a storage capacitor.

[0029] The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the storage capacitor comprises a first electrode plate located at the first gate layer and a second electrode plate located at the second gate layer.

[0030] The first initialization voltage switching structure on the substrate substrate has a projection that partially overlaps with the projection of the second electrode plate on the substrate substrate.

[0031] According to an embodiment of the present disclosure, the first initialization voltage switching structure has a wiring space between the first initialization voltage trace and the first sub-line.

[0032] The pixel driving circuit has a data writing transistor.

[0033] The first source-drain metal layer is provided with a data signal switching structure in the wiring space, one end of the data signal switching structure is connected with the data signal wire, and the other end is electrically connected with the first electrode of the data writing transistor.

[0034] According to an embodiment of the present disclosure, the pixel driving circuit has a node control transistor;

[0035] The display panel is provided with a third initialization voltage wire for loading a third initialization voltage, the third initialization voltage wire is electrically connected with the first electrode of the node control transistor;

[0036] The first initialization voltage switching structure is arranged between the third initialization voltage wire and the second connection line.

[0037] According to an embodiment of the present disclosure, the transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with a second initialization voltage wire for loading a second initialization voltage, the second initialization voltage wire is used for resetting a driving transistor of the pixel driving circuit;

[0038] The first connection line comprises a second initialization voltage auxiliary wire connected with the second initialization voltage wire;

[0039] The display panel further comprises a power voltage wire corresponding to each circuit area; the second initialization voltage auxiliary wire is located between the data signal wire and the power voltage wire;

[0040] The first source-drain metal layer has a second initialization voltage switching structure, the second initialization voltage switching structure is located between the second initialization voltage auxiliary wire and the power voltage wire, one end of the second initialization voltage switching structure is electrically connected with the second initialization voltage auxiliary wire through a via, and the other end is electrically connected with the second initialization voltage wire through a via.

[0041] According to an embodiment of the present disclosure, the pixel driving circuit has a driving transistor, a data writing transistor and a node control transistor; the second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the node control transistor are electrically connected;

[0042] The display panel is provided with a third initialization voltage wire for loading a third initialization voltage, the third initialization voltage wire is electrically connected with the first electrode of the node control transistor;

[0043] The first connection line comprises a third initialization voltage auxiliary wire electrically connected with the third initialization voltage wire;

[0044] The pixel driving circuit has a node control transistor;

[0045] The first source-drain metal layer has a third initialization voltage switching structure, one end of the third initialization voltage switching structure is electrically connected with the end of the first sub-line of the third initialization voltage auxiliary wire, and the other end is electrically connected with the third initialization voltage wire.

[0046] According to an embodiment of the present disclosure, the second connection wire is arranged adjacent to the third initialization voltage wire;

[0047] The third initialization voltage switching structure is arranged on the side of the third initialization voltage wire away from the second connection wire.

[0048] One end of the second sub-line of the first connection wire overlaps the projection of the third initialization voltage wire on the substrate substrate, and the other end overlaps the projection of the second connection wire on the substrate substrate.

[0049] According to an embodiment of the present disclosure, the initialization voltage auxiliary wire further comprises a third sub-line located in the second source-drain metal layer, the third sub-line and the second sub-line are arranged alternately and connected to form an overall wire.

[0050] According to another aspect of the present disclosure, a display device is provided, comprising the display panel.

[0051] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0052] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0053] Figure 1 is a schematic diagram of the distribution and connection relationship of the first connection wire and the second connection wire in the display panel according to an embodiment of the present disclosure.

[0054] Figure 2 is a schematic diagram of the film layer structure of the display panel according to an embodiment of the present disclosure.

[0055] Figure 3 is a schematic diagram of the pixel driving circuit according to an embodiment of the present disclosure.

[0056] FIG. 4 is a schematic diagram of a structure of a low-temperature polysilicon semiconductor layer in an embodiment of the present disclosure.

[0057] FIG. 5 is a schematic diagram of a structure of a first gate layer in an embodiment of the present disclosure.

[0058] FIG. 6 is a schematic diagram of a structure of a second gate layer in an embodiment of the present disclosure.

[0059] FIG. 7 is a schematic diagram of a structure of a first source-drain metal layer in an embodiment of the present disclosure.

[0060] FIG. 8 is a schematic diagram of a structure of a first source-drain metal layer in an embodiment of the present disclosure.

[0061] FIG. 9 is a schematic diagram of a structure of a first source-drain metal layer in an embodiment of the present disclosure.

[0062] FIG. 10 is a schematic diagram of a structure of a first source-drain metal layer in an embodiment of the present disclosure.

[0063] FIG. 11 is a schematic diagram of a structure of a second source-drain metal layer in an embodiment of the present disclosure.

[0064] FIG. 12 is a schematic diagram of a structure of a second source-drain metal layer in an embodiment of the present disclosure.

[0065] FIG. 13 is a schematic diagram of a structure of a second gate layer, a first source-drain metal layer, and a second source-drain metal layer in an embodiment of the present disclosure.

[0066] FIG. 14 is a schematic diagram of a structure of a first source-drain metal layer in an embodiment of the present disclosure.

[0067] FIG. 15 is a schematic diagram of a structure of a second source-drain metal layer in an embodiment of the present disclosure.

[0068] FIG. 16 is a schematic diagram of a structure of a second source-drain metal layer in an embodiment of the present disclosure.

[0069] Legend: PA, circuit area; VTL, initialization voltage trace; VTL1, first initialization voltage trace; VTL2, second initialization voltage trace; VTL3, third initialization voltage trace; VTLX, initialization voltage auxiliary trace; VTL1X, first initialization voltage auxiliary trace; VTL2X, second initialization voltage auxiliary trace; VTL3X, third initialization voltage auxiliary trace; MA1, first bridge portion; MA2, second bridge portion; MA3, third bridge portion; MA4, fourth bridge portion; MA5, fifth bridge portion; MA6, sixth bridge portion; MA7, seventh bridge portion; MA8, eighth bridge portion; VT1P, first initialization voltage transfer structure; VT2P, second initialization voltage transfer structure; VT3P, third initialization voltage transfer structure; SBT, substrate; DRL, driving layer; TL, transistor layer; BSM, metal light shielding layer; PSCL, low temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; ILD, interlayer dielectric layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; PDL, pixel definition layer; COML, common electrode layer; EL, light-emitting functional layer; PEL, pixel electrode layer; PIXL, pixel layer; PIX, sub-pixel; TFE, thin film encapsulation layer; T1, first reset transistor; M1, first polysilicon conductive structure; M2, second polysilicon conductive structure; M3, third polysilicon conductive structure; T2, threshold compensation transistor; M4, fourth polysilicon conductive structure; M5, fifth polysilicon conductive structure; T3, driving transistor; T4, data write transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, electrode reset transistor; T8, node control transistor; CST, storage capacitor; CP1, first electrode plate; CP2, second electrode plate; Vinit, initialization voltage; Vinit1, first initialization voltage; Vinit2, second initialization voltage; Vinit3, third initialization voltage; RP, first reset signal; RH, second reset signal; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node; GN, first scan signal; Vdata, data voltage; GP, second scan signal; VDD, power voltage; VSS, reference voltage; EM, enable signal; T1A, channel region of first capacitor reset transistor; T2A, channel region of threshold compensation transistor; T3A, channel region of driving transistor; T4A, channel region of data write transistor; T5A, channel region of first light-emitting control transistor; T6A, channel region of second light-emitting control transistor; T7A, channel region of electrode reset transistor;T8A, a channel region of a node control transistor; HB1, a first upper via region; HB2, a second upper via region; HB3, a third upper via region; HB4, a fourth upper via region; HB5, a fifth upper via region; HB6, a sixth upper via region; HB7, a seventh upper via region; HB8, an eighth upper via region; HB9, a ninth upper via region; HB10, a tenth upper via region; HB11, an eleventh upper via region; HB12, a twelfth upper via region; HB13, a thirteenth upper via region; HB14, a fourteenth upper via region; HB15, a fifteenth upper via region; HB16, a sixteenth upper via region; HB17, a seventeenth upper via region; HB18, an eighteenth upper via region; HA1, a first lower via region; HA2, a second lower via region; HA3, a third lower via region; HA4, a fourth lower via region; HA5, a fifth lower via region; HA6, a sixth lower via region; HA7, a seventh lower via region; HA8, an eighth lower via region; HA9, a ninth lower via region; HA10, a tenth lower via region; HA11, an eleventh lower via region; HA12, a twelfth lower via region; HA13, a thirteenth lower via region; HA14, a fourteenth lower via region; HA15, a fifteenth lower via region; HA16, a sixteenth lower via region; HA17, a seventeenth lower via region; HA18, an eighteenth lower via region; RPL, a first capacitor reset control signal line; RHL, a second capacitor reset control signal line; EML, an enable signal line; GNL, a first scanning signal line; DH, a row direction; DV, a column direction; DL, a data signal line; LA, a first connection line; LA1, a first sub-line; LA2, a second sub-line; LB, a second connection line; LL, a connection lead; P1, a bulge. DETAILED DESCRIPTION

[0070] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be simplified or omitted. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0071] Although relative terms are used in this description, such as "upper," "lower," to describe one component's relationship to another component of the icon, these terms are used only for convenience, e.g., based on the example orientation of the figures. It is to be understood that if the icon's device were turned over, such that the upper component became the lower component, the described orientation would be reversed. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly on" the other structure or that the structure is "indirectly on" the other structure via another structure.

[0072] The terms "one," "a," "an," "the" and "at least one" are used to mean that "one or more" of something is present; the terms "includes," "including," and "has" are used to mean "comprising," meaning something is present, not excluding additional things from being added to the described thing; the term "first," "second," and "third," etc. are used only as labels, and do not imply a limitation as to the number or order of objects.

[0073] In the embodiment of the present disclosure, the thin film transistor includes an active layer, a gate insulating layer and a gate which are stacked. The active layer is located in a semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region respectively. The channel region maintains a semiconductor property, and the source and the drain are both conductive. In the embodiment of the present disclosure, the functions of the "source" and the "drain" are sometimes exchanged with each other, i.e., the "source" and the "drain" can be exchanged with each other, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, etc. In the embodiment of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor.

[0074] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure layer A can also be located at the same physical height as the structure layer B or below the physical height of the structure layer B, wherein the substrate is the height reference.

[0075] It should be noted that the "same layer" of the embodiment of the present application can refer to a film layer on the same structure layer, for example, the film layer on the same layer can be a film layer of a specific pattern formed by the same film forming process. Of course, the film layer of the specific pattern can also be at different heights or have different thicknesses.

[0076] In the related art, in order to reduce the lower frame space of the display panel, realize the extreme narrow edge of the product, and improve the visual experience, the FIP technology (the diagonal wires of the fan-shaped area are integrated in the display area, that is, the horizontal wires are connected with the corresponding data signal wires, the vertical wires are connected with the end of the horizontal wires away from the data signal wires, and then the vertical wires are led out at the lower frame of the display panel) is often used. In the prior art, the FIP technology generally adopts three source-drain metal layers for wiring, the horizontal wires are arranged in the second source-drain metal layer, and the vertical wires are arranged in the third source-drain metal layer. The inventors believe that this implementation has certain limitations, for example, it will increase the preparation cost of the display panel to some extent.

[0077] Therefore, in the embodiments of the present disclosure, referring to FIG. 1 and FIG. 2, a display panel is provided, which includes a substrate SBT, a transistor layer TL, a first source-drain metal layer SD1, a second source-drain metal layer SD2 and a pixel layer PIXL which are sequentially stacked; wherein the display panel includes circuit areas PA arranged in an array along a row direction DH and a column direction DV, and the circuit areas PA are provided with pixel driving circuits for driving sub-pixels; the display panel is provided with data signal wires DL corresponding to each circuit area column VPA one by one and extending along the column direction DV, and is also provided with first connection lines LA corresponding to at least part of the circuit area columns VPA one by one and extending along the column direction DV, wherein the circuit area column VPA includes a plurality of circuit areas PA arranged in sequence along the column direction DV; the first connection line LA includes first sub-lines LA1 of the first source-drain metal layer SD1 and second sub-lines LA2 arranged in the second source-drain metal layer SD2 which are alternately arranged in sequence, and adjacent first sub-lines LA1 and second sub-lines LA2 are electrically connected through vias; the display panel further includes second connection lines LB extending along the row direction DH; wherein at least part of the first connection lines LA are electrically connected with the data signal wires DL through the second connection lines LB.

[0078] In the embodiments of the present disclosure, part of the first connection lines LA are connected with the data signal wires DL through the second connection lines LB, so as to realize the purpose of accumulating the connection lines for electrically connecting the display panel and the driving chip in the lower frame of the display panel, and further realize the reasonable layout of the connection lines for electrically connecting between the display panel and the driving chip, which helps to reduce the space of the lower frame of the display panel and better realize the narrow frame of the display panel; meanwhile, the first sub-lines LA1 of the first connection lines LA are arranged in the first source-drain metal layer SD1, the second sub-lines LA2 of the first connection lines LA are arranged in the second source-drain metal layer SD2, and the first sub-lines LA1 and the second sub-lines LA2 are connected through vias, which can reduce the preparation of one layer of source-drain metal layer compared with the prior art, and further can reduce the processing cost of the display panel.

[0079] In some embodiments of the present disclosure, referring to FIGS. 2, 3, 5 and 6, the pixel driving circuit has a storage capacitor CST; the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 which are sequentially stacked; the storage capacitor CST includes a first electrode plate CP1 located at the first gate layer GT1 and a second electrode plate CP2 located at the second gate layer GT2; and the connection position of the first sub-line LA1 and the second sub-line LA2 on the substrate SBT has a projection which partially overlaps with the projection of the second electrode plate CP2 on the substrate SBT (see FIG. 13).

[0080] The basic principle of the pixel driving circuit is described as follows in combination with the equivalent circuit diagram of the pixel driving circuit:

[0081] FIG. 3 illustrates an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure. It can be understood that the pixel driving circuit in the embodiment of the present disclosure can also be a pixel driving circuit of other structures. When the structure of the pixel driving circuit is changed, the structure of each film layer in the embodiment of the present disclosure can also be adjusted adaptively.

[0082] In the embodiment of the present disclosure, the pixel driving circuit can also be 8T1C (8 transistors and 1 storage capacitor), 9T1C (9 transistors and 1 storage capacitor), 10T1C (10 transistors and 1 storage capacitor), etc., which are not specifically limited in the present embodiment.

[0083] Referring to FIGS. 3, 5, 6, 7, 8, 9 and 10, in some embodiments of the present disclosure, the pixel driving circuit includes a first initialization voltage walk VL1 loading a first initialization voltage Vinit1, a second initialization voltage walk VL2 loading a second initialization voltage Vinit2, a third initialization voltage walk VL3 loading a third initialization voltage Vinit3, a first capacitor reset control signal line RPL loading a first reset signal RP, a first scan signal walk GNL loading a first scan signal GN, an enable signal line EML loading an enable signal EM, a second capacitor reset control signal line RHL loading a second reset signal RH, a power voltage walk VDDL loading a power voltage VDD, a data signal walk DL loading a data voltage VData, a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, an electrode reset transistor T7, a node control transistor T8 and a storage capacitor CST. The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, a fourth node N4 and a fifth node N5.

[0084] In some embodiments of the present disclosure, the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the electrode reset transistor T7, and the node control transistor T8 can all be P-type transistors.

[0085] The first electrode of the first reset transistor T1 is electrically connected to a first initialization voltage wire VL1 carrying a first initialization voltage Vinit1, the gate electrode of the first reset transistor T1 is connected to a first capacitor reset control signal line RPL carrying a first reset signal RP, and the second electrode of the first reset transistor T1 is connected to the first node N1. The first reset transistor T1 is configured to load the first initialization voltage Vinit1 to the first node N1 in response to the first reset signal RP.

[0086] The first electrode of the threshold compensation transistor T2 is electrically connected to the third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and the gate electrode of the threshold compensation transistor T2 is connected to a first scan signal wire GNL carrying a first scan signal GN. The threshold compensation transistor T2 is configured to be turned on in response to the first scan signal GN.

[0087] The first electrode of the driving transistor T3 is connected to the second node N2, the second electrode of the driving transistor T3 is connected to the third node N3, and the gate electrode of the driving transistor T3 is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage at the first node N1.

[0088] The first electrode of the data writing transistor T4 is electrically connected to a data signal wire DL carrying a data voltage VData, the second electrode of the data writing transistor T4 is electrically connected to the second node N2, and the gate electrode of the data writing transistor T4 is connected to the first scan signal wire GNL carrying the first scan signal GN. The data writing transistor T4 is configured to load the data voltage VData to the second node N2 in response to the first scan signal GN.

[0089] The first electrode of the first light-emitting control transistor T5 is electrically connected to the fifth node N5, the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2, and the gate electrode of the first light-emitting control transistor T5 is connected to an enable signal line EML carrying an enable signal EM.

[0090] It should be noted that in some embodiments, the enable signal EM loaded at the gate of the first light-emitting control transistor T5 and the enable signal EM loaded at the gate of the second light-emitting control transistor T6 can be set to open at different times, that is, the enable signal EM loaded at the gate of the first light-emitting control transistor T5 can be opened first, and then the enable signal EM loaded at the gate of the second light-emitting control transistor T6 can be opened; or, the enable signal EM loaded at the gate of the second light-emitting control transistor T6 can be opened first, and then the enable signal EM loaded at the gate of the first light-emitting control transistor T5 can be opened.

[0091] The first electrode of the second light-emitting control transistor T6 is connected with the third node N3, the second electrode of the second light-emitting control transistor T6 is connected with the fourth node N4, and the gate of the second light-emitting control transistor T6 is connected with the enable signal line EML loaded with the enable signal EM. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to be turned on in response to the enable signal EM.

[0092] The first electrode of the electrode reset transistor T7 is connected with the second initialization voltage wire VL2 loaded with the second initialization voltage Vinit2, the gate of the electrode reset transistor T7 is connected with the second capacitor reset control signal line RHL loaded with the second reset signal RH, and the second electrode of the electrode reset transistor T7 is connected with the fourth node N4. The electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second reset signal RH.

[0093] The first electrode of the node control transistor T8 is connected with the third initialization voltage wire VL3 loaded with the third initialization voltage Vinit3, the gate of the node control transistor T8 is connected with the second capacitor reset control signal line RHL loaded with the second reset signal RH, and the second electrode of the node control transistor T8 is connected with the second node N2. The node control transistor T8 is used to load the third initialization voltage Vinit3 to the second node N2 in response to the second reset signal RH.

[0094] As an example, in some embodiments, the second reset signal RH loaded at the gate of the electrode reset transistor T7 and the second reset signal RH loaded at the gate of the node control transistor can be set as the same gate signal line; of course, the second reset signal RH loaded at the gate of the electrode reset transistor T7 and the second reset signal RH loaded at the gate of the node control transistor can also be set as different gate signal lines.

[0095] The pixel electrode PE of the light-emitting element is electrically connected with the pixel driving circuit (not specifically shown in the drawings of the present application), and the common electrode is used to load the reference voltage VSS.

[0096] One end of the storage capacitor CST is connected with the first node N1, and the other end is electrically connected with the power voltage wire VDDL.

[0097] The display panel in the embodiments of the present disclosure will be described in detail below in combination with the structure of each film layer in the display panel:

[0098] FIG. 2 is a schematic diagram illustrating the film layer structure of a display panel in some embodiments of the present disclosure. Referring to FIG. 2, in some embodiments of the present disclosure, the display panel includes a driving layer DRL and a pixel layer PIXL which are sequentially stacked on the substrate SBT.

[0099] Optionally, the substrate SBT can be a substrate SBT of inorganic material, a substrate SBT of organic material, or a composite substrate formed by stacking a substrate SBT of inorganic material and a substrate SBT of organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, sapphire glass, etc.

[0100] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0101] Optionally, referring to FIG. 2, in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor CST (not shown in the drawings). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0102] It can be understood that the types of any two transistors among the transistors in the pixel driving circuit can be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in a pixel driving circuit, the active layer of some transistors can be made of low-temperature polysilicon semiconductor material and the active layer of some transistors can be made of metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors and some thin film transistors are metal oxide transistors.

[0103] Optionally, referring to FIG. 2, the driving layer DRL can include a buffer layer (for example, the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG. 2) stacked on the substrate SBT, a metal light shielding layer BSM arranged between the first buffer layer Buff1 and the substrate SBT, a semiconductor layer (for example, a low-temperature polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL) in the pixel layer PIXL, a gate insulating layer (for example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 shown in FIG. 2), a gate layer (for example, the first gate layer GT1 and the second gate layer GT2 shown in FIG. 2), an interlayer dielectric layer ILD, a source-drain metal layer (for example, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 shown in FIG. 2), a planarization layer (for example, the first planarization layer PLN1 and the second planarization layer PLN2 shown in FIG. 2), and the like. Each thin film transistor and the storage capacitor CST (not specifically labeled in the drawings of the present disclosure) can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer, and the like. Of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode, and the channel region of the transistor), and can also be used to form part of the wiring or the conductive structure by being conductive if necessary. The first source-drain metal layer SD1 can be used to form the scanning signal wiring. The gate layer can be used to form one or more of the reset control wiring, the light-emitting control wiring, and the like, can be used to form the gate electrode of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor CST. The source-drain metal layer can be used to form the data signal wiring, the driving power voltage wiring, and the like, and can also be used to form part of the electrode plate of the storage capacitor CST.

[0104] Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a metal light shielding layer BSM between the semiconductor layer and the substrate SBT, etc. Any one of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, etc. film layer can also be multi-layered as needed, for example, the driving layer DRL can include two different semiconductor layers, or include two or three source-drain metal layers, or include two or three gate layers; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or a new insulating film layer can be added as needed.

[0105] Optionally, the pixel layer PIXL can include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EL), and further define the light-emitting area and light-emitting area of the sub-pixel. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The part of the light-emitting functional layer EL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element as a sub-pixel. Among them, one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0106] In this example, the display panel is an OLED (Organic Light Emitting Diode) display panel. The light-emitting functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0107] It can be understood that the display panel can also be other types of display panels, for example, it can also be a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0108] Referring to FIG. 2, the display panel can further include a thin film encapsulation layer TFE, which can be disposed on a surface of the pixel layer PIXL away from the substrate base plate SBT, and can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layers can effectively block moisture and oxygen from the outside, so as to avoid water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layers can be located in the peripheral area. The organic encapsulation layers are located between two adjacent inorganic encapsulation layers, so as to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edges of the organic encapsulation layers can be located between the edges of the display area and the edges of the inorganic encapsulation layers.

[0109] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer (not specifically shown in the drawings) stacked in sequence on a side of the pixel layer PIXL away from the substrate base plate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier wall; the organic encapsulation layer covers the display area and extends to the inside of the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress on the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer, so as to isolate the organic encapsulation layer from water and oxygen. Of course, in other embodiments of the present disclosure, the display panel can also not be provided with the thin film encapsulation layer TFE, but other ways can be used to encapsulate and protect the pixel layer.

[0110] In some embodiments of the present disclosure, the display panel can further include a touch metal layer (not specifically shown in the drawings), which can be disposed on a side of the thin film transistor away from the pixel layer PIXL, so that the display panel has a touch function.

[0111] In this embodiment, referring to FIG. 2, the driving layer DRL can further include a transistor layer TL, a first source-drain metal layer SD1 and a second source-drain metal layer SD2; the transistor layer TL is a combination of various film layers disposed between the substrate base plate SBT and the first source-drain metal layer SD1, and can form various thin film transistors required by the pixel driving circuit.

[0112] In some embodiments of the present disclosure, the first connection line LA comprises connection leads LL and initialization voltage auxiliary traces VTLX arranged alternately in sequence along the row direction DH; wherein the connection leads LL are electrically connected to the data signal traces DL through the second connection line LB. The initialization voltage auxiliary traces VTLX are used to be electrically connected to the initialization voltage traces VTL in the first source-drain metal layer SD1 or the transistor layer TL. In this way, in some circuit areas PA, the connection leads LL are connected to the data signal traces DL through the second connection line LB, so as to realize the purpose of gathering the electrical connection lines of the driving chip in the lower frame of the display panel, which helps to realize the narrow frame of the display panel and improve the visual experience of the display panel; in other circuit areas PA, the initialization voltage auxiliary traces VTLX are electrically connected to the corresponding initialization voltage traces VTL, which helps to realize the meshing of the initialization voltage and improve the display uniformity of the display panel.

[0113] In some embodiments of the present disclosure, the first connection line LA is arranged between two adjacent circuit area columns VPA.

[0114] In some embodiments, the initialization voltage traces VTL comprise a first initialization voltage trace VTL1 for loading a first initialization voltage Vinit1 and extending along the row direction DH, a second initialization voltage trace VTL2 for loading a second initialization voltage Vinit2 and extending along the row direction DH, and a third initialization voltage trace VTL3 for loading a third initialization voltage Vinit3 and extending along the row direction DH; and the initialization voltage auxiliary traces VLX comprise a first initialization voltage auxiliary trace VL1X for being electrically connected to the first initialization voltage trace VTL1, a second initialization voltage auxiliary trace VL2X for being electrically connected to the second initialization voltage trace VTL2, and a third initialization voltage auxiliary trace VL3X for being electrically connected to the third initialization voltage trace VTL3. In this way, the first initialization voltage Vinit1 loaded on the first initialization voltage trace VTL1 can be loaded on the first initialization voltage auxiliary trace VL1X, so as to realize the meshing of the first initialization voltage Vinit1 and improve the display uniformity of the display panel; the second initialization voltage Vinit2 loaded on the second initialization voltage trace VTL2 can be loaded on the second initialization voltage auxiliary trace VL2X, so as to realize the meshing of the second initialization voltage Vinit2 and improve the display uniformity of the display panel; and the third initialization voltage Vinit3 loaded on the third initialization voltage trace VTL3 can be loaded on the third initialization voltage auxiliary trace VL3X, so as to realize the meshing of the third initialization voltage Vinit3 and improve the display uniformity of the display panel.

[0115] In some embodiments of the present disclosure, among the initialization voltage auxiliary wires VLX arranged in the row direction DH, the first initialization voltage auxiliary wire VL1X, the second initialization voltage auxiliary wire VL2X and the third initialization voltage auxiliary wire VL3X are arranged periodically in sequence. In this way, uniform distribution of the initialization voltage auxiliary wires VLX in the display panel is achieved, and the display uniformity of the display panel can be further improved (see FIG. 13).

[0116] It can be understood that, in some embodiments, among the initialization voltage auxiliary wires VLX arranged in the row direction DH, the first initialization voltage auxiliary wire VL1X, the third initialization voltage auxiliary wire VL3X and the second initialization voltage auxiliary wire VL2X can be arranged periodically in sequence; or, among the initialization voltage auxiliary wires VLX arranged in the row direction DH, the first initialization voltage auxiliary wire VL1X, the third initialization voltage auxiliary wire VL3X and the second initialization voltage auxiliary wire VL2X can be arranged periodically in sequence, and the like. The present disclosure does not make specific limitations on this in the embodiments.

[0117] In some embodiments of the present disclosure, the second connection line LB is arranged on the first source-drain metal layer and extends in the row direction DH; the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 arranged in sequence; the second gate layer GT2 is provided with a first initialization voltage wire VTL1 for loading a first initialization voltage Vinit1, and the first initialization voltage wire VTL1 is used for resetting the gate of the driving transistor T3 of the pixel driving circuit; the extension track of the second connection line LB is consistent with the extension track of the adjacent first initialization voltage wire VTL1.

[0118] As an example, the second connection line LB has an overlapping area with the first initialization voltage wire VTL1 on the substrate SBT in the orthographic projection, so that the longitudinal length of the pixel driving circuit can be compressed, and the possibility of improving the pixel density of the display panel is provided.

[0119] The driving layer DRL will be described in detail in combination with the positions of the transistors in the above 8T1C pixel driving circuit and the step-by-step conditions of the signal wires:

[0120] FIG. 4 illustrates a schematic diagram of a low-temperature polysilicon semiconductor layer PSCL in an embodiment of the present disclosure. Referring to FIG. 4, the active layers of the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the electrode reset transistor T7, and the node control transistor T8 are located on the low-temperature polysilicon semiconductor layer PSCL. The channel region of the data writing transistor T4A and the channel region of the node control transistor T8A are arranged along the column direction DV. The channel region of the first light-emitting control transistor T5A and the channel region of the second light-emitting control transistor T6A are arranged along the row direction DH. Along the row direction DH, the channel region of the driving transistor T3A is located between the channel region of the threshold compensation transistor T2A and the channel region of the data writing transistor T4A. The channel region of the driving transistor T3A is located between the channel region of the first light-emitting control transistor T5A and the channel region of the second light-emitting control transistor T6A. Along the column direction DV, the channel region of the electrode reset transistor T7A and the channel region of the driving transistor T3A are located on both sides of the channel region of the first light-emitting control transistor T5A.

[0121] The low-temperature polysilicon semiconductor layer PSCL is provided with a twelfth lower via region HA12, a second lower via region HA2, a fifth lower via region HA5, a fourteenth lower via region HA14, a seventh lower via region HA7, a third lower via region HA3, an eleventh lower via region HA11, a fourth lower via region HA4, and a ninth lower via region HA9. The twelfth lower via region HA12 is located at the first electrode of the first reset transistor T1. The second lower via region HA2 is located at the second electrode of the threshold compensation transistor T2. The fifth lower via region HA5 is located at the second electrode of the second light-emitting control transistor. The fourteenth lower via region HA14 is located at the first electrode of the electrode reset transistor T7. The seventh lower via region HA7 is located at the second electrode of the first light-emitting control transistor T5. The third lower via region HA3 is located at the first electrode of the first light-emitting control transistor T5. The eleventh lower via region HA11 is located at the first electrode of the data writing transistor T4. The fourth lower via region HA4 is located at the second electrode of the node control transistor T8. The ninth lower via region HA9 is located at the first electrode of the node control transistor T8.

[0122] In some embodiments of the present disclosure, the first reset transistor T1 includes a first polysilicon conductive structure M1, a second polysilicon conductive structure M2, and a third polysilicon conductive structure M3. The first polysilicon conductive structure M1 and the third polysilicon conductive structure M3 are arranged side by side along the column direction DV. The second polysilicon conductive structure M2 is arranged along the row direction DH, and the first polysilicon conductive structure M1 and the third polysilicon conductive structure M3 are electrically connected to each other on the side away from the driving transistor T3.

[0123] As an example, the first reset transistor T1 can be a double-gate structure.

[0124] In some embodiments of the present disclosure, the pixel driving circuit includes a threshold compensation transistor T2 and a driving transistor T3; a first electrode of the threshold compensation transistor T2 is connected with a second electrode of the driving transistor T3; a second electrode of the threshold compensation transistor T2 is electrically connected with a gate electrode of the driving transistor T3; a channel region of the threshold compensation transistor T2 is located in the low-temperature polysilicon semiconductor layer PSCL; the threshold compensation transistor T2 includes a fourth polysilicon conductive structure M4 arranged along the row direction DH and a fifth polysilicon conductive structure M5 arranged along the column direction DV; the fourth polysilicon conductive structure M4 is electrically connected with the first polysilicon conductive structure M1 on a side close to the driving transistor T3; and the fifth polysilicon conductive structure M5 is electrically connected on a side away from the first polysilicon conductive structure M1.

[0125] As an example, the threshold compensation transistor T2 can be a double-gate structure.

[0126] Figure 5 illustrates a schematic diagram of the first gate layer GT1 in the embodiments of the present disclosure. Referring to Figure 5, the first gate layer GT1 is provided with an enable signal line EML, a first capacitor reset control signal line RPL, a second capacitor reset control signal line RHL, a first scan signal line GNL, and a first electrode plate CP1 of a storage capacitor CST. The first capacitor reset control signal line RPL extends along the row direction DH and is used to load a first reset signal RP to the first reset transistor T1. The second capacitor reset control signal line RHL extends along the row direction DH and is used to load a second reset signal RH to the node control transistor T8. The enable signal line EML extends along the row direction DH and sequentially overlaps the channel region T5A of the first light-emitting control transistor and the channel region T6A of the second light-emitting control transistor, so as to multiplex the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The enable signal line EML is used to load an enable signal EM to the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The first electrode plate CP1 of the storage capacitor CST overlaps the channel region T3A of the driving transistor, so as to multiplex the gate of the driving transistor T3. The first scan signal line GNL extends along the row direction DH and can overlap the channel region T4A of the data writing transistor, so as to multiplex the gate of the data writing transistor T4. The first scan signal line GNL is used to load a first scan signal GN to the data writing transistor T4. Meanwhile, the first scan signal line GNL can overlap the channel region T2A of the threshold compensation transistor, so as to multiplex the gate of the channel region T2A of the threshold compensation transistor and load a first scan signal GN to the threshold compensation transistor. The second capacitor reset control signal line RHL extends along the row direction DH to multiplex the gates of the electrode reset transistor T7 and the node control transistor T8. The second capacitor reset control signal line RHL is used to load a second reset signal RH to the electrode reset transistor T7 and the node control transistor T8. The first electrode plate CP1 of the storage capacitor CST has a first lower via region HA1.

[0127] Figure 6 illustrates a schematic diagram of the second gate layer GT2 in the embodiments of the present disclosure. Referring to Figure 6, the second gate layer GT2 is provided with a first initialization voltage line VTL1, a second initialization voltage line VTL2, and a second electrode plate CP2 of a storage capacitor CST, which extend along the row direction DH. The second initialization voltage line VTL2 has a thirteenth lower via region HA13. The second electrode plate CP2 of the storage capacitor CST has an eighth lower via region HA8. The first initialization voltage line VTL1 has a fifteenth lower via region HA15.

[0128] In some embodiments of the present disclosure, the second initialization voltage line VTL2 has a bulge P1. The projection of the bulge P1 on the substrate SBT overlaps the projection of the active layer of the first reset transistor T1 on the substrate SBT.

[0129] FIG. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. 14 illustrate schematic diagrams of the first source-drain metal layer SD1 in the embodiments of the present disclosure; wherein FIG. 7 is a schematic diagram of the structure of the first source-drain metal layer when the first connection line LA is a connection lead LL in one circuit area PA; FIG. 8 is a schematic diagram of the first source-drain metal layer when the first connection line LA is a first initialization voltage auxiliary trace VTL1X in one circuit area PA; FIG. 9 is a schematic diagram of the first source-drain metal layer when the first connection line LA is a second initialization voltage auxiliary trace VTL2X in one circuit area PA; FIG. 10 is a schematic diagram of the first source-drain metal layer when the first connection line LA is a third initialization voltage auxiliary trace VTL3X in one circuit area PA.

[0130] The first source-drain metal layer SD1 has a first bridge MA1, a second bridge MA2, a third bridge MA3, a fourth bridge MA4, a fifth bridge MA5, a sixth bridge MA6, a seventh bridge MA7, an eighth bridge MA8, and the first source-drain metal layer SD1 further includes a first initialization voltage switching structure VT1P (see FIG. 8), a second initialization voltage switching structure VT2P (see FIG. 9), a third initialization voltage switching structure VT3P (see FIG. 10), and a third initialization voltage trace VTL3.

[0131] The first bridge MA1 is provided with a first upper via region HB1 and a second upper via region HB2, wherein the first upper via region HB1 overlaps the first lower via region HA1 and is connected by a via; the second upper via region HB2 overlaps the second lower via region HA2 and is connected by a via; in this way, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the driving transistor T3 through the first bridge MA1.

[0132] The second bridge MA2 is provided with a third upper via region HB3 and a fourth upper via region HB4, wherein the third upper via region HB3 overlaps the third lower via region HA3 and is connected by a via; and the fourth upper via region HB4 overlaps the fourth lower via region HA4 and is connected by a via; in this way, the second electrode of the first light-emitting control transistor T5 is electrically connected to the second electrode of the node control transistor T8 through the second bridge MA2.

[0133] The third bridge MA3 is provided with a fifth upper via region HB5 and a sixth upper via region HB6, wherein the fifth upper via region HB5 overlaps the fifth lower via region HA5 and is connected by a via; in this way, the signal of the second source-drain metal layer SD2 can be loaded to the second electrode of the second light-emitting control transistor T6 through the third bridge MA3.

[0134] The fourth bridge MA4 is provided with an eighth upper via hole area HB8, a seventh lower via hole area HA7 and a sixteenth lower via hole area HA16; wherein the seventh upper via hole area HB7 overlaps with the seventh lower via hole area HA7 and is connected through a via hole; the eighth upper via hole area HB8 overlaps with the eighth lower via hole area HA8 and is connected through a via hole; in this way, the power supply voltage VDD on the second source-drain metal layer SD2 can be loaded to the first electrode of the first light-emitting control transistor and the second electrode plate CP2 of the storage capacitor CST through the fourth bridge.

[0135] The fifth bridge MA5 is provided with a tenth lower via hole area HA10 and an eleventh upper via hole area HB11; wherein the eleventh upper via hole area HB11 overlaps with the tenth lower via hole area HA11 and is connected through a via hole; in this way, the data signal loaded by the data signal wire DL can be loaded to the first electrode of the data write transistor T4 through the fifth bridge MA5.

[0136] The sixth bridge MA6 is provided with a twelfth upper via hole area HB12 and a thirteenth upper via hole area HB13; wherein the twelfth upper via hole area HB12 overlaps with the twelfth lower via hole area HA12 and is connected through a via hole; the thirteenth upper via hole area HB13 overlaps with the thirteenth lower via hole area HA13 and is connected through a via hole; in this way, the first initialization voltage Vinit1 loaded on the first initialization voltage wire VTL1 can be loaded to the first electrode of the first reset transistor T1 through the sixth bridge MA6.

[0137] In some embodiments of the present disclosure, the transistor layer TL comprises a first gate layer GT1 and a second gate layer GT2 arranged in sequence; the second gate layer GT2 is provided with a first initialization voltage wire VTL1 for loading a first initialization voltage Vinit1, the first initialization voltage wire VTL1 being used for resetting the gate of the driving transistor T3 of the pixel driving circuit; the first connection line LA comprises a first initialization voltage auxiliary wire VTL1X connected with the first initialization voltage wire VTL1; the first source-drain metal layer SD1 has a first initialization voltage transfer structure VT1P (see FIG. 8), one end of the first initialization voltage transfer structure VT1P being electrically connected with the first initialization voltage auxiliary wire VTL1X, and the other end being connected with the first initialization voltage wire VTL1 through a via hole; the first initialization voltage transfer structure VT1P is overlapped with the second electrode plate CP2 in the orthographic projection of the substrate SBT. In this way, the first initialization voltage Vinit1 loaded by the first initialization voltage wire VTL1 is loaded to the first initialization voltage auxiliary wire VTL1X through the first initialization voltage transfer structure VT1P, and the gridization of the first initialization voltage Vinit1 is realized in sequence, which helps to improve the display uniformity of the display panel.

[0138] In the embodiment, the first initialization voltage switching structure VT1P has a wiring space between the first initialization voltage wire VTL1 and the first sub-line LA1; the pixel driving circuit has a data writing transistor T4; the first source-drain metal layer SD1 is provided with a data signal switching structure DP (a fifth bridge MA5) in the wiring space, one end of the data signal switching structure DP is connected with the data signal wire DL, and the other end is electrically connected with the first electrode of the data writing transistor T4.

[0139] As an example, the first initialization voltage switching structure VT1P is arranged between the third initialization voltage wire VTL3 and the second connection line LB. The first initialization voltage switching structure VT1P can include a vertical segment L1, an inclined segment L2, and a horizontal segment L3.

[0140] The one end of the vertical segment L1 is electrically connected with the sixth bridge MA6, the inclined segment L2 is electrically connected with the one end of the vertical segment L1 away from the sixth bridge MA6, the one end of the horizontal segment L3 is electrically connected with the inclined segment L2 away from the vertical segment L1, and the other end of the horizontal segment L3 is electrically connected with the first sub-line LA1. It should be noted that in the embodiment of the present disclosure, the horizontal segment L3 can be electrically connected with the middle part of the first sub-line LA1, of course, in some embodiments, the horizontal segment L3 can also be electrically connected with the end part of the first sub-line LA1.

[0141] In some embodiments of the present disclosure, the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 arranged in sequence; the second gate layer GT2 is provided with a second initialization voltage wire VTL2 for loading a second initialization voltage Vinit2, and the second initialization voltage wire VTL2 is used for resetting the gate of a driving transistor T3 of the pixel driving circuit; the first connection line LA includes a second initialization voltage auxiliary wire VTL2X connected with the second initialization voltage wire VTL2; the display panel further includes a power voltage wire VDDL arranged corresponding to each circuit area; the second initialization voltage auxiliary wire VTL2X is located between the data signal wire DL and the power voltage wire VDDL; the first source-drain metal layer SD1 has a second initialization voltage switching structure VT2P, the second initialization voltage switching structure VT2P is located between the second initialization voltage auxiliary wire VTL2X and the power voltage wire VDDL, one end of the second initialization voltage switching structure VT2P is electrically connected with the second initialization voltage auxiliary wire VTL2X through a via, and the other end is electrically connected with the second initialization voltage wire VTL2 through a via.

[0142] The seventh bridge MA7 (the second initialization voltage transfer structure VT2P) is provided with a fifteenth upper via hole region HB15 and a fourteenth lower via hole region HA14 (see FIG. 9); wherein the fifteenth upper via hole region HB15 is overlapped with the fifteenth lower via hole region and connected through a via hole. In this way, the second initialization voltage Vinit2 loaded on the second initialization voltage trace VTL2 is loaded to the corresponding trace located at the second source-drain metal layer SD2 through the seventh bridge MA7, and the gridization of the second initialization voltage Vinit2 is realized in sequence, which helps to improve the display uniformity of the display panel.

[0143] In the embodiments of the present disclosure, in the corresponding circuit region PA, the seventh bridge MA7 (the second initialization voltage transfer structure VT2P) can be arranged at the corresponding position even if the gridization of the second initialization voltage Vinit2 is not arranged, so as to further improve the display uniformity of the display panel.

[0144] In some other embodiments of the present disclosure, in the corresponding circuit region PA, if the gridization of the second initialization voltage Vinit2 is not arranged, the second initialization voltage transfer structure VT2P can not be arranged in the corresponding circuit region PA.

[0145] The eighth bridge MA8 (the first sub-line LA1) is provided with a seventeenth lower via hole region HA17 and an eighteenth lower via hole region HA18, so that the gridization of the first initialization voltage Vinit1, the gridization of the second initialization voltage Vinit2 and the gridization of the third initialization voltage Vinit3 in part of the circuit region can be realized through the eighth bridge MA8 (the first sub-line LA1), and the electrical connection between the first connection line LA located at the first source-drain metal layer SD1 and the second connection line LB located at the second source-drain metal layer SD2 can be realized, so that compared with the prior art, one layer of source-drain metal layer can be reduced, and the cost of the display panel can be reduced.

[0146] The third initialization voltage trace VTL3 has a ninth upper via hole region HB9, wherein the ninth upper via hole region HB9 is overlapped with the ninth lower via hole region HA9 and connected through a via hole. In this way, the third initialization voltage Vinit3 can be loaded to the first electrode of the node control transistor T8.

[0147] As an example, the second initialization voltage transfer structure VT2P is arranged on the side of the second connection line LB away from the third initialization voltage trace VTL3.

[0148] In some embodiments of the present disclosure, the pixel driving circuit has a driving transistor T3, a data writing transistor T4, and a node control transistor T8; the second electrode of the data writing transistor T4, the first electrode of the driving transistor T3, and the second electrode of the node control transistor T8 are electrically connected; the display panel is provided with a third initialization voltage wire VTL3 for loading a third initialization voltage Vinit3, and the third initialization voltage wire VTL3 is electrically connected with the first electrode of the node control transistor T8; the first connection line LA includes a third initialization voltage auxiliary wire VTL3X electrically connected with the third initialization voltage wire VTL3; the first source-drain metal layer SD1 has a third initialization voltage transfer structure VT3P (see FIG. 10), one end of the third initialization voltage transfer structure VT3P is electrically connected with the end of the first sub-line LA1 of the third initialization voltage auxiliary wire VTL3X, and the other end is electrically connected with the third initialization voltage wire VTL3. In this way, the third initialization voltage Vinit3 loaded on the third initialization voltage wire VTL3 can be loaded on the third initialization voltage auxiliary wire VTL3X through the third initialization voltage transfer structure VT3P to realize the gridding of the third initialization voltage Vinit3, thereby improving the display uniformity of the display panel.

[0149] In this embodiment, the second connection line LB is arranged adjacent to the third initialization voltage wire VTL3; the third initialization voltage transfer structure VT3P is arranged on the side of the third initialization voltage wire VTL3 away from the second connection line LB; one end of the second sub-line LA2 of the first connection line LA is in the orthographic projection of the substrate SBT and overlaps the orthographic projection of the third initialization voltage wire VTL3 on the substrate SBT, and the other end of the first connection line LA is in the orthographic projection of the substrate SBT and overlaps the orthographic projection of the second connection line LB on the substrate SBT.

[0150] In some embodiments of the present disclosure, the third initialization voltage transfer structure VT3P can include a straight section L4, one end of the straight section L4 is electrically connected with the end of the second sub-line LA2, and the other end of the straight section L4 is electrically connected with the third initialization voltage wire VTL3, so as to realize the electrical connection between the third initialization voltage wire VTL3 and the first sub-line LA1.

[0151] In the embodiments of the present disclosure, the electrical connection between the straight section L4 and the end of the first sub-line LA1 can reduce the overlapping phenomenon between the straight section L4 and the first sub-line LA1 while realizing the electrical connection between the straight section L4 and the first sub-line LA1, so as to reduce the material loss in the preparation to a certain extent.

[0152] FIG. 11, FIG. 12 and FIG. 15 illustrate the schematic diagram of the second source-drain metal layer SD2 in the embodiments of the present disclosure. FIG. 11 is a schematic diagram of the second source-drain metal layer SD2 corresponding to one circuit region PA when the first connection line LA is the connection lead LL or the first initialization voltage auxiliary trace VTL1X or the third initialization voltage auxiliary trace VTL3X in the circuit region PA; FIG. 12 is a schematic diagram of the second source-drain metal layer SD2 corresponding to one circuit region PA when the first connection line LA is the second initialization voltage auxiliary trace VTL2X in the circuit region PA.

[0153] The second source-drain metal layer SD2 has the first conductive part MB1, the second conductive part MB2, the power voltage trace VDDL, the data signal trace DL, the first connection line LA, the first initialization voltage auxiliary trace VTL1X, the second initialization voltage auxiliary trace VTL2X, and the third initialization voltage auxiliary trace VTL3X.

[0154] The first conductive part MB1 has a sixth upper via region HB6, wherein the sixth upper via region HB6 overlaps with the sixth lower via region HA6 and is connected by a via, so as to achieve the purpose of loading the signal to the third bridge part MA3 through the first conductive part MB1. In some embodiments, in the adjacent circuit region PA, the area of the first conductive part MB1 can be adjusted to adapt to different sub-pixels due to the different areas occupied by different sub-pixels. Therefore, the size of the first conductive part MB1 in the adjacent circuit region PA can be different.

[0155] The power voltage trace VDDL has a sixteenth upper via region HB16; the sixteenth upper via region HB16 overlaps with the sixteenth lower via region HA16 and is connected by a via, so as to achieve the purpose of loading the power voltage VDD to the fourth bridge part MA4 through the power voltage trace VDDL.

[0156] The data signal trace DL has a tenth upper via region HB10; the tenth upper via region HB10 overlaps with the tenth lower via region HA10 and is connected by a via, so as to achieve the purpose of loading the data signal to the first electrode of the data writing transistor T4 through the fifth bridge part MA5 through the data signal trace DL.

[0157] The first initialization voltage auxiliary trace VTL1X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; the seventeenth upper via region HB17 overlaps with the seventeenth lower via region HA17 and is connected by a via, so as to achieve the purpose of loading the first initialization voltage Vinit1 to the first initialization voltage auxiliary trace VTL1X, and further achieve the gridding of the first initialization voltage Vinit1.

[0158] The second initialization voltage auxiliary wire VTL2X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; the seventeenth upper via region HB17 and the seventeenth lower via region HA17 overlap and are connected by a via, so as to achieve the purpose of loading the second initialization voltage Vinit2 to the second initialization voltage auxiliary wire VTL2X, and further achieve the gridding of the second initialization voltage Vinit2.

[0159] The third initialization voltage auxiliary wire VTL3X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; the seventeenth upper via region HB17 and the seventeenth lower via region HA17 overlap and are connected by a via, so as to achieve the purpose of loading the third initialization voltage Vinit3 to the third initialization voltage auxiliary wire VTL3X, and further achieve the gridding of the third initialization voltage Vinit3.

[0160] The second conductive part MB2 has a fourteenth upper via region HB14, and the fourteenth upper via region HB14 and the fourteenth lower via region HA14 overlap and are connected by a via, so as to achieve the purpose of transferring the second initialization voltage Vinit2 loaded on the seventh bridge part MA7 to the second sub-line LA2 of the first connection line LA through the second conductive part MB2, and further achieve the gridding of the second initialization voltage Vinit2.

[0161] In the above-mentioned embodiments of the present disclosure, the initialization voltage auxiliary wire VTLX is taken as an example of the first connection line LA located at the SD1 and the second connection line LB located at the second source-drain metal layer SD2.

[0162] It can be understood that the initialization voltage auxiliary wire VTLX of the embodiments of the present disclosure can also adopt other embodiments.

[0163] For example, in the example of FIG. 16, the initialization voltage auxiliary wire VTLX further includes a third sub-line LA3 located at the second source-drain metal layer SD2, and the third sub-line LA3 and the second sub-line LA2 are arranged alternately and connected to form an integral wire.

[0164] In this embodiment, the initialization voltage auxiliary wire VTLX includes the second sub-line LA2 and the third sub-line LA3 located at the second source-drain metal layer SD2, and includes the first sub-line LA1 located at the first source-drain metal layer SD1, wherein the second sub-line LA2 and the third sub-line LA3 of the initialization voltage auxiliary wire VTLX are connected to form an integral wire, and the first sub-line LA1 is arranged in parallel with the third sub-line LA3 to reduce the resistance of the initialization voltage auxiliary wire VTLX, and further improve the uniformity of the initialization voltage.

[0165] The display device can be a smart phone screen, a smart watch screen, or other types of display devices. Since the display device has any one of the display panels described in the display panel embodiments, it has the same beneficial effects, which will not be described herein again.

[0166] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising a substrate substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer which are sequentially stacked; wherein, The display panel comprises circuit areas arranged in a row direction and a column direction, and the circuit areas are provided with pixel driving circuits for driving sub-pixels; The display panel is provided with data signal wires corresponding to each circuit area column and extending in the column direction, and is also provided with first connection lines corresponding to at least part of the circuit area columns and extending in the column direction, wherein the circuit area columns comprise a plurality of circuit areas arranged in the column direction in sequence; The first connection line comprises first sub-lines arranged in the first source-drain metal layer and second sub-lines arranged in the second source-drain metal layer, and adjacent first sub-lines and second sub-lines are electrically connected through vias; The display panel further comprises second connection lines extending in the row direction; wherein at least part of the first connection lines are electrically connected to the data signal wires through the second connection lines.

2. The display panel of claim 1, wherein, The first connection line comprises connection leads and initialization voltage auxiliary wires arranged in the row direction in sequence; The connection leads are electrically connected to the data signal wires through the second connection lines; The initialization voltage auxiliary wires are used for electrical connection with initialization voltage wires located in the first source-drain metal layer or the transistor layer.

3. The display panel of claim 2, wherein, The initialization voltage wires comprise first initialization voltage wires for loading a first initialization voltage and extending in the row direction, second initialization voltage wires for loading a second initialization voltage and extending in the row direction, and third initialization voltage wires for loading a third initialization voltage and extending in the row direction; The initialization voltage auxiliary wires comprise first initialization voltage auxiliary wires for electrical connection with the first initialization voltage wires, second initialization voltage auxiliary wires for electrical connection with the second initialization voltage wires, and third initialization voltage auxiliary wires for electrical connection with the third initialization voltage wires.

4. The display panel of claim 3, wherein, Among each initialization voltage auxiliary wire arranged in the row direction, the first initialization voltage auxiliary wire, the second initialization voltage auxiliary wire, and the third initialization voltage auxiliary wire are arranged in sequence in cycles.

5. The display panel of claim 1, wherein, The second connection line is arranged in the first source-drain metal layer and extends in the row direction; The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with first initialization voltage wires for loading a first initialization voltage, and the first initialization voltage wires are used for resetting the gate of a driving transistor of the pixel driving circuit; The extension track of the second connection line is consistent with the extension track of the adjacent first initialization voltage wire.

6. The display panel of claim 1, wherein, The first connection line is arranged between two adjacent circuit area columns.

7. The display panel of claim 1, wherein, The pixel driving circuit has a storage capacitor; The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; The storage capacitor comprises a first electrode plate located in the first gate layer and a second electrode plate located in the second gate layer; The connection positions of the first sub-line and the second sub-line on the substrate substrate have a projection that partially overlaps with the projection of the second electrode plate on the substrate substrate.

8. The display panel of claim 1, wherein, The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with a first initialization voltage trace for loading a first initialization voltage, and the first initialization voltage trace is used for resetting a gate of a driving transistor of the pixel driving circuit; The first connection line comprises a first initialization voltage auxiliary trace connected with the first initialization voltage trace; The first source-drain metal layer has a first initialization voltage switching structure, one end of the first initialization voltage switching structure is electrically connected with the first initialization voltage auxiliary trace, and the other end is connected with the first initialization voltage trace through a via hole.

9. The display panel of claim 8, wherein, The pixel driving circuit has a storage capacitor; The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the storage capacitor comprises a first electrode plate located at the first gate layer and a second electrode plate located at the second gate layer; The first initialization voltage switching structure overlaps the second electrode plate in the orthographic projection of the substrate substrate.

10. The display panel of claim 8, wherein, The first initialization voltage switching structure has a wiring space between the first initialization voltage trace and the first sub-line; The pixel driving circuit has a data writing transistor; The first source-drain metal layer is provided with a data signal switching structure in the wiring space, one end of the data signal switching structure is connected with the data signal trace, and the other end is electrically connected with a first electrode of the data writing transistor.

11. The display panel of claim 8, wherein, The pixel driving circuit has a node control transistor; The display panel is provided with a third initialization voltage trace for loading a third initialization voltage, the third initialization voltage trace is electrically connected with a first electrode of the node control transistor; The first initialization voltage switching structure is arranged between the third initialization voltage trace and the second connection line.

12. The display panel of claim 1, wherein, The transistor layer comprises a first gate layer and a second gate layer arranged in sequence; the second gate layer is provided with a second initialization voltage trace for loading a second initialization voltage, and the second initialization voltage trace is used for resetting a driving transistor of the pixel driving circuit; The first connection line comprises a second initialization voltage auxiliary trace connected with the second initialization voltage trace; The display panel further comprises a power voltage trace corresponding to each circuit region; the second initialization voltage auxiliary trace is located between the data signal trace and the power voltage trace; The first source-drain metal layer has a second initialization voltage switching structure, the second initialization voltage switching structure is located between the second initialization voltage auxiliary trace and the power voltage trace, one end of the second initialization voltage switching structure is electrically connected with the second initialization voltage auxiliary trace through a via hole, and the other end is electrically connected with the second initialization voltage trace through a via hole.

13. The display panel of claim 1, wherein, The pixel driving circuit has a driving transistor, a data writing transistor and a node control transistor; a second electrode of the data writing transistor, a first electrode of the driving transistor and a second electrode of the node control transistor are electrically connected; The display panel is provided with a third initialization voltage trace for loading a third initialization voltage, and the third initialization voltage trace is electrically connected with the first electrode of the node control transistor; The first connection line includes a third initialization voltage auxiliary trace electrically connected with the third initialization voltage trace; The pixel driving circuit has a node control transistor; The first source-drain metal layer has a third initialization voltage switching structure, one end of the third initialization voltage switching structure is electrically connected with the end of the first sub-line of the third initialization voltage auxiliary trace, and the other end is electrically connected with the third initialization voltage trace.

14. The display panel of claim 13, wherein, The second connection line is arranged adjacent to the third initialization voltage trace; The third initialization voltage switching structure is arranged on the side of the third initialization voltage trace away from the second connection line; One end of the second sub-line of the first connection line overlaps the projection of the third initialization voltage trace on the substrate in the projection of the substrate, and the other end overlaps the projection of the second connection line on the substrate in the projection of the substrate.

15. The display panel of claim 2, wherein, The initialization voltage auxiliary trace further includes a third sub-line located in the second source-drain metal layer, and the third sub-line and the second sub-line are arranged alternately and connected to form an integral trace.

16. A display device comprising: The display panel comprises any one of the display panels according to claims 1 to 15.

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