Multi-stage delay line with tree-based structure

Abstract

A multi-stage delay line (300) configured to receive an input signal (In) and generate an output signal (Out) with a selected time delay is provided. The multi-stage delay line (300) comprises a number M of delay stages (DS1, DS2, …DSM) connected in series. Each stage comprises a first delay unit (310) comprising a number N of delay cells (∆t 1, ∆t 2 ..., ∆t N ,connected in parallel and a second delay unit (320) comprising a delay cell (∆t). The first delay unit (310) is connected in series with the second delay unit (320). The multi-stage delay line (300) further comprises a multiplexer (MUX) configured to receive outputs from the M delay stages (DS1, DS2, …DSM) and generate an output signal (Out) with a selected time delay by selecting an output among the outputs of the M delay stages as the output signal based on a digital control word received at a control input (Ctl) of the multiplexer (MUX).

Description

[0001] MULTI-STAGE DELAY LINE WITH TREE-BASED STRUCTURE

[0002] TECHNICAL FIELD

[0003] Embodiments herein relate to delay lines. In particular, they relate to multi-stage delay line with tree-based structure and signal generation circuits comprising the multi-stage delay line, electronic apparatus comprising the signal generation circuits.

[0004] BACKGROUND

[0005] Delay lines are essential parts in many systems relating to clock signal generation and clock synchronization such as delay locked loops (DLLs), phase locked loops (PLLs), phase shifters and many other blocks. The simplest form of a delay cell in a Complementary metal- oxide-sem iconductor (CMOS) technologies is an inverter. An example of simple controlled delay line is shown in Fig. 1 , where a series of inverters 101, 102, ... are taped with a multiplexer MUX, as shown in A. Efendovich, et.al . , "Multifrequency zero-jitter delay-locked loop", IEEE Journal of Solid-State Circuits, vol. 29, no. 1 , pp. 67-70, Jan. 1994. Depending on the desired delay the multiplexer MUX is programmed to output a signal with the desired delay. An alternative is to use an inverter that is loaded with a switchable capacitor, as shown in Fig. 2.

[0006] Unfortunately, even in advanced CMOS technologies the minimum delay of an inverter is in the order of 10ps which is not short enough for many applications such as DLL or PLL applications. Lower delay than one gate delay is achieved by using switch capacitors which require time to charge and high resolution is possible to achieve since small capacitors are easy to fabricate. However, linearity is an issue. This is due to the interconnect parasitic and mismatches as discussed in S. Levantino, et.al., "An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs", IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1762-1772, Aug. 2014. More advanced architectures such as constant slope Digital-to-Time Converter (DTC) discussed in J. Z. et.al., "A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging", IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1412-1423, June 2015, offers good performance. However, larger area and extra design are required. Furthermore, higher delay range is more difficult to achieve.

[0007] SUMMARY

[0008] Therefor it is an object of embodiments herein to provide a delay line with improved performance.

[0009] According to a first aspect of embodiments herein, the object is achieved by a multistage delay line configured to receive an input signal and generate an output signal with a selected time delay. The multi-stage delay line comprises a number M of delay stages connected in series. Each stage comprises a first delay unit comprising a number N of delay cells connected in parallel and a second delay unit comprising a delay cell. The first delay unit is connected in series with the second delay unit. The first delay stage is configured to receive the input signal. The multi-stage delay line further comprises a multiplexer configured to receive outputs from the M delay stages and generate an output signal with a selected time delay by selecting an output among the outputs of the M delay stages as the output signal based on a digital control word received at a control input of the multiplexer.

[0010] According to some embodiments herein, the delay cells in the first and second delay units may be implemented with same standard delay cell.

[0011] According to some embodiments herein, the multiplexer may be implemented with the same standard delay cell as the first and second delay units.

[0012] According to a second of embodiments herein, the object is achieved by a method for controlling a multiplexer comprised in the multi-stage delay line described above for generating an output signal with a selected time delay. The method comprises receiving a digital control word representing a desired time delay setting and determining if the digital control word is used for controlling the multiplexer for the first time. If it is used for the first time, applying the digital control word to the multiplexer and storing the digital control word in a list. If it is not used for the first time, checking the list with stored digital control word and selecting a digital word e.g. the next digital control word from the list. Then applying the selected digital word to the multiplexer.

[0013] Embodiments herein provide a multi-stage delay line that can achieve an arbitrarily high resolution thanks to its unique architecture where the delay resolution may be smaller than a gate delay by selecting different paths with different delays. The multi-stage delay line can be modelled by a tree with multiple paths with heterogeneous delays grouped to form a high-resolution delay line that covers a range of intermediate delays. The multi-stage delay line can be controlled to generate different intermediate delays ranging between a minimum and a maximum delays resulting in a sub-gate delay resolution. The multi-stage delay line offers a unique property where for the same desired delay, there are multiple paths that can be chosen from the multi-stage delay line. This is very useful to reduce the impact of the delay line nonlinearity induced by process, voltage, and temperature (PVT) variations. The multi-stage delay line may be implemented with standard digital cells making it possible to be implemented in a digital flow. This is one of the main motivations for present day circuit design which is finding digital friendly designs that can incorporate the already available standard cells from the semiconductor foundry.

[0014] The multi-stage delay line according to embodiment herein has some advantages, for examples:

[0015] . Higher resolution may be achieved by increasing the number of parallel cells in the first delay unit and configuring the delay time difference between the delay cells in the first and second delay units.

[0016] . High linearity may be achieved by controlling the multiplexer with different digital settings for the same desired delay which can mitigate parameter variations and spread induced by PVT resulting in more statistical averaging and a linear characteristic.

[0017] . Fully digital designs are possible since only active components are needed making it possible to implement the multi-stage delay line using standard cells only.

[0018] Therefore, the embodiments herein provide an improved delay line with regard to, e.g. delay range, delay resolution, linearity, size and implementations etc.

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Examples of embodiments herein are described in more detail with reference to attached drawings in which:

[0021] Figure 1 is a schematic block view of an example delay line according to prior art;

[0022] Figure 2 is a schematic block view of another example delay line according to prior art;

[0023] Figure 3 is a schematic block view of an example multi-stage delay line according to embodiments herein;

[0024] Figure 4 is a schematic block view illustrating another example multi-stage delay line according to embodiments herein;

[0025] Figure 5 is a schematic diagram illustrating a binary tree structure to model a multi-stage delay line according to embodiments herein;

[0026] Figure 6 is a schematic diagram illustrating a binary tree structure to model a 3-stage delay line according to embodiments herein;

[0027] Figure 7 is a diagram illustrating the characteristic of a 3-stage delay line and the number of possible paths for each delay setting;

[0028] Figure 8 is a schematic diagram illustrating a tree structure of a 5-stage delay line according to embodiments herein; Figure 9 is a diagram illustrating the characteristic of a 3-stage delay line with and without mismatch according to embodiments herein;

[0029] Figure 10 is a schematic block view illustrating an example of a tri-state inverter;

[0030] Figure 11 is a schematic block view illustrating an example of an 8-stage delay line implemented with tri-state inverters;

[0031] Figure 12 is a schematic block view illustrating an example of an 8-stage delay line with one- layer multiplxer;

[0032] Figure 13 is a schematic block view illustrating an example of an 8-stage delay line with multi-layer multiplexer;

[0033] Figure 14 is a flow chart illustrating a method for controlling the multiplexer of the multi-stage delay line;

[0034] Figure 15 is a block diagram illustrating a signal generation circuit in which the multi-stage delay line according to embodiments herein may be implemented; and

[0035] Figure 16 is a block diagram illustrating an electronic device in which the multi-stage delay line according to embodiments herein may be implemented.

[0036] DETAILED DESCRIPTION

[0037] The basic structure of a delay line with programmable delay is shown in Fig. 1. In represents a clock signal that needs to be delayed. Control signal Ctl is a digital signal that controls a multiplexer MUX to select an output among the outputs of the inverters 101 , 102... to be an output signal Out with the desired delay. The resolution of such delay line is then an inverter delay. A simpler design with higher resolution is to use an inverter loaded by a controlled capacitor bank Ci to program the delay, as shown in Fig.2. Since small capacitances are easier to fabricate, arbitrary resolution can be achieved. If the current into the capacitance can be increased by increasing the inverter size, then finer resolution can be achieved. However, this kind of programmable delay line suffers from linearity degradation due to capacitor mismatch and systematic layout errors.

[0038] A proposed delay line according to embodiments herein is shown in Fig.3, where a multi-stage delay line 300 is configured to receive an input signal In and generate an output signal Out with a selected time delay. The multi-stage delay line 300 comprises a number M of delay stages DSi, DS2, ...DSM connected in series. Each stage comprises a first delay unit 310 comprising a number N of delay cells connected in parallel and a second delay unit 320 comprising a delay cell AT. The first delay unit 310 is connected in series with the second delay unit 320. The first delay stage DS1 is configured to receive the input signal In. The multi-stage delay line 300 further comprises a multiplexer MUX configured to receive outputs from the M delay stages DS1, DS2, ... DSM and generate an output signal Out. The multiplexer MUX is configured to generate the output signal Out with a selected time delay by selecting an output among the outputs of the M delay stages as the output signal based on a digital control word received at a control input Ctl of the multiplexer MUX. The digital control words for controlling the MUX and the delay cells in each delay stage may be generated by a control unit. For different delays, different digital control words may be generated and applied to the control inputs Ctl of the MUX and the delay cells.

[0039] As shown in Fig.3, both outputs from the first delay unit 310 and second delay unit 320 in each delay stage are connected to the MUX, so the MUX has 2xM inputs. However, according to some embodiments herein, only the outputs from the first delay unit 310 or only the outputs from the second delay unit 320 in each delay stage are connected to the MUX, then the MUX only needs to have M inputs.

[0040] Therefore, according to some embodiments herein, the output of the second delay unit 320 in each delay stage DSi, DS2, ... DSM is an output of the M delay stages DS1, DS2, ... DSM, and the outputs of the second delay units 320 are connected to the respective inputs of the multiplexer MUX.

[0041] According to some embodiments herein, the output of the first delay unit 310 in each delay stage DS1, DS2, ... DSM is an output of the M delay stages DS1, DS2, ... DSM, and the outputs of the first delay units 310 are connected to the respective inputs of the multiplexer MUX.

[0042] According to some embodiments herein, the delay cells in the first and second delay units 310, 320 may be implemented with same standard delay cell. The multiplexer MUX may also be implemented with the same standard delay cell as the first and second delay units 310, 320.

[0043] According to some embodiments herein, each of the delay cells ATVAT2;.„ATWineach of the first delay unit 310 may have a size of one unit delay cell. The size of the unit delay cell in the first delay unit 310 relative to the delay cell AT in the second delay unit 320 may not be restricted. To ensure the delay cell in the second delay unit 320 can drive the following stage with efficient power consumption, the delay cell AT in the second delay unit 320 may, for instance, have a size equal to a sum of the sizes of the unit delay cells in each of the first delay unit 310 divided by 2.

[0044] The multiple delay stages are cascaded resulting in heterogenous delays depending on the control word Ctl. Selection of the delay paths is of paramount importance to achieve uniform resolution. Fig. 4 shows an example of a multi-stage delay line 400 with two branches, i.e. each of the first delay unit 310 comprises two delay cells AT1, AT2. The multistage delay line 400 may be modelled by a binary tree 500 as shown in Fig. 5, which captures all the possible delay routes or paths. The two delay cells and AT2in each of the first delay unit 310 are represented by the inclined lines 511a, 512a, 521a, 522a, 523a, 524a, 531a, 532a, 533a, 534a, 535a, 536a, 537a, 538a while the vertical lines 511b, 512b, 521b, 522b, 523b, 524b, 531b, 532b, 533b, 534b, 535b, 536b, 537b, 538b represent the delay cells AT in each of the second delay unit 320. Each stage DSi, DS2, ... DSM may be modelled by one level in the tree 500, where the first three stages DS1, DS2, DS3 are shown in Fig. 5. This means that the first stage DS1 in the multi-stage delay line is represented by the first 4 branches. And the second stage DS2 is then represented by the next 8 branches and the third one is the whole 16 branches. It is of course in theory possible to make A tunable as well e.g. replaced by two delay cells AT1;AT2or even be removed.

[0045] Let’ assume that the AT1;AT2and AT are 5ps, 10ps and 10ps respectively, which is modelled by a three-stage tree 600 shown in Fig. 6, where the delay times 5ps, 10ps and 10ps are noted on the branches. The tree model 600 constitutes of 29 nodes representing all the possible combinations of delay programming. The number of branches in the tree is given by:

[0046] Where sections are the number of delay stages., n is the number of parallel delay cells in each of the first delay unit 310. The delay value together with the number of hits, i.e. the setting values for that particular delay value are shown in Fig. 7. As can be seen in the figure the characteristic of the delay line 710 is linear with a resolution of 5ps (for curve 710, the y-axis has the unit ps), i.e. the difference between the parallel delay cells. For the same delay value there is often more than one possible setting value indicated by line 720. That is, there is often more than one setting value that corresponds to the same effective delay setting. This is extremely attractive to mitigate the mismatch effect by choosing different setting values for a given delay value at different instants in time, e.g. according to a pattern or in a random or pseudorandom fashion.

[0047] To achieve even higher resolution, it is recommended to increase the number of parallel cells. To see the potential improvement, a 5-stage delay line with three parallel delay cells in each of the first delay unit are modelled as shown in Fig.8, where the 5-stage delay line results in 726 branches, calculated by the following equation: A lot of redundancy in the delay settings can give more freedom to achieve high linearity. To investigate the linearity, delay cells implemented by inverter have been simulated and results are shown in Fig. 9, where the characteristic of the delay line with mismatch indicated by line 910, the characteristic of the delay line without mismatch indicated by line 920, and the number of setting values for the same delay indicated by line 930, are shown. For the curves 910 and 920, the y-axis has the unit ps. The delay values for the delay cells are 12.5ps, 10ps, 7.5ps for the 3 parallel delay cells in the first delay unit 310 and 7.5ps for the delay cell in the second delay unit 320. As can be seen in the figure, if the first 4 or 5 setting values are discarded then the delay line is highly linear even with mismatch.

[0048] According to some embodiments herein, a standard cell of tri-state buffer inverter may be used to implement the multi-stage delay line 300, 400. Fig. 10 shows an example of tri- state inverter 1000 implemented by CMOS transistors Mi, M2, M3, M4, where figure (a) is a schematic diagram of the tri-state inverter and figure (b) is a symbol of the tri-state inverter. Since inverters are used, every second output is taken resulting in dead zones at the beginning of the characteristic of the delay line. For example, if two inverters used in the first delay unit 310 is 8ps andlOps and an inverter used in the second delay unit 320 is 8ps, then repeating this structure for a number of stages, the possible delay values when taking the outputs after the second delay unit 320 are 16ps, 18ps, 32ps, 34ps... etc. As can be seen there is a gap between the delay values 18ps and 32ps. Progressing further in the delay stages, the delay values get populated but the delay values between 18ps and 32ps will be unavailable resulting in a dead zone. However, this is not an issue as one can just ignore the first 2 or 3 stages and use the stages afterwards. The dead zone is of course dependent on the delay in each inverter.

[0049] For example, an 8-stage delay line 1100 has been implemented by tri-state inverters, as shown in Fig. 11. Each stage of the 8-stage delay line 1100 comprises a first delay unit 1110 comprising three parallel tri-state inverters h, I2, 13, where one of the parallel inverters h comprises two inverters connected in parallel to act as one with double device sizes. Each stage of the 8-stage delay line 1100 further comprises a second delay unit 1120 comprising a tri-state inverter I4. The first stage is repeated 8 times, where only the inverters in the first delay stage are labelled as h, I2, I3, and I4 which are then repeated and therefore the same labels are assumed for the other stages. The minimum unit size of the tri-state inverter is used as a base unit cell such that the sum of the parallel inverters h, I2, I3 in the first delay unit 1110 is equal to twice of the inverter I4 in the second delay unit 1120, i.e. the buffering stage, where its output is fed to the MUX. Tri-state inverter was used to enable current saving when later stages are not used, resulting in less than e.g. 130 uA rms for the 8-stage delay line. Furthermore, the MUX may be implemented by tri-stage inverters as well allowing for more power saving. However, any delay cell may be used to implement the multi-stage delay line 300, 400 according to embodiments herein.

[0050] The sizing of the inverters is key to achieve resolution and linearity. An example of how to achieve high resolution and linearity is by sizing the inverters with 2x, 1x, 1x and 2x for h, I2 and I3, and I4 inverters respectively, where x is unit size of the inverter. With 8-stage delay line, all the possible setting values or control words Ctl with e.g. 3 bits, have been simulated, i.e. 38= 6561 simulations. The simulations show that the inverter delays with 12ps, 14ps, 18ps and 12ps for h, l2 and I3, and I4 respectively, can result in a delay resolution of 2ps. To increase the delay range depending on requirements, more stages may be added. The multistage delay line has superior performance if all the paths are used making it attractive for low-cost CMOS implementations. The difference between the time delays of the delay cells in the first and second delay units 310, 320 may be configured to achieve a desired time delay resolution. By selecting different paths, desired delay time and delay resolution can be selected.

[0051] The multiplexer MUX can introduce static errors that result in a non-linear characteristic. To reduce the effect of static errors, uniform MUX layout is proposed using e.g. the same delay cells as used in the multi-stage delay line. Fig. 12 shows an example 8- stage delay line 1200 where the multiplexer 1210 is implemented using the same delay cells as used in the 8-stage delay line 1200 and implemented as a one-layer multiplexer. The one- layer multiplexer 1210 is configured to receive respective outputs from the M delay stages DS1, DS2, ... DSM, where M=8, at its multiple inputs and select one of its inputs as the output of the multiplexer Out based on the control word.

[0052] The multiplexer MUX may be implemented as a multi-layer multiplexer with a number J of layers. Fig. 13 shows an example 8-stage delay line 1300 with a 3-layer multiplexer 1310. The 1stlayer multiplexer 1311 is configured to receive respective outputs from the 8 delay stages DS1, DS2, ... DSs at its inputs and select one of every pair of its inputs as one of its outputs. The 2ndlayer multiplexer 1312 is configured to receive at its inputs the respective outputs from the 1st layer multiplexer 1311 and select one of every pair of its inputs as one of its outputs. The 3rd layer multiplexer 1313 is configured to receive at its inputs the respective outputs from the 2nd layer multiplexer 1312 and select one of its two inputs as its output, i.e. the output signal Out of the 3-layer multiplexer 1310.

[0053] For a general case, where the number of stages is M and the number of multiplexer layers is J, the 1stlayer multiplexer is configured to receive the outputs from the M delay stages DS1, DS2, ... DSM and select one of every pair of its inputs as one of its outputs, the ithlayer multiplexer is configured to receive the outputs from the (i-1)thlayer multiplexer and select one of every pair of its inputs as one of its outputs, where i=2, ... J-1 , and the Jthlayer multiplexer is configured to receive the outputs from the (J-1)thlayer multiplexer and select one of its two inputs as the output of the multi-layer multiplexer.

[0054] To improve the linearity of the multi-stage delay line 300, 400, 1100, 1200, 1300 according to embodiments herein, a method for controlling the multiplexer MUX, 1210, 1310 to generate the output signal Out with a selected time delay will be described with reference to Fig. 14. The method is a tree-based search method and may be used to program the multi-stage delay line 300, 400, 1100, 1200, 1300 for the same selected delay time using different setting values of the digital control word Ctrl. The method comprises the following actions which may be performed in any suitable order or simultaneously.

[0055] Action 1410

[0056] Reading a digital control word representing a desired time delay setting value.

[0057] Action 1420

[0058] Determining if the digital control word is used for controlling the multiplexer MUX, 1210, 1310 for the first time.

[0059] Action 1430

[0060] If it is used for the first time, applying the digital control word to the multiplexer MUX, 1210, 1310.

[0061] Action 1440

[0062] Storing the digital control word in a list. This is to keep track of what digital control words have been used.

[0063] Action 1450

[0064] If it is not used for the first time, checking the list with stored digital control word.

[0065] Action 1460

[0066] Selecting a digital word e.g. the next digital control word from the list. By not using the same digital control word for the same desired time delay, different paths of the delay line can be used which mitigates the mismatch effect. Different control word may be chosen at a regular or even random fashion for the desired time delay.

[0067] Action 1470

[0068] Applying the selected digital word to the multiplexer MUX, 1210, 1310.

[0069] The method for controlling the multiplexer MUX, 1210, 1310 to generate the output signal Out with a selected time delay may be performed by a control unit or a processing unit comprised in a signal generation circuit. Fig. 15 is a block diagram illustrating an example signal generation circuit SGC 1500. The signal generation circuit SGC 1500 comprises a multi-stage delay line 300, 400, 1200, 1300 according to embodiments herein, a process unit PU 1510. The signal generation circuit SGC 1500 may be any one of a delay locked loop (DLL), a phase locked loop, a phase shifter, a time interleaved analog to digital converter etc. The PU 1510 may comprise a reading unit RU 1511 , a determining unit DU 1512, an applying unit AU 1513, a memory unit MeU 1514 etc.

[0070] The process unit PU 1510 is configured to perform any one of the method Actions 1410-1470 described above.

[0071] The process unit PU 1510 is configured to, be means of e.g. the reading unit RU 1511 being configured to, read a digital control word representing a desired time delay setting value.

[0072] The process unit PU 1510 is configured to, be means of e.g. the determining unit DU 1512 being configured to, determine if the digital control word is used for controlling the multiplexer MUX, 1210, 1310 for the first time.

[0073] If it is used for the first time, the process unit PU 1510 is configured to, be means of e.g. the applying unit AU 1513 being configured to, apply the digital control word to the multiplexer MUX, 1210, 1310.

[0074] The process unit PU 1510 is configured to, be means of e.g. the applying unit AU 1513 being configured to, store the digital control word in a list in e.g. the memory unit MeU 1514. This is to keep track of what digital control words have been used.

[0075] If it is not used for the first time, the process unit PU 1510 is configured to, be means of e.g. the determining unit DU 1512 being configured to, check the list with stored digital control word.

[0076] The process unit PU 1510 is configured to, be means of e.g. the determining unit DU 1512 being configured to, select a digital word e.g. the next digital control word, from the list.

[0077] The process unit PU 1510 is configured to, be means of e.g. the applying unit AU 1513 being configured to, apply the selected digital word to the multiplexer MUX, 1210, 1310.

[0078] Those skilled in the art will also appreciate that the reading unit RU 1511, determining unit DU 1512, applying unit AU 1513 described above for the process unit PU 1510 may be referred to as one circuit or one unit, a combination of analog and digital circuits, one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each unit. Further, the signal generation circuit SGC 1500, one or more of these processors, the combination of analog and digital circuits as well as the other digital hardware, may be included in a single application-specific integrated circuitry (ASIC), or several processors and various analog / digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC). The multi-stage delay line 300, 400, 1100, 1200, 1300 may be employed in various integrated circuits, electronic circuits, devices or apparatus, communication devices or apparatus where delaying a signal with a desired time is needed. Fig. 16 shows a block diagram of an electronic device 1600 in which the multi-stage delay line 300, 400, 1100, 1200, 1300 according to embodiments herein may be implemented. The electronic device 1600 may comprise a signal generation circuit SGC 1500 which may be one of a delay locked loop (DLL), a phase locked loop, a phase shifter, a time interleaved analog to digital converter etc. The multi-stage delay line 300, 400, 1200, 1300 according to embodiments herein may be implemented in the signal generation circuit SGC 1500.

[0079] The electronic device 1600 may further comprise a receiver or a transmitter or both i.e. a transceiver TX / RX 1610. The electronic device 1600 may comprise other units, where a memory MeM1620, a processing unit PU 1630 are shown. The electronic device 1600 may be any one of a base station, a wireless communication device such as a user equipment or a mobile device for a cellular communication system.

[0080] The embodiments herein for controlling the multiplexer MUX, 1210, 1310 to generate the output signal Out with a selected time delay may be implemented through one or more processors, such as the processing unit PU 1630 in the electronic device 1600, together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product 1640, for instance in the form of a data carrier carrying computer program code 1650 for performing the embodiments herein when being loaded into the electronic device 1600. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server or cloud and downloaded to the electronic device 1600.

[0081] The word "comprise" or “comprising”, when used herein, shall be interpreted as nonlimiting, i.e. meaning "consist at least of".

[0082] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

CLAIMS1. A multi-stage delay line (300, 400, 1100, 1200, 1300) configured to receive an input signal (In) and generate an output signal (Out) with a selected time delay, the multistage delay line (300, 400, 1100, 1200, 1300) comprises: a number M of delay stages (DSi, DS2, ... DSM) connected in series, wherein each stage comprises a first delay unit (310) comprising a number N of delay cells (AT1;AT2...ATW) connected in parallel and a second delay unit (320) comprising a delay cell (AT) , wherein the first delay unit (310) is connected in series with the second delay unit (320), and the first delay stage (DS1) is configured to receive the input signal (In); and a multiplexer (MUX) configured to receive outputs from the M delay stages (DS1, DS2, ... DSM) and generate an output signal (Out) with a selected time delay by selecting an output among the outputs of the M delay stages as the output signal based on a digital control word received at a control input (Ctl) of the multiplexer (MUX).

2. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to claim 1 , wherein an output of the second delay unit (320) in each delay stage (DS1 , DS2, ... DSM) is an output of the M delay stages, and the outputs of the second delay units (320) are connected to the respective inputs of the multiplexer (MUX).

3. The multi-stage delay line (300, 400, 1100, 1200, 1300) according any one of claims 1-2, wherein an output of the first delay unit (310) in each delay stage (DS1, DS2,... DSM) is an output of the M delay stages, and the outputs of the first delay units (310) are connected to the respective inputs of the multiplexer (MUX).

4. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-3, wherein the delay cells (AT1;AT2... ATW, A ) in the first and second delay units (310, 320) are implemented with same standard delay cell.

5. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to claim 4, wherein the multiplexer (MUX) is implemented with the same standard delay cell as the first and second delay units (310, 320).

6. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-5, wherein each of the delay cells (AT1;AT2, ... ATW) in each first delay unit (310)has a size of one unit delay cell, and the delay cell ( AT) in the second delay unit (320) has a size equal to a sum of the sizes of the unit delay cells in each first delay unit (310) divided by 2.

7. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-6, wherein the difference between the time delays of the delay cells ( T1, T2„„ TW, T) in the first and second delay units (310, 320) are configured to achieve a desired time delay resolution.

8. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-7, wherein the delay cell (AT1;AT27... ATW, ) is implemented by a tri-state inverter.

9. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-8, wherein the multiplexer (MUX) is implemented as a one-layer multiplexer (1210), and the multiplexer (1210) is configured to receive the outputs from the M delay stages (DSi, DS2, ... DSM) at its multiple inputs and select one of its inputs as the output (Out) of the multiplexer (1210).

10. The multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-8, wherein the multiplexer (MUX) is implemented as a multi-layer multiplexer (1310) with a number J of layers, and wherein the 1stlayer multiplexer (1311) is configured to receive the outputs from the M delay stages (DS1, DS2, ... DSM) and select one of every pair of its inputs as one of its output, the ithlayer multiplexer (1312) is configured to receive the outputs from the (i-1)thlayer multiplexer (1311) and select one of every pair of its inputs as one of its output, where i=2, ... J-1 , and the Jthlayer multiplexer is configured to receive the outputs from the (J-1)thlayer and select one of its two inputs as the output (Out) of the multi-layer multiplexer (1310).11 . A method for controlling a multiplexer (MUX) comprised in a multi-stage delay line (300, 400, 1210, 1310) for generating an output signal (Out) with a selected time delay, wherein the multi-stage delay line (300, 400, 1210, 1310) comprises a number M of delay stages (DS1, DS2, ... DSM) connected in series and the multiplexer (MUX) comprising multiple inputs configured to receive outputs from the M delay stages (DS1, DS2, ... DSM) and generate the output signal (Out) based on a digital control word, the method comprises: reading (1410) a digital control word representing a desired time delay setting;determining (1420) if the digital control word is used for controlling the multiplexer (MUX) for the first time; if it is used for the first time, applying (1430) the digital control word to the multiplexer (MUX) and storing the digital control word in a list; if it is not used for the first time, checking (1450) the list with stored digital control word; selecting (1460) a digital word from the list; applying (1470) the selected digital word to the multiplexer (MUX).

12. A signal generation circuit (1500) comprising a multi-stage delay line (300, 400, 1100, 1200, 1300) according to any one of claims 1-10.

13. The signal generation circuit (1500) according to claim 12 is any one of a delay locked loop, DLL, a phase locked loop, a phase shifter, a time interleaved analog to digital converter.

14. An electronic device (1600) comprising a signal generation circuit (1500) according to any one of claims 12-13.

15. The electronic device (1600) according to claim 14, wherein the electronic device is any one of a wireless communication device, a base station for a cellular communications system.

16. A computer program product (1640) comprising program code (1650) which when the program is executed by a computer / processor, cause the computer / processor to carry out the method according to claim 11.

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