Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which crack formation can be suppressed.　A first external electrode 3A includes: a first base electrode layer 31A of the first external electrode, said layer being connected to a first internal electrode 15A and disposed to run from a fifth surface F5 to a first surface F1; a second base electrode layer 32A of the first external electrode, said layer being connected to the first internal electrode 15A and disposed to run from a sixth surface F6 to the first surface F1; a first resin electrode layer 34A disposed to run on the first base electrode layer 31A of the first external electrode, the first surface F1, and on the second base electrode layer 32A of the first external electrode; and a first plated layer 36A disposed on the first resin electrode layer 34A. The first surface F1 has a first region 21, which is the region between the region where the first base electrode layer 31A of the first external electrode is disposed and the region where the second base electrode layer 32A of the first external electrode is disposed, and which is the region where the first resin electrode layer 34A is disposed. The first region 21 overlaps, in a lamination direction T, a central part of a multilayer body 2 in a second direction W.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, a three-terminal multilayer ceramic capacitor has been known in which, in addition to a first external electrode and a second external electrode provided at both longitudinal ends of the laminate, a third external electrode is formed on a side surface of the laminate (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-031965

[0004] Multilayer ceramic capacitors are mounted on a substrate, for example, by solder. If the substrate on which the multilayer ceramic capacitor is mounted is warped, stress caused by the warping of the substrate is transmitted to the laminate via the solder and external electrodes, which may cause cracks in the laminate. If the cracks reach the interior of the laminate, defects such as short circuits may occur in the multilayer ceramic capacitor.

[0005] Furthermore, in the case of a three-terminal multilayer ceramic capacitor, cracks are likely to occur at the locations where the laminate comes into contact with the ends of the external electrodes that face each other in the longitudinal direction of the laminate.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of cracks.

[0007] In order to achieve the above object, a multilayer ceramic capacitor of the present invention comprises: an inner layer portion including a plurality of dielectric layers and a plurality of internal electrodes stacked alternately; a laminate having first and second surfaces facing each other in a stacking direction, third and fourth surfaces facing each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces facing each other in a second direction perpendicular to the stacking direction and the first direction; and external electrodes arranged on an outer surface of the laminate, wherein the plurality of internal electrodes include first internal electrodes extended to the fifth and sixth surfaces, and second internal electrodes opposed to the first internal electrodes and extended to the fifth surface, and the external electrodes include first external electrodes connected to the first internal electrodes and arranged from the third surface to the first surface, the fifth surface, and the sixth surface; and a third external electrode connected to the second internal electrode and arranged from the fifth surface to the first surface, wherein the first external electrode comprises: a first base electrode layer of a first external electrode connected to the first internal electrode and arranged from the fifth surface to the first surface; a second base electrode layer of a first external electrode connected to the first internal electrode and arranged from the sixth surface to the first surface; a first resin electrode layer arranged on the first base electrode layer of the first external electrode, the first surface, and the second base electrode layer of the first external electrode; and a first plating layer arranged on the first resin electrode layer, wherein the first surface has a first region between a region where the first base electrode layer of the first external electrode is arranged and a region where the second base electrode layer of the first external electrode is arranged, and the first region overlaps with a center portion of the laminate in the second direction.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing the occurrence of cracks.

[0009] 1 is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment; FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1; FIG. 4 is a cross-sectional view taken along a first internal electrode of a laminate; FIG. 5 is a cross-sectional view taken along a second internal electrode of a laminate; and FIG. 6 is a plan view of a portion of a multilayer ceramic capacitor near a third surface, viewed from the first surface side.

[0010] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described with reference to FIGS.

[0011] (Multilayer Ceramic Capacitor 1) As shown in Fig. 1, the multilayer ceramic capacitor 1 is a so-called three-terminal multilayer ceramic capacitor. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 3 disposed on the outer surfaces of the laminate 2. The laminate 2 is substantially rectangular parallelepiped-shaped and has six outer surfaces. As shown in Figs. 2 and 3, the laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked.

[0012] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the first direction L. The directions perpendicular to both the first direction L and the stacking direction T are referred to as the second direction W.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides of the stacking direction T are referred to as the first surface F1 and the second surface F2, a pair of outer surfaces extending in the stacking direction T and on both sides of the first direction L are referred to as the third surface F3 and the fourth surface F4, and a pair of outer surfaces extending in the stacking direction T and on both sides of the second direction W are referred to as the fifth surface F5 and the sixth surface F6.

[0014] (Laminate 2) The laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The portions where three outer surfaces of the laminate 2 intersect are referred to as "corners." The portions where two outer surfaces of the laminate 2 intersect are referred to as "ridge portions." The corners and ridge portions of the laminate 2 are preferably rounded.

[0015] The outer dimensions of the laminate are, for example, 0.3 mm to 5.0 mm in the stacking direction T, 0.6 mm to 5.7 mm in the first direction L, and 0.3 mm to 5.0 mm in the second direction W. The dimension of the laminate 2 in the first direction L is, for example, equal to or greater than the dimension of the laminate 2 in the second direction W. The outer dimensions of the multilayer ceramic capacitor 1 can be measured with a micrometer.

[0016] (Inner Layer Portion 11) As shown in FIGS. 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15.

[0017] (Dielectric Layer 14) The dielectric layer 14 is formed of a dielectric ceramic containing, for example, BaTiO3 as a main component. The dielectric ceramic may contain a Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or the like as a secondary component.

[0018] (Internal electrode 15) The internal electrode 15 is formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The internal electrode 15 preferably contains Cu, Ni, or a Cu-Ni alloy as its main component. Furthermore, it preferably contains Sn as a secondary component. When a Sn layer is formed at the interface between the internal electrode 15 and the dielectric layer 14, it is possible to reduce electric field concentration at the interface between the internal electrode 15 and the dielectric layer 14, thereby improving reliability in high-temperature environments.

[0019] The internal electrode 15 includes a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A and the second internal electrodes 15B are alternately arranged in the stacking direction T. The first internal electrodes 15A and the second internal electrodes 15B are sometimes collectively referred to as "internal electrodes 15." When the internal electrode 15 contains Sn, only one of the first internal electrodes 15A and the second internal electrodes 15B may contain Sn. After the first internal electrodes 15A are continuously stacked, the second internal electrodes 15B may be arranged between the first internal electrodes 15A. By continuously arranging the first internal electrodes 15A, the resistance of the first internal electrodes 15A can be reduced.

[0020] (First internal electrode 15A) As shown in Fig. 4, the first internal electrode 15A is extended to the fifth face F5 and the sixth face F6. The first internal electrode 15A has, for example, a substantially H-shape when viewed in the stacking direction T. The first internal electrode 15A is spaced apart from the third face F3 and the fourth face F4. The first internal electrode 15A has a first opposing portion 15Aa and a plurality of (for example, four) first extended portions 15Ab.

[0021] The first opposing portion 15Aa is a part of the first internal electrode 15A, and is a portion opposing the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 15Aa is located in the center between the third face F3 and the fourth face F4.

[0022] The first lead portion 15Ab is a portion of the first internal electrode 15A that is led out to the outer surface of the laminate 2. For example, the four first lead portions 15Ab include a first lead portion 15Ab that is led out to a portion of the fifth surface F5 closer to the third surface F3, a first lead portion 15Ab that is led out to a portion of the fifth surface F5 closer to the fourth surface F4, a first lead portion 15Ab that is led out to a portion of the sixth surface F6 closer to the third surface F3, and a first lead portion 15Ab that is led out to a portion of the sixth surface F6 closer to the fourth surface F4.

[0023] (Second Internal Electrode 15B) As shown in Fig. 5, the second internal electrode 15B is extended to the fifth face F5, more specifically, to the fifth face F5 and the sixth face F6. The second internal electrode 15B has, for example, a substantially cross shape. The second internal electrode 15B is spaced apart from the third face F3 and the fourth face F4. The second internal electrode 15B has a second opposing portion 15Ba and a plurality of (for example, two) second extended portions 15Bb.

[0024] The second opposing portion 15Ba is a portion of the second internal electrode 15B that faces the first internal electrode 15A adjacent to it in the stacking direction T. The second opposing portion 15Ba is located in the center between the side surfaces B.

[0025] The second lead portion 15Bb is a portion of the first internal electrode 15A that is led out to the outer surface of the laminate 2. For example, the two first lead portions 15Ab include a first lead portion 15Ab that is led out to the center of the fifth surface F5 in the first direction L, and another first lead portion 15Ab that is led out to the center of the fifth surface F5 in the first direction L.

[0026] The first opposing portion 15Aa and the second opposing portion 15Ba may be collectively referred to as "opposing portion 15a." The first drawn portion 15Ab and the second drawn portion 15Bb may be collectively referred to as "drawing portion 15b."

[0027] (External electrode 3) The external electrode 3 includes a first external electrode 3A connected to the first internal electrode 15A and arranged from the third face F3 to the first face F1, the fifth face F5, and the sixth face F6, a second external electrode 3B connected to the first internal electrode 15A and arranged from the fourth face F4 to the first face F1, the fifth face F5, and the sixth face F6, a third external electrode 3C connected to the second internal electrode 15B and arranged from the fifth face F5 to the first face F1, and a fourth external electrode 3D connected to the second internal electrode 15B and arranged from the sixth face F6 to the first face F1.

[0028] (First External Electrode 3A) The first external electrode 3A is preferably disposed from the third face F3 to the first face F1, the second face F2, the fifth face F5, and the sixth face F6.

[0029] The first external electrode 3A has a first base electrode layer 31A of the first external electrode connected to the first internal electrode 15A and arranged from the fifth face F5 to the first face F1, a second base electrode layer 32A of the first external electrode connected to the first internal electrode 15A and arranged from the sixth face F6 to the first face F1, a first resin electrode layer 34A arranged on the first base electrode layer 31A of the first external electrode, the first face F1, and the second base electrode layer 32A of the first external electrode, and a first plating layer 36A arranged on the first resin electrode layer 34A.

[0030] The first base electrode layer 31A of the first external electrode is preferably disposed from the fifth face F5 across the first face F1 and the second face F2. The first base electrode layer 31A of the first external electrode preferably covers the fifth face F5, the ridge between the fifth face F5 and the first face F1, and the ridge between the fifth face F5 and the second face F2. In addition, the first base electrode layer 31A is preferably disposed so as to wrap around onto the first face F1 and the second face F2.

[0031] The second base electrode layer 32A of the first external electrode is preferably disposed from the sixth face F6 across the first face F1 and the second face F2. The second base electrode layer 32A of the first external electrode preferably covers the sixth face F6, the ridge between the sixth face F6 and the first face F1, and the ridge between the sixth face F6 and the second face F2. In addition, the second base electrode layer 32A is preferably disposed so as to wrap around onto the first face F1 and the second face F2.

[0032] The first and second base electrode layers 31A, 32A of the first external electrodes are baked layers containing, for example, a conductive metal and glass. The conductive metal may be, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), gold (Au), an Ag—Pd alloy, or the like, and is preferably Cu.

[0033] The first base electrode layer 31A of the first external electrode is connected to the first lead portion 15Ab that is extended to a portion of the fifth surface F5 closer to the third surface F3. The second base electrode layer 32A of the first external electrode is connected to the first lead portion 15Ab that is extended to a portion of the sixth surface F6 closer to the third surface F3. In other words, the first external electrode 3A is connected to the first lead portion 15Ab that is extended to a portion of the fifth surface F5 closer to the third surface F3 and the first lead portion 15Ab that is extended to a portion of the sixth surface F6 closer to the third surface F3. On the first surface F1, the first base electrode layer 31A of the first external electrode and the second base electrode layer 32A of the first external electrode are spaced apart in the second direction W, and more specifically, face each other in the second direction W. On the second surface F2, the first underlying electrode layer 31A of the first external electrode and the second underlying electrode layer 32A of the first external electrode are arranged at a distance from each other in the second direction W, and more specifically, are opposed to each other in the second direction W.

[0034] It is preferable that the first resin electrode layer 34A is arranged on the first base electrode layer 31A of the first external electrode, the first surface F1, on the second base electrode layer 32A of the first external electrode, the second surface F2, and the third surface F3.

[0035] The first resin electrode layer 34A contains a thermosetting resin and a metal component.

[0036] The thermosetting resin may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin, which has excellent heat resistance, moisture resistance, adhesion, etc., is one of the most suitable resins.

[0037] Because the first resin electrode layer 34A contains such a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the first resin electrode layer 34A functions as a buffer layer. Therefore, the first resin electrode layer 34A suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0038] The first resin electrode layer 34A preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds.

[0039] The metal component may be Au, Ag, Cu, Ni, Sn, Bi, Zn, or an alloy containing any of these. The metal component preferably contains Ag. The metal component is, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as the metal component of the first resin electrode layer 34A.

[0040] The metal component may be a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, the metal powder is preferably a powder of a base metal such as Cu, Ni, Sn, or Bi, or an alloy thereof, and more preferably Cu. This allows the base metal to be inexpensive while maintaining the properties of Ag.

[0041] The first plating layer 36A is disposed, for example, over the entire surface of the first resin electrode layer 34A. The first plating layer 36A is composed of, for example, at least one metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or an alloy containing such a metal. Although not shown, the first plating layer 36A includes, for example, a Ni plating layer disposed on the first resin electrode layer 34A and a Sn plating layer disposed on the Ni plating layer. However, the configuration of the first plating layer 36A is not limited thereto and may be, for example, a single-layer structure.

[0042] (Second External Electrode 3B) The second external electrode 3B is preferably disposed from the fourth face F4 to the first face F1, the second face F2, the fifth face F5, and the sixth face F6.

[0043] The second external electrode 3B has a first base electrode layer 31B of the second external electrode connected to the first internal electrode 15A and arranged from the fifth face F5 to the first face F1, a second base electrode layer 32B of the second external electrode connected to the first internal electrode 15A and arranged from the sixth face F6 to the first face F1, a second resin electrode layer 34B arranged on the first base electrode layer 31B of the second external electrode, the first face F1, and the second base electrode layer 32B of the second external electrode, and a second plating layer 36B arranged on the second resin electrode layer 34B.

[0044] The structure of the multilayer ceramic capacitor 1 is generally symmetrical in the first direction L. The configuration of the second external electrode 3B and its surrounding configuration generally correspond to the configuration of the first external electrode 3A and its surrounding configuration. The configuration of the first base electrode layer 31B of the second external electrode corresponds to the configuration of the first base electrode layer 31A of the first external electrode, the configuration of the second base electrode layer 32B of the second external electrode corresponds to the configuration of the second base electrode layer 32A of the first external electrode, the configuration of the second resin electrode layer 34B corresponds to the configuration of the first resin electrode layer 34A, and the configuration of the second plating layer 36B corresponds to the configuration of the first plating layer 36A. Therefore, a detailed description of the configuration of the second external electrode 3B and its surrounding configuration will be omitted.

[0045] (Third External Electrode 3C) The third external electrode 3C is preferably disposed from the fifth face F5 across the first face F1 and the second face F2.

[0046] The third external electrode 3C has a third base electrode layer 37C connected to the second internal electrode 15B and arranged from the fifth face F5 to the first face F1, and a third plating layer 38C.

[0047] The third base electrode layer 37C is preferably disposed from the fifth face F5 to the first face F1 and the second face F2.

[0048] The third base electrode layer 37C is a baked layer containing, for example, a conductive metal and glass. The conductive metal is, for example, Ni, Cu, Ag, Pd, Au, an Ag—Pd alloy, or the like, and is preferably Cu.

[0049] The third base electrode layer 37C is connected to the first lead portion 15Ab that is drawn to the center of the fifth surface F5 in the first direction L. In other words, the third external electrode 3C is connected to the second lead portion 15Bb that is drawn to the center of the fifth surface F5 in the first direction L.

[0050] The third plating layer 38C is disposed on the third base electrode layer 37C. The third plating layer 38C is composed of, for example, at least one metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or an alloy containing such a metal. Although not shown, the third plating layer 38C includes, for example, a Ni plating layer disposed on the third base electrode layer 37C and a Sn plating layer disposed on the Ni plating layer. However, the configuration of the third plating layer 38C is not limited to this and may be, for example, a single-layer structure.

[0051] (Fourth External Electrode 3D) The fourth external electrode 3D is preferably disposed from the sixth face F6 across the first face F1 and the second face F2.

[0052] The fourth external electrode 3D has a fourth base electrode layer 37D connected to the second internal electrode 15B and arranged from the sixth face F6 to the first face F1, and a fourth plating layer 38D.

[0053] The structure of the multilayer ceramic capacitor 1 is generally symmetrical in the second direction W. The configuration of the fourth external electrode 3D and its surrounding configuration generally correspond to the configuration of the third external electrode 3C and its surrounding configuration. The configuration of the fourth base electrode layer 37D corresponds to the configuration of the third base electrode layer 37C, and the configuration of the fourth plating layer 38D corresponds to the configuration of the third plating layer 38C. Therefore, a detailed description of the configuration of the fourth external electrode 3D and its surrounding configuration will be omitted.

[0054] The first base electrode layer 31A of the first external electrode, the second base electrode layer 32A of the first external electrode, the third base electrode layer 37C, and the fourth base electrode layer 37D may be collectively referred to as the "base electrode layers 31, 32, 37." The first plating layer 36A, the second plating layer 36B, the third plating layer 38C, and the fourth plating layer 38D may be collectively referred to as the "plating layers 36, 38."

[0055] 6, the first surface F1 has a first region 21, which is a region sandwiched between a region where the first base electrode layer 31A of the first external electrode is disposed and a region where the second base electrode layer 32A of the first external electrode is disposed, and is a region where the first resin electrode layer 34A is disposed. Of the first surface F1, the region sandwiched between the region where the first base electrode layer 31A of the first external electrode is disposed and the region where the second base electrode layer 32A of the first external electrode is disposed is, for example, the first region 21 over the entire region.

[0056] The first region 21 includes a central position in the second direction W of the laminate 2. The first base electrode layer 31A of the first external electrode and the second base electrode layer 32A of the first external electrode are, for example, spaced apart from a position overlapping the central position in the second direction W of the laminate 2 and the stacking direction T.

[0057] In addition, the "central position in the second direction W of the laminate 2" refers to the position in the laminate 2 that overlaps with the central line CL in the stacking direction T when a straight line (referred to as the "central line CL") parallel to the first direction L passing through the central part of the second direction W of the third surface F3 is drawn in a planar view of the stacking direction T of the laminate 2.

[0058] The dimension of the first region 21 in the second direction W is equal to or greater than one-third of the dimension of the laminate 2 in the second direction W. The separation distance in the second direction W between the first base electrode layer 31A of the first external electrode and the second base electrode layer 32A of the first external electrode is equal to or greater than one-third of the dimension of the laminate 2 in the second direction W.

[0059] The dimension in the second direction W of the portion of the first base electrode layer 31A of the first external electrode that is located on the first surface F1 is 10 μm or more. The dimension in the second direction W of the portion of the second base electrode layer 32A of the first external electrode that is located on the first surface F1 is 10 μm or more.

[0060] The distance in the first direction L from the tip of the first base electrode layer 31A of the first external electrode in the first direction L to the periphery of the first resin electrode layer 34A is 5 μm or more.

[0061] The shortest distance between the first plating layer 36A and the third plating layer 38C (referred to as "distance D4") is 100 μm or more.

[0062] The configuration of the multilayer ceramic capacitor 1 is generally symmetrical with respect to the stacking direction T. Therefore, the configuration of the second surface F2 and the configuration around the second surface F2 generally correspond to the configuration of the first surface F1 and the configuration around the first surface F1. Detailed description of the configuration of the second surface F2 and the configuration around the second surface F2 will be omitted.

[0063] (Method of measuring dimensions and distances)

[0064] The dimensions D1, D21, D22, distance D3, and distance D4 are each measured using a microscope at a magnification of 50 to 100 times.

[0065] When the dimensions D1, D21, D22, and distance D3 are measured, the first resin electrode layer 34A, the first base electrode layer 31A of the first external electrode, and the second base electrode layer 32A of the first external electrode are appropriately exposed. The first resin electrode layer 34A, the first base electrode layer 31A of the first external electrode, and the second base electrode layer 32A of the first external electrode are exposed, for example, by polishing.

[0066] A virtual straight line including a line segment that connects the first underlying electrode layer 31A of the first external electrode and the second underlying electrode layer 32A of the first external electrode over the shortest distance and is parallel to the second direction W is defined as a "reference line SL1." The dimensions D1, D21, and D22 are measured on the reference line SL1.

[0067] (Method for manufacturing the multilayer ceramic capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of the embodiment will be described. Note that the method for forming the second external electrode 3B corresponds to the method for forming the first external electrode 3A, and the method for forming the fourth external electrode 3D corresponds to the method for forming the third external electrode 3C. Therefore, the methods for forming the second external electrode 3B and the fourth external electrode 3D will not be described here.

[0068] (Internal electrode pattern forming process) First, ceramic green sheets are prepared by forming ceramic slurry into sheets. Next, patterns of the first internal electrodes 15A and the second internal electrodes 15B are printed on the ceramic green sheets using a conductive paste. This results in ceramic green sheets on which the first internal electrodes 15A are arranged and ceramic green sheets on which the second internal electrodes 15B are arranged. The patterns of the first internal electrodes 15A and the second internal electrodes 15B are formed by printing, for example, screen printing, gravure printing, letterpress printing, or the like.

[0069] (Laminating Process) Next, the ceramic green sheets on which the first internal electrodes 15A are arranged and the ceramic green sheets on which the second internal electrodes 15B are arranged are alternately laminated. Next, on both sides of the laminated ceramic green sheets in the lamination direction T, ceramic green sheets for outer layer portions, which will become the outer layer portions 12, are laminated. The ceramic green sheets for outer layer portions are thermocompression bonded to the ceramic green sheets. This results in a mother block.

[0070] Each outer layer portion 12 may be formed by laminating a plurality of ceramic green sheets or by a single ceramic green sheet. The ceramic green sheets for the inner layer portion and the ceramic green sheets for the outer layer portion may contain different components.

[0071] (Mother Block Cutting Process) Next, the mother block is divided along cutting lines corresponding to the dimensions of the laminate. The mother block is cut, for example, in a first direction L and a second direction W. This results in multiple rectangular blocks (referred to as "laminated chips"). It is preferable that the corners and ridges of the laminated chips are rounded, for example, by barrel polishing.

[0072] (Laminate Firing Step) Next, the laminated chip is heated at a predetermined firing temperature in a nitrogen atmosphere for a predetermined time, thereby obtaining the laminated body 2.

[0073] (Base electrode layer forming process) Next, a conductive paste containing copper and glass is applied onto the laminate 2. The conductive paste that will become the first base electrode layer 31A of the first external electrode and the conductive paste that will become the third base electrode layer 37C are applied, for example, from the fifth face F5 to the first face F1 and the second face F2, respectively. The conductive paste that will become the second base electrode layer 32A of the first external electrode is connected to the first internal electrode 15A and is applied, for example, from the sixth face F6 to the first face F1 and the second face F2.

[0074] (Base Electrode Layer Baking Process) Next, the laminate 2 on which the base electrode layers 31, 32, and 37 have been formed is heated in a nitrogen atmosphere at a predetermined baking temperature for a predetermined time, thereby baking the base electrode layers 31, 32, and 37 to the laminate 2. Note that the laminate baking process and the base electrode layer baking process may be performed simultaneously after the material for the base electrode layer 31 has been placed on the laminate chip.

[0075] (Resin Electrode Layer Forming Process) Next, a conductive resin paste containing a conductive resin and a metal component is prepared as the conductive resin paste that will become the first resin electrode layer 34A. The conductive resin paste is applied to the laminate 2 on which the base electrode layers 31, 32, and 37 have been formed, for example, onto the first base electrode layer 31A of the first external electrode, the first surface F1, and onto the second base electrode layer 32A of the first external electrode, the second surface F2, and the third surface F3. The application method is, for example, a dipping method.

[0076] (Resin electrode layer firing process) Next, the laminate 2 to which the conductive resin paste has been applied is subjected to a heat treatment. As the heat treatment, the laminate 2 is dried in a hot air oven at 150°C or higher and 180°C or lower for 10 minutes. Then, the laminate 2 is cured in an air atmosphere at 200°C or higher and 280°C or lower for 60 minutes. This thermal curing forms the first resin electrode layer 34A.

[0077] (Plating Process) Next, a first plating layer 36A is formed on the first resin electrode layer 34A. For example, a Ni plating layer is formed on the first resin electrode layer 34A, and a Sn plating layer is formed on the Ni plating layer. A third plating layer is formed on the third base electrode layer 37C. For example, a Ni plating layer is formed on the first resin electrode layer 34A, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, electrolytic plating.

[0078] As a result of the above, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0079] Experimental Examples Multilayer ceramic capacitors were fabricated as samples of examples and comparative examples by the above-described manufacturing method. Using the obtained samples, a substrate bending test and a moisture resistance test were carried out.

[0080] 1. Fabrication of Multilayer Ceramic Capacitor As a sample of the example, a multilayer ceramic capacitor having a structure similar to that of the multilayer ceramic capacitor 1 described above (the structure shown in FIGS. 1 to 6) was fabricated. The dimensions of the multilayer ceramic capacitor were L×W×T = 1.0 mm×0.5 mm×0.5 mm. The base electrode layers 31, 32, and 37 contained Cu as a primary component and Si as a glass component. The first resin electrode layer 34A contained epoxy resin as a thermosetting resin and Ag as a metal component. The first plating layer 36A had a two-layer structure consisting of a Ni plating layer and a Sn plating layer. The method for fabricating the sample multilayer ceramic capacitor was the same as that described in the description of the embodiment.

[0081] Experimental Examples 1 to 8 were set as examples. For each example, the dimension in the second direction W of the portion of the first base electrode layer 31A of the first external electrode located on the first surface F1 (sometimes referred to as the "first base electrode layer W dimension of the first external electrode") and the dimension in the second direction W of the portion of the second base electrode layer 32A of the first external electrode located on the first surface F1 (sometimes referred to as the "second base electrode layer W dimension of the first external electrode") were changed. For each example, the distance in the second direction W between the first base electrode layer 31A of the first external electrode and the second base electrode layer 32A of the first external electrode on the first surface F1 (in other words, the dimension in the second direction W of the first region 21; sometimes referred to as the "first region W dimension") was changed. Note that, in each example and comparative example, the dimension in the first base electrode layer W of the first external electrode and the dimension in the second base electrode layer W of the first external electrode were the same.

[0082] The W dimension of the first base electrode layer of the first external electrode and the W dimension of the second base electrode layer of the first external electrode were gradually decreased from Example 1 to Example 8. The W dimension of the first region was gradually increased from Example 1 to Example 8. Table 1 shows the W dimension of the first base electrode layer of the first external electrode, the W dimension of the second base electrode layer of the first external electrode, and the W dimension of the first region for each Example.

[0083] In Examples 1 to 4, the dimension of the first region W was set as a ratio to the dimension of the laminate in the second direction W (sometimes referred to as the "laminated body W dimension"). In Examples 5 to 8, the dimension of the first region W was set as an absolute value of the dimension (μm).

[0084] Comparative Example 1 was set as a comparative example. A multilayer ceramic capacitor having a structure generally similar to that of the sample of Experimental Example 1 was fabricated as a sample of Comparative Example 1. However, the first resin electrode layer 34A was not provided in the multilayer ceramic capacitor of the comparative example, and instead a base electrode layer was provided. Therefore, in the comparative example, the first plating layer 36A was disposed directly on the first base electrode layer 31A of the first external electrode.

[0085] In Comparative Example 1, the first resin electrode layer 34A is not disposed on the first surface F1. Therefore, in Comparative Example 1, the first surface F1 does not have the first region 21. For this reason, in Table 1, the dimension of the first region W of Comparative Example 1 is marked with "-".

[0086] 2. Evaluation Next, the prepared samples were evaluated by the following methods.

[0087] <Substrate Bending Test> The substrate bending test was a test to confirm the susceptibility of cracks to occur in the laminate. Each sample was mounted on a substrate using solder. Next, a metal push rod with a diameter of 1.0 mm was pressed against the surface of the substrate on which the multilayer ceramic capacitor was not mounted, thereby bending the substrate. The substrate was bent by 3.0 mm and held for 60 seconds, applying mechanical stress to the substrate and the multilayer ceramic capacitor. Next, it was confirmed whether cracks occurred in the laminate. For each example and comparative example, the test was performed on 50 samples. The number of samples in which cracks were observed for each example and comparative example is shown in Table 1.

[0088] <Moisture Resistance Test> The moisture resistance test is a test to confirm moisture resistance reliability. Each sample was mounted on a substrate using solder. Next, each sample was placed in a high-temperature, high-humidity chamber at a temperature of 125°C and a relative humidity of 95% RH, and tested under conditions of a voltage of 4 V and a test time of 144 hours. Samples whose insulation resistance value (IR value) decreased by two or more digits were determined to have deteriorated moisture resistance. Tests were conducted on 72 samples for each example and comparative example. The number of samples whose moisture resistance deteriorated for each example and comparative example is shown in Table 1.

[0089] <Determination of Pass / Fail> A determination of pass / fail was made for each of the Examples and Comparative Examples. When the number of samples in which cracks occurred was 5 or less and the number of samples in which moisture resistance was deteriorated was 2 or less, the result was determined to be "pass".

[0090] In cases where the number of samples in which cracks occurred was 20 or less and the number of samples in which moisture resistance was degraded was 10 or less, and the judgment did not fall under "good," the judgment was made "generally good."

[0091] When the number of samples in which cracks occurred was more than 20, or when the number of samples in which moisture resistance was deteriorated was more than 10, the sample was judged to be "poor."

[0092]

[0093] 3. Measurement Results Table 1 shows the laminate W dimension, the results of the substrate bending test, the results of the moisture resistance test, and the evaluation results for the comparative example and experimental examples 1 to 8.

[0094] As shown in Table 1, when the first resin electrode layer 34A was not provided in the laminate 2 (in other words, when the first region 21 did not have the first region 21), cracks were confirmed in more than 10 samples in the substrate bending test (see Comparative Example 1). In addition, good results were obtained in the moisture resistance test.

[0095] When the dimension of the first region W was 100 μm or more (one-fifth the dimension of the laminate W), the evaluation result was good or generally good (see Examples 1 to 8).

[0096] This confirmed that the occurrence of cracks can be suppressed by providing the first resin electrode layer 34A in the laminate 2. Furthermore, it was confirmed that when the dimension of the first region 21 in the second direction W is equal to or greater than 1 / 5 of the dimension of the laminate 2 in the second direction W, the occurrence of cracks can be suppressed while ensuring moisture resistance reliability.

[0097] Furthermore, when the dimension of the first region W was 167 μm or more (one-third of the dimension of the laminate W), the number of samples in which cracks occurred in the substrate bending test was 10 or less (see Examples 2 to 8).

[0098] This confirmed that when the dimension of the first region 21 in the second direction W is 1 / 3 or more of the dimension of the laminate 2 in the second direction W, the occurrence of cracks can be more effectively suppressed while ensuring moisture resistance reliability.

[0099] When the first region W dimension was 480 μm or less (i.e., when the first base electrode layer W dimension of the first external electrode was 10 μm or more and the second base electrode layer W dimension of the first external electrode was 10 μm or more), the number of samples whose moisture resistance deteriorated in the moisture resistance test was two or less (see Examples 1 to 6). On the other hand, when the first region W dimension was 482 μm (when the first base electrode layer W dimension of the first external electrode was 9 μm and the second base electrode layer W dimension of the first external electrode was 9 μm), the number of samples whose moisture resistance deteriorated in the moisture resistance test was three (see Example 7).

[0100] This confirmed that moisture resistance reliability can be more suitably ensured when the dimension in the second direction W of the portion of the first base electrode layer 31A of the first external electrode that is arranged on the first surface F1 is 10 μm or more, and the dimension in the second direction of the portion of the second base electrode layer 32A of the first external electrode that is arranged on the first surface F1 is 10 μm or more.

[0101] The larger the first region W dimension (the smaller the W dimension of the first base electrode layer of the first external electrode and the W dimension of the second base electrode layer of the first external electrode), the better the results of the substrate bending test. On the other hand, the smaller the first region W dimension (the larger the W dimension of the first base electrode layer of the first external electrode and the W dimension of the second base electrode layer of the first external electrode), the better the results of the moisture resistance test.

[0102] When the first region W dimension was 480 μm (i.e., when the W dimension of the first base electrode layer of the first external electrode was 10 μm and the W dimension of the second base electrode layer of the first external electrode was 10 μm), the number of defective samples in the substrate bending test and the number of defective samples in the moisture resistance test were each one (see Example 3). When the W dimension of the first base electrode layer of the first external electrode was 10 μm and the W dimension of the second base electrode layer of the first external electrode was 10 μm, particularly good results were obtained in terms of both suppressing crack occurrence and improving moisture resistance reliability.

[0103] (Effects of the Embodiment) According to the present embodiment, the following effects can be obtained.

[0104] The multilayer ceramic capacitor 1 includes an inner layer portion 11 including a plurality of dielectric layers 14 and a plurality of internal electrodes 15 stacked alternately, a laminate 2 having a first face F1 and a second face F2 facing a stacking direction T, a third face F3 and a fourth face F4 facing a first direction L orthogonal to the stacking direction T, and a fifth face F5 and a sixth face F6 facing a second direction W orthogonal to the stacking direction T and the first direction L, and an external electrode 3 arranged on an outer surface of the laminate 2. The plurality of internal electrodes 15 include a first internal electrode 15A extended to the fifth face F5 and the sixth face F6, and a second internal electrode 15B facing the first internal electrode 15A and extended to the fifth face F5. The external electrode 3 includes a first external electrode 3A connected to the first internal electrode 15A and arranged from the third face F3 to the first face F1, the fifth face F5, and the sixth face F6, a second external electrode 3B connected to the first internal electrode 15A and arranged from the fourth face F4 to the first face F1, the fifth face F5, and the sixth face F6, and a third external electrode 3C connected to the second internal electrode 15B and arranged from the fifth face F5 to the first face F1. The first external electrode 3A includes a first base electrode layer 31A of the first external electrode connected to the first internal electrode 15A and disposed from the fifth face F5 to the first face F1, a second base electrode layer 32A of the first external electrode connected to the first internal electrode 15A and disposed from the sixth face F6 to the first face F1, a first resin electrode layer 34A disposed on the first base electrode layer 31A of the first external electrode, the first face F1, and the second base electrode layer 32A of the first external electrode, and a first plating layer 36A disposed on the first resin electrode layer 34A. The first face F1 has a first region 21 between the region where the first base electrode layer 31A of the first external electrode is disposed and the region where the second base electrode layer 32A of the first external electrode is disposed, where the first resin electrode layer 34A is disposed. The first region 21 overlaps the center of the laminate 2 in the second direction W in the stacking direction T.

[0105] In a three-terminal multilayer ceramic capacitor, cracks that occur near the point where the tip of the external electrode facing the first direction L contacts the laminate are more likely to occur near the center of the external electrode in the second direction W.

[0106] However, with this configuration, the first surface F1 has a first region 21, which is a region between the region where the first base electrode layer 31A of the first external electrode is arranged and the region where the second base electrode layer 32A of the first external electrode is arranged, and is a region where the first resin electrode layer 34A is arranged. In this case, the first base electrode layer of the first external electrode and the second base electrode layer of the first external electrode are not arranged in a portion of the first region that overlaps with the center of the second direction W of the laminate in the stacking direction T. This makes it possible to suppress transmission of stress to the portion of the first surface F1 that overlaps with the center of the second direction W of the laminate in the stacking direction T via the first base electrode layer of the first external electrode and the second base electrode layer of the first external electrode.

[0107] Furthermore, a first resin electrode layer is disposed in a portion of the first region that overlaps with the center of the laminate in the second direction W and the stacking direction T. When a relatively large force acts on the first resin electrode layer 34A in a direction that separates the first external electrode 3A and the laminate 2, the first resin electrode layer 34A may, for example, be torn or peeled off from the laminate. Furthermore, when a force acts on the first resin electrode layer 34A in a direction that brings the first external electrode 3A and the laminate 2 closer to each other, the first resin electrode layer 34A functions as a buffer layer. Therefore, it is possible to suppress the transmission of stress to the portion of the first surface F1 that overlaps with the center of the laminate in the second direction W and the stacking direction T.

[0108] As a result, it is possible to suppress the transmission of stress to areas of the laminate 2 where cracks are likely to occur, and therefore it is possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks in the laminate 2.

[0109] The dimension of the first region 21 in the second direction W is equal to or greater than one-third of the dimension of the stack 2 in the second direction W.

[0110] According to this configuration, the size of the first region 21 can be ensured sufficiently, so that the occurrence of cracks can be more reliably suppressed.

[0111] The dimension in the second direction W of the portion of the first base electrode layer 31A of the first external electrode that is arranged on the first surface F1 is 10 μm or more, and the dimension in the second direction W of the portion of the second base electrode layer 32A of the first external electrode that is arranged on the first surface F1 is 10 μm or more.

[0112] If moisture penetrates into the laminate 2, the functionality of the multilayer ceramic capacitor 1 may be impaired. The portions of the surface of the laminate 2 where the internal electrodes 15 are drawn out are thought to be likely to serve as paths for moisture to penetrate into the laminate 2. In addition, moisture is thought to be likely to penetrate into the boundary between the tip end of the first base electrode layer 31A of the first external electrode in the second direction W and the first surface F1.

[0113] However, with this configuration, the boundary between the first surface F1 and the tip end of the first base electrode layer 31A of the first external electrode in the second direction W can be located sufficiently far from the portion of the fifth surface F5 where the internal electrode 15 is drawn out, thereby preventing moisture from reaching the portion of the fifth surface F5 where the internal electrode 15 is drawn out, and therefore preventing moisture from penetrating into the laminate 2.

[0114] The boundary between the first surface F1 and the tip end of the second base electrode layer 32A of the first external electrode in the second direction W can be located sufficiently far from the portion of the sixth surface F6 where the internal electrode 15 is drawn out. This prevents moisture from reaching the portion of the sixth surface F6 where the internal electrode 15 is drawn out, thereby preventing moisture from penetrating into the laminate 2. This improves the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0115] A distance D3 in the first direction L from the tip of the first base electrode layer 31A of the first external electrode in the first direction L to the periphery of the first resin electrode layer 34A is 5 μm or more.

[0116] With this configuration, the first resin electrode layer 34A can be more reliably interposed between the first plating layer 36A and the tip portion in the first direction L of the first base electrode layer 31A of the first external electrode. Therefore, the action of the first resin electrode layer 34A can suitably suppress the transmission of stress from the first plating layer 36A to the tip portion in the first direction L of the first base electrode layer 31A of the first external electrode. This can suitably suppress the occurrence of cracks in the laminate 2.

[0117] The third external electrode 3C has a third plating layer 38C, and the shortest distance D4 between the first plating layer 36A and the third plating layer 38C is 100 μm or more.

[0118] With this configuration, the first plating layer 36A and the third plating layer 38C can be sufficiently spaced apart, thereby suppressing the occurrence of a short circuit between the first external electrode 3A and the third external electrode 3C.

[0119] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0120] In the above embodiment, the configuration of the multilayer ceramic capacitor 1 is generally symmetrical with respect to the stacking direction T, but it does not necessarily have to be symmetrical with respect to the stacking direction T. For example, the first external electrode 3A does not necessarily have to be disposed on the second surface F2.

[0121] In the above embodiment, the configuration of the multilayer ceramic capacitor 1 is generally symmetrical in the first direction L, but it does not necessarily have to be symmetrical in the first direction L. Also, in the above embodiment, the configuration of the multilayer ceramic capacitor 1 is generally symmetrical in the second direction W, but it does not necessarily have to be symmetrical in the second direction W. For example, the second external electrode 3B does not necessarily have a configuration corresponding to the first external electrode 3A.

[0122] In the above embodiment, the first internal electrode 15A has a substantially H-shape when viewed in the stacking direction T, but the shape of the first internal electrode is not limited to this. The first internal electrode may have a lead portion that is connected to the first external electrode 3A and the second external electrode 3B, and that is exposed on the fifth surface to connect to the first external electrode 3A (the first base electrode layer 31A of the first external electrode), and a lead portion that is exposed on the sixth surface to connect to the first external electrode 3A (the second base electrode layer 32A of the first external electrode). For example, the first internal electrode may have two lead portions that are exposed on the fifth surface and one lead portion that is exposed on the sixth surface, and one of the two lead portions exposed on the fifth surface and the lead portion exposed on the sixth surface may be connected to the first external electrode, and the other of the two lead portions exposed on the fifth surface may be connected to the second external electrode.

[0123] In the above embodiment, the second internal electrode 15B has a substantially cross shape when viewed in the stacking direction T, but the shape of the second internal electrode is not limited to this. For example, the second internal electrode may have a plurality of portions exposed on the fifth surface, or a plurality of portions exposed on the sixth surface.

[0124] In the above embodiment, the multilayer ceramic capacitor 1 has one third external electrode 3C and one fourth external electrode 3D, but this is not limited thereto. The multilayer ceramic capacitor may have a plurality of third external electrodes or a plurality of fourth external electrodes.

[0125] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 External electrode 3A First external electrode 3B Second external electrode 3C Third external electrode 14 Dielectric layer 15 Internal electrode 15A First internal electrode 15B Second internal electrode 21 First region 31A First base electrode layer of first external electrode 32A Second base electrode layer of first external electrode 34A First resin electrode layer 36A First plating layer 38C Third plating layer F1 First surface F2 Second surface F3 Third surface F4 Fourth surface F5 Fifth surface F6 Sixth surface

Claims

1. A laminate having an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes, a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, and external electrodes arranged on the outer surface of the laminate, wherein the plurality of internal electrodes include first internal electrodes extended to the fifth surface and the sixth surface, and second internal electrodes opposed to the first internal electrodes and extended to the fifth surface, and the external electrodes include a first external electrode connected to the first internal electrode and arranged from the third surface to the first surface, the fifth surface, and the sixth surface, a second external electrode connected to the first internal electrode and arranged from the fourth surface to the first surface, the fifth surface, and the sixth surface, and a third external electrode connected to the second internal electrode and arranged from the fifth surface to the first surface, the first external electrode has: a first base electrode layer of the first external electrode connected to the first internal electrode and arranged from the fifth surface to the first surface; a second base electrode layer of the first external electrode connected to the first internal electrode and arranged from the sixth surface to the first surface; a first resin electrode layer arranged on the first base electrode layer of the first external electrode, the first surface, and the second base electrode layer of the first external electrode; and a first plating layer arranged on the first resin electrode layer; the first surface has a first region, which is a region between a region where the first base electrode layer of the first external electrode is arranged and a region where the second base electrode layer of the first external electrode is arranged, and the first region overlaps with a center portion of the laminate in the second direction in the stacking direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the dimension of said first region in said second direction is at least one-third of the dimension of said laminate in said second direction.

3. A multilayer ceramic capacitor as described in claim 2, wherein the dimension in the second direction of a portion of the first base electrode layer of the first external electrode that is arranged on the first surface is 10 μm or more, and the dimension in the second direction of a portion of the second base electrode layer of the first external electrode that is arranged on the first surface is 10 μm or more.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the distance in the first direction from the tip in the first direction of the first base electrode layer of the first external electrode to the periphery of the first resin electrode layer is 5 μm or more.

5. The multilayer ceramic capacitor according to claim 4, wherein the third external electrode has a third plating layer, and the shortest distance between the first plating layer and the third plating layer is 100 μm or more.

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