Rectifier circuit, inverter circuit, and power supply circuit

Abstract

A rectifier circuit (RC1) includes a two-series transistor (SC1) and a loss reduction circuit (LR1). The two-series transistor (SC1) is composed of a high breakdown voltage transistor (HT1) on the high voltage side and a low breakdown voltage transistor (LT1) on the low voltage side. The loss reduction circuit (LR1) is composed of a high breakdown voltage diode (HD1), a PMOS (PT1), and a buffer capacitor (BC1).

Description

Rectifier circuits, inverter circuits and power supply circuits

[0001] The following disclosure relates to a rectifier circuit, an inverter circuit, and a power supply circuit. This application claims priority to Japanese Patent Application No. 2024-107456, filed on July 3, 2024, the contents of which are incorporated herein by reference.

[0002] An example of the configuration of a rectifier circuit is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0003] JP 2016-220468 A

[0004] Even with such a rectifier circuit, there is still room for improvement.

[0005] Disclosed herein are low-loss rectifier circuits, inverter circuits, and power supply circuits.

[0006] In order to solve the above problems, a rectifier circuit according to one embodiment of the present disclosure includes two series-connected transistors and a loss reduction circuit. The two series-connected transistors are configured such that a high-voltage transistor is disposed on the high-voltage side and a low-voltage transistor is disposed on the low-voltage side. The high-voltage terminal of the low-voltage transistor is connected to the reference terminal of the high-voltage transistor. The control terminal of the high-voltage transistor is connected to the reference terminal of the low-voltage transistor directly or via a capacitor. The loss reduction circuit includes a high-voltage diode, a PMOS, and a buffer capacitor. The high-voltage diode has a cathode connected to the high-voltage terminal of the high-voltage transistor and an anode connected to the high-voltage terminal of the PMOS. The PMOS has a reference terminal connected to the positive electrode of the buffer capacitor and a control terminal connected to the reference terminal of the low-voltage transistor directly or via a capacitor. The buffer capacitor has a negative electrode connected to the reference terminal of the high-voltage transistor.

[0007] In order to solve the above problem, an inverter circuit according to one aspect of the present disclosure includes the above rectifier circuit.

[0008] In order to solve the above problem, a power supply circuit according to one aspect of the present disclosure includes the above rectifier circuit.

[0009] According to the present disclosure, it is possible to reduce losses in rectifier circuits and power supply circuits.

[0010] 1 is a diagram showing a rectifier circuit of the present disclosure; 2 is a diagram showing a modified example of the rectifier circuit of the present disclosure; 3 is a diagram showing an operating waveform of the rectifier circuit of the present disclosure when a reverse voltage transition occurs; 4 is a diagram showing an operating waveform of the rectifier circuit of the present disclosure when a forward voltage transition occurs; 5 is a diagram showing a power supply circuit including the rectifier circuit of the present disclosure;

[0011] [Embodiment 1] The abbreviations used in this specification are as follows: MOS stands for metal-oxide-semiconductor field-effect transistor, SJMOS stands for super-junction metal-oxide-semiconductor field-effect transistor, IGBT stands for insulated-gate bipolar transistor, JFET stands for junction field effect transistor, and HEMT stands for high electron mobility transistor. COSS stands for the total parasitic capacitance between the high-voltage terminal and the reference terminal, and between the high-voltage terminal and the control terminal, of a transistor described below. The reverse recovery current includes not only the charge that flows backward until carriers disappear when the PN junction is reverse biased, but also the charge that charges the parasitic capacitance. Furthermore, the reverse recovery current also includes the charge that flows backward through the channel of the high-voltage transistor in the period from when the low-voltage transistor is turned off until the high-voltage transistor reaches the off state in a two-series transistor configuration described below.

[0012] A transistor is defined as follows: A transistor has a control terminal, a reference terminal, and a high-voltage terminal; applying a voltage to the control terminal relative to the reference terminal turns the transistor on. When the transistor is on, it allows current to flow from the high-voltage terminal to the reference terminal, or from the reference terminal to the high-voltage terminal. When an N-type transistor is off, it receives a voltage at the high-voltage terminal relative to the reference terminal, limiting current conduction. In contrast, a P-type transistor receives a negative voltage and suppresses negative current conduction. Unless otherwise specified, MOS refers to N-type MOS, and P-type MOS is written as PMOS. Transistors include MOS, SJMOS, IGBT, GaN-HEMT, SiC-JFET, etc., which have the above definitions of on and off.

[0013] In this specification, as an example of the notation of the reference numerals in the drawings, the rectifier circuit RC1 is also simply referred to as RC1.

[0014] (Overview of Embodiment 1) This embodiment discloses a boost circuit UC1 in which the rectifier section of a typical boost circuit is replaced with a rectifier circuit RC1. UC1 shown in FIG. 1 uses 200 V from an input power supply DC1 to supply 400 V to an output capacitor OC1. UC1 includes a switching element SW1, which is an SJMOS with a breakdown voltage of 600 V and an on-resistance of 50 mΩ, a 1 mH coil CO1, and RC1. A load is connected in parallel to CO1. The negative terminal of OC1 is the same node as the negative terminal of DC1, which is the low-voltage side. The other end of OC1, which is the positive terminal, is the high-voltage side. The upper side of the figure is the high-voltage side, and the lower side is the low-voltage side.

[0015] (Basic Configuration of Rectifier Circuit RC1) RC1 includes two series-connected transistors SC1 and a loss reduction circuit LR1. SC1 has the following configuration: A high-voltage transistor HT1 is arranged on the high-voltage side, and a low-voltage transistor LT1 is arranged on the low-voltage side. The high-voltage terminal of LT1 is connected to the reference terminal of HT1. The control terminal of HT1 is connected to the reference terminal of LT1 directly or via a capacitor. LR1 has the following configuration: It includes a high-voltage diode HD1, a PMOS transistor PT1, and a buffer capacitor BC1. The cathode of HD1 is connected to the high-voltage terminal of HT1, and the anode is connected to the high-voltage terminal of PT1. The reference terminal of PT1 is connected to the positive electrode of BC1, and the control terminal is connected to the reference terminal of LT1 directly or via an optional capacitor. The negative electrode of BC1 is connected to the reference terminal of HT1. In this embodiment, the control terminal of PT1 is connected to the positive electrode of AC1.

[0016] (Additional Circuits to Loss Reduction Circuit LR1) In this embodiment, an absorption diode AD1, an absorption capacitor AC1, and a pump diode PD1 are added to LR1. These AD1, AC1, and PD1 are considered as additional elements of LR1. The anode of AD1 is connected to the high-voltage terminal of LT1. The positive electrode of AC1 is connected to the cathode of AD1, and the negative electrode is connected to the reference terminal of LT1. The anode of PD1 is connected to the positive electrode of AC1, and the cathode is connected to the positive electrode of BC1.

[0017] With the above-described configuration of RC1, the loss generated in HT1 can be reduced by LR1. Without LR1, the reverse recovery current generated in HT1 would flow from the high-voltage OC1 via HT1, LT1, and SW1 back to OC1, resulting in large losses. LR1 reduces losses by directing the reverse recovery current back to the low-voltage BC1 via PT1, HD1, and HT1, returning to BC1.

[0018] (Details of Each Element of the Two-Series Transistor SC1) HT1 is an SJMOS with a breakdown voltage of 600V, an on-resistance of 90mΩ, and a threshold voltage of 6V. The gate capacitor GC1 of the high-voltage transistor is a multilayer ceramic capacitor supplied with 15V via an external power supply. LT1 is an MOS with a breakdown voltage of 30V, an on-resistance of 4mΩ, and a threshold voltage of 2V. The drain breakdown voltage of LT1 is set to 0.2 times or less the drain breakdown voltage of HT1 to reduce the increase in parasitic capacitance due to serialization. The on-resistance of LT1 is set to less than half the on-resistance of HT1 to reduce the increase in resistance due to serialization. A gate drive circuit (not shown) is connected to the control terminal of LT1 to control the on / off of LT1. The 15V of GC1 is set to be greater than or equal to the threshold voltage of HT1, so that HT1 can be turned on when LT1 is on. GC1 can be eliminated if the threshold voltage of HT1 is 0V or less.

[0019] (Details of each element of loss reduction circuit LR1) The breakdown voltage of HD1 is 600V, which is set in the range of 0.5 to 1.5 times the drain breakdown voltage of HT1. The parasitic capacitance of HD1 is 10pF, which is set to half or less of the parasitic capacitance of HT1, 50pF. The reverse recovery time of HD1 is half or less of the reverse recovery time of HT1, and preferably 0.1nsec or more. BC1 is a multilayer ceramic capacitor, and its voltage is set to 17V. PT1 is a PMOS with a drain breakdown voltage of 30V, an on-resistance of 50mΩ, and a threshold value of 2V. The threshold value of the PMOS is preferably 0.5V to 20V.

[0020] (Details of elements added to loss reduction circuit LR1) AD1 and PD1 are Schottky barrier diodes with a breakdown voltage of 30 V. AC1 is a multilayer ceramic capacitor, and its voltage is set to 18 V.

[0021] The voltages of BC1 and AC1 and the withstand voltages of PT1, AD1 and PD1 are suitable for reducing losses if they are not more than twice the drain withstand voltage of LT1 and are not less than 5V.

[0022] (Another Connection Example of the Control Terminal of PMOS PT1) Here, another connection example of the control terminal of PT1 is disclosed using FIG. 2. The difference between the rectifier circuits RC2 and RC1 shown in FIG. 2 is that RC2 includes a loss reduction circuit LR2 instead of LR1. The difference between LR2 and LR1 is that LR2 includes a gate drive capacitor CG2, a gate drive resistor RG2, and a pull-down resistor DR2. FIG. 2 only shows the changes from FIG. 1 and the reference symbols required for explanation; the rest is the same as RC1 in FIG. 1. The control terminal of PT1 is connected to the reference terminal of LT1 via CG2. RG2 is connected in parallel to both ends of CG2. DR2 is connected between the control terminal and reference terminal of PT1. This control terminal connection using CG2 also makes it possible to reduce losses in SC1.

[0023] (Key Points of Circuit Operation of Rectifier Circuit RC1) The main circuit operation of RC1 is to turn off LT1, charge COSS of LT1 with current flowing from the high-voltage side via HT1, increase the voltage at the high-voltage terminal of LT1, and raise the voltage between the reference terminal and control terminal of PT1 to 0.5 V or higher. In this embodiment, PT1 turns on when the voltage between the reference terminal and control terminal of PT1 reaches 2 V or higher. Turning PT1 on allows the reverse recovery current of HT1 to flow from the low-voltage BC1. The reverse recovery current from the low-voltage BC1 has less loss than the reverse recovery current from the high-voltage OC1.

[0024] (Details of Circuit Operation of Rectifier Circuit RC1) Figures 3 and 4 are composed of five graphs, and the horizontal axis is the same for all five graphs. V_RC1 is the voltage of RC1 after the underscore, and V_AC1 and V_BC1 have the same meaning. V_LT1GS is the voltage at the control terminal of LT1, V_LT1DS is the voltage at the high-voltage terminal of LT1, and V_PT1SG is the voltage at the control terminal of PT1 with the polarity reversed. I_RC1 is the forward current of RC1, and the same is true for I_AD1 and I_PD1. I_HD1 is the forward current of HD1 with the polarity reversed. I_RC1 was measured at the current measurement location CP1 in Figure 1. Figure 3 shows the time period when reverse voltage application to RC1 begins, and Figure 4 shows the time period when forward voltage application to RC1 begins.

[0025] The circuit operation from turning off LT1 to the generation of reverse recovery current will be explained using Figure 3. After turning off LT1, turning on SW1 applies a reverse voltage to RC1. V_LT1GS drops, and V_RC1 rises as SW1 turns on. Reverse recovery current flowing from the high voltage side through HT1 charges COSS of LT1, causing V_LT1DS to rise. The rise in voltage of V_LT1DS increases the voltage of V_PT1SG, turning on PT1. The rise in voltage at the high voltage terminal of LT1 causes current from HT1 to charge AC1 via AD1. The graph shows that I_AD1 increases V_AC1, charging AC1.

[0026] When PT1 is turned on, a reverse recovery current of HT1 flows from BC1 through PT1 and HD1. Forward conduction of I_HD1 can be confirmed. Immediately after that, the voltage at the high voltage terminal of HT1 becomes higher than BC1, causing a reverse recovery current of HD1 to flow, after which HD1 turns off. The graph shows that forward conduction of I_HD1 causes V_BC1 to drop, discharging BC1.

[0027] (Loss Reduction Effect of Loss Reduction Circuit LR1) The negative I_RC1 flowing at 6.0E-07 seconds is the reverse recovery current of RC1 from OC1. When LR1 is not implemented, the reverse recovery current is 260 nC, whereas in this embodiment, the reverse recovery current is 180 nC, which means that the reverse recovery current from OC1 is reduced. This reduces the loss in the rectifier circuit.

[0028] (Power Supply to Loss Reduction Circuit LR1 by Additional Elements) After the reverse recovery current of RC1 flows, turning off SW1 at any timing applies a forward voltage to RC1, causing the circuit to conduct rectified current through RC1. The circuit operation during this period will be explained using Figure 4. The conduction of the positive rectified current I_RC1 discharges COSS of LT1, lowering V_LT1DS and V_PT1SG and turning off PT1. At the same time, BC1 is charged from AC1 via PD1. I_PD1 confirms the decrease in V_AC1, which is the discharge of AC1, and the increase in V_BC1, which is the charge of BC1. In this way, BC1 can be supplied with power by the additional element of LR1.

[0029] (When no additional elements are implemented in the loss reduction circuit LR1) Even when no additional elements are implemented in the loss reduction circuit LR1, LR1 can reduce the reverse recovery current of RC1. Specifically, by providing an external power supply connected to BC1 and supplying power from that external power supply to BC1, it becomes possible to reduce the reverse recovery current.

[0030] [Embodiment 2] RC1 can be replaced with various rectifier units or rectifier circuits. Figure 5 shows an example of a configuration in which RC1 and RC2 are used in the rectifier unit of an inverter circuit IN5. IN5 is incorporated into a power supply circuit PC5. PC5 can reduce power loss by reducing the reverse recovery current of RC1 or RC2.

[0031] Please note that the values ​​given above are merely examples. To adjust the circuit operation, it is possible to insert a resistor in the wiring, add a capacitor between two wirings to increase the capacitance, etc.

[0032] [Additional Notes] The presently contemplated embodiments of the invention disclosed above may be modified in various ways as needed, and it is intended that such modifications be incorporated into the scope of the appended claims insofar as they fall within the scope of the present invention.

Claims

1. A rectifier circuit comprising two series-connected transistors and a loss reduction circuit, wherein the two series-connected transistors are configured such that a high-voltage transistor is arranged on the high-voltage side and a low-voltage transistor is arranged on the low-voltage side, the high-voltage terminal of the low-voltage transistor is connected to a reference terminal of the high-voltage transistor, and the control terminal of the high-voltage transistor is connected to the reference terminal of the low-voltage transistor directly or via a capacitor, the loss reduction circuit is configured such that a high-voltage diode, a PMOS, and a buffer capacitor are provided, the high-voltage diode having a cathode connected to the high-voltage terminal of the high-voltage transistor and an anode connected to the high-voltage terminal of the PMOS, the PMOS having a reference terminal connected to the positive electrode of the buffer capacitor and a control terminal connected to the reference terminal of the low-voltage transistor directly or via a capacitor, the rectifier circuit comprising:

2. The rectifier circuit according to claim 1, wherein the loss reduction circuit further comprises an absorption diode, an absorption capacitor, and a pump diode, the absorption diode having an anode connected to the high-voltage terminal of the low-voltage transistor, the absorption capacitor having a positive electrode connected to the cathode of the absorption diode and a negative electrode connected to the reference terminal of the low-voltage transistor, and the pump diode having an anode connected to the positive electrode of the absorption capacitor and a cathode connected to the positive electrode of the buffer capacitor.

3. The rectifier circuit according to claim 1, wherein the rectifier circuit operates by turning off the low-voltage transistor, charging the COSS of the low-voltage transistor with a current flowing from the high-voltage side through the high-voltage transistor, increasing the voltage of the high-voltage terminal of the low-voltage transistor, and causing the voltage between the reference terminal and control terminal of the PMOS to become 0.5 V or higher.

4. An inverter circuit comprising the rectifier circuit of claim 1.

5. A power supply circuit comprising the rectifier circuit according to claim 1.

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