Electronic device

Abstract

This electronic device comprises: a driving element layer including a pixel driving unit; a light-emitting element comprising a first electrode, an intermediate layer disposed on the first electrode and including at least a light-emitting layer, and a second electrode disposed on the intermediate layer; a pixel defining layer in which an opening exposing at least a portion of the first electrode is defined; a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driving unit and the second electrode; a connection wiring disposed between the pixel driving unit and the pixel defining layer and electrically connected to the pixel driving unit and the connection electrode; and a separator disposed on the pixel defining layer, wherein the second electrode is in contact with the connection electrode at a first contact region adjacent to the separator and at a second contact region adjacent to a side surface of the connection wiring.

Description

electronic devices

[0001] The present invention relates to an electronic device with improved contact reliability.

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, and game consoles feature display panels for displaying images. Display panels include light-emitting elements and circuits for driving the light-emitting elements. The light-emitting elements included in the display panel emit light and generate images in response to voltage applied by the circuit. Research is being conducted on the connection between light-emitting elements and circuits to improve the reliability of display panels.

[0003] The present invention aims to provide an electronic device with improved contact reliability.

[0004] An electronic device according to an embodiment of the present invention includes a driving element layer including a pixel driving unit, a light-emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode and including at least a light-emitting layer, and a second electrode disposed on the intermediate layer, a pixel defining layer disposed on the driving element layer and having an opening defining an opening exposing at least a portion of the first electrode, a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driving unit and the second electrode, a connection wire disposed between the pixel driving unit and the pixel defining layer and electrically connected to the pixel driving unit and the connection electrode, and a separator disposed on the pixel defining layer, wherein in each of a first contact area adjacent to the separator and a second contact area adjacent to a side surface of the connection wire, the second electrode can contact the connection electrode.

[0005] In the first contact area, the lower surface of the second electrode can be in contact with the upper surface of the connecting electrode.

[0006] A tip portion is defined at least in a portion of the edge of the above connecting wire, and the second contact area may be adjacent to the tip portion.

[0007] The above connecting wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and each side of the first layer and the third layer may protrude more than a side of the second layer.

[0008] One end of the connecting electrode is connected to the side surface of the second layer, and one end of the second electrode can be in contact with the one end of the connecting electrode connected to the side surface of the second layer.

[0009] Each of the other end of the connecting electrode and the other end of the second electrode can be disposed on the upper surface of the first layer.

[0010] The one end of the above connecting electrode can contact the side surface of the second layer.

[0011] The electronic device further includes a capping pattern disposed between the connecting wire and the connecting electrode, one end of the capping pattern is in contact with the side surface of the second layer, the other end of the capping pattern is disposed on the upper surface of the first layer, and the one end of the second electrode can be in contact with the one end of the capping pattern that is in contact with the side surface of the second layer.

[0012] The first through hole defined in the pixel definition film can expose the tip portion defined in at least a portion of the edge of the connecting wiring.

[0013] The electronic device further includes an intermediate insulating layer, wherein the driving element layer is disposed below the pixel defining film and covers a portion of the connection wiring, and a second through hole defined in the intermediate insulating layer can expose the tip portion defined at least in a portion of the edge of the connection wiring.

[0014] The electronic device further includes a lower insulating layer disposed between the driving element layer and the connection wiring, and the connection wiring can be connected to the pixel driving unit through a contact hole penetrating the lower insulating layer.

[0015] The above connecting electrode has a ring shape and surrounds the opening, and the first contact area has a ring shape and can surround at least a portion of the opening.

[0016] The above connecting electrode includes a first edge and a second edge surrounding the first edge, and the second edge can overlap the separator.

[0017] A portion of the above connecting electrode may be covered by the separator.

[0018] The light-emitting element includes a plurality of light-emitting elements, the pixel driver includes a plurality of pixel drivers, the connecting electrode includes a plurality of connecting electrodes, the plurality of connecting electrodes electrically connect the plurality of light-emitting elements and the plurality of pixel drivers, respectively, and a gap between adjacent connecting electrodes among the plurality of connecting electrodes can overlap the separator.

[0019] The intermediate layer further includes a functional layer, and the functional layer includes a first intermediate functional layer disposed on the first electrode, and a second intermediate functional layer disposed on the light-emitting layer, and the light-emitting layer can be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0020] The electronic device may further include a first dummy layer disposed on the separator and including the same material as the functional layer, and a second dummy layer disposed on the first dummy layer and including the same material as the second electrode.

[0021] An electronic device according to an embodiment of the present invention may include a driving element layer including a pixel driver, a light-emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode and including at least a light-emitting layer, and a second electrode disposed on the intermediate layer, a pixel defining layer disposed on the driving element layer and having an opening defining an opening exposing at least a portion of the first electrode, a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driver and the second electrode, a connection wire disposed between the pixel driver and the pixel defining layer and electrically connected to the pixel driver and the connection electrode, and a separator disposed on the pixel defining layer. An edge of the connection electrode overlaps the separator, a tip portion is defined on at least a portion of the edge of the connection wire, and the connection electrode may be connected to at least a portion of the edge of the connection wire in which the tip portion is defined.

[0022] In each of the first contact area adjacent to the separator and the second contact area adjacent to the tip portion of the connecting wire, the second electrode can be in contact with the connecting electrode.

[0023] The above connecting wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, wherein each side of the first layer and the third layer protrudes more than a side of the second layer, one end of the connecting electrode is connected to the side of the second layer, and one end of the second electrode can be in contact with the one end of the connecting electrode connected to the side of the second layer.

[0024] According to the above, the light emitting element and the pixel driver can be stably contacted, thereby improving contact reliability.

[0025] In an electronic device of one embodiment, a connecting electrode electrically connected to a pixel driver and a cathode of a light-emitting element may be connected over a relatively wide area by making contact in an area adjacent to a separator provided for pixel separation, thereby improving contact reliability. The connecting electrode and the pixel driver may be electrically connected via a connecting wire.

[0026] In one embodiment of the electronic device, the connecting electrode may contact not only the top surface of the connecting wire but also the side surface thereof, thereby further improving the contact reliability between the connecting electrode and the connecting wire. In one aspect, since a tip portion is defined in the connecting wire, the cathode may contact one end of the connecting electrode that is in contact with the side surface of the connecting wire. Accordingly, the cathode may contact the connecting electrode not only in the area adjacent to the separator but also in the area adjacent to the tip portion of the connecting wire, thereby further improving the contact reliability between the connecting electrode and the cathode.

[0027] Accordingly, relatively high luminance can be maintained even with a lower driving voltage, which may require a low margin for the driving voltage and reduce power consumption. That is, for example, embodiments of the present invention can support display devices (and electronic devices including display devices) with a low margin for the driving voltage, thereby helping to reduce power consumption. In one aspect, relatively high contact reliability can be maintained even in high-temperature and high-humidity environments.

[0028] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention.

[0029] FIG. 2a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0030] FIG. 2b is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0031] Figure 2c is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0032] FIG. 3a is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0033] FIG. 3b is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0034] FIG. 4A is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0035] FIG. 4b is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0036] FIG. 4c is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0037] FIG. 4d is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0038] Figure 5 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0039] FIG. 6 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment of the present invention.

[0040] FIG. 7 is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0041] Figure 8 is a graph showing the luminance according to the first power voltage in one embodiment and comparative example of the present invention.

[0042] Figures 9a and 9b are images related to the UHAST evaluation of a comparative example of the present invention.

[0043] Figures 10a and 10b are images related to UHAST evaluation of one embodiment of the present invention.

[0044] Figure 11 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0045] FIG. 12 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment of the present invention.

[0046] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0047] Identical drawing numbers indicate identical components. In the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" includes any combination of one or more of the associated components.

[0048] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. The terms used herein are used to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0049] For example, terms such as "below," "below," "above," and "above" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0050] The term "substantially" as used herein means approximately or actually. "Substantially the same" means approximately or actually the same, and "substantially the same" means approximately or actually the same. "Substantially perpendicular" means approximately or actually perpendicular, and "substantially parallel" means approximately or actually parallel. "Substantially the same shape" means approximately or actually the same shape, and "substantially corresponding" means approximately or actually corresponding.

[0051] As used herein, the term "adjacent" may refer to elements that are relatively close to each other (e.g., within a target distance). Additionally, in some cases, "adjacent" may also refer to elements that are in contact with each other.

[0052] For example, terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] The terms "part" and "unit" refer to a software component or hardware component that performs a specific function. A hardware component may include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A software component may refer to executable code and / or data used by the executable code within an addressable storage medium. Accordingly, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, or variables.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0055] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0056] FIG. 1 is a block diagram of an electronic device (DD) according to one embodiment of the present invention.

[0057] Referring to FIG. 1, an electronic device (DD) may include a display panel (DP), a panel driver (SDC, EDC, DDC), a power supply (PWS), and a timing controller (TC). In the present embodiment, the display panel (DP) is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following embodiment, an organic light-emitting display panel will be described in detail as an example. The panel driver (SDC, EDC, DDC) may include a scan driver (SDC), an emissive driver (EDC), and a data driver (DDC).

[0058] The display panel (DP) may include scan lines (GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn), emission lines (ESL1 to ESLn), and data lines (DL1 to DLm). The display panel (DP) may include a plurality of pixels connected to the scan lines (GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn), emission lines (ESL1 to ESLn), and data lines (DL1 to DLm). (Where, m and n are integers greater than 1)

[0059] For example, a pixel (PXij, where i and j are integers greater than 1) located on the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) can be connected to the i-th first scan line (or write scan line, GWLi), the i-th second scan line (or compensation scan line, GCLi), the i-th third scan line (or first initialization scan line, GILi), the i-th fourth scan line (or second initialization scan line, GBLi), the i-th fifth scan line (or reset scan line, GRLi), the j-th data line (DLj), and the i-th emission line (ESLi).

[0060] A pixel (PXij) may include a plurality of light-emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel (PXij) may receive a first power voltage (VDD), a second power voltage (VSS), a third power voltage (or reference voltage, VREF), a fourth power voltage (or first initialization voltage, VINT1), a fifth power voltage (or second initialization voltage, VINT2), and a sixth power voltage (or compensation voltage, VCOMP) through a power supply unit (PWS).

[0061] The first power supply voltage (VDD) and the second power supply voltage (VSS) are set to voltage values ​​so that current can flow to the light-emitting element and cause it to emit light. For example, the first power supply voltage (VDD) can be set to a higher voltage than the second power supply voltage (VSS).

[0062] The third power supply voltage (VREF) may be a voltage for initializing the gate of the driving transistor included in the pixel (PXij). The third power supply voltage (VREF) may be used to implement a predetermined grayscale by utilizing a voltage difference with respect to the data signal. For this purpose, the third power supply voltage (VREF) may be set to a predetermined voltage within the voltage range of the data signal.

[0063] The fourth power supply voltage (VINT1) may be a voltage for initializing a capacitor included in a pixel (PXij). The fourth power supply voltage (VINT1) may be set to a voltage lower than the third power supply voltage (VREF). For example, the fourth power supply voltage (VINT1) may be set to a voltage lower than the difference between the third power supply voltage (VREF) and the threshold voltage of the driving transistor. However, embodiments of the present invention are not limited thereto.

[0064] The fifth power supply voltage (VINT2) may be a voltage for initializing the cathode of the light-emitting element included in the pixel (PXij). The fifth power supply voltage (VINT2) may be set to a voltage lower than the first power supply voltage (VDD) or the fourth power supply voltage (VINT1), or may be set to a voltage similar to or equal to the third power supply voltage (VREF), but is not limited thereto, and the fifth power supply voltage (VINT2) may also be set to a voltage similar to or equal to the first power supply voltage (VDD).

[0065] The sixth power supply voltage (VCOMP) can supply a predetermined current to the driving transistor when compensating for the threshold voltage of the driving transistor.

[0066] Although FIG. 1 illustrates that the first to sixth power voltages (VDD, VSS, VREF, VINT1, VINT2, VCOMP) are all supplied from the power supply unit (PWS), embodiments of the present invention are not limited thereto. For example, the first power voltage (VDD) and the second power voltage (VSS) are both supplied regardless of the structure of the pixel (PXij), and at least one of the third power voltage (VREF), the fourth power voltage (VINT1), the fifth power voltage (VINT2), and the sixth power voltage (VCOMP) may not be supplied depending on the structure of the pixel (PXij).

[0067] In an embodiment of the present invention, signal lines connected to pixels (PXij) can be set in various ways corresponding to the circuit structure of the pixels (PXij).

[0068] The scan driver (SDC) receives a first control signal (SCS) from the timing controller (TC), and can supply scan signals to each of the first scan lines (GWL1 to GWLn), the second scan lines (GCL1 to GCLn), the third scan lines (GIL1 to GILn), the fourth scan lines (GBL1 to GBLn), and the fifth scan lines (GRL1 to GRLn) based on the first control signal (SCS).

[0069] The scan signal can be set to a voltage that can turn on the transistors that receive the scan signal. For example, the scan signal supplied to the P-type transistor can be set to a logic low level, and the scan signal supplied to the N-type transistor can be set to a logic high level. Hereinafter, the meaning of "the scan signal is supplied" can be understood as that the scan signal is supplied at a logic level that turns on the transistor controlled by the scan signal.

[0070] In Fig. 1, for convenience of explanation, the scan driver (SDC) is illustrated as having a single configuration; however, embodiments of the present invention are not limited thereto. According to embodiments, a plurality of scan drivers may be included to supply scan signals to each of the first scan lines (GWL1 to GWLn), the second scan lines (GCL1 to GCLn), the third scan lines (GIL1 to GILn), the fourth scan lines (GBL1 to GBLn), and the fifth scan lines (GRL1 to GRLn).

[0071] The light emitting driver (EDC) can supply light emitting signals to the light emitting lines (ESL1 to ESLn) based on the second control signal (ECS). For example, the light emitting signals can be sequentially supplied to the light emitting lines (ESL1 to ESLn).

[0072] The transistors connected to the light-emitting lines (ESL1 to ESLn) of the present invention may be configured as N-type transistors. At this time, the light-emitting signal supplied to the light-emitting lines (ESL1 to ESLn) may be set to a gate-off voltage. The transistors receiving the light-emitting signal may be turned off when the supplied light-emitting signal is the gate-off voltage, and in other cases, the transistors may be turned on.

[0073] The second control signal (ECS) includes a light-emitting start signal and clock signals, and the light-emitting driver (EDC) can be implemented as a shift register that sequentially shifts the light-emitting start signal in a pulse form using the clock signals to sequentially generate and output a light-emitting signal in a pulse form.

[0074] The data driver (DDC) can receive a third control signal (DCS) and image data (RGB) from the timing controller (TC). The data driver (DDC) can convert the image data (RGB) in digital format into an analog data signal (i.e., a data signal). The data driver (DDC) can supply the data signal to the data lines (DL1 to DLm) in response to the third control signal (DCS).

[0075] The third control signal (DCS) may include a data enable signal, a horizontal start signal, a data clock signal, etc. that instruct the output of a valid data signal. For example, the data driving unit (DDC) may include a shift register that shifts the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch that latches image data (RGB) in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., data in digital form) into data signals in analog form, and buffers (or amplifiers) that output the data signals to the data lines (DL1 to DLm).

[0076] The power supply unit (PWS) can supply a first power voltage (VDD), a second power voltage (VSS), and a third power voltage (VREF) for driving pixels (PXij) to the display panel (DP). The power supply unit (PWS) can supply at least one of a fourth power voltage (VINT1), a fifth power voltage (VINT2), and a sixth power voltage (VCOMP) to the display panel (DP).

[0077] For example, the power supply unit (PWS) can supply the first power voltage (VDD), the second power voltage (VSS), the third power voltage (VREF), the fourth power voltage (VINT1), the fifth power voltage (VINT2), and the sixth power voltage (VCOMP) to the display panel (DP) via a first power line (VDL, see FIG. 2a), a second power line (VSL, see FIG. 2a), a third power line (or a reference voltage line, VRL, see FIG. 2a), a fourth power line (or a first initialization voltage line, VIL1, see FIG. 2a), a fifth power line (or a second initialization voltage line, VIL2, see FIG. 2a), and a sixth power line (or a compensation voltage line, VCL, see FIG. 2a), which are not illustrated.

[0078] The power supply unit (PWS) may be implemented as a power management integrated circuit, but is not limited thereto.

[0079] The timing control unit (TC) can generate a first control signal (SCS), a second control signal (ECS), a third control signal (DCS), and a fourth control signal (PCS) based on input image data (IRGB), a synchronization signal (Sync, e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal (DE), and a clock signal. The first control signal (SCS) can be supplied to a scan driver (SDC), the second control signal (ECS) can be supplied to an emission driver (EDC), the third control signal (DCS) can be supplied to a data driver (DDC), and the fourth control signal (PCS) can be supplied to a power supply unit (PWS). The timing control unit (TC) can rearrange the input image data (IRGB) to correspond to the arrangement of pixels (PXij) in the display panel (DP) to generate image data (RGB) (or frame data).

[0080] The scan driver (SDC), the emission driver (EDC), the data driver (DDC), the power supply unit (PWS), and / or the timing controller (TC) may be formed directly on the display panel (DP) or may be provided in the form of separate driver chips and connected to the display panel (DP). In one aspect, at least two of the scan driver (SDC), the emission driver (EDC), the data driver (DDC), the power supply unit (PWS), and the timing controller (TC) may be provided as one driver chip. For example, the data driver (DDC) and the timing controller (TC) may be provided as one driver chip.

[0081] While the electronic device (DD) according to one embodiment has been described above with reference to FIG. 1, the electronic device of the embodiments of the present invention is not limited thereto. Depending on the pixel configuration, additional signal lines may be added or omitted. In one aspect, the connection relationship between a pixel and signal lines may also be changed. For example, if one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0082] Figures 2a, 2b, and 2c are equivalent circuit diagrams of pixels according to one embodiment of the present invention. Figures 2a, 2b, and 2c illustrate equivalent circuit diagrams of pixels (PXij, PXij-1, and PXij-2) connected to the ith first scan line (GWLi, hereinafter referred to as the first scan line) and connected to the jth data line (DLj, hereinafter referred to as the data line), respectively.

[0083] As illustrated in FIG. 2a, a pixel (PXij) includes a light-emitting element (LD) and a pixel driver (PDC). The light-emitting element (LD) is connected to a first power line (VDL) and the pixel driver (PDC).

[0084] A pixel driver (PDC) may be connected to a plurality of scan lines (GWLi, GCLi, GILi, GBLi, GRLi), a data line (DLj), an emission line (ESLi), and a plurality of power voltage lines (VDL, VSL, VIL1, VIL2, VRL, VCL). The pixel driver (PDC) may include first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), a first capacitor (C1), and a second capacitor (C2). Hereinafter, in the present specification, for example, each of the first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8) is an N-type transistor. However, embodiments of the present invention are not limited thereto. Some of the first to eighth transistors (T1 to T8) may be N-type transistors, and the rest may be P-type transistors, or each of the first to eighth transistors (T1 to T8) may be a P-type transistor, and the present invention is not limited to any one embodiment.

[0085] The gate of the first transistor (T1) may be connected to a first node (N1). A first electrode of the first transistor (T1) may be connected to a second node (N2), and a second electrode may be connected to a third node (N3). The first transistor (T1) may be a driving transistor. The first transistor (T1) may control a driving current (ILD) flowing from a first power line (VDL) to a second power line (VSL) via a light emitting element (LD) in response to a voltage of the first node (N1). At this time, the first power voltage (VDD) may be set to a voltage having a higher potential than the second power voltage (VSS).

[0086] In this specification, “electrically connected between a transistor and a signal line or between transistors” means “the source, drain, and gate of the transistor have an integral shape with the signal line or are connected through a connecting electrode.”

[0087] The second transistor (T2) may include a gate connected to a write scan line (GWLi), a first electrode connected to a data line (DLj), and a second electrode connected to a first node (N1). The second transistor (T2) may supply a data signal (DATA) to the first node (N1) in response to a write scan signal (GW) transmitted through the write scan line (GWLi). The second transistor (T2) may be turned on when the write scan signal (GW) is supplied to the write scan line (GWLi), and may electrically connect the data line (DLj) and the first node (N1).

[0088] A third transistor (T3) may be connected between a first node (N1) and a reference voltage line (VRL). A first electrode of the third transistor (T3) may receive a reference voltage (VREF) through the reference voltage line (VRL), and a second electrode of the third transistor (T3) may be connected to the first node (N1). In the present embodiment, a gate of the third transistor (T3) may receive a reset scan signal (GR) through an ith fifth scan line (GRLi, hereinafter referred to as a reset scan line). When the reset scan signal (GR) is supplied to the reset scan line (GRLi), the third transistor (T3) may be turned on and provide the reference voltage (VREF) to the first node (N1).

[0089] A fourth transistor (T4) may be connected between a third node (N3) and a first initialization voltage line (VIL1). A first electrode of the fourth transistor (T4) may be connected to the third node (N3), and a second electrode of the fourth transistor (T4) may be connected to a first initialization voltage line (VIL1) that provides a first initialization voltage (VINT1). The fourth transistor (T4) may be referred to as a first initialization transistor. A gate of the fourth transistor (T4) may receive a first initialization scan signal (GI) through an ith third scan line (GILi, hereinafter referred to as the first initialization scan line). The fourth transistor (T4) may be turned on when the first initialization scan signal (GI) is supplied to the first initialization scan line (GILi), and may supply the first initialization voltage (VINT1) to the third node (N3).

[0090] The fifth transistor (T5) may be connected between a compensation voltage line (VCL) and a second node (N2). A first electrode of the fifth transistor (T5) may receive a compensation voltage (VCOMP) through the compensation voltage line (VCL), and a second electrode of the fifth transistor (T5) may be connected to a second node (N2) and electrically connected to a first electrode of the first transistor (T1). A gate of the fifth transistor (T5) may receive a compensation scan signal (GC) through an ith second scan line (GCLi, hereinafter referred to as compensation scan line). When the compensation scan signal (GC) is supplied to the compensation scan line (GCLi) (e.g., during a compensation period), the fifth transistor (T5) may be turned on and provide a compensation voltage (VCOMP) to the second node (N2), and the compensation voltage (VCOMP) may compensate for a threshold voltage of the first transistor (T1) during the compensation period.

[0091] The sixth transistor (T6) may be connected between the first transistor (T1) and the light-emitting element (LD). Specifically, the gate of the sixth transistor (T6) may receive a light-emitting signal (EM) through the ith light-emitting line (ESLi, hereinafter referred to as light-emitting line). The first electrode of the sixth transistor (T6) may be connected to the cathode of the light-emitting element (LD) through the fourth node (N4), and the second electrode of the sixth transistor (T6) may be connected to the first electrode of the first transistor (T1) through the second node (N2). The sixth transistor (T6) may be referred to as a first light-emitting control transistor. When the light-emitting signal (EM) is supplied to the light-emitting line (ESLi), the sixth transistor (T6) may be turned on and electrically connect the light-emitting element (LD) and the first transistor (T1).

[0092] The seventh transistor (T7) may be connected between the second power line (VSL) and the third node (N3). The first electrode of the seventh transistor (T7) is connected to the second electrode of the first transistor (T1) through the third node (N3), and the second electrode of the seventh transistor (T7) may receive the second power voltage (VSS) through the second power line (VSL). The gate of the seventh transistor (T7) may be electrically connected to the light emitting line (ESLi). The seventh transistor (T7) may be referred to as a second light emitting control transistor. When the light emitting signal (EM) is supplied to the light emitting line (ESLi), the seventh transistor (T7) is turned on and electrically connects the second electrode of the first transistor (T1) and the second power line (VSL).

[0093] In this embodiment, the sixth transistor (T6) and the seventh transistor (T7) are shown as being connected to the same light-emitting line (ESLi) and turned on through the same light-emitting signal (EM), but this is merely an example, and the sixth transistor (T6) and the seventh transistor (T7) may be turned on independently by different signals that are distinct from each other. In addition, in the pixel driver (PDC) according to one embodiment of the present invention, either the sixth transistor (T6) or the seventh transistor (T7) may be omitted.

[0094] The eighth transistor (T8) may be connected between the second initialization voltage line (VIL2) and the fourth node (N4). That is, the eighth transistor (T8) may include a gate connected to the ith fourth scan line (GBLi, hereinafter referred to as the second initialization scan line), a first electrode connected to the second initialization voltage line (VIL2), and a second electrode connected to the fourth node (N4). The eighth transistor (T8) may be referred to as a second initialization transistor. The eighth transistor (T8) may supply a second initialization voltage (VINT2) to the fourth node (N4) corresponding to the cathode of the light-emitting element (LD) in response to the second initialization scan signal (GB) transmitted through the second initialization scan line (GBLi). The cathode of the light-emitting element (LD) may be initialized by the second initialization voltage (VINT2).

[0095] In the present embodiment, some of the second to eighth transistors (T2, T3, T4, T5, T6, T7, and T8) may be turned on simultaneously through the same scan signal. For example, the eighth transistor (T8) and the fifth transistor (T5) may be turned on simultaneously through the same scan signal. For example, the eighth transistor (T8) and the fifth transistor (T5) may be operated by the same compensation scan signal (GC). The eighth transistor (T8) and the fifth transistor (T5) may be turned on / off simultaneously through the same compensation scan signal (GC). In this case, the compensation scan line (GCLi) and the second initialization scan line (GBLi) may be provided as a substantially single scan line. Accordingly, the cathode initialization of the light-emitting element (LD) and the threshold voltage compensation of the first transistor (T1) may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0096] In one aspect, according to the present invention, the cathode initialization of the light emitting element (LD) and the threshold voltage compensation of the first transistor (T1) can be performed by applying the same power supply voltage. For example, the compensation voltage line (VCL) and the second initialization voltage line (VIL2) can be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor can be performed with a single power supply voltage, so that the design of the driving unit can be simplified. However, this is illustrated as an example, and in one embodiment of the present invention, it is not limited to any one embodiment.

[0097] A first capacitor (C1) may be placed between a first node (N1) and a third node (N3). The first capacitor (C1) may store a differential voltage between the first node (N1) and the third node (N3). The first capacitor (C1) may be referred to as a storage capacitor.

[0098] The second capacitor (C2) may be disposed between the third node (N3) and the second power line (VSL). That is, one electrode of the second capacitor (C2) may be connected to the second power line (VSL) supplied with the second power voltage (VSS), and the other electrode of the second capacitor (C2) may be connected to the third node (N3). The second capacitor (C2) may store a charge corresponding to a voltage difference between the second power voltage (VSS) and the third node (N3). The second capacitor (C2) may be referred to as a hold capacitor. The second capacitor (C2) may have a higher storage capacity compared to the first capacitor (C1). Accordingly, the second capacitor (C2) may minimize a voltage change of the third node (N3) in response to a voltage change of the first node (N1).

[0099] In the present embodiment, the light emitting element (LD) may be connected to the pixel driver (PDC) through the fourth node (N4). The light emitting element (LD) may include an anode connected to the first power line (VDL) and a cathode opposite thereto. In the present embodiment, the light emitting element (LD) may be connected to the pixel driver (PDC) through the cathode. That is, in the pixel (PXij) according to the present invention, the connection node through which the light emitting element (LD) and the pixel driver (PDC) are connected may be the fourth node (N4), and the fourth node (N4) may correspond to the connection node between the first electrode of the sixth transistor (T6) and the cathode of the light emitting element (LD). Accordingly, the potential of the fourth node (N4) may substantially correspond to the cathode potential of the light emitting element (LD).

[0100] Specifically, the anode of the light emitting element (LD) is connected to the first power line (VDL) and a first power voltage (VDD), which is a constant voltage, is applied, and the cathode can be connected to the first transistor (T1) through the sixth transistor (T6). That is, in the present embodiment in which the first to eighth transistors (T1 to T8) are N-type transistors, the potential of the third node (N3) corresponding to the source of the first transistor (T1), which is a driving transistor, may not be directly affected by the characteristics of the light emitting element (LD). Therefore, even if deterioration of the light emitting element (LD) occurs, the influence on the transistors constituting the pixel driver (PDC), particularly on the gate-source voltage (Vgs) of the driving transistor, can be reduced. That is, the amount of change in the driving current due to deterioration of the light emitting element (LD) can be reduced, so that the afterimage defect of the display panel due to increased usage time can be reduced and the lifespan can be improved.

[0101] Alternatively, as illustrated in FIG. 2b, the pixel (PXij-1) may include a pixel driver (PDC-1) including two transistors (T1, T2) and a first capacitor (C1). The pixel driver (PDC-1) may be connected to a light emitting element (LD), a write scan line (GWLi), a data line (DLj), a first power line (VDL), and a second power line (VSL). The pixel driver (PDC-1) illustrated in FIG. 2b may correspond to the pixel driver (PDC) illustrated in FIG. 2a, in which the third to eighth transistors (T3 to T8) and the second capacitor (C2) are omitted.

[0102] Each of the first and second transistors (T1, T2) may be N-type or P-type. In the present exemplary embodiment, each of the first and second transistors (T1, T2) is an N-type transistor.

[0103] A first transistor (T1) may include a gate connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The second node (N2) may be a node connected to a first power line (VDL), and the third node (N3) may be a node connected to a second power line (VSL). The first transistor (T1) is connected to a light-emitting element (LD) through the second node (N2) and to the second power line (VSL) through the third node (N3). The first transistor (T1) may be a driving transistor.

[0104] The second transistor (T2) may include a gate that receives a write scan signal (GW) through a write scan line (GWLi), a first electrode connected to a data line (DLj), and a second electrode connected to a first node (N1). The second transistor (T2) may supply a data signal (DATA) to the first node (N1) in response to the write scan signal (GW) transmitted through the write scan line (GWLi).

[0105] The first capacitor (C1) may include an electrode connected to a first node (N1) and an electrode connected to a third node (N3). The first capacitor (C1) may store a data signal (DATA) transmitted to the first node (N1).

[0106] The light emitting element (LD) may include an anode and a cathode. In the present embodiment, the anode of the light emitting element (LD) is connected to the first power line (VDL), and the cathode is connected to the pixel driver (PDC-1) via the second node (N2). In the present embodiment, the cathode of the light emitting element (LD) may be connected to the first transistor (T1). The light emitting element (LD) may emit light in response to the amount of current flowing in the first transistor (T1) of the pixel driver (PDC-1).

[0107] In the present embodiment where the first and second transistors (T1, T2) are N-type transistors, the second node (N2) to which the cathode of the light-emitting element (LD) and the pixel driver (PDC-1) are connected may correspond to the drain of the first transistor (T1). That is, the change in the gate-source voltage (Vgs) of the first transistor (T1) due to the light-emitting element (LD) can be prevented. Accordingly, the amount of change in the driving current due to deterioration of the light-emitting element (LD) can be reduced, so that the afterimage defect of the display panel due to increased usage time can be reduced and the lifespan can be improved.

[0108] Alternatively, as illustrated in FIG. 2c, the pixel (PXij-2) may include a pixel driver (PDC-2) including six transistors (T1, T2, T3, T4a, T5a, T6a) and two capacitors (C1, C2).

[0109] The pixel driver (PDC-2) can be connected to a light emitting element (LD), a write scan line (GWLi), a reset scan line (GRLi), a compensation scan line (GCLi), an ith first light emitting line (ESL1i, hereinafter referred to as the first light emitting line), an ith second light emitting line (ESL2i, hereinafter referred to as the second light emitting line), a data line (DLj), a first power line (VDL), a second power line (VSL), a third power line (VRL), and an initialization voltage line (VIL).

[0110] The pixel driver (PDC-2) illustrated in Fig. 2c may have a structure similar to that of the pixel driver (PDC) illustrated in Fig. 2a, with the fourth transistor (T4) and the fifth transistor (T5) omitted. Since the area of ​​the pixel driver (PDC-2) illustrated in Fig. 2c is smaller than that of the pixel driver (PDC-1) illustrated in Fig. 2a, high resolution implementation may be easier.

[0111] Each of the first to sixth transistors (T1, T2, T3, T4a, T5a, T6a) may be an N-type or a P-type. In the present exemplary embodiment, each of the first to sixth transistors (T1, T2, T3, T4a, T5a, T6a) is an N-type transistor.

[0112] A first transistor (T1) may include a gate connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The second node (N2) may be a node connected to a first power line (VDL), and the third node (N3) may be a node connected to a second power line (VSL). The first transistor (T1) is connected to a light-emitting element (LD) through the second node (N2) and to the second power line (VSL) through the third node (N3). The first transistor (T1) may be a driving transistor.

[0113] The second transistor (T2) may include a gate that receives a write scan signal (GW) through a write scan line (GWLi), a first electrode connected to a data line (DLj), and a second electrode connected to a first node (N1). The second transistor (T2) may supply a data signal (DATA) to the first node (N1) in response to the write scan signal (GW) transmitted through the write scan line (GWLi).

[0114] A third transistor (T3) may be connected between a first node (N1) and a reference voltage line (VRL). A first electrode of the third transistor (T3) may receive a reference voltage (VREF) through the reference voltage line (VRL), and a second electrode of the third transistor (T3) may be connected to the first node (N1). In the present embodiment, a gate of the third transistor (T3) may receive a reset scan signal (GR) through a reset scan line (GRLi). When the reset scan signal (GR) is supplied to the reset scan line (GRLi), the third transistor (T3) may be turned on and provide the reference voltage (VREF) to the first node (N1).

[0115] The fourth transistor (T4a) may be connected between the first transistor (T1) and the light-emitting element (LD). Specifically, the gate of the fourth transistor (T4a) may receive the first light-emitting signal (EM1) through the first light-emitting line (ESL1i). The first electrode of the fourth transistor (T4a) may be connected to the cathode of the light-emitting element (LD) through the fourth node (N4), and the second electrode of the fourth transistor (T4a) may be connected to the first electrode of the first transistor (T1) through the second node (N2). The fourth transistor (T4a) may be referred to as a first light-emitting control transistor. When the first light-emitting signal (EM1) is supplied to the first light-emitting line (ESL1i), the fourth transistor (T4a) may be turned on and electrically connect the light-emitting element (LD) and the first transistor (T1).

[0116] The fifth transistor (T5a) may be connected between the second power line (VSL) and the third node (N3). The first electrode of the fifth transistor (T5a) is connected to the second electrode of the first transistor (T1) through the third node (N3), and the second electrode of the fifth transistor (T5a) may receive the second power voltage (VSS) through the second power line (VSL). The gate of the fifth transistor (T5a) may be electrically connected to the second light-emitting line (ESL2i). The fifth transistor (T5a) may be referred to as a second light-emitting control transistor. When the second light-emitting signal (EM2) is supplied to the second light-emitting line (ESL2i), the fifth transistor (T5a) is turned on and electrically connects the second electrode of the first transistor (T1) and the second power line (VSL).

[0117] In the present embodiment, the fourth transistor (T4a) and the fifth transistor (T5a) may be connected to the first and second light-emitting lines (ESL1i, ESL2i) that are distinct from each other and may be turned on through the first and second light-emitting signals (EM1, EM2) that are distinct from each other. That is, the fourth transistor (T4a) and the fifth transistor (T5a) may be turned on independently from each other. However, this is an example, and embodiments of the present invention are not limited thereto. For example, in one embodiment of the present invention, the fourth transistor (T4a) and the fifth transistor (T5a) may be connected to the same light-emitting line and may be controlled by the same light-emitting signal. In addition, in the pixel driver (PDC-2) according to one embodiment of the present invention, either the fourth transistor (T4a) or the fifth transistor (T5a) may be omitted.

[0118] The sixth transistor (T6a) may be connected between the initialization voltage line (VIL) and the fourth node (N4). That is, the sixth transistor (T6a) may include a gate connected to the compensation scan line (GCLi), a first electrode connected to the initialization voltage line (VIL), and a second electrode connected to the fourth node (N4). The sixth transistor (T6a) may be referred to as an initialization transistor. The sixth transistor (T6a) may supply the initialization voltage (VINT) to the fourth node (N4) corresponding to the cathode of the light-emitting element (LD) in response to the compensation scan signal (GC) transmitted through the compensation scan line (GCLi). The cathode of the light-emitting element (LD) may be initialized by the initialization voltage (VINT).

[0119] A first capacitor (C1) may be placed between a first node (N1) and a third node (N3). The first capacitor (C1) may store a differential voltage between the first node (N1) and the third node (N3). The first capacitor (C1) may be referred to as a storage capacitor.

[0120] The second capacitor (C2) may be placed between the third node (N3) and the second power line (VSL). That is, one electrode of the second capacitor (C2) may be connected to the second power line (VSL) supplied with the second power voltage (VSS), and the other electrode of the second capacitor (C2) may be connected to the third node (N3). The second capacitor (C2) may store a charge corresponding to the voltage difference between the second power voltage (VSS) and the third node (N3). The second capacitor (C2) may be referred to as a hold capacitor.

[0121] The light emitting element (LD) may include an anode and a cathode. In the present embodiment, the anode of the light emitting element (LD) is connected to the first power line (VDL), and the cathode is connected to the pixel driver (PDC-2) via the fourth node (N4). In the present embodiment, the cathode of the light emitting element (LD) may be connected to the first transistor (T1) via the fourth transistor (T4a). The light emitting element (LD) may emit light in response to the amount of current flowing in the first transistor (T1) of the pixel driver (PDC-2).

[0122] In the present embodiment where the first to sixth transistors (T1, T2, T3, T4a, T5a, T6a) are N-type transistors, the potential of the third node (N3) corresponding to the source of the first transistor (T1), which is a driving transistor, may not be directly affected by the characteristics of the light-emitting element (LD). Therefore, even if deterioration of the light-emitting element (LD) occurs, the influence on the transistors constituting the pixel driver (PDC-2), particularly on the gate-source voltage (Vgs) of the driving transistor, can be reduced. That is, the amount of change in driving current due to deterioration of the light-emitting element (LD) can be reduced, so that afterimage defects of the display panel due to increased usage time can be reduced and the lifespan can be improved.

[0123] FIG. 2a, FIG. 2b, and FIG. 2c illustrate circuits for pixel drivers (PDC, PDC-1, PDC-2) according to one embodiment of the present invention, and the display panel according to one embodiment of the present invention may be designed in various ways in terms of the number or arrangement of transistors and the number or arrangement of capacitors as long as the circuit is connected to the cathode of the light-emitting element (LD), and is not limited to any one embodiment.

[0124] FIGS. 3A and 3B are schematic plan views illustrating a display panel according to one embodiment of the present invention. Some components are omitted in each of FIGS. 3A and 3B. The present invention will now be described with reference to FIGS. 3A and 3B.

[0125] Referring to FIG. 3A, a display panel (DP) of one embodiment may be divided into a display area (DA) and a peripheral area (or non-display area, NDA). The display area (DA) may include a plurality of light-emitting units (EP).

[0126] The light-emitting portions (EP) may be regions that are each illuminated by pixels (PXij, see FIG. 1). Specifically, each of the light-emitting portions (EP) may correspond to a light-emitting aperture (OP-PDL, see FIG. 5) described below. The light-emitting aperture (OP-PDL) may be referred to as an aperture or an opening.

[0127] The peripheral area (NDA) may be positioned adjacent to the display area (DA). In the present embodiment, the peripheral area (NDA) is illustrated as a shape surrounding the edge of the display area (DA). However, this is merely an example, and the peripheral area (NDA) may be positioned on one side of the display area (DA), or may be omitted, and is not limited to any one embodiment.

[0128] In the present embodiment, a scan driver (SDC) and a data driver (DDC) may be mounted on a display panel (DP). In one embodiment, the scan driver (SDC) may be disposed in a display area (DA), and the data driver (DDC) may be disposed in a peripheral area (NDA). The scan driver (SDC) may overlap at least some of a plurality of light-emitting units (EP) disposed in the display area (DA) on a plane. Since the scan driver (SDC) is disposed in the display area (DA), the area of ​​the peripheral area (NDA) may be reduced compared to a conventional display panel in which the scan driver is disposed in the peripheral area, and an electronic device with a thin bezel may be easily implemented.

[0129] Unlike the one illustrated in FIG. 3A, the scan driver (SDC) may be provided in two distinct parts. The two scan drivers (SDC) may be spaced apart from each other to the left and right with the center of the display area (DA) between the two scan drivers (SDC). Alternatively, the scan drivers (SDC) may be provided in a greater number, such as two or more, and are not limited to any one embodiment.

[0130] Fig. 3a illustrates an example of a display panel, and a data driver (DDC) may be arranged in a display area (DA). In this case, some of the light-emitting units (EP) arranged in the display area (DA) may overlap with the data driver (DDC) on a plane.

[0131] In one embodiment, the data driver (DDC) may be provided in the form of a separate driver chip independent from the display panel (DP) and connected to the display panel (DP). However, this is merely an example, and the data driver (DDC) may be formed in the same process as the scan driver (SDC) to form the display panel (DP), and is not limited to any one embodiment.

[0132] As illustrated in FIG. 3B, the display panel (DP) may have a form in which a length corresponding to the first direction (DR1) is longer than a length corresponding to the second direction (DR2). A plurality of pixels (PX11 to PXnm) arranged in n rows and m columns are exemplarily illustrated in the display area (DA). In the present embodiment, the display panel (DP) may include a plurality of scan drivers (SDC1, SDC2). The scan drivers (SDC1, SDC2) are exemplarily illustrated as including a first scan driver (SDC1) and a second scan driver (SDC2) that are spaced apart from each other in the first direction (DR1).

[0133] The first scan driver (SDC1) may be connected to some of the scan lines (GL1 to GLn), and the second scan driver (SDC2) may be connected to other some of the scan lines (GL1 to GLn). For example, the first scan driver (SDC1) may be connected to odd-numbered scan lines among the scan lines (GL1 to GLn), and the second scan driver (SDC2) may be connected to even-numbered scan lines among the scan lines (GL1 to GLn).

[0134] For ease of explanation, pads (PD) of data lines (DL1 to DLm) are illustrated in Fig. 3b. The pads (PD) may be defined at the ends of the data lines (DL1 to DLm). The data lines (DL1 to DLm) may be connected to a data driver (DDC, see Fig. 3a) through the pads (PD).

[0135] According to the present invention, the pads (PD) may be arranged in opposite areas of the display area (DA) and the peripheral area (NDA) spaced apart from each other between the opposite areas. For example, some of the pads (PD) may be arranged on the upper side, that is, on the side adjacent to the first scan line (GL1) among the scan lines (GL1 to GLn), and other of the pads (PD) may be arranged on the lower side, that is, on the side adjacent to the last scan line (GLn) among the scan lines (GL1 to GLn). In the present embodiment, the pads (PD) connected to odd-numbered data lines among the data lines (DL1 to DLm) may be arranged on the upper side, and the pads (PD) connected to even-numbered data lines among the data lines (DL1 to DLm) may be arranged on the lower side.

[0136] Although not shown, the display panel (DP) may include a plurality of upper data drivers connected to pads (PD) arranged on the upper side and / or a plurality of lower data drivers connected to pads (PD) arranged on the lower side. However, this is described by way of example, and the display panel (DP) may include one upper data driver connected to pads (PD) arranged on the upper side and / or one lower data driver connected to pads (PD) arranged on the lower side. The pads (PD) according to one embodiment of the present invention may be arranged on one side (for example, only on one side) of the display panel (DP) and connected to a single data driver, and are not limited to any one embodiment.

[0137] In one aspect, as described above in FIG. 3A, the display panel (DP) in FIG. 3B may also have a scan driver and / or a data driver disposed in the display area (DA), and accordingly, some of the light emitting units disposed in the display area (DA) may overlap with the scan driver and / or the data driver on a plane.

[0138] FIGS. 4A to 4D are enlarged plan views of a portion of a display panel according to one embodiment of the present invention.

[0139] In Fig. 4a, light emitting units (UT11, UT12, UT21, UT22) of two rows and two columns are exemplarily illustrated. Referring to Fig. 4a, the light emitting units of the first row (Rk) include light emitting units constituting the first row, first column light emitting unit (UT11) and the first row, second column light emitting unit (UT12), and the light emitting units of the second row (Rk+1) include light emitting units constituting the second row, first column light emitting unit (UT21) and the second row, second column light emitting unit (UT22).

[0140] Each of the light-emitting parts (EP1, EP2, EP3) may correspond to a light-emitting opening (OP-PDL, see FIG. 5) described below. That is, each of the light-emitting parts (EP1, EP2, EP3) may be an area where light is emitted by the light-emitting element described above. The light-emitting parts (EP1, EP2, EP3) may correspond to a unit that constitutes an image displayed on a display panel (DP, see FIG. 1). More specifically, each of the light-emitting parts (EP1, EP2, EP3) may correspond to an area defined by the light-emitting opening (OP-PDL) described below, particularly, an area defined by a lower surface of the light-emitting opening (OP-PDL).

[0141] The light emitting units (EP1, EP2, EP3) may include a first light emitting unit (EP1), a second light emitting unit (EP2), and a third light emitting unit (EP3). The first light emitting unit (EP1), the second light emitting unit (EP2), and the third light emitting unit (EP3) may emit lights of different colors. For example, the first light emitting unit (EP1) may emit red light, the second light emitting unit (EP2) may emit green light, and the third light emitting unit (EP3) may emit blue light, but the color combination is not limited thereto. In addition, at least two of each of the first to third light emitting units (EP1, EP2, EP3) may emit light of the same color. For example, all of the first to third light emitting units (EP1, EP2, EP3) may emit blue light, or all of them may emit white light.

[0142] Among the first to third light-emitting units (EP1, EP2, EP3), the third light-emitting unit (EP3) that displays light emitted by the third light-emitting element may include two sub-light-emitting units (EP31, EP32) spaced apart from each other in the second direction (DR2). However, this is merely an example, and the third light-emitting unit (EP3) may be provided as a single pattern having an integral shape like the first and second light-emitting units (EP1, EP2), or at least one of the first and second light-emitting units (EP1, EP2) may include spaced apart sub-light-emitting units, and is not limited to any one embodiment.

[0143] The first row (Rk) light emitting units may include first to third light emitting units (EP1, EP2, EP3) constituting the first row, first column light emitting unit (UT11) and first to third light emitting units (EP1, EP2, EP3a) constituting the first row, second column light emitting unit (UT12), and the second row (Rk+1) light emitting units may include first to third light emitting units (EP1, EP2, EP3a) constituting the second row, first column light emitting unit (UT21) and first to third light emitting units (EP1, EP2, EP3) constituting the second row, second column light emitting unit (UT22).

[0144] In one embodiment of the present invention, the shapes of the light emitting parts constituting the first row, first column light emitting unit (UT11) and the shapes of the light emitting parts constituting the second row, second column light emitting unit (UT22) may be substantially the same. In one aspect, the shapes of the light emitting parts constituting the first row, second column light emitting unit (UT12) and the shapes of the light emitting parts constituting the second row, first column light emitting unit (UT21) may be substantially the same. The shapes of the light emitting parts constituting the first row, first column light emitting unit (UT11) may be different from the shapes of the light emitting parts constituting the first row, second column light emitting unit (UT12). For example, some of the light emitting parts of the first row (Rk) and some of the light emitting parts of the second row (Rk+1) may have symmetrical shapes.

[0145] In one embodiment of the present invention, the third light emitting part (EP3a) of the second row, first column light emitting unit (UT21) and the third light emitting part (EP3) of the first row, first column light emitting unit (UT11) may have a shape and arrangement form that are line-symmetrical with respect to an axis parallel to the first direction (DR1), and the third light emitting part (EP3) of the second row, second column light emitting unit (UT22) and the third light emitting part (EP3a) of the first row, second column light emitting unit (UT12) may have a shape and arrangement form that are line-symmetrical with respect to an axis parallel to the first direction (DR1). However, this is exemplary, and embodiments of the present invention are not limited thereto.

[0146] Fig. 4b illustrates light emitting units arranged in a row. For ease of explanation, Fig. 4b illustrates a plurality of second electrodes (EL2_1, EL2_2, EL2_3), a plurality of pixel driver units (PDC1, PDC2, PDC3), first to third connection electrodes (CNE1, CNE2, CNE3), and a separator (SPR). Fig. 4c illustrates a separator (SPR), a plurality of light emitting units (EP1, EP2, EP3) arranged within an area partitioned by the separator (SPR), and a plurality of connection electrodes (CNE1, CNE2, CNE3) among the configurations of the display panel.

[0147] Referring to FIGS. 4b and 4c, the second electrodes (EL2_1, EL2_2, EL2_3) can be electrically disconnected by being separated from each other by a separator (SPR). In the present embodiment, one light emitting unit (UT11) can include three light emitting parts (EP1, EP2, EP3). Accordingly, the light emitting unit (UT11) can include three second electrodes (EL2_1, EL2_2, EL2_3, hereinafter referred to as first to third cathodes), three pixel driving parts (PDC1, PDC2, PDC3), and three connection electrodes (CNE1, CNE2, CNE3). However, this is merely an example, and the number and arrangement of the light emitting parts included in the light emitting unit (UT11) can be designed in various ways and are not limited to any one embodiment.

[0148] Each of the first to third pixel driving units (PDC1, PDC2, PDC3) is electrically connected to each of the first to third light-emitting elements (LD1, LD2, LD3) including the first to third light-emitting units (EP1, EP2, EP3). In this specification, “connected” includes not only cases where they are connected by direct physical contact but also cases where they are electrically connected.

[0149] In one aspect, each area where the first to third pixel driving units (PDC1, PDC2, PDC3) are defined on a plane as in FIG. 4b may correspond to a unit in which transistor and capacitor elements constituting a circuit (PDC, see FIG. 2a) for driving a light-emitting element of a pixel are repeatedly arranged.

[0150] The first to third pixel driving units (PDC1, PDC2, PDC3) can be sequentially arranged along the first direction (DR1). In one aspect, the arrangement positions of the first to third pixel driving units (PDC1, PDC2, PDC3) can be designed independently regardless of the positions or shapes of the first to third light-emitting units (EP1, EP2, EP3).

[0151] For example, the first to third pixel driving units (PDC1, PDC2, PDC3) may be arranged in a region defined by the separator (SPR), that is, in a position different from the positions where the first to third cathodes (EL2_1, EL2_2, EL2_3) are arranged, or may be designed to have a shape and area different from the shapes of the first to third cathodes (EL2_1, EL2_2, EL2_3). Alternatively, the first to third pixel driving units (PDC1, PDC2, PDC3) may be arranged to overlap the positions where the first to third light-emitting units (EP1, EP2, EP3) exist, and may be designed to have a shape having an area similar to the first to third cathodes (EL2_1, EL2_2, EL2_3) in a region defined by the separator (SPR).

[0152] In this embodiment, each of the first to third pixel driving units (PDC1, PDC2, PDC3) is illustrated as a rectangular shape, each of the first to third light emitting units (EP1, EP2, EP3) is arranged in a smaller area and a different shape, and the first to third cathodes (EL2_1, EL2_2, EL2_3) are arranged in a position overlapping the first to third light emitting units (EP1, EP2, EP3), but are illustrated as an irregular shape.

[0153] Accordingly, as illustrated in FIG. 4B, the first pixel driver (PDC1) may be positioned at a position partially overlapping the first light-emitting unit (EP1), the second light-emitting unit (EP2), and other adjacent light-emitting units. The second pixel driver (PDC2) may be positioned at a position overlapping the first light-emitting unit (EP1), the second light-emitting unit (EP2), and the third cathode (EL2_3). The third pixel driver (PDC3) may be positioned at a position overlapping the third light-emitting unit (EP3). This is merely an example, and the positions of the first to third pixel drivers (PDC1, PDC2, PDC3) may be designed in various shapes and arrangements independently from the first to third light-emitting units (EP1, EP2, EP3) and are not limited to any one embodiment.

[0154] The light emitting unit (UT11) may include first to third connection electrodes (CNE1, CNE2, CNE3). The first connection electrode (CNE1) may electrically connect a first light emitting element (LD1) forming a first light emitting portion (EP1) (or a first light emitting portion (EP1) is defined) and a first pixel driver (PDC1), the second connection electrode (CNE2) may electrically connect a second light emitting element (LD2) forming a second light emitting portion (EP2) and a second pixel driver (PDC2), and the third connection electrode (CNE3) may electrically connect a third light emitting element (LD3) forming a third light emitting portion (EP3) and a third pixel driver (PDC3).

[0155] Specifically, the first to third connection electrodes (CNE1, CNE2, CNE3) can electrically connect the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third pixel drivers (PDC1, PDC2, PDC3) in a one-to-one correspondence, respectively.

[0156] Each of the first to third connection electrodes (CNE1, CNE2, CNE3) may be disposed on a pixel defining layer (PDL, see FIG. 5) to be described later. Each of the first to third connection electrodes (CNE1, CNE2, CNE3) may have a ring shape surrounding the corresponding first to third light-emitting portions (EP1, EP2, EP3). In one embodiment of the present invention, it is illustrated as an example that each of the first to third connection electrodes (CNE1, CNE2, CNE3) has a ring shape of a closed line, but is not limited thereto. For example, at least some of the first to third connection electrodes (CNE1, CNE2, CNE3) may have an open ring shape in which a portion is disconnected.

[0157] Since the first to third connection electrodes (CNE1, CNE2, CNE3) have a ring shape, the degree of freedom of the positions at which the first to third connection electrodes (CNE1, CNE2, CNE3) and the first to third pixel drivers (PDC1, PDC2, PDC3) are connected can be improved. For example, the first connection electrode (CNE1) can be connected to the first pixel driver (PDC1) through the first connection portion (CNP1), the second connection electrode (CNE2) can be connected to the second pixel driver (PDC2) through the second connection portion (CNP2), and the third connection electrode (CNE3) can be connected to the third pixel driver (PDC3) through the third connection portion (CNP3).

[0158] In one embodiment of the present invention, the third pixel driver (PDC3) and the third light-emitting element (LD3) constituting the third light-emitting element (EP3) may be electrically connected through a connection wire (CN3). Specifically, the connection wire (CN3) may correspond to a node (see the fourth node (N4) of FIG. 2A, the second node (N2) of FIG. 2B, or the fourth node (N4) of FIG. 2C) in which the light-emitting element (LD, see FIG. 2A) is connected to the pixel driver (PDC of FIG. 2A, PDC-1 of FIG. 2B, or PDC-2 of FIG. 2C). The connection wire (CN3) may include a light-emitting connection portion (CE3) and a driving connection portion (CD3). The light-emitting connection portion (CE3) may be provided on one side of the connection wire (CN3), and the driving connection portion (CD3) may be provided on the other side of the connection wire (CN3).

[0159] The driving connection part (CD3) may be a part of the connection wire (CN3) that is connected to the pixel driver (PDC3). In the present embodiment, the driving connection part (CD3) may be connected to one electrode of a transistor constituting the pixel driver (PDC3). Specifically, the driving connection part (CD3) may be connected to the drain of the sixth transistor (T6) illustrated in FIG. 2a, the drain of the first transistor (T1) illustrated in FIG. 2b, or the drain of the fourth transistor (T4a) illustrated in FIG. 2c. Accordingly, the position of the driving connection part (CD3) may correspond to the position of the transistor physically connected to the connection wire (CN3) among the pixel drivers.

[0160] The light-emitting connection portion (CE3) may be a portion of the connection wiring (CN3) that is connected to the light-emitting element (LD3). In the present embodiment, the light-emitting connection portion (CE3) may be connected to the connection electrode (CNE3).

[0161] Although FIGS. 4A and 4B illustrate a connection wire (CN3) connecting a third pixel driver (PDC3) and a third light-emitting element (LD3), the first pixel driver (PDC1) and the first light-emitting element (LD1) may also be electrically connected through a connection wire (CN, see FIG. 5), and the second pixel driver (PDC2) and the second light-emitting element (LD2) may also be electrically connected through a connection wire (CN, see FIG. 5). In one aspect, although FIGS. 4A and 4B illustrate a driving connection unit (CD3) and a light-emitting connection unit (CE3) included in a third connection unit (CNP3), each of the first connection unit (CNP1) and the second connection unit (CNP2) may also include a connection wire (CN, see FIG. 5), a driving connection unit (CD, see FIG. 5), and a light-emitting connection unit (CE, see FIG. 5). A more detailed description of the connecting wire (CN), the driving connection (CD), and the light emitting connection (CE) will be described later with reference to FIGS. 5 and 7.

[0162] The first connection electrode (CNE1) may include a first edge (EG11) surrounding at least a portion of the first light-emitting portion (EP1) and a second edge (EG12) surrounding the first edge (EG11). The second connection electrode (CNE2) may include a first edge (EG21) surrounding at least a portion of the second light-emitting portion (EP2) and a second edge (EG22) surrounding the first edge (EG21). The third connection electrode (CNE3) may include a first edge (EG31) surrounding at least a portion of the third light-emitting portion (EP3) and a second edge (EG32) surrounding the first edge (EG31).

[0163] The first to third connecting electrodes (CNE1, CNE2, CNE3) may be arranged to be spaced apart from each other. For example, gaps (GP1, GP2, GP3) between a plurality of adjacent connecting electrodes among the first to third connecting electrodes (CNE1, CNE2, CNE3) may overlap with the separator (SPR). For example, first edges (EG11, EG21, EG31) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may not be covered by the separator (SPR), and second edges (EG12, EG22, EG32) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may overlap with the separator (SPR). Alternatively, the second edges (EG12, EG22, EG32) of the first to third connecting electrodes (CNE1, CNE2, CNE3) may be covered by a separator (SPR).

[0164] In one embodiment of the present invention, the light emitting connection portion (CE3) of the first and second connection portions (CNP1, CNP2) and the third connection portion (CNP3) may be arranged at a non-overlapping position on a plane with the first to third light emitting portions (EP1, EP2, EP3). For example, a light emitting opening (OP-PDL, see FIG. 5) and first through holes (OP-P, see FIG. 5) spaced apart from the light emitting opening (OP-PDL) may be defined in the pixel defining layer (PDL).

[0165] The first through-holes (OP-P) may include a first-first through-hole (OP-P1), a first-second through-hole (OP-P2), and a first-third through-hole (OP-P3). The first and second connecting portions (CNP1, CNP2) may be arranged to correspond to the first-first and first-second through-holes (OP-P1, OP-P2), respectively, and the light-emitting connecting portion (CE3) of the third connecting portion (CNP3) may be arranged to correspond to the first-third through-hole (OP-P3). The light-emitting opening (OP-PDL) may include a first light-emitting opening (OP-PDL1), a second light-emitting opening (OP-PDL2), and a third light-emitting opening (OP-PDL3). The first to third light-emitting portions (EP1, EP2, EP3) can be defined to correspond to the first to third light-emitting openings (OP-PDL1, OP-PDL2, OP-PDL3), respectively. Accordingly, the light-emitting connection portion (CE3) of the first and second connection portions (CNP1, CNP2) and the third connection portion (CNP3) can be positioned at a position spaced apart from the first to third light-emitting portions (EP1, EP2, EP3).

[0166] The first to third connection electrodes (CNE1, CNE2, CNE3) may be arranged on a pixel defining layer (PDL, see FIG. 5). When viewed in a plan view, the first connection electrode (CNE1) may surround the first light-emitting opening (OP-PDL1), the second connection electrode (CNE2) may surround the second light-emitting opening (OP-PDL2), and the third connection electrode (CNE3) may surround the third light-emitting openings (OP-PDL3).

[0167] According to one embodiment of the present invention, the driving connection part (CD3) of the third connection part (CNP3), which is a position where the connection wire (CN3) connects to the transistor (TR, see FIG. 5) of the third pixel driver (PDC3), is defined at a position that does not overlap with the light-emitting connection part (CE3) of the third connection part (CNP3) on a plane and may be positioned at a position that overlaps with the third light-emitting part (EP3). Since the third cathode (EL2_3) and the third pixel driver (PDC3) are connected through the connection wire (CN3), restrictions on the position or shape of the third light-emitting part (EP3) in the design of the pixel driver (PDC3) are reduced, so that the degree of freedom in design can be improved. In one embodiment, the driving connection part (CD, see FIG. 5) of the first connection part (CNP1), which is a position where the connection wiring (CN, see FIG. 5) connects to the transistor (TR, see FIG. 5) of the first pixel driver (PDC1), may be disposed at a position that does not overlap with the first light-emitting part (EP1) on the plane, and the driving connection part (CD, see FIG. 5) of the second connection part (CNP2), which is a position where the connection wiring (CN, see FIG. 5) connects to the transistor (TR, see FIG. 5) of the second pixel driver (PDC2), may be disposed at a position that does not overlap with the second light-emitting part (EP2).

[0168] The first to third cathodes (EL2_1, EL2_2, EL2_3) can be connected to the first to third connection electrodes (CNE1, CNE2, CNE3). For example, the lower surfaces of the first to third cathodes (EL2_1, EL2_2, EL2_3) can be connected (or in contact) with the upper surfaces of the first to third connection electrodes (CNE1, CNE2, CNE3), respectively. Accordingly, the contact reliability (or connection stability) of the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third connection electrodes (CNE1, CNE2, CNE3) can be further improved.

[0169] In one aspect, the connection regions where the first to third cathodes (EL2_1, EL2_2, EL2_3) and the first to third connection electrodes (CNE1, CNE2, CNE3) are connected may surround at least a portion of each of the first to third light-emitting openings (OP-PDL1, OP-PDL2, OP-PDL3). The first to third cathodes (EL2_1, EL2_2, EL2_R) and the first to third connection electrodes (CNE1, CNE2, CNE3) may be connected in a region adjacent to the separator (SPR), and each of the contact regions may be defined as contact regions adjacent to the separator (SPR). That is, the first to third cathodes (EL2_1, EL2_2, EL2_R) and the first to third connection electrodes (CNE1, CNE2, CNE3) are not connected at a specific point, but can be connected over a relatively wide area, for example, an area similar to the shape of each of the first to third connection electrodes (CNE1, CNE2, CNE3). That is, the area of ​​the connection contact is increased, so that the connection can proceed stably.

[0170] Figure 4d illustrates a separator (SPR), light-emitting parts (EP1, EP2, EP3), and a first electrode (EL1).

[0171] Referring to FIG. 4d, the first electrode (EL1, hereinafter referred to as anode) of the light-emitting element (LD, see FIG. 5) according to one embodiment of the present invention may be commonly provided to the first to third light-emitting portions (EP1, EP2, EP3). That is, the anode (EL1) may be formed as a single layer integral with the entire display area (DA), and thus the anode (EL1) layer may be arranged to overlap the separator (SPR). Alternatively, the anodes (EL1) of each of the light-emitting elements (LD) may be formed as independent conductive patterns spaced apart from each other and electrically connected to each other through other conductive layers, and thus the anode (EL1) patterns may be arranged to not overlap the separator (SPR).

[0172] As described above, a first power supply voltage (VDD, see FIG. 2a) may be applied to the anode (EL1), and a common voltage may be provided to all light-emitting units. The anode (EL1) may be connected to a first power supply line (VDL, see FIG. 2a) that provides the first power supply voltage (VDD) in the peripheral area (NDA), or may be connected to a first power supply line (VDL, see FIG. 2a) in the display area (DA), and is not limited to any one embodiment.

[0173] According to the present embodiment, a plurality of openings may be defined in the anode (EL1), and the openings may penetrate the anode (EL1) layer. The openings in the anode (EL1) layer may be positioned at positions that do not overlap with the light-emitting portions (EP, see FIG. 3a), and may be generally defined at positions that overlap with the separator (SPR). The openings may facilitate the discharge of gas generated from an organic layer disposed under the anode (EL1), for example, a sixth insulating layer (60, see FIG. 5) described below. Accordingly, the gas of the organic layer disposed under the light-emitting element may be sufficiently discharged during the display panel manufacturing process, and the gas emitted from the organic layer after manufacturing may be reduced, thereby reducing the rate at which the light-emitting element deteriorates.

[0174] Fig. 5 is a cross-sectional view of a display panel (DP) according to an embodiment of the present invention. Fig. 6 is an enlarged cross-sectional view of a portion of a display panel (DP) according to an embodiment of the present invention. Fig. 7 is an enlarged cross-sectional view of a portion of a display panel (DP) according to an embodiment of the present invention. Fig. 5 is a cross-sectional view showing a portion corresponding to line I-I' of Fig. 4a. Fig. 6 is an enlarged cross-sectional view of area AA' of Fig. 5. Fig. 7 is an enlarged cross-sectional view of area BB' of Fig. 5.

[0175] Referring to FIGS. 5 to 7, a display panel (DP) of one embodiment may include a base layer (BS), a driving element layer (DDL), a connection line (CN), a light emitting element layer (LDL), an encapsulation layer (ECL), and a sensing layer (ISL). However, this is an example, and in one embodiment of the present invention, the display panel (DP) may not include the sensing layer (ISL).

[0176] A driving device layer (DDL) may include a plurality of insulating layers (10, 20, 30, 40, 50, 60) disposed on a base layer (BS), and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers (10, 20, 30, 40, 50, 60). The conductive patterns and semiconductor patterns may be disposed between the insulating layers (10, 20, 30, 40, 50, 60) to form a pixel driver (PDC). For easy explanation, FIG. 5 illustrates a cross-section of one area among the areas where one light-emitting unit is disposed.

[0177] The base layer (BS) may be a member that provides a base surface on which a pixel driver (PDC) is arranged. The base layer (BS) may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer (BS) may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer (BS) may be an inorganic layer, an organic layer, or a composite material layer.

[0178] The base layer (BS) may have a multilayer structure. The base layer (BS) may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0179] The polymer resin layer may include a polyimide-based resin. In addition, the polymer resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the present specification, the "~~-based" resin means one that includes a "~~" functional group.

[0180] Each of the insulating layers, conductive layers, and semiconductor layers disposed on the base layer (BS) can be formed by, for example, coating and deposition. Thereafter, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, and signal lines.

[0181] The driving element layer (DDL) may include first to sixth insulating layers (10, 20, 30, 40, 50, 60) sequentially stacked on the base layer (BS) and a pixel driver (PDC). FIG. 5 illustrates one transistor (TR) and two capacitors (C1, C2) of the pixel driver (PDC). In this specification, the fifth insulating layer (50) may be referred to as a lower insulating layer, and the sixth insulating layer (60) may be referred to as a middle insulating layer.

[0182] The transistor (TR) corresponds to a transistor connected to the light emitting element (LD) through a connection wire (CN) and a connection electrode (CNE), i.e., a connection transistor connected to a node corresponding to the cathode of the light emitting element (LD) (the fourth node (N4) of FIG. 2A, the second node (N2) of FIG. 2B, or the fourth node (N4) of FIG. 2C), and specifically, may correspond to the sixth transistor (T6) of FIG. 2A, the first transistor (T1) of FIG. 2B, or the fourth transistor (T4a) of FIG. 2C. In one embodiment, although not shown, other transistors constituting the pixel driver (PDC) may have the same structure as the transistor (TR, hereinafter referred to as connection transistor) illustrated in FIG. 5. However, this is merely an example, and other transistors constituting the pixel driver (PDC) may have a structure different from that of the connection transistor (TR), and are not limited to any one embodiment.

[0183] A first insulating layer (10) may be disposed on the base layer (BS). The first insulating layer (10) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer (10) is illustrated as a single-layer silicon oxide layer. In one embodiment, the insulating layers described below may be inorganic layers and / or organic layers, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-described materials, but is not limited thereto.

[0184] In one aspect, the first insulating layer (10) may cover the lower conductive layer (BCL). That is, the display panel (DP) may further include a lower conductive layer (BCL) arranged to overlap the connection transistor (TR). The lower conductive layer (BCL) may block an electric potential caused by a polarization phenomenon of the base layer (BS) from affecting the connection transistor (TR). In one aspect, the lower conductive layer (BCL) may block light incident on the connection transistor (TR) from below. At least one of an inorganic barrier layer and a buffer layer may be further arranged between the lower conductive layer (BCL) and the base layer (BS).

[0185] The bottom conductive layer (BCL) may include a reflective metal. For example, the bottom conductive layer (BCL) may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0186] In the present embodiment, the lower conductive layer (BCL) may be connected to the source of the connection transistor (TR, or transistor) through the source electrode pattern (W1). In this case, the lower conductive layer (BCL) may be synchronized with the source of the transistor (TR). However, this is merely an example, and the lower conductive layer (BCL) may be connected to the gate of the transistor (TR) and may be synchronized with the gate. Alternatively, the lower conductive layer (BCL) may be connected to another electrode and independently receive a constant voltage or pulse signal. Alternatively, the lower conductive layer (BCL) may be provided in a form isolated from other conductive patterns. The lower conductive layer (BCL) according to one embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0187] A connection transistor (TR) may be disposed on a first insulating layer (10). The connection transistor (TR) may include a semiconductor pattern (SP) and a gate electrode (GE). The semiconductor pattern (SP) may be disposed on the first insulating layer (10). The semiconductor pattern (SP) may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the present invention is not limited thereto, and the semiconductor pattern (SP) may include amorphous silicon, low-temperature crystalline silicon, or polycrystalline silicon.

[0188] A semiconductor pattern (SP) may include a source region (SR), a drain region (DR), and a channel region (CR), which are distinguished according to the degree of conductivity. The channel region (CR) may be a portion that overlaps with the gate electrode (GE) on a plane. The source region (SR) and the drain region (DR) may be portions spaced apart from the channel region (CR) between the source region (SR) and the drain region (DR). For example, when the semiconductor pattern (SP) is an oxide semiconductor, each of the source region (SR) and the drain region (DR) may be a reduced region. Accordingly, the source region (SR) and the drain region (DR) have a relatively high reduced metal content compared to the channel region (CR). Alternatively, when the semiconductor pattern (SP) is polycrystalline silicon, each of the source region (SR) and the drain region (DR) may be a highly doped region.

[0189] The source region (SR) and the drain region (DR) may have relatively high conductivity compared to the channel region (CR). The source region (SR) may correspond to the source electrode of the connection transistor (TR), and the drain region (DR) may correspond to the drain electrode of the connection transistor (TR). As illustrated in FIG. 5, separate source electrode patterns (W1) and drain electrode patterns (W2) may be further provided, each connected to the source region (SR) and the drain region (DR). Specifically, the separate source electrode patterns (W1) and drain electrode patterns (W2) may be formed integrally with one of the lines constituting the pixel driver (see PDC of FIG. 2a, PDC-1 of FIG. 2b, or PDC-2 of FIG. 2c), and are not limited to any one embodiment.

[0190] The second insulating layer (20) overlaps a plurality of pixels in common and can cover the semiconductor pattern (SP). The second insulating layer (20) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer (20) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the second insulating layer (20) may be a single-layer silicon oxide layer.

[0191] The gate electrode (GE) may be disposed on the second insulating layer (20). The gate electrode (GE) may correspond to the gate of the connection transistor (TR). In one aspect, the gate electrode (GE) may be disposed on the upper side of the semiconductor pattern (SP). However, this is merely an example, and the gate electrode (GE) may also be disposed on the lower side of the semiconductor pattern (SP), and is not limited to any one embodiment.

[0192] The gate electrode (GE) may include, but is not particularly limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof.

[0193] A third insulating layer (30) may be disposed on the gate electrode (GE). The third insulating layer (30) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer (40) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0194] Among the plurality of conductive patterns (W1, W2, CPE1, CPE2, CPE3), the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) constitute the first capacitor (C1). The first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) may be spaced apart from each other by the first insulating layer (10) and the second insulating layer (20) between the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2).

[0195] In one embodiment of the present invention, the first capacitor electrode (CPE1) and the lower conductive layer (BCL) may have an integral shape. In one aspect, the second capacitor electrode (CPE2) and the gate electrode (GE) may have an integral shape.

[0196] A third capacitor electrode (CPE3) may be disposed on a third insulating layer (30). The third capacitor electrode (CPE3) may be spaced apart from the third insulating layer (30) between the third capacitor electrode (CPE3) and the second capacitor electrode (CPE2) and from the second capacitor electrode (CPE2). The third capacitor electrode (CPE3) and the second capacitor electrode (CPE2) may overlap on a plane. The third capacitor electrode (CPE3) may constitute the second capacitor electrode (CPE2) and the second capacitor (C2).

[0197] A fourth insulating layer (40) may be disposed on the third insulating layer (30) and / or the third capacitor electrode (CPE3). The fourth insulating layer (40) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer (40) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0198] A source electrode pattern (W1) and a drain electrode pattern (W2) may be disposed on a fourth insulating layer (40). The source electrode pattern (W1) may be connected to a source region (SR) of a connection transistor (TR) through a first contact hole (CNT1), and the source electrode pattern (W1) and the source region (SR) of the semiconductor pattern (SP) may function as a source of the connection transistor (TR). The drain electrode pattern (W2) may be connected to a drain region (DR) of the connection transistor (TR) through a second contact hole (CNT2), and the drain electrode pattern (W2) and the drain region (DR) of the semiconductor pattern (SP) may function as a drain of the connection transistor (TR). A fifth insulating layer (50) may be disposed on the source electrode pattern (W1) and the drain electrode pattern (W2).

[0199] A connection wiring (CN) may be arranged on the fifth insulating layer (50). The connection wiring (CN) may electrically connect the pixel driver (PDC) and the light emitting element (LD). That is, the connection wiring (CN) may electrically connect the connection transistor (TR) and the light emitting element (LD). The connection wiring (CN) may be a connection node connecting the pixel driver (PDC) and the light emitting element (LD). That is, the connection wiring (CN) may correspond to the fourth node (N4, see FIG. 2a) illustrated in FIG. 2a, the second node (N2, see FIG. 2b) illustrated in FIG. 2b, or the fourth node (N4, see FIG. 2c) illustrated in FIG. 2c.

[0200] The connection wiring (CN) of FIG. 5 may correspond to the connection wiring that electrically connects the first pixel driver (PDC1, see FIG. 4b) and the first light-emitting element (LD1, see FIG. 4c). However, the connection wiring that electrically connects the second pixel driver (PDC2, see FIG. 4b) and the second light-emitting element (LD2, see FIG. 4c), and the connection wiring (CN3, see FIG. 4a) that electrically connects the third pixel driver (PDC3, see FIG. 4b) and the third light-emitting element (LD3, see FIG. 4c) may also have a structure similar to the connection wiring (CN) of FIG. 5.

[0201] A sixth insulating layer (60) may be disposed on the connection wiring (CN). The sixth insulating layer (60) may be disposed on the fifth insulating layer (50) to cover at least a portion of the connection wiring (CN). Each of the fifth insulating layer (50) and the sixth insulating layer (60) may be an organic layer. For example, each of the fifth insulating layer (50) and the sixth insulating layer (60) may include a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, and blends thereof.

[0202] The sixth insulating layer (60) may be provided with a second through hole (OP-60) that exposes at least a portion of the connection wiring (CN). The connection wiring (CN) may be connected to the connection electrode (CNE) through a portion exposed from the sixth insulating layer (60), and may be electrically connected to the light emitting element (LD). That is, the connection wiring (CN) may electrically connect the connection transistor (TR) and the light emitting element (LD) together with the connection electrode (CNE). In the present specification, the area where the connection wiring (CN) and the connection electrode (CNE) are connected may be referred to as a connection area (CNA). The connection area (CNA) may be defined within the second through hole (OP-60). In the display panel (DP) according to an embodiment of the present invention, the sixth insulating layer (60) may be omitted or provided in multiple forms, and is not limited to any one embodiment.

[0203] A light-emitting device layer (LDL) may be disposed on a driving device layer (DDL). The light-emitting device layer (LDL) may include a pixel defining layer (PDL), a light-emitting device (LD), and a separator (SPR).

[0204] The pixel defining layer (PDL) may be an organic layer. For example, the pixel defining layer (PDL) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0205] In one embodiment, the pixel defining layer (PDL) may have a light-absorbing property and may have, for example, a black color. That is, the pixel defining layer (PDL) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer (PDL) may correspond to a light-shielding pattern having light-shielding properties.

[0206] An opening (OP-PDL, hereinafter referred to as an emission opening) exposing at least a portion of a first electrode (EL1) to be described later may be defined in a pixel defining layer (PDL). A plurality of emission openings (OP-PDL) may be provided and arranged to correspond to each of the emission elements. All components of the emission element (LD) may be arranged to overlap in the emission opening (OP-PDL), and may be an area where light emitted by the emission element (LD) is substantially displayed. Accordingly, the shape of the first emission portion (EP1, see FIG. 4A) may substantially correspond to the shape of the emission opening (OP-PDL) on a plane. An area corresponding to the first emission portion (EP1), that is, an area defined by the emission opening (OP-PDL), may be referred to as an emission area (EA).

[0207] A connection electrode (CNE) may be arranged on a pixel defining layer (PDL). The connection electrode (CNE) may electrically connect a pixel driver (PDC) and a light emitting element (LD). That is, the pixel driver (PDC) may be electrically connected to the light emitting element (LD) via a connection line (CN) and the connection electrode (CNE). The connection electrode (CNE) may correspond to the first connection electrode (CNE1) illustrated in FIG. 4a. The second connection electrode (CNE2, see FIG. 4a) and the third connection electrode (CNE3, see FIG. 4a) may also have structures similar to the connection electrode (CNE).

[0208] The connecting electrode (CNE) may include a first edge (EG1c) adjacent to the light-emitting aperture (OP-PDL) and a second edge (EG2c) surrounding the first edge (EG1c). The second electrode (EL2) of the light-emitting element (LD) may be in contact with the connecting electrode (CNE) in an area adjacent to the second edge (EG2c).

[0209] The connecting electrode (CNE) may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the material constituting the connecting electrode (CNE) is not limited to the above examples. For example, the connecting electrode (CNE) may also include a metallic material.

[0210] A pixel defining layer (PDL) may define a first through hole (OP-P) spaced apart from a light-emitting opening (OP-PDL). A plurality of first through holes (OP-P) may be provided and arranged to correspond to each light-emitting element. The size of the first through hole (OP-P) defined in the pixel defining layer (PDL) may be larger than the size of the second through hole (OP-60) defined in the sixth insulating layer (60). A connection electrode (CNE) may be arranged within the first through hole (OP-P) and the second through hole (OP-60) and may be connected to a connection wire (CN).

[0211] The light emitting element (LD) may include a first electrode (EL1), an intermediate layer (IML), and a second electrode (EL2).

[0212] The first electrode (EL1) may be a semi-transparent, transparent, or reflective electrode. According to one embodiment of the present invention, the first electrode (EL1) may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (EL1) may include a stacked structure of ITO / Ag / ITO.

[0213] In the present embodiment, the first electrode (EL1) may be an anode of the light emitting element (LD). That is, the first electrode (EL1) may be connected to a first power line (VDL, see FIG. 2A) and may be applied with a first power voltage (VDD, see FIG. 2A). The first electrode (EL1) may be connected to the first power line (VDL) within a display area (DA, see FIG. 3A or 3B) or may be connected to the first power line (VDL) in a peripheral area (NDA). In the latter case, the first power line (VDL) may be arranged in the peripheral area (NDA, see FIG. 3A or 3B) and the first electrode (EL1) may have a shape extending to the peripheral area (NDA).

[0214] In the cross-sectional view of FIG. 5, the first electrode (EL1) is illustrated as overlapping the light-emitting opening (OP-PDL) and not overlapping the separator (SPR). However, as described above in FIG. 4d, the first electrodes (EL1) of the light-emitting elements may have a single shape and a mesh or lattice shape in which the openings are defined in some areas. That is, as long as the same first power supply voltage (VDD) can be applied to the first electrodes (EL1) of each of the plurality of light-emitting elements, the shape of the first electrodes (EL1) may be provided in various ways and is not limited to any one embodiment.

[0215] An intermediate layer (IML) may be disposed between a first electrode (EL1) and a second electrode (EL2). The intermediate layer (IML) may include an emission layer (EML) and a functional layer (FNL). The light-emitting element (LD) may include the intermediate layer (IML) in various structures and is not limited to any one embodiment. For example, the functional layer (FNL) may be provided as a plurality of layers, or may be provided as two or more layers spaced apart from the emission layer (EML) between two or more layers.

[0216] Referring to FIGS. 5 and 6, the functional layer (FNL) may be disposed between the first electrode (EL1) and the second electrode (EL2). The functional layer (FNL) may include a first intermediate functional layer (FNLa) disposed between the first electrode (EL1) and the light-emitting layer (EML), and a second intermediate functional layer (FNLb) disposed between the second electrode (EL2) and the light-emitting layer (EML). In the present embodiment, the light-emitting layer (EML) is illustrated as being inserted into the functional layer (FNL). That is, it can be understood that the light-emitting layer (EML) is disposed between the first intermediate functional layer (FNLa) and the second intermediate functional layer (FNLb).

[0217] The functional layer (FNL) can control the movement of charges between the first electrode (EL1) and the second electrode (EL2). For example, the first intermediate functional layer (FNLa) can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer (FNLb) can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0218] The light-emitting layer (EML) may include an organic light-emitting material. In addition, the light-emitting layer (EML) may include an inorganic light-emitting material, or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In the present embodiment, the light-emitting layers (EML) included in each adjacent light-emitting portion (EP, see FIG. 3a) may include light-emitting materials that display different colors. For example, the light-emitting layer (EML) included in each light-emitting portion (EP) may provide light of any one of blue, red, and green. However, the present invention is not limited thereto, and the light-emitting layers (EML) disposed in all light-emitting portions (EP) may include light-emitting materials that display the same color. In this case, the light-emitting layers (EML) may provide blue light or white light.

[0219] The second electrode (EL2) may be disposed on the intermediate layer (IML). As described above, the second electrode (EL2) may be electrically connected to the pixel driver (PDC) by being connected to the connection electrode (CNE). That is, the second electrode (EL2) may be electrically connected to the connection transistor (TR) through the connection electrode (CNE).

[0220] A separator (SPR) may be disposed on a pixel defining layer (PDL). In one aspect, the separator (SPR) may be disposed on a connection electrode (CNE) disposed on the pixel defining layer (PDL) and a gap (GP) between the connection electrode (CNE) and an adjacent connection electrode.

[0221] In one embodiment, the second electrode (EL2) and the functional layer (FNL) may be formed by common deposition on a plurality of pixels through an open mask. At this time, the second electrode (EL2) and the functional layer (FNL) may be divided by a separator (SPR). As described above, the separator (SPR) may have a closed line shape for each light-emitting portion, and accordingly, the second electrode (EL2) and the functional layer (FNL) may have a divided shape for each light-emitting portion. That is, the second electrode (EL2) and the intermediate layer (IML) may be electrically independent for each adjacent pixel.

[0222] In one embodiment, the separator (SPR) may have a reverse taper shape. That is, the separator (SPR) may have a shape whose width increases as it gets farther from the upper surface of the pixel defining layer (PDL). The side surface (TP) of the separator (SPR) may have a shape with an obtuse taper angle inclined from the upper surface of the pixel defining layer (PDL). However, this is merely an example, and if the separator (SPR) can electrically disconnect the second electrode (EL2) for each pixel, the taper angle of the separator (SPR) may be set in various ways, and for example, may have a dual structure with different taper angles. In one aspect, the separator (SPR) may have a structure such as a tip portion and is not limited to any one embodiment.

[0223] As illustrated in FIGS. 5 and 6, the separator (SPR) may have a double reverse taper shape. The side surface (TP) of the separator (SPR) may include a first side surface (TP1) and a second side surface (TP2) having different taper angles. The taper angle formed by the first side surface (TP1) of the separator (SPR) with respect to the upper surface of the pixel defining layer (PDL) and the taper angle formed by the second side surface (TP2) with respect to the upper surface of the pixel defining layer (PDL) may be different from each other. Each of the taper angles may be an obtuse angle. For example, as illustrated in FIG. 6, the taper angle formed by the first side surface (TP1) with respect to the upper surface of the pixel defining layer (PDL) may be smaller than the taper angle formed by the second side surface (TP2) with respect to the upper surface of the pixel defining layer (PDL). However, this is merely an example, and the taper angles can be set in various ways as long as the separator (SPR) can electrically disconnect the second electrode (EL2) for each pixel. In one aspect, the separator (SPR) may have a structure similar to a tip portion and is not limited to any one embodiment.

[0224] The separator (SPR) may include an insulating material, and in particular, an organic insulating material. The separator (SPR) may also include an inorganic insulating material, may be composed of multiple layers of organic and inorganic insulating materials, and may include a conductive material, depending on the embodiment. That is, as long as the second electrode (EL2) can be electrically isolated for each pixel, the separator (SPR) is not particularly limited in terms of the type of material.

[0225] A dummy layer (UP) may be disposed on the separator (SPR). The dummy layer (UP) may include a first dummy layer (UP1) disposed on the separator (SPR) and a second dummy layer (UP2) disposed on the first dummy layer (UP1). The first dummy layer (UP1) may be formed by the same process as the intermediate layer (IML) and may include the same material. The first dummy layer (UP1) may include a 1-1 dummy layer (UP1a) and a 1-2 dummy layer (UP1b). The 1-1 dummy layer (UP1a) may be formed by the same process as the first intermediate functional layer (FNLa) and may include the same material. The 1-2 dummy layer (UP1b) may be formed by the same process as the second intermediate functional layer (FNLb) and may include the same material. The second dummy layer (UP2) may be formed by the same process as the second electrode (EL2) and may include the same material. That is, the first dummy layer (UP1) and the second dummy layer (UP2) may be formed simultaneously during the process of forming the functional layer (FNL) and the second electrode (EL2). As illustrated in FIG. 6, the dummy layer (UP) may be formed not only on the upper surface of the separator (SPR) but also on a portion of the side surface (TP). In another embodiment, the display panel (DP) may not include the dummy layer (UP). The dummy layer (UP) may be in non-contact with the connection electrode (CNE) and the second electrode (EL2). The second dummy layer (UP2) included in the dummy layer (UP) may be in non-contact with the connection electrode (CNE) and the second electrode (EL2).

[0226] The second electrode (EL2) is in contact with the connection electrode (CNE) through a contact area (CA). The contact area (CA) may include a first contact area (CAa) and a second contact area (CAb). The first contact area (CAa) is provided adjacent to the separator (SPR). The second contact area (CAb) is provided adjacent to a side of the connection wiring (CN) exposed by the first and second through-holes (OP-P, OP-60). A detailed description of the second contact area (CAb) will be described later, and the first contact area (CAa) will be described in detail with reference to FIGS. 5 and 6 .

[0227] In the first contact area (CAa), the upper surface (CNE-us) of the connection electrode (CNE) is in contact with the lower surface (EL2-bs) of the second electrode (EL2). In one embodiment, since the separator (SPR) has a reverse tapered shape and the first contact area (CAa) is provided adjacent to (e.g., relatively close, within a target distance) the separator (SPR), at least a portion of the first contact area (CAa) where the second electrode (EL2) and the connection electrode (CNE) are in contact may be disposed below the side surface (TP) of the separator (SPR). The first contact area (CAa) may have a ring shape that surrounds at least a portion of the light-emitting opening (OP-PDL) of the pixel defining layer (PDL) on a plane.

[0228] In one embodiment, at least a portion of the connecting electrode (CNE) may be disposed under the separator (SPR). The separator (SPR) may be disposed over a gap (GP) between the connecting electrode (CNE) and an adjacent connecting electrode adjacent to the connecting electrode (CNE), and a second edge (EG2c) of the second electrode (EL2) may be covered by the separator (SPR).

[0229] A display panel (DP) of one embodiment may include an intermediate area (MA) disposed between an emission area (EA) in which a light emitting element (LD) is disposed and a first contact area (CAa). The intermediate area (MA) may be an area in which at least a portion of an intermediate layer (IML) is disposed. In the intermediate area (MA), a functional layer (FNL) included in the intermediate layer (IML) may be disposed between a connection electrode (CNE) and a second electrode (EL2). That is, in the intermediate area (MA), the connection electrode (CNE) and the second electrode (EL2) may be spaced apart from each other, with the functional layer (FNL) between the connection electrode (CNE) and the second electrode (EL2).

[0230] The intermediate region (MA) may be adjacent to the first contact region (CAa). The functional layer (FNL) disposed in the intermediate region (MA) may include the first intermediate functional layer (FNLa) and the second intermediate functional layer (FNLb) described above. The first intermediate functional layer (FNLa) may be disposed between the first electrode (EL1) and the emission layer (EML) in the emission region (EA), and the second intermediate functional layer (FNLb) may be disposed between the second electrode (EL2) and the emission layer (EML) in the emission region (EA).

[0231] In the display panel (DP) of one embodiment, the functional layer (FNL) and the second electrode (EL2) may be formed through different deposition process methods. The second electrode (EL2) may be formed by a deposition method that can deposit a deposition material at a lower incident angle than the deposition method for forming the functional layer (FNL). The functional layer (FNL) may be formed, for example, by a thermal evaporation method, and the second electrode (EL2) may be covered by a sputtering method. Accordingly, in the process of forming the functional layer (FNL), the material for forming the functional layer (FNL) may not penetrate below the side surface (TP) of the separator (SPR), thereby exposing a part of the connection electrode (CNE), and the second electrode (EL2) may be formed closer to the separator (SPR) than the functional layer (FNL), so that the second electrode (EL2) may contact the upper surface (CNE-us) of the exposed connection electrode (CNE). That is, a first contact area (CAa) where the second electrode (EL2) and the connection electrode (CNE) come into contact can be formed through differences in the deposition process methods in the functional layer (FNL) and second electrode (EL2) formation processes.

[0232] In one embodiment, as illustrated in FIG. 5, a connection area (CNA) where a connection electrode (CNE) is connected to a connection wire (CN) may be disposed between a light-emitting area (EA) and a first contact area (CAa). The connection area (CNA) may overlap an intermediate area (MA). At least a portion of an intermediate layer (IML) may be disposed to overlap the connection area (CNA). In the display panel (DP) of one embodiment, a functional layer (FNL) included in the intermediate layer (IML) may be disposed to overlap the connection area (CNA).

[0233] According to one embodiment of the present invention, the connection electrode (CNE) has a shape that surrounds at least a portion of the light-emitting area (EA) where the light-emitting element (LD) is arranged. Therefore, the degree of freedom of the position at which the connection electrode (CNE) and the light-emitting element (LD) are connected and the degree of freedom of the position at which the connection electrode (CNE) and the pixel driver (PDC) are connected can be improved. In one aspect, the upper surface (CNE-us) of the connection electrode (CNE) can be in contact with the lower surface (EL2-bs) of the second electrode (EL2) of the light-emitting element (LD) through the first contact area (CAa) defined adjacent to the separator (SPR). Accordingly, the contact reliability of the connection electrode (CNE) and the second electrode (EL2) can be improved, and since the lower surface of the connection electrode (CNE) and the upper surface of the connection wiring (CN) are in contact, the contact reliability can be improved. According to one embodiment, the display panel (DP) can have the size of the first and second through-holes (OP-P, OP-60) for connecting the connection electrode (CNE) and the connection wire (CN) through the described structure reduced or minimized, thereby easily increasing the area or resolution of the light-emitting portion of the display panel (DP).

[0234] As illustrated in FIGS. 5 and 7, the connection electrode (CNE) may be electrically connected to the pixel driver (PDC) through the connection wiring (CN). As described above, the connection wiring (CN) may include a driving connection portion (CD) and a light emitting connection portion (CE). The driving connection portion (CD) may be a portion of the connection wiring (CN) that is connected to the pixel driver (PDC) and may be a portion that is substantially connected to the connection transistor (TR). In the present embodiment, the driving connection portion (CD) may be connected to the drain electrode pattern (W2) through a contact hole penetrating the fifth insulating layer (50) and may be electrically connected to the drain region (DR) of the semiconductor pattern (SP) through the drain electrode pattern (W2). The light emitting connection portion (CE) may be a portion of the connection wiring (CN) that is connected to the connection electrode (CNE). The light emitting connection portion (CE) may be defined in an area exposed from the sixth insulating layer (60) and may be a portion to which the connection electrode (CNE) is connected. At this time, a tip portion (TIP) can be defined in the luminescent connection portion (CE).

[0235] Referring to FIGS. 5 and 7, the light emitting connection portion (CE) of the connection wiring (CN) will be described in more detail. As illustrated in FIGS. 5 and 7, the connection wiring (CN) may have a three-layer structure. A tip portion (TIP) may be defined at at least a portion of an edge of the connection wiring (CN). The edge of the connection wiring (CN) where the tip portion (TIP) is defined may correspond to a portion of the edge of the connection wiring (CN) that is exposed from the sixth insulating layer (60) and the pixel defining film (PDL) by the first and second through-holes (OP-P, OP-60). In other words, the first and second through-holes (OP-P, OP-60) may expose the tip portion (TIP) of the connection wiring (CN) from the sixth insulating layer (60) and the pixel defining film (PDL).

[0236] Specifically, the connecting wiring (CN) may include a first layer (L1), a second layer (L2), and a third layer (L3) sequentially laminated along a third direction (DR3). The side surface (CN_W) of the connecting wiring (CN) may include a side surface (L1_W) of the first layer (L1), a side surface (L2_W) of the second layer (L2), and a side surface (L3_W) of the third layer (L3).

[0237] The second layer (L2) may include a different material from the first layer (L1). In one aspect, the second layer (L2) may include a different material from the third layer (L3). The second layer (L2) may have a relatively thicker thickness than the first layer (L1). Additionally, the second layer (L2) may have a relatively thicker thickness than the third layer (L3). The second layer (L2) may include a highly conductive material. In one embodiment, the second layer (L2) may include aluminum (Al).

[0238] In one embodiment, the first layer (L1) may include a material having a lower etch rate than the second layer (L2). That is, the second layer (L2) may be composed of materials having a high etch selectivity with respect to the first layer (L1). In one embodiment, the first layer (L1) may include titanium (Ti), and the second layer (L2) may include aluminum (Al). In this case, the side surface (L1_W) of the first layer (L1) may be defined on the outside relative to the side surface (L2_W) of the second layer (L2). That is, the light emitting connection portion (CE) of the connection wiring (CN) may have a shape in which the side surface (L1_W) of the first layer (L1) protrudes outward from the side surface (L2_W) of the second layer (L2). That is, the light-emitting connection portion (CE) of the connecting wire (CN) may have a shape in which the side surface (L2_W) of the second layer (L2) is sunken inward from the side surface (L1_W) of the first layer (L1).

[0239] In one aspect, the third layer (L3) may include a material having a lower etch rate than the second layer (L2). That is, the third layer (L3) and the second layer (L2) may be composed of materials having a high etch selectivity to each other. In one embodiment, the third layer (L3) may include titanium (Ti), and the second layer (L2) may include aluminum (Al). In this case, the side surface (L3_W) of the third layer (L3) may be defined on the outside relative to the side surface (L2_W) of the second layer (L2). That is, the light emitting connection portion (CE) of the connection wiring (CN) may have a shape in which the side surface (L3_W) of the third layer (L3) protrudes outward from the side surface (L2_W) of the second layer (L2). That is, the light emitting connection portion (CE) of the connecting wire (CN) may have an undercut shape or an overhang structure, and a tip portion (TIP) may be defined in the connecting wire (CN) by a portion that protrudes compared to the second layer (L2) among the third layer (L3).

[0240] The sixth insulating layer (60) and the pixel defining layer (PDL) can expose at least a portion of the tip portion (TIP) and at least a portion of the side surface (L2_W) of the second layer (L2). Specifically, a second through hole (OP-60) exposing one side of the connection line (CN) can be defined in the sixth insulating layer (60), and a first through hole (OP-P) overlapping the second through hole (OP-60) can be defined in the pixel defining layer (PDL). The planar area of ​​the first through hole (OP-P) can be larger than the planar area of ​​the second through hole (OP-60). However, the embodiments of the present invention are not limited thereto, and as long as at least a portion of the tip portion (TIP) and at least a portion of the second side surface (L2_W) can be exposed, the planar area of ​​the first through hole (OP-P) can be smaller than or equal to the planar area of ​​the second through hole (OP-60).

[0241] A connection electrode (CNE) may be disposed on the pixel defining layer (PDL). The connection electrode (CNE) may also be disposed on a portion of the sixth insulating layer (60) exposed by the first through hole (OP-P) of the pixel defining layer (PDL). In one aspect, the connection electrode (CNE) may also be disposed on a portion of the connection wiring (CN) exposed by the second through hole (OP-60) of the sixth insulating layer (60). As illustrated in FIG. 7, the connection electrode (CNE) may include one end (CEN1) disposed along the upper surface of the fifth insulating layer (50) and the other end (CEN2) disposed along the upper surface of the connection wiring (CN) defining a tip portion (TIP). That is, when viewed in cross section, the connection electrode (CNE) may have a shape in which the connection is partially disconnected with respect to the tip portion (TIP) in an area where the light-emitting connection portion (CE) is defined. However, when viewed from a planar perspective, the connecting electrode (CNE) may be an integral shape that is entirely connected within an area defined by a closed line by a separator (SPR) (see Fig. 4).

[0242] An intermediate layer (IML) may be disposed on the connecting electrode (CNE). The intermediate layer (IML) may also be disposed on a portion of the sixth insulating layer (60) exposed by the first through hole (OP-P) of the pixel defining layer (PDL). In one aspect, the intermediate layer (IML) may also be disposed on a portion of the connecting wire (CN) exposed by the second through hole (OP-60) of the sixth insulating layer (60). As illustrated in FIG. 7, the intermediate layer (IML) may include one end (IN1) disposed along the upper surface of the fifth insulating layer (50) and the other end (IN2) disposed along the upper surface of the connecting wire (CN) defining a tip portion (TIP). That is, when viewed in cross section, the intermediate layer (IML) may have a shape in which the connection is partially disconnected with respect to the tip portion (TIP) in the area where the light-emitting connection portion (CE) is defined. However, when viewed from a planar perspective, the intermediate layer (IML) may be an integral shape that is entirely connected within an area defined by a closed line by the separator (SPR) (see Fig. 4).

[0243] A second electrode (EL) may be disposed on the intermediate layer (IML). The second electrode (EL2) may also be disposed on a portion of the sixth insulating layer (60) exposed by the first through hole (OP-P) of the pixel defining layer (PDL). In one aspect, the second electrode (EL2) may also be disposed on a portion of the connection wire (CN) exposed by the second through hole (OP-60) of the sixth insulating layer (60). As illustrated in FIG. 7, the second electrode (EL2) may include one end (EN1) of the second electrode (EL2) disposed along the upper surface of the fifth insulating layer (50) and the other end (EN2) disposed along the upper surface of the connection wire (CN) defining the tip portion (TIP). That is, when viewed in cross section, the second electrode (EL2) may have a shape in which the connection is partially disconnected with respect to the tip portion (TIP) in the area where the light emitting connection portion (CE) is defined. However, when viewed from a planar perspective, the second electrode (EL2) may be an integral shape that is entirely connected within a region defined by a closed curve by the separator (SPR) (see Fig. 4).

[0244] One end (CEN1) of the connecting electrode (CNE) is arranged along the side surface (L2_W) of the second layer (L2) so as to be in contact with the side surface (L2_W) of the second layer (L2). That is, the side surface of the connecting wire (CN) is exposed by the first and second through-holes (OP-P, OP-60), so that the connecting electrode (CNE) can be formed to be in contact with the exposed side surface of the connecting wire (CN) (i.e., the side surface (L2_W) of the second layer (L2)).

[0245] As described above, the second electrode (EL2) can be in contact with the connection electrode (CNE) through the second contact area (CAb). The second contact area (CAb) can be provided adjacent to the side surface (L2_W) of the second layer (L2) exposed from the sixth insulating layer (60) and the pixel defining layer (PDL) by the first and second through-holes (OP-P, OP-60). In the second contact area (CAb), one end portion (EN1) of the second electrode (EL2) can be in contact with one end portion (CEN1) of the connection electrode (CNE) that is in contact with the side surface (L2_W) of the second layer (L2). Specifically, through the difference in the deposition angles of the second electrode (EL2) and the intermediate layer (IML), the second electrode (EL2) can be formed to contact one end (CEN1) of the connection wire (CN) exposed from the intermediate layer (IML) by the tip portion (TIP). That is, the second electrode (EL2) can be connected to the connection electrode (CNE) without a separate patterning process for the intermediate layer (IML), and can be connected to the connection wire (CN) through the connection electrode (CNE). Accordingly, the light emitting element (LD) can be electrically connected to the pixel driver (PDC) through the connection wire (CN).

[0246] In the present embodiment, the connection area (CNA) may include a first connection area (CNAa) and a second connection area (CNAb). The first connection area (CNAa) may be defined as an area where the connection electrode (CNE) is connected to the third layer (L3) of the connection wiring (CN) exposed by the first and second through-holes (OP-P, OP-60). The second connection area (CNAb) may be defined as an area where the connection electrode (CNE) is connected to the first layer (L1) and the second layer (L2) of the connection wiring (CN) exposed by the first and second through-holes (OP-P, OP-60). That is, the second connection area (CNAb) may correspond to an area where the connection electrode (CNE) is partially disconnected by the tip portion (TIP) and connected to an edge of the connection wiring (CN) where the tip portion (TIP) is defined below the tip portion (TIP).

[0247] According to the present embodiment, the connection electrode (CNE) is in contact with not only the top surface but also the side surface of the connection wire (CN), so that the contact reliability between the connection electrode (CNE) and the connection wire (CN) can be further improved. In one aspect, since the tip portion (TIP) is defined in the connection wire (CN), the cathode (EL2) can be in contact with one end of the connection electrode (CNE) that is in contact with the side surface of the connection wire (CN). Accordingly, the cathode (EL2) is in contact with the connection electrode (CNE) not only in the area adjacent to the separator (SPR) but also in the area adjacent to the tip portion (TIP) of the connection wire (CN), so that the contact reliability between the connection electrode (CNE) and the cathode (EL2) can be further improved. Accordingly, a relatively high luminance can be maintained even with a lower driving voltage, so that a low margin with respect to the driving voltage can be required, and power consumption can be reduced. That is, for example, embodiments of the present invention support maintaining relatively high luminance even at low driving voltages, so that the display device (DD) (and electronic devices including the display device (DD)) can be implemented with a low margin for driving voltage and power consumption can be reduced. In one aspect, relatively high contact reliability can be maintained even in high temperature and high humidity environments.

[0248] In FIGS. 5 and 7, the other end (CEN2) of the connecting electrode (CNE), the other end (IN2) of the intermediate layer (IML), and the other end (EN2) of the second electrode (EL2) are illustrated as covering the side surface (L3_W) of the third layer (L3), but this is merely an example, and at least a portion of the side surface (L3_W) of the third layer (L3) may be exposed from the other end (CEN2) of the connecting electrode (CNE), the other end (IN2) of the intermediate layer (IML), and / or the other end (EN2) of the second electrode (EL2).

[0249] Referring again to FIG. 5, an encapsulation layer (ECL) may be disposed on the light emitting element layer (LDL). The encapsulation layer (ECL) may cover the light emitting element (LD) and the separator (SPR). The encapsulation layer (ECL) may include a first inorganic layer (IL1), an organic layer (OL), and a second inorganic layer (IL2) that are sequentially laminated. However, the present invention is not limited thereto, and the encapsulation layer (ECL) may additionally include a plurality of inorganic layers and organic layers. In one aspect, the encapsulation layer (ECL) may be a glass substrate.

[0250] The first and second inorganic layers (IL1, IL2) protect the light emitting element (LD) from moisture and oxygen outside the display panel (DP), and the organic layer (OL) can protect the light emitting element (LD) from foreign substances such as particles remaining during the formation of the first inorganic layer (IL1). The first and second inorganic layers (IL1, IL2) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer (OL) may include an acrylic-based organic layer, and the type of material is not limited to any one.

[0251] The sensing layer (ISL) can sense an external input. In the present embodiment, the sensing layer (ISL) can be formed on the encapsulation layer (ECL) through a continuous process. At this time, the sensing layer (ISL) can be expressed as being directly disposed on the encapsulation layer (ECL). Directly disposed may mean that no other components are disposed between the sensing layer (ISL) and the encapsulation layer (ECL). In other words, a separate adhesive member may not be disposed between the sensing layer (ISL) and the encapsulation layer (ECL). However, this is merely an example, and in the display panel (DP) according to an embodiment of the present invention, the sensing layer (ISL) may be formed separately and then coupled to the display panel (DP) through an adhesive member, and is not limited to any one embodiment.

[0252] The sensing layer (ISL) may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer (MTL1) and a second sensing conductive layer (MTL2), and the plurality of insulating layers may include first to third sensing insulating layers (71, 72, 73). However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0253] Each of the first to third sensing insulating layers (71, 72, 73) may have a single-layer structure or a multi-layer structure laminated along the third direction (DR3). The first to third sensing insulating layers (71, 72, 73) may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers (71, 72, 73) may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0254] The first sensing conductive layer (MTL1) may be disposed between the first sensing insulating layer (71) and the second sensing insulating layer (72), and the second sensing conductive layer (MTL2) may be disposed between the second sensing insulating layer (72) and the third sensing insulating layer (73). A portion of the second sensing conductive layer (MTL2) may be connected to the first sensing conductive layer (MTL1) through a contact hole (CNT) formed in the second sensing insulating layer (72). Each of the first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may have a single-layer structure or a multi-layer structure stacked along the third direction (DR3).

[0255] The sensing conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

[0256] The multilayered sensing conductive layer may include metal layers. The metal layers may have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). Alternatively, the multilayered sensing conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0257] The first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) can form a sensor that detects an external input in the sensing layer (ISL). The sensor can be driven by a capacitive method, and can be driven by either a mutual capacitive method or a self-capacitive method. However, this is described as an example, and the sensor can also be driven by a resistive method, an ultrasonic method, or an infrared method in addition to a capacitive method, and is not limited to any one embodiment.

[0258] Each of the first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer (MTL1) and the second sensing conductive layer (MTL2) may have various materials and various shapes as long as the visibility of the image displayed by the display panel (DP) is not reduced, and are not limited to any one embodiment.

[0259] Fig. 8 is a graph showing the luminance according to the first power supply voltage (VDD) in one embodiment of the present invention and a comparative example. In explaining Fig. 8, the display panel of one embodiment of the present invention has a structure corresponding to Fig. 5. In explaining Fig. 8, the display panel of the comparative example of the present invention has a structure in which the side portion of the connection wiring is not exposed from the insulating layer and the pixel defining film and the tip portion of the connection wiring is not defined.

[0260] Graph 1 is a graph for a light-emitting element that provides red light in one embodiment of the present invention, and Graph 2 is a graph for a light-emitting element that provides red light in a comparative example of the present invention. Graph 3 is a graph for a light-emitting element that provides green light in one embodiment of the present invention, and Graph 4 is a graph for a light-emitting element that provides green light in a comparative example of the present invention. Graph 5 is a graph for a light-emitting element that provides blue light in one embodiment of the present invention, and Graph 6 is a graph for a light-emitting element that provides blue light in a comparative example of the present invention.

[0261] Referring to FIGS. 1, 5, and 8, as the first power supply voltage (VDD) decreases, the luminance of light provided through the light emitting element (LD) decreases. Referring to Graphs 1 and 2, in the case of a light emitting element (LD) that provides red light, it can be confirmed that, according to an embodiment of the present invention, the rate at which the luminance of light decreases is lower as the first power supply voltage (VDD) decreases compared to the comparative example. Referring to Graphs 3 and 4, in the case of a light emitting element (LD) that provides green light, it can be confirmed that, according to an embodiment of the present invention, the rate at which the luminance of light decreases is lower as the first power supply voltage (VDD) decreases compared to the comparative example. Referring to Graphs 5 and 6, in the case of a light emitting element (LD) that provides blue light, it can be confirmed that, according to an embodiment of the present invention, the rate at which the luminance of light decreases is lower as the first power supply voltage (VDD) decreases compared to the comparative example. That is, according to one embodiment of the present invention, it can be confirmed that relatively high luminance can be maintained even with a relatively low first power supply voltage (VDD) for all of red light, green light, and blue light. Therefore, according to one embodiment of the present invention, the margin for the first power supply voltage (VDD) can be lower than the margin relied on in the comparative example, and thus power consumption can be reduced.

[0262] FIGS. 9A and 9B are images related to the UHAST evaluation of a comparative example of the present invention. FIGS. 10A and 10B are images related to the UHAST evaluation of an embodiment of the present invention. The display panel (DP', DP'-H) of the comparative example of the present invention used in the UHAST evaluation of FIGS. 9A and 9B has a structure in which the side portion of the connection wiring is not exposed from the insulating layer and the pixel defining film and the tip portion of the connection wiring is not defined. The display panel (DP, DP-H) of the embodiment of the present invention used in the UHAST evaluation of FIGS. 10A and 10B has a structure corresponding to FIG. 5.

[0263] The UHAST evaluations in FIGS. 9A and 10B were conducted under temperature conditions of 85°C and humidity conditions of 85%. FIGS. 9A and 10A are images showing the screens of the display panels (DP', DP) before conducting the UHAST evaluation, and FIGS. 9B and 10B are images showing the screens of the display panels (DP'-H, DP-H) after being exposed to temperature conditions of 85°C and humidity conditions of 85% for 240 hours.

[0264] First, referring to FIGS. 9A and 9B, in the case of the comparative example of the present invention, when exposed to high temperature and high humidity conditions, it can be confirmed that the brightness decreases and the screen becomes stained. That is, in the case of the comparative example of the present invention, when exposed to high temperature and high humidity conditions, it can be confirmed that the brightness provided through the light-emitting element decreases as the contact reliability decreases.

[0265] On the other hand, referring to FIGS. 10A and 10B, it can be confirmed that in one embodiment of the present invention, even when exposed to high temperature and high humidity conditions, the brightness is maintained at a similar level and no staining occurs on the screen. That is, in one embodiment of the present invention, even when exposed to high temperature and high humidity conditions, it can be confirmed that contact reliability is maintained, thereby preventing or reducing a decrease in the brightness provided through the light-emitting element.

[0266] Fig. 11 is a cross-sectional view of a display panel (DP-1) according to an embodiment of the present invention. Fig. 12 is a cross-sectional view showing an enlarged portion of a portion of a display panel (DP-1) according to an embodiment of the present invention. Fig. 12 shows an enlarged cross-sectional view of the CC' region of Fig. 11. The same / similar reference numerals are used for configurations identical / similar to those described in Figs. 5 to 7, and duplicate descriptions are omitted.

[0267] Referring to FIGS. 11 and 12, the display panel (DP-1) of one embodiment may further include a capping pattern (CPP) compared to the display panel (DP) illustrated in FIG. 5. The capping pattern (CPP) may be disposed on the sixth insulating layer (60). In one aspect, the capping pattern (CPP) may also be disposed on a portion of the connection wiring (CN) exposed by the second through hole (OP-60) of the sixth insulating layer (60). The capping pattern (CPP) may be disposed to overlap the connection wiring (CN), and specifically, may be disposed to overlap the light emitting connection portion (CE) and / or the tip portion (TIP).

[0268] In one aspect, as shown in FIGS. 11 and 12, when viewed in cross section, the capping pattern (CPP) may have a shape that is partially disconnected with respect to the tip portion (TIP) in an area where the light emitting connection portion (CE) is defined. However, when viewed in plan, the capping pattern (CPP) may have a shape that is entirely connected within an area defined as a closed line by the separator (SPR) (see FIG. 4). In one aspect, one end (CPN1) of the partially disconnected capping pattern (CPP) may contact a side surface (L2_W) of the second layer (L2) of the connection wiring (CN), and the other end (CPN2) of the capping pattern (CPP) may be arranged on an upper portion of the third layer (L3) of the connection wiring (CN) to cover the tip portion (TIP).

[0269] The capping pattern (CPP) may include a conductive material. Accordingly, the connection electrode (CNE) and the second electrode (EL2) may be electrically connected to the connection wiring (CN) through the capping pattern (CPP). That is, the capping pattern (CPP) may contact the side surface (L2_W) of the second layer (L2) of the connection wiring (CN), and then the connection electrode (CNE) may contact the capping pattern (CPP), and the second electrode (EL2) may contact the connection electrode (CNE), so that all may be electrically connected. The capping pattern (CPP) is arranged relatively outside the second layer (L2) of the connection wiring (CN), and the connection electrode (CNE) can be electrically connected to the second layer (L2) only by being connected to the capping pattern (CPP) instead of the side surface (L2_W) of the second layer (L2), so that connection between the connection wiring (CN) and the connection electrode (CNE) can be made more easily, and through this, connection between the second electrode (EL2) and the connection wiring (CN) can also be made more easily.

[0270] In one embodiment of the present invention, the capping pattern (CPP) may include a material having relatively low reactivity compared to the second layer (L2) of the connection wiring (CN). For example, the capping pattern (CPP) may include copper (Cu), silver (Ag), a transparent conductive oxide, etc. Since the side surface (L2_W) of the second layer (L2) of the connection wiring (CN) is protected by the capping pattern (CPP) having relatively low reactivity, oxidation of the material included in the second layer (L2) can be prevented. In one aspect, it is also possible to prevent a phenomenon in which a silver (Ag) component included in the first electrode (EL1) layer is reduced during an etching process for patterning the first electrode (EL1) and remains as a particle that causes a defect.

[0271] In one embodiment, the capping pattern (CPP) may be formed through the same process as the first electrode (EL1) and may include the same material as the first electrode (EL1). However, this is merely an example, and the capping pattern (CPP) may be formed through a different process than the first electrode (EL1) and may include a different material, and is not limited to any one embodiment.

[0272] According to the above, the light emitting element and the pixel driver can be stably contacted, thereby improving contact reliability.

[0273] In an electronic device of one embodiment, a connecting electrode electrically connected to a pixel driver and a cathode of a light-emitting element may be connected over a relatively wide area by making contact in an area adjacent to a separator provided for pixel separation, thereby improving contact reliability. The connecting electrode and the pixel driver may be electrically connected via a connecting wire.

[0274] In one embodiment of the electronic device, the connecting electrode may contact not only the top surface of the connecting wire but also the side surface thereof, thereby further improving the contact reliability between the connecting electrode and the connecting wire. In one aspect, since a tip portion is defined in the connecting wire, the cathode may contact one end of the connecting electrode that is in contact with the side surface of the connecting wire. Accordingly, the cathode may contact the connecting electrode not only in the area adjacent to the separator but also in the area adjacent to the tip portion of the connecting wire, thereby further improving the contact reliability between the connecting electrode and the cathode.

[0275] Accordingly, relatively high luminance can be maintained even with a lower driving voltage, which may require a low margin for the driving voltage and reduce power consumption. That is, for example, embodiments of the present invention can support a display device (DD) (and an electronic device including the display device (DD)) with a low margin for the driving voltage, thereby helping to reduce power consumption. In one aspect, relatively high contact reliability can be maintained even in high temperature and high humidity environments.

[0276] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0277] Electronic devices include a display panel for displaying images, and the display panel may include a light-emitting element and a pixel driver for driving the light-emitting element. The invention relates to an electronic device, etc., and to an electrical connection structure between a light-emitting element and a pixel driver for improving the reliability of the display panel and the electronic device, and is industrially applicable.

Claims

1. A driving element layer including a pixel driving unit; A light emitting element disposed on the driving element layer, the light emitting element including a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer; A pixel defining film disposed on the driving element layer and having an opening that exposes at least a portion of the first electrode; A connecting electrode disposed on the pixel defining film and electrically connected to the pixel driver and the second electrode; A connection wiring positioned between the pixel driver and the pixel defining film and electrically connected to the pixel driver and the connection electrode; and including a separator disposed on the pixel defining film, An electronic device wherein the second electrode is in contact with the connecting electrode in each of the first contact area adjacent to the separator and the second contact area adjacent to the side of the connecting wire.

2. In paragraph 1, An electronic device in which, in the first contact area, the lower surface of the second electrode contacts the upper surface of the connecting electrode.

3. In paragraph 1, An electronic device wherein a tip portion is defined at least in a portion of an edge of the above connecting wiring, and the second contact area is adjacent to the tip portion.

4. In paragraph 3, The above connecting wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, An electronic device in which each side of the first layer and the third layer protrudes more than the side of the second layer.

5. In paragraph 4, One end of the above connecting electrode is connected to the side surface of the second layer, An electronic device in which one end of the second electrode is in contact with one end of the connecting electrode connected to the side surface of the second layer.

6. In paragraph 5, An electronic device wherein each of the other end of the connecting electrode and the other end of the second electrode is disposed on the upper surface of the first layer.

7. In paragraph 6, An electronic device in which the one end of the above connecting electrode contacts the side surface of the second layer.

8. In paragraph 6, Further comprising a capping pattern disposed between the above connecting wire and the above connecting electrode, One end of the capping pattern is in contact with the side surface of the second layer, and the other end of the capping pattern is disposed on the upper surface of the first layer, An electronic device in which the one end of the second electrode is in contact with the one end of the capping pattern that is in contact with the side surface of the second layer.

9. In paragraph 3, An electronic device in which the first through hole defined in the pixel definition film exposes the tip portion defined in at least a portion of the edge of the connecting wiring.

10. In paragraph 9, The driving element layer is disposed below the pixel defining film and further includes an intermediate insulating layer covering a portion of the connecting wiring, An electronic device in which a second through hole defined in the intermediate insulating layer exposes the tip portion defined in at least a portion of the edge of the connecting wire.

11. In paragraph 1, The driving element layer further includes a lower insulating layer disposed between the pixel driving unit and the connecting wiring, An electronic device in which the above-mentioned connecting wiring is connected to the pixel driver through a contact hole penetrating the lower insulating layer.

12. In paragraph 1, The above connecting electrode has a ring shape and surrounds the opening, An electronic device wherein the first contact area has a ring shape and surrounds at least a portion of the opening.

13. In paragraph 1, An electronic device wherein the connecting electrode comprises a first edge and a second edge surrounding the first edge, the second edge overlapping the separator.

14. In paragraph 1, An electronic device wherein a portion of the above connecting electrode is covered by the above separator.

15. In paragraph 1, The above light-emitting element includes a plurality of light-emitting elements, The pixel driver includes a plurality of pixel drivers, The above connecting electrode includes a plurality of connecting electrodes, The above plurality of connecting electrodes electrically connect the plurality of light-emitting elements and the plurality of pixel drivers, respectively, An electronic device wherein the gap between adjacent connecting electrodes among the plurality of connecting electrodes overlaps the separator.

16. In paragraph 1, The above intermediate layer further includes a functional layer, An electronic device in which the functional layer includes a first intermediate functional layer disposed on the first electrode and a second intermediate functional layer disposed on the light-emitting layer, and the light-emitting layer is disposed between the first intermediate functional layer and the second intermediate functional layer.

17. In paragraph 16, A first dummy layer disposed on the separator and containing the same material as the functional layer; and An electronic device further comprising a second dummy layer disposed on the first dummy layer and containing the same material as the second electrode.

18. A driving element layer including a pixel driving unit; A light emitting element disposed on the driving element layer, the light emitting element including a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer; A pixel defining film disposed on the driving element layer and having an opening that exposes at least a portion of the first electrode; A connecting electrode disposed on the pixel defining film and electrically connected to the pixel driver and the second electrode; A connection wiring positioned between the pixel driver and the pixel defining film and electrically connected to the pixel driver and the connection electrode; and including a separator disposed on the pixel defining film, The edge of the above connecting electrode overlaps with the above separator, At least a portion of the edge of the above connecting wire has a tip portion defined, An electronic device in which the above connecting electrode is connected to at least a portion of the edge of the above connecting wire in which the tip portion is defined.

19. In paragraph 18, An electronic device in which the second electrode is in contact with the connecting electrode in each of the first contact area adjacent to the separator and the second contact area adjacent to the tip portion of the connecting wire.

20. In paragraph 18, The above connecting wiring includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, Each side of the first layer and the third layer protrudes more than the side of the second layer, One end of the above connecting electrode is connected to the side surface of the second layer, An electronic device in which one end of the second electrode is in contact with one end of the connecting electrode connected to the side surface of the second layer.

Images