Detector array substrate and preparation method therefor, and detector

Abstract

A detector array substrate, comprising: a photoelectric conversion structure (PD). The photoelectric conversion structure (PD) comprises a first side wall (SW1) and a second side wall (SW2) that are adjacent to each other; the first side wall (SW1) is located on the side of the second side wall (SW2) away from a base substrate (BS); the first side wall (SW1) surrounds a first portion of the photoelectric conversion structure (PD); the second side wall (SW2) surrounds a second portion of the photoelectric conversion structure (PD); the included angle between the second side wall (SW2) and a second direction (D2) is an acute angle; the orthographic projection of the first portion of the photoelectric conversion structure (PD) on the base substrate (BS) covers the orthographic projection of the second portion of the photoelectric conversion structure (PD) on the base substrate (BS); the orthographic projections of the first portion and the second portion of the photoelectric conversion structure (PD) on a plane in a first direction (D1) are located within the orthographic projection of a first insulating layer (IL1) on the plane in the first direction (D1); the first direction (D 1) is perpendicular to the base substrate (BS), and the second direction (D2) is parallel to the base substrate (BS).

Description

Detector array substrate and its fabrication method, detector Technical Field

[0001] This disclosure relates to the field of detector technology, and in particular to a detector array substrate, a detector, and a method for fabricating the detector array substrate. Background Technology

[0002] Indirect X-ray detectors offer advantages such as low-dose rapid prototyping, high conversion efficiency, and high noise ratio, making them widely used in high-end medical products. However, they also place extremely high demands on product characteristics. Flat panel X-ray detectors (FPXDs) exhibit image retention, known as lag, in the dark images produced after illumination. The lag characteristics of existing indirect X-ray detectors (single-frame lag = 3.4%, multi-frame lag = 0.4%) cannot meet the requirements of high-specification products (single-frame lag < 2.5%, multi-frame lag < 0.3%).

[0003] Summary of the Invention

[0004] On one hand, this disclosure provides a detector array substrate, comprising: a substrate having a plurality of pixel regions arranged in an array thereon, wherein each pixel region includes: a thin-film transistor including a source and a drain; a first insulating layer located on the side of the thin-film transistor away from the substrate; a photoelectric conversion structure located on the side of the thin-film transistor away from the substrate, the photoelectric conversion structure including a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being located on the side of the first semiconductor layer away from the substrate; and a first electrode layer located on the side of the photoelectric conversion structure close to the substrate, the first electrode layer being electrically connected to the photoelectric conversion structure, and the... The first electrode layer is electrically connected to the thin-film transistor; wherein the photoelectric conversion structure includes an adjacent first sidewall and a second sidewall, the first sidewall being located on the side of the second sidewall away from the substrate, the first sidewall surrounding a first portion of the photoelectric conversion structure, the second sidewall surrounding a second portion of the photoelectric conversion structure, the angle between the second sidewall and a second direction being an acute angle, the orthographic projection of the first portion and the second portion of the photoelectric conversion structure onto the plane containing the first direction being located within the orthographic projection of the first insulating layer onto the plane containing the first direction, the first direction being perpendicular to the substrate, and the second direction being parallel to the substrate.

[0005] In some embodiments, the orthographic projection of the first portion of the photoelectric conversion structure onto the substrate covers the orthographic projection of the second portion of the photoelectric conversion structure onto the substrate.

[0006] In some embodiments, in the first direction, the thickness of the first semiconductor layer is H1, and the thickness of the second portion of the photoelectric conversion structure is T, wherein T > H1.

[0007] In some embodiments, the photoelectric conversion structure further includes an intrinsic semiconductor layer located between the first semiconductor layer and the second semiconductor layer, wherein the thickness of the intrinsic semiconductor layer in the first direction is H2, and T≤0.5H2+H1.

[0008] In some embodiments, the angle between the second sidewall and the second direction is in the range of 25°-45°.

[0009] In some embodiments, the photoelectric conversion structure further includes a passivation layer covering the first sidewall and the second sidewall.

[0010] In some embodiments, each pixel region further includes a second electrode layer located on the side of the second semiconductor layer away from the substrate, wherein the second electrode layer is in electrical contact with the second semiconductor layer, and the orthographic projection of the second electrode layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate.

[0011] In some embodiments, the orthographic projection of the second electrode layer on the substrate coincides with the orthographic projection of the second semiconductor layer on the substrate.

[0012] In some embodiments, each pixel region further includes a second insulating layer located on the side of the thin-film transistor and the first electrode layer away from the substrate, and on the side of the first insulating layer close to the substrate, wherein the second insulating layer covers the first sidewall and the second sidewall of the photoelectric conversion structure.

[0013] In some embodiments, the thickness of the second insulating layer covering the first sidewall of the photoelectric conversion structure is greater than the thickness of the second insulating layer covering the second sidewall of the photoelectric conversion structure.

[0014] In some embodiments, the first electrode layer includes a first metal layer and a second metal layer, the second metal layer being located on the side of the first metal layer away from the substrate, and the second metal layer being in direct contact with the first semiconductor layer.

[0015] In some embodiments, in the first direction, the total thickness of the photoelectric conversion structure is H; in the second direction, the distance from the intersection of the second metal layer and the second sidewall to the edge of the second metal layer is greater than 1.1H.

[0016] In some embodiments, the material of the second metal layer is Mo.

[0017] In some embodiments, the first metal layer includes a first metal sublayer and a second metal sublayer, the first metal sublayer being located on the side of the second metal sublayer away from the substrate, and the material of the first metal sublayer being different from the material of the second metal layer.

[0018] In some embodiments, each pixel region further includes: a third insulating layer located on the side of the first insulating layer away from the substrate; a third metal layer located on the side of the third insulating layer away from the substrate, the third metal layer including a bias line portion and a light-shielding portion; and a first via penetrating the first insulating layer, the second insulating layer, and the third insulating layer, wherein the bias line portion is electrically connected to the second electrode layer through the first via, and the orthogonal projection of the light-shielding portion on the substrate covers the orthogonal projection of the thin-film transistor on the substrate.

[0019] In some embodiments, the detector array substrate further includes a fourth insulating layer located on the side of the third metal layer away from the substrate.

[0020] In some embodiments, the detector array substrate further includes a conductive pattern located on the side of the fourth insulating layer away from the substrate. The conductive pattern includes a transparent conductive portion and a cutout portion. The orthogonal projection of the transparent conductive portion on the substrate covers the orthogonal projection of the first sidewall and the second sidewall of the photoelectric conversion structure on the substrate.

[0021] In some embodiments, the thin-film transistor includes: a gate located on a substrate; a gate insulating layer located on the side of the gate away from the substrate, wherein the orthographic projection of the gate insulating layer on the substrate overlaps the orthographic projection of the gate on the substrate; and an active layer located on the side of the gate insulating layer away from the substrate, the active layer being electrically connected to the source and the drain, respectively, wherein the orthographic projection of the active layer on the substrate partially overlaps with the orthographic projections of the source and the drain on the substrate. The detector array substrate further includes: a fifth insulating layer located on the side of the thin-film transistor away from the substrate, the fifth insulating layer including a second via exposing the source, and the first electrode layer being electrically connected to the source through the second via.

[0022] In some embodiments, the first electrode layer covers a portion of the fifth insulating layer, and in a first direction, the thickness of the portion of the fifth insulating layer covered by the first electrode layer is b, and the thickness of the portion of the fifth insulating layer not covered by the first electrode layer is less than 0.8b.

[0023] In some embodiments, the detector array substrate further includes gate lines arranged along the row direction of the pixel regions arranged in the array, and data lines arranged along the column direction of the pixel regions arranged in the array. The gate lines are disposed on the same layer as the gate and electrically connected, and the data lines are disposed on the same layer as the source and electrically connected. The detector array substrate further includes a bonding region located around the pixel regions. In the bonding region, gate line bonding portions and data line bonding portions are disposed on the same layer as the first electrode layer. The gate line bonding portions are electrically connected to the gate lines through a third via penetrating the fifth insulating layer and the gate insulating layer. The data line bonding portions are electrically connected to the data lines through a fourth via penetrating the fifth insulating layer. In a first direction, the thickness of the portion of the fifth insulating layer covered by the gate line bonding portion or the data line bonding portion is b, and the thickness of the portion of the fifth insulating layer not covered by the gate line bonding portion or the data line bonding portion is less than 0.8b.

[0024] In some embodiments, the thin-film transistor includes: a gate located on a substrate; a gate insulating layer located on the side of the gate away from the substrate, wherein the orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the gate on the substrate; and an active layer located on the side of the gate insulating layer away from the substrate, wherein the active layer is electrically connected to the source and the drain, respectively, and the orthographic projection of the active layer on the substrate covers the orthographic projection of the source, the drain, and the first electrode layer on the substrate, and wherein the source and the first electrode layer are integral.

[0025] According to another aspect of this disclosure, this disclosure also provides a detector, including a detector array substrate according to any of the foregoing embodiments.

[0026] According to another aspect of this disclosure, a method for fabricating a detector array substrate is also provided, comprising: providing a substrate having a plurality of pixel regions arranged in an array thereon; forming a corresponding thin-film transistor in each pixel region, wherein the thin-film transistor includes a source and a drain; forming a first electrode layer electrically connected to the thin-film transistor; forming a photoelectric conversion structure on a side of the first electrode layer away from the substrate, the photoelectric conversion structure being electrically connected to the first electrode layer, the photoelectric conversion structure including a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being located on the side of the first semiconductor layer away from the substrate; and etching the photoelectric conversion structure such that the photoelectric conversion structure includes adjacent... A first sidewall and a second sidewall, wherein the first sidewall is located on the side of the second sidewall away from the substrate, the first sidewall surrounds a first portion of the photoelectric conversion structure, and the second sidewall surrounds a second portion of the photoelectric conversion structure, the angle between the second sidewall and the second direction is an acute angle, the orthographic projection of the first portion of the photoelectric conversion structure on the substrate covers the orthographic projection of the second portion of the photoelectric conversion structure on the substrate, the orthographic projections of the first portion and the second portion of the photoelectric conversion structure on the plane containing the first direction are located within the orthographic projection of the first insulating layer on the plane containing the first direction, the first direction being perpendicular to the substrate, and the second direction being parallel to the substrate.

[0027] In some embodiments, etching the photoelectric conversion structure includes: performing a first etching step using SF6, Cl2, and He; and performing a second etching step using SF6, Cl2, He, and O2. Attached Figure Description

[0028] To more clearly describe the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a top view of a detector array substrate according to an embodiment of the present disclosure;

[0030] Figure 2 is a schematic cross-sectional view of the detector array substrate taken along line MN in Figure 1;

[0031] Figure 3 is a detailed view of the PD structure in Figure 2;

[0032] Figure 4 shows another detailed view of the PD structure in Figure 2;

[0033] Figure 5 is a partial top view of the pixel region of the detector array substrate according to an embodiment of the present disclosure;

[0034] Figure 6 is a partial cross-sectional schematic diagram of the pixel region of the detector array substrate according to an embodiment of the present disclosure;

[0035] Figure 7 is a detailed schematic diagram of region A in Figure 2 in some embodiments;

[0036] Figure 8 is a detailed schematic diagram of region A in Figure 2 in some other embodiments;

[0037] Figure 9 is a detailed schematic diagram of region A in Figure 2 in some other embodiments;

[0038] Figure 10 is a partial top view of the pixel region of the detector array substrate according to an embodiment of the present disclosure;

[0039] Figure 11 is a top view of a detector array substrate according to an embodiment of the present disclosure;

[0040] Figure 12 is a schematic cross-sectional view of the detector array substrate taken along line GG' in Figure 11;

[0041] Figure 13 is a schematic cross-sectional view of the detector array substrate taken along line DD' in Figure 11;

[0042] Figure 14 is another cross-sectional schematic diagram of the detector array substrate according to an embodiment of the present disclosure;

[0043] Figure 15 is another cross-sectional schematic diagram of the detector array substrate according to an embodiment of the present disclosure;

[0044] Figure 16 is a comparison chart of lag tests between detectors in related technologies and detectors according to embodiments of this disclosure.

[0045] It should be understood that the accompanying drawings are merely schematic illustrations of exemplary embodiments of the present disclosure and are not intended to limit the scope of the disclosure, and need not be drawn strictly to scale. Furthermore, in the drawings, the same or similar reference numerals are used to refer to the same or similar parts. Detailed Implementation

[0046] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] It is understood that the various figures in the embodiments of this disclosure are only used to schematically show the connection relationship between the various components. The dimensions of the various components in the figures are not drawn to scale, and their relative positional relationship may not completely correspond to the actual position.

[0048] The researchers in this publication discovered that the primary cause of Lag in X-ray flat panel detectors is the capture and release of photogenerated carriers by defects in the film layer of the photoelectric conversion structure. Specifically, after illumination, defects capture photogenerated carriers, which are then released sequentially during subsequent image acquisition. Taking a PIN structure photoelectric conversion structure as an example, film defects mainly include internal defects and sidewall defects. Internal defects are primarily related to PIN structure deposition, and the main influencing factors include: interface defects between the P-type semiconductor layer and the intrinsic semiconductor layer; interface defects between the N-type semiconductor layer and the intrinsic semiconductor layer; internal defects in the intrinsic semiconductor layer; and the doping concentration of the P-type and N-type semiconductor layers. Sidewall defects are mainly related to the etching of the PIN structure, which generates numerous defects on the sidewalls.

[0049] This disclosure provides a detector array substrate in which the etching of the PIN structure employs new etching conditions to form a specific sidewall morphology, reducing interface defects between the N-type semiconductor layer and the intrinsic semiconductor layer, and forming a passivation layer on the sidewall surface to reduce sidewall defects of the PIN structure. At the same time, it increases the coverage ratio of the upper electrode (i.e., the incident light electrode), reduces the influence of internal defects in the intrinsic semiconductor layer in areas without upper electrode coverage, and significantly improves single-frame and multi-frame Lag characteristics.

[0050] Figure 1 is a top view of a detector array substrate according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of the detector array substrate taken along line MN in Figure 1. Figure 3 is a detailed view of the PD structure in Figure 2.

[0051] As shown in Figures 1-3, this disclosure provides a detector array substrate, including a substrate BS, on which multiple pixel regions PX are arranged in an array. The substrate can be, for example, a glass substrate, in which case a rigid FPXD can be fabricated. Alternatively, the substrate can be a glass substrate coated with a flexible material, such as PI, in which case the glass substrate can be removed in a suitable step to fabricate a flexible FPXD. Each pixel region PX includes: a thin-film transistor (TFT) including a source electrode (S) and a drain electrode (D); a first insulating layer IL1 located on the side of the TFT away from the substrate BS; a photoelectric conversion structure PD located on the side of the TFT away from the substrate BS, the photoelectric conversion structure PD including a first semiconductor layer N and a second semiconductor layer P, the second semiconductor layer P being located on the side of the first semiconductor layer N away from the substrate BS; and a first electrode layer E1 located on the side of the photoelectric conversion structure PD close to the substrate BS, the first electrode layer E1 being electrically connected to the photoelectric conversion structure PD and the thin-film transistor TFT. As shown in Figure 3, the photoelectric conversion structure PD includes an adjacent first sidewall SW1 and a second sidewall SW2. The first sidewall SW1 is located on the side of the second sidewall SW2 away from the substrate BS. The first sidewall SW1 surrounds the first part PD1 of the photoelectric conversion structure, and the second sidewall SW2 surrounds the second part PD2 of the photoelectric conversion structure. The angle θ between the second sidewall SW2 and the second direction D2 is an acute angle. The orthographic projection of the first part PD1 of the photoelectric conversion structure onto the substrate BS1 covers the orthographic projection of the second part PD2 of the photoelectric conversion structure onto the substrate BS. The orthographic projections of the first part PD1 and the second part PD2 of the photoelectric conversion structure onto the plane containing the first direction D1 are located within the orthographic projection of the first insulating layer IL1 onto the plane containing the first direction D1. The first direction D1 is perpendicular to the substrate BS, and the second direction D2 is parallel to the substrate BS.

[0052] It should be noted that the photoelectric conversion structure shown in Figures 2 and 3 is an example of a PIN structure, where the first semiconductor layer N can be an N-type semiconductor layer, the second semiconductor layer P can be a P-type semiconductor layer, and an intrinsic semiconductor layer I can be disposed between the first semiconductor layer N and the second semiconductor layer P. However, this does not represent a limitation compared to this disclosure. The inventive concept of this disclosure can also be applied to photoelectric conversion structures with only two semiconductor layers, such as PN junction photodiodes. Furthermore, in the figures of this application, such as Figures 2 and 3, the first sidewall SW1 of the photoelectric conversion structure PD is shown to be approximately parallel to the first direction D1. Those skilled in the art will understand that in actual products, due to the influence of the manufacturing process, there will be a certain angle between the first sidewall SW1 and the first direction. This angle can be, for example, in the range of 0-30°, and this disclosure does not limit it. The photoelectric conversion structure with a PIN structure can be made of Si material, for example. The total thickness of the P-type semiconductor layer, the intrinsic semiconductor layer, and the N-type semiconductor layer can be from 900 nm to 1500 nm, for example, 1000 nm. The P-type semiconductor layer can be, for example, about 50 nm, and the intrinsic semiconductor layer can be, for example, about 900 nm.

[0053] As shown in Figure 3, in the first direction D1, the thickness of the first semiconductor layer N is H1, and the thickness of the second part PD2 of the photoelectric conversion structure is T, where T > H1. In other words, the second sidewall of the photoelectric conversion structure obliquely cuts away a portion of the interface between the first semiconductor layer N and the intrinsic semiconductor layer I.

[0054] The photoelectric conversion structure provided in this embodiment reduces interface defects between the N-type semiconductor layer and the intrinsic semiconductor layer by etching away a portion of the interface. This effectively reduces the capture and release of photogenerated carriers by interface defects, thereby reducing image residue on the dark-state image after illumination and effectively reducing the product's Lag.

[0055] As shown in Figure 3, the photoelectric conversion structure further includes an intrinsic semiconductor layer I located between the first semiconductor layer N and the second semiconductor layer P. The thickness of the intrinsic semiconductor layer I in the first direction D1 is H2, where T ≤ 0.5H2 + H1. In other words, the second sidewall is located in the lower middle part of the sidewall of the photoelectric conversion structure.

[0056] In Figure 3, the angle between the second sidewall SW2 and the second direction D2 is shown as θ. The researchers in this disclosure found that if the angle θ is too large, the interface between the N-type semiconductor layer and the intrinsic semiconductor layer cut off by the second sidewall will decrease; conversely, if the angle θ is too small, the area of ​​the second sidewall will be too large, leading to an increase in sidewall defects. When θ is in the range of 25°-45°, an optimal balance is achieved between the interface between the cut-off N-type semiconductor layer and the intrinsic semiconductor layer and the sidewall defects, resulting in optimal improvement of Lag.

[0057] The photoelectric conversion structure described in this embodiment is obtained by etching under oxygen-containing conditions (the specific etching conditions will be described in detail in the preparation process below). This oxygen-containing etching condition forms dangling bonds on the sidewalls of the photoelectric conversion structure. In other words, this oxygen-containing etching condition forms a passivation layer covering the first and second sidewalls on the sidewalls of the photoelectric conversion structure, which improves the sidewall defects of the photoelectric conversion structure, effectively reduces the capture and release of photogenerated carriers by the sidewall defects, and reduces the phenomenon of image residue on the dark-state image after illumination, that is, effectively reduces the Lag of the product.

[0058] It should be noted that the passivation layer covering the first and second sidewalls described above is extremely thin, only on the order of a few atoms or molecules thick, and is almost undetectable in the scanning electron microscope images of the device. Figure 4 schematically shows a schematic diagram of the PD structure, in which the passivation layer PVX covering the first and second sidewalls is indicated by bold black lines.

[0059] As shown in Figure 2, each pixel region also includes a second electrode layer E2. The second electrode layer E2 is located on the side of the second semiconductor layer P away from the substrate BS. The second electrode layer E2 is in electrical contact with the second semiconductor layer P, and the orthographic projection of the second electrode layer P onto the substrate BS lies within the orthographic projection of the second semiconductor layer P onto the substrate BS. Using the etching conditions provided in this embodiment, the proportion of the second electrode covering the second semiconductor layer P can be increased, the uncovered working area of ​​the photoelectric conversion structure can be reduced, and defects can be significantly reduced. Figure 5 is a partial top view of the pixel structure of the detector array substrate according to an embodiment of this disclosure. In the embodiment shown in Figure 5, the orthographic projection of the second electrode E2 onto the substrate coincides with the orthographic projection PDE1 of the second semiconductor layer onto the substrate. That is, the second electrode E2 completely covers the P-type semiconductor layer, the PIN structure is fully functional, there is no defect impact from the unused area, and the lag reduction is significantly improved.

[0060] Since the second electrode E2 is located on the light-incident side of the photoelectric conversion structure PD, the material of the second electrode E2 can be a transparent conductive oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide) or IGZO (indium gallium zinc oxide).

[0061] In some embodiments, the first insulating layer may be an organic insulating layer, such as a resin, used to fill the FPXD, making the product film layer more uniform and facilitating subsequent film layer preparation. In this case, as shown in FIG2, each pixel region may also include a second insulating layer IL2. The second insulating layer IL2 is located on the side of the thin film transistor TFT and the first electrode layer E1 away from the substrate BS, and on the side of the first insulating layer IL1 close to the substrate BS, that is, in the direction perpendicular to the substrate BS, the second insulating layer IL2 is located between the first insulating layer IL1 and the substrate BS. The second insulating layer IL2 covers the first sidewall SW1 and the second sidewall SW2 of the photoelectric conversion structure. Here, "covering" means that the second insulating layer IL2 is deposited on the first sidewall SW1 and the second sidewall SW2, directly covering the first sidewall SW1 and the second sidewall SW2. As shown in FIG2, the second insulating layer IL2 also covers the surface of the second electrode layer E2 facing away from the substrate BS. After the photoelectric conversion structure (PD) is etched and formed, a second insulating layer (IL2) can be prepared before depositing the resin material for the first insulating layer (IL1). The material of the second insulating layer (IL2) can be, for example, SiNx. The second insulating layer (IL2) also passivates the first sidewalls (SW1) and second sidewalls (SW2) of the photoelectric conversion structure. Besides the passivation layer formed under oxygen-containing etching conditions that exists in the form of dangling bonds, the second insulating layer can also reduce sidewall defects on the first sidewalls (SW1) and second sidewalls (SW2). The second insulating layer (IL2) can protect the photoelectric conversion structure (PD) and improve the adhesion of the resin material. The deposition of the second insulating layer can be achieved using PECVD (plasma-enhanced chemical vapor deposition) technology. Under the action of plasma, the precursor substances in the reaction gas are activated and decomposed, forming active ions and free radicals, which then undergo chemical reactions on the surface to form the desired compound film. Therefore, the second insulating layer can completely cover and protect the sidewall morphology of the photoelectric conversion structure. Figure 6 schematically illustrates a photoelectric conversion structure covered by a second insulating layer, wherein the thickness T1 of the first sidewall of the photoelectric conversion structure covered by the second insulating layer is greater than the thickness T2 of the second sidewall of the photoelectric conversion structure covered by the second insulating layer. Here, "the thickness of the first sidewall of the photoelectric conversion structure covered by the second insulating layer" refers to the thickness of the second insulating layer in the direction perpendicular to the first sidewall, and "the thickness of the second sidewall of the photoelectric conversion structure covered by the second insulating layer" refers to the thickness of the second insulating layer in the direction perpendicular to the second sidewall.In some embodiments, the average deposition thickness of the second insulating layer can be 2000 Å, wherein the thickness of the second insulating layer on the surface of the photoelectric conversion structure facing away from the substrate and covering the first sidewall of the photoelectric conversion structure is approximately 2000 Å, and the thickness of the second insulating layer covering the second sidewall of the photoelectric conversion structure is approximately 1000 Å. In this embodiment, the thickness of the second insulating layer covering the second sidewall of the photoelectric conversion structure is approximately half the thickness of the second insulating layer covering the first sidewall of the photoelectric conversion structure, because the tilted structure of the second sidewall of the photoelectric conversion structure reduces the deposition efficiency of the second insulating layer on the second sidewall.

[0062] Figure 7 is a detailed schematic diagram of region A in Figure 2 in some embodiments. As shown in Figure 7, in some embodiments, the first electrode layer E1 may include a single metal layer, such as Ti. Figure 8 is a detailed schematic diagram of region A in Figure 2 in other embodiments. As shown in Figure 8, in some embodiments, the first electrode layer E1 includes a first metal layer E11 and a second metal layer E12. The second metal layer E12 is located on the side of the first metal layer E11 away from the substrate BS, and the second metal layer E12 is in direct contact with the first semiconductor layer. The first metal layer E11 includes a first metal sublayer E111 and a second metal sublayer E112. The first metal sublayer E111 is located on the side of the second metal sublayer E112 away from the substrate BS, and the material of the first metal sublayer E111 is different from the material of the second metal layer E12. For example, the material of the second metal sublayer may be Ti, the material of the first metal sublayer E111 may be Al, and the material of the second metal layer E12 may be Ti. When the material of the second metal layer is Ti or other materials that are not etchable, the entire surface of the first electrode is not affected by etching, and the surface is relatively smooth. In some embodiments, as shown in Figures 7 and 8, the total thickness of the photoelectric conversion structure is H in the first direction, and the distance from the intersection of the first electrode and the second sidewall to the edge of the second electrode in the second direction can be set, for example, to 2H.

[0063] Figure 9 is a detailed schematic diagram of region A in Figure 2 in some embodiments. As shown in Figure 9, in some embodiments, the material of the second metal layer E12 is etched during the etching process of the photoelectric conversion structure. For example, if the material of the second metal layer E12 is Mo, the second metal layer Mo will be etched away during the etching process, resulting in a rough morphology on the surface of the first metal layer. This reduces the reflection of incident light and minimizes the impact on the sidewalls of the photoelectric conversion structure. Under suitable etching conditions, the total thickness of the photoelectric conversion structure is H in the first direction; in the second direction, the distance from the intersection of the second metal layer and the second sidewall to the edge of the second metal layer is greater than 1.1H, for example, it can be 1.2H. The second metal layer at other locations is basically etched away, with only a small amount remaining, forming the rough morphology on the surface of the first metal layer. The reason why the portion of the second metal layer close to the second sidewall can retain a width of about 1.2H is because the photoresist protects this portion of the second metal layer close to the photoelectric conversion structure during the etching process. In some embodiments, as shown in FIG9, the first metal layer E11 includes a first metal sublayer E111 and a second metal sublayer E112. The first metal sublayer E111 is located on the side of the second metal sublayer E112 away from the substrate BS, and the material of the first metal sublayer E111 is different from the material of the second metal layer E112. For example, the material of the first metal sublayer E111 can be Mo, the material of the second metal sublayer E112 can be Al, and the material of the second metal layer E12 can be Mo. During the etching process of the photoelectric conversion structure, most of the Mo in the second metal layer will be etched away, forming a rough morphology. However, since the Al material of the first metal sublayer E111 will not be etched, the second metal sublayer E112 covered by the first metal sublayer E111 will also not be etched. In some embodiments, the thickness of the Mo in the second metal sublayer E112 can be, for example, The thickness of Al in the first metallic sublayer E111 can be, for example, The thickness of Mo in the second metal layer E12 can be, for example,

[0064] As shown in Figure 2, each pixel region may further include: a third insulating layer IL3, located on the side of the first insulating layer IL1 away from the substrate BS; a third metal layer, located on the side of the third insulating layer IL3 away from the substrate BS, the third metal layer including a bias line portion BL and a light-shielding portion SL; and a first via VH1 penetrating the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3, wherein the bias line portion BL is electrically connected to the second electrode layer E2 through the first via VH1, and the orthogonal projection of the light-shielding portion SL on the substrate BS covers the orthogonal projection of the thin-film transistor on the substrate. The bias line portion BL of the third metal layer is connected to a control chip, providing a bias voltage to the photoelectric conversion structure PD, which sets the photoelectric conversion structure PD in a biased state; the light-shielding portion SL of the third metal layer blocks light incident on the thin-film transistor, preventing light from affecting the characteristics of the thin-film transistor.

[0065] As shown in Figure 2, each pixel region may further include a fourth insulating layer IL4, located on the side of the third metal layer away from the substrate BS. The fourth insulating layer IL4 can protect the detector array substrate and reduce scratches and other problems, and is typically made of SiNx material.

[0066] As shown in Figure 2, each pixel region may further include a conductive pattern CP located on the side of the fourth insulating layer IL4 away from the substrate BS. Figure 10 is a partial top view of a pixel region of a detector array substrate according to an embodiment of the present disclosure. As shown in Figure 10, the conductive pattern CP includes a transparent conductive portion TCP and a cutout portion HLP. The orthographic projection of the transparent conductive portion TCP on the substrate BS covers the orthographic projections of the first sidewall SW1 and the second sidewall SW2 of the photoelectric conversion structure PD on the substrate BS. In Figure 10, PDE1 indicates the first edge of the projection of the sidewall of the photoelectric conversion structure PD on the substrate BS, and PDE2 indicates the second edge of the projection of the sidewall of the photoelectric conversion structure PD on the substrate BS.

[0067] If there is no protection above the sidewalls of the photoelectric conversion structure, when the product is subjected to uneven external potential disturbances or unevenly distributed charged ions, a new electric field is generated due to the mechanism of induced electrons. This electric field is superimposed on the original reverse bias electric field vector of the photoelectric conversion structure, causing inconsistencies in the electric field between pixels. Consequently, the amount of electron migration between different pixels differs within the same integration time, which manifests as uneven grayscale in the product image, i.e., mura in the image. By setting the conductive pattern as shown in Figures 2 and 10, the orthogonal projection of its transparent conductive part TCP on the substrate BS covers the orthogonal projection of the first sidewall SW1 and the second sidewall SW2 of the photoelectric conversion structure PD on the substrate BS, which can play a good electrostatic shielding role. It can also provide electrostatic protection for the back-end processes after the sensing substrate is finished (such as attaching OCA (optical clear adhesive) layer, suction cup adsorption and placement, etc.), which will ultimately significantly reduce the occurrence rate of electrostatic mura and image unevenness, and improve product yield. At the same time, this design will not affect the photoelectric response sensitivity of the sensing substrate. On the other hand, the conductive pattern CP can also promote the dissipation of locally generated static electricity. On the other hand, by giving the conductive pattern CP a hollow portion HLP, where the hollow portion HLP at least partially overlaps with the orthographic projection of the light-incident surface of the photoelectric conversion structure PD on the substrate BS, the transmittance of the conductive pattern CP to light (especially visible light) can be improved, thereby allowing more light to be sensed by the photoelectric conversion structure PD. The hollow design reduces the coverage area of ​​the conductive pattern CP on the sensing substrate, thus improving the adhesion between the detector array substrate and the resin layer or scintillator materials such as cesium iodide while ensuring the anti-static effect. The material of the transparent conductive portion can be a transparent conductive oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0068] The thin-film transistors disclosed herein can be of various forms, such as amorphous silicon thin-film transistors, oxide thin-film transistors, or LTPS thin-film transistors.

[0069] In some embodiments, as shown in FIG2, the thin-film transistor may include: a gate G located on a substrate; a gate insulating layer GI located on the side of the gate G away from the substrate BS, wherein the orthographic projection of the gate insulating layer GI on the substrate BS overlaps the orthographic projection of the gate G on the substrate BS; and an active layer ACT located on the side of the gate insulating layer GI away from the substrate BS, wherein the active layer ACT is electrically connected to the source S and the drain D, respectively, and the orthographic projection of the active layer ACT on the substrate BS partially overlaps with the orthographic projections of the source S and the drain D on the substrate BS. The detector array substrate further includes: a fifth insulating layer IL5 located on the side of the thin-film transistor away from the substrate BS, wherein the fifth insulating layer IL5 includes a second via VH2 exposing the source S, and the first electrode layer E1 is electrically connected to the source S through the second via VH2.

[0070] During the etching process of the photoelectric conversion structure, a certain amount of over-etching is required to ensure that there is no residue. Therefore, over-etching will etch the fifth insulating layer IL5, resulting in a loss of IL5, which is about one-quarter of the original thickness. In some embodiments, as shown in Figures 7-9, the first electrode layer E1 covers a portion of the fifth insulating layer IL5. In a first direction, the thickness of the portion of the fifth insulating layer IL5 covered by the first electrode layer E1 is b, and the thickness of the portion of the fifth insulating layer IL5 not covered by the first electrode layer E1 is less than 0.8b, for example, it can be 0.75b.

[0071] In addition to the fifth insulating layer being etched in the pixel area or the gap between pixel areas, the fifth insulating layer in the bonding area will also be etched.

[0072] As shown in Figure 1, the detector array substrate further includes gate lines GL arranged along the row direction of the pixel regions arranged in the array, and data lines DL arranged along the column direction of the pixel regions arranged in the array. The gate lines GL are disposed on the same layer as the gate G and electrically connected, and the data lines DL are disposed on the same layer as the drain D and electrically connected. The source of the thin-film transistor is electrically connected to the photoelectric conversion structure to receive the electrical signal output by the photoelectric conversion structure, and the electrical signal is output to the data lines through the drain.

[0073] Figure 11 is a top view of a detector array substrate according to an embodiment of the present disclosure. As shown in Figure 11, the detector array substrate further includes a bonding region BD located around the pixel region, in which a gate bonding portion GLBP and a data line bonding portion DLBP, disposed on the same layer as the first electrode layer E1, are arranged. Figure 12 is a cross-sectional view of the detector array substrate taken along line GG' in Figure 11. Figure 13 is a cross-sectional view of the detector array substrate taken along line DD' in Figure 11. In Figures 12 and 13, the gate bonding portion and the data line bonding portion are shown as a second metal sublayer E112, a first metal sublayer E111, and a second metal layer E12 of the first electrode layer, respectively. Most of the second metal layer E12 is etched away, with only a small amount remaining in the third via VH3 and the fourth via VH4. As shown in Figures 12 and 13, the gate line bonding portion is electrically connected to the gate line GL through a third via VH3 penetrating the fifth insulating layer IL5 and the gate insulating layer GI. The data line bonding portion is electrically connected to the data line DL through a fourth via VH4 penetrating the fifth insulating layer IL5. In the first direction, the thickness of the portion of the fifth insulating layer IL5 covered by the gate line bonding portion or the data line bonding portion is b, and the thickness of the portion of the fifth insulating layer IL5 not covered by the gate line bonding portion or the data line bonding portion is less than 0.8b, for example, it can be 0.75b. In the actual fabrication process, the ideal etching state of the photodetector structure can be determined by monitoring the thickness of the portion of the fifth insulating layer not covered by the gate line bonding portion or the data line bonding portion in the bonding region to drop to about 0.75b.

[0074] The cross-sectional structure shown in Figure 2 has been used to describe some embodiments of the detector array substrate provided in this disclosure. In other embodiments, the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 shown in Figure 2 may be the same insulating layer, as shown in the cross-sectional schematic diagram of the detector array substrate in Figure 14. As shown in Figure 14, the first insulating layer IL1 may be a thick SiNx layer, which can reduce the number of photolithography steps, simplify the fabrication process, effectively improve the yield coefficient, reduce costs, and enhance product competitiveness.

[0075] The thin-film transistor disclosed herein can also employ an ESL structure. Figure 15 is another cross-sectional schematic diagram of a detector array substrate according to an embodiment of this disclosure. As shown in Figure 15, the thin-film transistor includes: a gate G located on a substrate BS; a gate insulating layer GI located on the side of the gate G away from the substrate BS, wherein the orthographic projection of the gate insulating layer GI on the substrate BS covers the orthographic projection of the gate G on the substrate BS; and an active layer ACT located on the side of the gate insulating layer GI away from the substrate BS, wherein the active layer ACT is electrically connected to the source S and the drain D, respectively, and the orthographic projection of the active layer ACT on the substrate BS covers the orthographic projections of the source S, the drain D, and the first electrode layer E1 on the substrate BS, and the source S and the first electrode layer E1 are integral.

[0076] In embodiments of this disclosure, the gate of the thin-film transistor can be composed of stacked Al and Mo layers, the thicknesses of which can be respectively... and The active layer is a semiconductor dielectric layer, which can be made of Si-based materials or IGZO; the source and drain can be made of stacked Mo / AL / Mo or Ti / AlTi structures.

[0077] According to another aspect of this disclosure, a detector is also provided, including the detector array substrate described in any of the foregoing embodiments. Figure 16 is a comparison diagram of lag tests between detectors in the related art and detectors according to embodiments of this disclosure. The detector in the related art has a lag value of 3.41% for a single frame test and a lag value of 0.35% for a 10-frame test, while the detector according to embodiments of this disclosure has a lag value of 1.5% for a single frame test and a lag value of 0.2% for a 10-frame test. The detector according to embodiments of this disclosure reduces lag by more than 50% for both single-frame and multi-frame tests, significantly improving product performance.

[0078] According to another aspect of this disclosure, a method for fabricating a detector array substrate is also provided, comprising: providing a substrate having a plurality of pixel regions arranged in an array thereon; forming a corresponding thin-film transistor in each pixel region, wherein the thin-film transistor includes a source and a drain; forming a first electrode layer electrically connected to the thin-film transistor; forming a photoelectric conversion structure on a side of the first electrode layer away from the substrate, the photoelectric conversion structure being electrically connected to the first electrode layer, the photoelectric conversion structure including a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being located on the side of the first semiconductor layer away from the substrate; and etching the photoelectric conversion structure such that the photoelectric conversion structure includes an adjacent first semiconductor layer and a second semiconductor layer. The photoelectric conversion structure comprises a first sidewall and a second sidewall. The first sidewall is located on the side of the second sidewall away from the substrate. The first sidewall surrounds a first portion of the photoelectric conversion structure, and the second sidewall surrounds a second portion of the photoelectric conversion structure. The angle between the second sidewall and a second direction is an acute angle. The orthographic projection of the first portion of the photoelectric conversion structure onto the substrate covers the orthographic projection of the second portion of the photoelectric conversion structure onto the substrate. The orthographic projections of the first and second portions of the photoelectric conversion structure onto the plane containing the first direction lie within the orthographic projection of the first insulating layer onto the plane containing the first direction. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. Etching the photoelectric conversion structure includes: a first etching step using SF6, Cl2, and He; and a second etching step using SF6, Cl2, He, and O2.

[0079] In some embodiments, the detector array substrate shown in FIG2 can be fabricated using the following steps:

[0080] Step S1: Form a gate electrode layer on the substrate, the gate electrode layer including a gate G and a gate line GL;

[0081] Step S2: Form the gate insulating layer GI;

[0082] Step S2: Form the active layer ACT;

[0083] Step S4: Form source and drain electrode layers, such that the source and drain electrode layers include source S, drain D, and data line DL, thereby obtaining a thin film transistor;

[0084] Step S5: Form a fifth insulating layer IL5, which has a second via VH2 that exposes the source electrode;

[0085] Step S6: Form the first electrode E1, and make the first electrode E1 electrically connected to the source S of the thin film transistor through the via VH2;

[0086] Step S7: Fabricate the photoelectric conversion structure PD, including forming a first semiconductor layer N, forming an intrinsic semiconductor layer I, forming a second semiconductor layer P, and etching the photoelectric conversion structure PD;

[0087] Step S8: Form the second electrode E2;

[0088] Step S9: Form the second insulating layer IL2;

[0089] Step S10: Form the first insulating layer IL1;

[0090] Step S11: Form the third insulating layer IL3;

[0091] Step S12: Form a third metal layer, including the bias line portion BL and the light-shielding portion SL:

[0092] Step S13: Form the fourth insulating layer IL4;

[0093] Step S14: Form a conductive pattern CP.

[0094] Because the photoelectric conversion structure film of indirect X-ray sensors is relatively thick, typically approximately... Etching is difficult and requires complex conditions. Related technologies mainly involve four steps: BT + 1st etching + 2nd etching + AT. The 1st etching conditions are: power 5000W, pressure 120mtorr, SF6 250sccm, Cl2 1500sccm, He 500sccm; the 2nd etching conditions are: power 6500W, pressure 30mtorr, SF6 500sccm, Cl2 1000sccm, He 1000sccm.

[0095] This study investigated and validated various parameters of the 1st and 2nd etching conditions using single-factor and DOE methods, and developed new etching conditions, including:

[0096] First etching conditions: power 5000W, pressure 120mtorr, SF6 250sccm, Cl2 600sccm, He 200sccm; reducing gas flow rate and increasing the proportion of Cl2 and He gas improved the etching rate and plasma uniformity.

[0097] 2nd etching conditions: power 4000W, pressure 90mtorr, SF6 250sccm, Cl2 500sccm, O2 200sccm; reduce power and pressure, improve lateral etching, reduce vertical bombardment to reduce damage to sidewalls and reduce defect formation.

[0098] The photoelectric conversion structure is etched using the above-mentioned new etching conditions to form a specific sidewall morphology, which reduces the interface defects between the N-type semiconductor layer and the intrinsic semiconductor layer. The oxygen-containing etching conditions form a passivation layer on the sidewall surface to reduce the sidewall defects of the PIN structure. At the same time, the coverage ratio of the upper electrode (i.e., the incident light electrode) is increased, and the influence of internal defects in the intrinsic semiconductor layer in the area without upper electrode coverage is reduced, which significantly improves the Lag characteristics of single frame and multi-frame.

[0099] Compared with the fabrication method of the detector array substrate shown in Figure 2, the fabrication method of the detector array substrate in the example shown in Figure 14 does not include steps S9 and S11, which can reduce the number of photolithography steps, simplify the fabrication process, effectively improve the productivity coefficient, reduce costs and improve product competitiveness.

[0100] Compared with the fabrication method of the detector array substrate shown in Figure 2, the fabrication method of the detector array substrate in the example shown in Figure 15 does not include step S5, which can reduce the number of photolithography steps, simplify the fabrication process, effectively improve the productivity coefficient, reduce costs and improve product competitiveness.

[0101] It should be noted that the order of some steps in the above manufacturing method can be adjusted as needed. For example, the order of steps S1 to S4 can be adjusted according to the specific structure of the switching element T. For example, the order of steps for manufacturing the bias line layer and the transparent conductive layer can be interchanged.

[0102] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0103] In this disclosure, "electrical connection" includes the situation where components are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0104] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0105] The "patterning process" as described in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0106] "Same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask to form a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0107] In this disclosure, "the orthographic projection of A covers the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A is located within the orthographic projection of B".

[0108] As used herein, “approximately” or “about” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0109] In the accompanying drawings, the thickness of certain areas and layers may be exaggerated for clarity. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed descriptions are omitted. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the description of this disclosure to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical concept of this disclosure.

[0110] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0111] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0112] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the foregoing terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine the different embodiments or examples described herein and the features of the different embodiments or examples without contradiction.

[0113] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0114] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0115] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0116] As those skilled in the art will understand, although the steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order unless the context clearly indicates otherwise. Additional or alternatively, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps. Furthermore, other method steps may be inserted between steps. Inserted steps may represent improvements to the method described herein, or may be unrelated to the method. Moreover, a given step may not be fully completed before the next step begins.

[0117] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A detector array substrate, comprising: A substrate having multiple pixel regions arranged in an array thereon, wherein each pixel region includes: Thin-film transistors, including source and drain electrodes; A first insulating layer is located on the side of the thin-film transistor away from the substrate. A photoelectric conversion structure is located on the side of the thin-film transistor away from the substrate. The photoelectric conversion structure includes at least a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located on the side of the first semiconductor layer away from the substrate. The first electrode layer is located on the side of the photoelectric conversion structure close to the substrate. The first electrode layer is electrically connected to the photoelectric conversion structure and to the thin film transistor. The photoelectric conversion structure includes an adjacent first sidewall and a second sidewall. The first sidewall is located on the side of the second sidewall away from the substrate. The first sidewall surrounds a first part of the photoelectric conversion structure, and the second sidewall surrounds a second part of the photoelectric conversion structure. The angle between the second sidewall and the second direction is an acute angle. The orthographic projection of the first part and the second part of the photoelectric conversion structure onto the plane containing the first direction lies within the orthographic projection of the first insulating layer onto the plane containing the first direction. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate.

2. The detector array substrate according to claim 1, wherein the first portion of the photoelectric conversion structure projects onto the substrate and overlaps the second portion of the photoelectric conversion structure with its projection onto the substrate.

3. The detector array substrate according to claim 1 or 2, wherein, In the first direction, the thickness of the first semiconductor layer is H1, and the thickness of the second part of the photoelectric conversion structure is T, where T > H1.

4. The detector array substrate according to claim 3, wherein the photoelectric conversion structure further comprises an intrinsic semiconductor layer located between the first semiconductor layer and the second semiconductor layer, the intrinsic semiconductor layer having a thickness H2 in the first direction, wherein, T≤0.5H2+H1.

5. The detector array substrate according to any one of claims 1-4, wherein, The angle between the second sidewall and the second direction is in the range of 25°-45°.

6. The detector array substrate according to any one of claims 1-5, wherein, The photoelectric conversion structure also includes a passivation layer covering the first sidewall and the second sidewall.

7. The detector array substrate according to any one of claims 1-6, wherein each pixel region further comprises a second electrode layer, the second electrode layer being located on the side of the second semiconductor layer away from the substrate, wherein, The second electrode layer is in electrical contact with the second semiconductor layer, and the orthographic projection of the second electrode layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate.

8. The detector array substrate according to claim 7, wherein, The orthographic projection of the second electrode layer on the substrate coincides with the orthographic projection of the second semiconductor layer on the substrate.

9. The detector array substrate according to any one of claims 1-8, wherein each pixel region further comprises a second insulating layer, the second insulating layer being located on the side of the thin-film transistor and the first electrode layer away from the substrate, and on the side of the first insulating layer close to the substrate, wherein, The second insulating layer covers the first sidewall and the second sidewall of the photoelectric conversion structure.

10. The detector array substrate according to claim 9, wherein the thickness of the second insulating layer covering the first sidewall of the photoelectric conversion structure is greater than the thickness of the second insulating layer covering the second sidewall of the photoelectric conversion structure.

11. The detector array substrate according to any one of claims 1-10, wherein, The first electrode layer includes a first metal layer and a second metal layer, the second metal layer being located on the side of the first metal layer away from the substrate, and the second metal layer being in direct contact with the first semiconductor layer.

12. The detector array substrate according to claim 11, wherein, In the first direction, the total thickness of the photoelectric conversion structure is H; in the second direction, the distance from the intersection of the second metal layer and the second sidewall to the edge of the second metal layer is greater than 1.1H.

13. The detector array substrate according to claim 12, wherein, The material of the second metal layer is Mo.

14. The detector array substrate according to claim 11, wherein, The first metal layer includes a first metal sublayer and a second metal sublayer, the first metal sublayer being located on the side of the second metal sublayer away from the substrate, and the material of the first metal sublayer being different from the material of the second metal layer.

15. The detector array substrate according to claim 9, wherein each pixel region further comprises: The third insulating layer is located on the side of the first insulating layer away from the substrate. A third metal layer is located on the side of the third insulating layer away from the substrate, and the third metal layer includes a bias line portion and a light-shielding portion; and A first via penetrating the first insulating layer, the second insulating layer, and the third insulating layer. in, The bias line portion is electrically connected to the second electrode layer through the first via, and the light-shielding portion's orthogonal projection on the substrate covers the orthogonal projection of the thin-film transistor on the substrate.

16. The detector array substrate according to claim 15, further comprising: The fourth insulating layer is located on the side of the third metal layer away from the substrate.

17. The detector array substrate according to claim 16, further comprising: A conductive pattern is located on the side of the fourth insulating layer away from the substrate. The conductive pattern includes a transparent conductive portion and a cutout portion. The orthographic projection of the transparent conductive portion on the substrate covers the orthographic projection of the first sidewall and the second sidewall of the photoelectric conversion structure on the substrate.

18. The detector array substrate according to claim 1, wherein, The thin-film transistor includes: The gate located on the substrate; A gate insulating layer is located on the side of the gate away from the substrate, and the orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the gate on the substrate; An active layer is located on the side of the gate insulating layer away from the substrate. The active layer is electrically connected to the source and the drain, respectively. The orthographic projection of the active layer on the substrate partially overlaps with the orthographic projections of the source and the drain on the substrate, respectively. The detector array substrate further includes a fifth insulating layer located on the side of the thin-film transistor away from the substrate, the fifth insulating layer including a second via exposing the source electrode, and the first electrode layer being electrically connected to the source electrode through the second via.

19. The detector array substrate according to claim 18, wherein, The first electrode layer covers a portion of the fifth insulating layer. In a first direction, the thickness of the portion of the fifth insulating layer covered by the first electrode layer is b, and the thickness of the portion of the fifth insulating layer not covered by the first electrode layer is less than 0.8b.

20. The detector array substrate according to claim 18, further comprising gate lines arranged along the row direction of the pixel regions arranged in the array, and data lines arranged along the column direction of the pixel regions arranged in the array, wherein the gate lines are disposed on the same layer as the gate and electrically connected, and the data lines are disposed on the same layer as the source and electrically connected, wherein... The detector array substrate further includes a bonding region surrounding the pixel region. In the bonding region, a gate line bonding portion and a data line bonding portion are arranged on the same layer as the first electrode layer. The gate line bonding portion is electrically connected to the gate line through a third via penetrating the fifth insulating layer and the gate insulating layer. The data line bonding portion is electrically connected to the data line through a fourth via penetrating the fifth insulating layer. In a first direction, the thickness of the portion of the fifth insulating layer covered by the gate line bonding portion or the data line bonding portion is b, and the thickness of the portion of the fifth insulating layer not covered by the gate line bonding portion or the data line bonding portion is less than 0.8b.

21. The detector array substrate according to claim 1, wherein, The thin-film transistor includes: The gate located on the substrate; A gate insulating layer is located on the side of the gate away from the substrate, and the orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the gate on the substrate; An active layer is located on the side of the gate insulating layer away from the substrate. The active layer is electrically connected to the source and the drain, respectively. The orthographic projection of the active layer on the substrate covers the orthographic projection of the source, the drain, and the first electrode layer on the substrate. The source and the first electrode layer are integral.

22. A detector comprising a detector array substrate according to any one of claims 1-21.

23. A method for fabricating a detector array substrate, comprising: A substrate is provided on which multiple pixel regions are arranged in an array; A corresponding thin-film transistor is formed in each pixel region, wherein the thin-film transistor includes a source and a drain. A first electrode layer is formed, and the first electrode layer is electrically connected to the thin-film transistor; A photoelectric conversion structure is formed on the side of the first electrode layer away from the substrate. The photoelectric conversion structure is electrically connected to the first electrode layer. The photoelectric conversion structure includes a first semiconductor layer and a second semiconductor layer, with the second semiconductor layer located on the side of the first semiconductor layer away from the substrate. The photoelectric conversion structure is etched such that it includes an adjacent first sidewall and a second sidewall, the first sidewall being located on the side of the second sidewall away from the substrate, the first sidewall surrounding a first portion of the photoelectric conversion structure, and the second sidewall... The second part of the photoelectric conversion structure is surrounded by a wall, and the angle between the second sidewall and the second direction is an acute angle. The orthographic projection of the first part of the photoelectric conversion structure on the substrate covers the orthographic projection of the second part of the photoelectric conversion structure on the substrate. The orthographic projections of the first part and the second part of the photoelectric conversion structure on the plane containing the first direction are located within the orthographic projection of the first insulating layer on the plane containing the first direction. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate.

24. The method according to claim 23, wherein, Etching the photoelectric conversion structure includes: The first etching step was performed using SF6, Cl2, and He; and The second etching step was performed using SF6, Cl2, He, and O2.

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