Embedded packaging structure, power supply module and electronic device

Abstract

An embedded packaging structure, a power supply module and an electronic device. The embedded packaging structure comprises: a first embedded frame, a second embedded frame and a third embedded frame that are successively stacked; and an input capacitor, an inductor and an output capacitor, which are embedded in the embedded packaging structure, the output capacitor being located in the first embedded frame, the inductor being located in the second embedded frame, the input capacitor being located in the third embedded frame, and the side of the third embedded frame away from the second embedded frame being provided with a chip interface. The chip interface is used for interconnection with a chip, and the chip may be arranged on the third embedded frame, so as to construct a multi-layer embedded four-layer stacked architecture. This arrangement can reduce heat dissipation thermal resistance of power supply chips, reduce power path parasitics, reduce the risk of electrical stress, and meet product requirements in different application scenarios.

Description

Embedded packaging structures, power modules and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202410924391.X, filed on July 10, 2024, entitled "Embedded Packaging Structure, Power Supply Module and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic component packaging technology, and in particular to an embedded packaging structure, a power module, and an electronic device. Background Technology

[0003] For embedded component packaging (ECP) substrates, high current, high power density, high efficiency, low thermal resistance, and low stress are the goals to meet the development needs of the computing power industry. A typical power chip packaging module is formed by stacking inductors, embedded substrates, and capacitors in sequence. The chip has a relatively high thermal resistance, and in high-current module scenarios, this embedded solution cannot achieve the heat dissipation target for high power consumption. In addition, some input capacitors are located in the same embedded frame as the chip, and the long connection path leads to large parasitics and a high risk of electrical stress. Summary of the Invention

[0004] This application provides an embedded packaging structure, a power module, and an electronic device. By optimizing the embedded packaging structure, heat dissipation and reliability are effectively improved.

[0005] A first aspect of this application provides an embedded package structure, comprising a first embedded frame, a second embedded frame, and a third embedded frame stacked sequentially, and an input capacitor, an inductor, and an output capacitor embedded within the embedded package structure. The output capacitor is located in the first embedded frame, the inductor in the second embedded frame, and the input capacitor in the third embedded frame. A chip interface is provided on the side of the third embedded frame furthest from the second embedded frame. This chip interface is used for interconnection with a chip, which can be disposed on the third embedded frame, thereby constructing a multi-layer embedded four-layer stacked architecture.

[0006] By applying the embodiments of this application, on the one hand, the heat dissipation path of the chip located on the outer layer of the architecture has a smaller thermal resistance, and the heat dissipation risk can be effectively controlled. On the other hand, based on the structural feature that the third embedded frame with embedded input capacitors is arranged vertically adjacent to the chip, the vertical path of interconnection between the input capacitor and the chip is relatively short, with less parasitic interference and lower electrical stress risk. At the same time, based on the effective shortening of the connection path between the chip and the input capacitor, the fluctuation of the electrical signal of the input chip can be further reduced, the filtering effect of the input capacitor can be improved, and thus the reliability of chip operation can be guaranteed.

[0007] Furthermore, in this embodiment, the chip, input capacitor, and output capacitor are centrally located, maximizing the use of the planar layout area for arranging the corresponding components, resulting in high space utilization. Taking chip layout as an example, compared to the traditional architecture where some input capacitors are co-embedded with the chip, this embodiment can increase the number of chips arranged within the same layout area, thereby increasing the current density per unit area. Moreover, compared to the architecture where input capacitors and other signal resistors and capacitors are surface-mounted on the bottom of the inductor, this embodiment avoids the drawback of unreliable component soldering quality, resulting in better reliability.

[0008] In addition, the output capacitors are integrated on the first embedded frame, which reduces the parasitic path from the inductor output terminal and the output capacitor to the motherboard, while improving the filtering effect of the output capacitor, reducing the fluctuation of the output voltage, and improving the steady-state power supply output efficiency.

[0009] Based on the first aspect, this application also provides a first implementation of the first aspect: the embedded packaging structure further includes a chip embedding frame, in which a chip is embedded and stacked on a third embedding frame. Thus, a fully embedded four-layer stacked architecture is constructed, resulting in better product process consistency.

[0010] In practical applications, the chip can be exposed in the chip embedding frame, which can minimize thermal resistance and improve heat dissipation efficiency.

[0011] Based on the first implementation of the first aspect, this application also provides a second implementation of the first aspect: a signal capacitor is further embedded within the chip's embedded frame. This optimizes the circuit design, improves the signal quality of the chip's signal pins, and enhances the reliability of controls such as triggering, mode switching, or adjusting the operating frequency.

[0012] Based on the first aspect, this application also provides a third implementation of the first aspect: the embedded packaging structure further includes a chip packaging layer, which includes a chip and is stacked on the third embedded frame. Thus, a multi-layer embedded four-layer stacked architecture is constructed, resulting in better assembly processability.

[0013] For example, the chip can be a flip chip and is fixed by plastic encapsulation to form a chip packaging layer; or, the chip can also be a square flat leadless package.

[0014] In practical applications, the chip can be exposed in the chip packaging layer, which can minimize thermal resistance and improve heat dissipation efficiency.

[0015] Based on the third implementation of the first aspect, this application also provides a fourth implementation of the first aspect: the chip package layer further includes a signal capacitor. This optimizes the circuit design, improves the signal quality of the chip signal pins, and enhances the reliability of controls such as triggering, mode switching, or adjusting the operating frequency.

[0016] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, this application also provides a fifth implementation of the first aspect: at least one of the first embedded frame and the third embedded frame has a resistor embedded within it. Thus, for the power supply module, the input-side resistor and input capacitor can be co-embedded in the third embedded frame, and the output-side resistor and output capacitor can be co-embedded in the first embedded frame, effectively reducing path loss through optimized circuit design.

[0017] For example, the embedded elements in the first embedded frame and the third embedded frame can be arranged as a single-layer element stack, a two-layer element stack, or other multi-layer element stack, respectively.

[0018] Other examples include resistors and capacitors embedded in the first and third embedded frames, which can be double-pin resistor-capacitor components, providing more flexible wiring and connection methods, and facilitating optimized circuit design to achieve current flow and current sharing.

[0019] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, this application also provides a sixth embodiment of the first aspect: the outer peripheral sidewall of each embedded frame has a connecting side, the connecting side being used to construct a power path or signal line. Exemplarily, a copper plating process can be used to form the connecting side, thereby creating vertical interconnections between layers, which further facilitates heat dissipation while enabling rapid signal and current transmission.

[0020] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, this application also provides a seventh implementation of the first aspect: each embedded frame has a connecting sidewall inside, and the connecting sidewall is used to construct power paths or signal lines. In this way, the current carrying and interconnection of power paths and signal lines between layers can be realized, improving the current carrying capacity while taking into account good heat dissipation efficiency.

[0021] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, the embodiments of this application also provide an eighth implementation of the first aspect: the interconnection layers of each embedded frame are interconnected by blind slots or blind vias, or the interconnection layers of each embedded frame are interconnected by copper paste or silver paste, or the interconnection layers of each embedded frame are interconnected by solder.

[0022] In practical applications, the copper interconnects between the interconnect layers of each embedded frame, formed by blind slots or blind vias, or by copper paste, or by silver paste, have little impact on the overall power path layout and wiring of the module.

[0023] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, this application also provides a ninth embodiment of the first aspect: an inductor embedded in a second embedded frame, the terminals of which are connected to the interconnect layer traces of the second embedded frame through an interconnect structure, and the terminals are arranged in a sheet shape. This allows for obtaining the largest possible copper area for the terminal interconnects, effectively reducing the parasitic resistance of the interconnect path on the inductor terminal side, and further reasonably controlling the risk of electrical stress.

[0024] Based on the ninth embodiment of the first aspect, this application also provides a tenth embodiment of the first aspect: the interconnect structure is a through-hole or a blind trench, the through-hole being a fully electroplated through-hole or a resin-filled through-hole, and the blind trench being a fully electroplated blind trench or a resin-filled trench. In practical applications, when the inductor thickness is thin and the through-hole depth or blind trench depth is small, a fully electroplated through-hole or a fully electroplated blind trench can be used. When the inductor thickness is thick and the through-hole depth or blind trench depth is large, a resin-filled through-hole or a resin-filled blind trench can be used to obtain good process feasibility and reliability.

[0025] A second aspect of this application provides a power module comprising a chip, an inductor, an input capacitor, and an output capacitor, wherein the chip, inductor, input capacitor, and output capacitor are packaged using the embedded packaging structure described above. Based on the structural characteristics of this embedded packaging structure, the power module provided in this application can reduce the thermal resistance of the power chip, decrease power path parasitics, reduce electrical stress risks, and meet the product requirements of different application scenarios.

[0026] A third aspect of this application provides an electronic device, which includes a motherboard and a power module. The power module is disposed on the motherboard and is the power module as described above.

[0027] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc. Attached Figure Description

[0028] Figure 1 is a cross-sectional schematic diagram of an embedded packaging structure provided in an embodiment of this application;

[0029] Figure 2 is a schematic diagram of a process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0030] Figure 3 is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0031] Figure 4 is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0032] Figure 5 is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0033] Figure 6 is a cross-sectional schematic diagram of another combined embedded frame provided in an embodiment of this application;

[0034] Figure 7 is a cross-sectional schematic diagram of another combined embedded frame provided in an embodiment of this application;

[0035] Figure 8 is a cross-sectional schematic diagram of another embedded packaging structure provided in an embodiment of this application;

[0036] Figure 9 is a schematic diagram of a process flow for a power module formed based on the embedded packaging structure shown in Figure 8.

[0037] Figure 10 is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 8.

[0038] Figure 11 is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 8.

[0039] Figure 12 is a cross-sectional schematic diagram of another embedded packaging structure provided in an embodiment of this application;

[0040] Figure 13 is a schematic diagram of a process flow for a power module formed based on the embedded packaging structure shown in Figure 12.

[0041] Figure 14 is a cross-sectional schematic diagram of another embedded packaging structure provided in an embodiment of this application;

[0042] Figure 15 is a schematic diagram of a process flow for a power module formed based on the embedded packaging structure shown in Figure 14.

[0043] Figure 16 is a cross-sectional schematic diagram of another embedded packaging structure provided in an embodiment of this application;

[0044] Figure 17 is a schematic diagram of a process flow for a power module formed based on the embedded packaging structure shown in Figure 16.

[0045] Figure 18 is a schematic cross-sectional view of an embedded frame for stacked double-layer components provided in an embodiment of this application.

[0046] Figure 19 is a schematic diagram of another chip packaging layer assembly relationship provided in an embodiment of this application;

[0047] Figure 20 is a schematic diagram of the process flow of another second embedded frame provided in the embodiment of this application;

[0048] Figure 21 is a schematic diagram of the structure of seven types of inductor windings provided in the embodiments of this application;

[0049] Figure 22 is a partial interconnection diagram of the terminals on one side of the inductor provided in an embodiment of this application;

[0050] Figure 23 is a schematic diagram of an inductor terminal provided in an embodiment of this application;

[0051] Figure 24 is a schematic diagram of the interconnection structure of four types of inductor terminals provided in the embodiments of this application;

[0052] Figure 25 shows the junction temperature effect obtained by simulation tests based on the power module described in the embodiment of this application and the comparative example;

[0053] Figure 26 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] This application provides a solution for an embedded packaging structure that achieves low thermal resistance and low parasitics, applicable to various high-integration, high-density application scenarios.

[0055] ECP technology is used to embed electronic components within a substrate, reducing transmission losses in the connection paths between components, improving product integration, and reducing module size. In practical applications, ECP technology can be used in various scenarios. As product functionality continues to evolve, achieving high current, high heat dissipation, and high reliability has become a core requirement for embedded packaging structures.

[0056] Taking the embedded packaging structure used in power chip packaging modules as an example, in a typical embedded vertical power supply architecture, some input capacitors are co-embedded with the chip in the intermediate embedded frame. The connection path between the input capacitors and the chip is relatively long, resulting in significant parasitics and a high risk of electrical stress. Another portion of the input capacitors, along with other signal resistors and capacitors, are surface-mounted on the intermediate embedded frame, located at the bottom of the inductor. Inspecting the soldering quality after surface mounting is difficult, compromising product yield and posing a high reliability risk. Furthermore, in the architecture formed by stacking inductors, embedded substrates, and capacitor boards, this embedded solution cannot achieve the high-power heat dissipation target under high-current scenarios.

[0057] Based on this, this application provides an embedded packaging structure, which includes a first embedded frame, a second embedded frame, and a third embedded frame stacked sequentially, and an input capacitor, an inductor, and an output capacitor embedded in each embedded frame; wherein the output capacitor is located in the first embedded frame, the inductor is located in the second embedded frame, and the input capacitor is located in the third embedded frame, and a chip interface is provided on the side of the third embedded frame away from the second embedded frame. In this way, the chip can be disposed on the third embedded frame, forming a multi-layer embedded four-layer stacked architecture.

[0058] With this configuration, the heat dissipation path of the chip located on the outer layer of the architecture has a smaller thermal resistance, and the heat dissipation risk is effectively controlled. Based on the structural feature that the third embedded frame with embedded input capacitors is arranged vertically adjacent to the chip, the vertical path of interconnection between the input capacitor and the chip is relatively short, with less parasitic interference and lower electrical stress risk. At the same time, the effective shortening of the connection path between the chip and the input capacitor can further reduce the fluctuation of the electrical signal of the input chip, improve the filtering effect of the input capacitor, and thus ensure the reliability of chip operation.

[0059] Furthermore, in this embodiment, the chip, input capacitor, and output capacitor are centrally located, maximizing the use of the planar layout area to arrange the corresponding components, resulting in high space utilization. Taking chip layout as an example, compared to the traditional architecture where some input capacitors are co-embedded with the chip, this embodiment can increase the number of chips and improve the current density per unit area within the same layout area.

[0060] In addition, the output capacitors are integrated on the first embedded frame, which reduces the parasitic path from the inductor output terminal and the output capacitor to the motherboard, while improving the filtering effect of the output capacitor, reducing the fluctuation of the output voltage, and improving the steady-state power supply output efficiency.

[0061] Furthermore, compared to the architecture where input capacitors and other signal resistors and capacitors are mounted on the bottom of the inductor, the embodiment of this application, based on the layered arrangement of components, can avoid the defects of unreliable component soldering quality. Overall, it has better reliability.

[0062] To better understand the technical solution and effects of this application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings and focusing on the power module. Please refer to Figure 1, which is a cross-sectional schematic diagram of an embedded packaging structure provided by an embodiment of this application.

[0063] As shown in Figure 1, the embedded packaging structure includes three embedded frames stacked sequentially. From bottom to top, as shown in the figure, they are the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13. The chip packaging layer 14 is stacked on the third embedded frame 13, forming a four-layer stacked power module 10. It should be understood that other functional components of this power module can be implemented using existing technology, and therefore will not be described further here.

[0064] Chip 1, input capacitor 2, inductor 3, and output capacitor 4 are integrated into this four-layer stacked architecture. Specifically, output capacitor 4 is located in the first embedded frame 11, inductor 3 is located in the second embedded frame 12, and input capacitor 2 is located in the third embedded frame 13. The third embedded frame 13 has a chip interface 1311 for accommodating the chip package layer 14, enabling interconnection with the pins of chip 1.

[0065] In a practical implementation, chip 1 can first be surface-mounted on a three-layer embedded frame, soldered and interconnected with chip interface 1311, and then fixed to the three-layer embedded frame through a molding process. Chip 1 can also be exposed, with molding material covering the outer periphery of chip 1 to form the chip encapsulation layer 14. In other words, chip 1 is exposed on the surface of the power module 10, and the heat dissipation path of chip 1 is not affected by other embedded layers, resulting in lower thermal resistance. "Exposed" here includes the case where the outer surface of chip 1 is completely flush with the outer surface of the molding material, and also includes the case where the outer surface of chip 1 and the outer surface of the molding material are close to flush within the allowable tolerance range. Utilizing the high thermal conductivity of the silicon-based material of chip 1, the junction temperature is effectively reduced.

[0066] Vertically, the chip package layer 14 is arranged adjacent to the third embedded frame 13, and each input capacitor 2 is vertically adjacent to the chip package layer 14. The interconnection path between the input capacitor 2 and the chip 1 is shown by the arrow in Figure 1. This vertical path is relatively short, which can reduce path parasitics. The DC internal resistance (DCR) between the input capacitor 2 and the chip 1 can be reduced to 10% of that of a typical traditional architecture, and the AC inductance (ACL) can be reduced to 25% of that of a typical traditional architecture. Overall, it can effectively reduce the risk of electrical stress and meet the matching requirements of high current and high power density. At the same time, the effective shortening of the connection path between the chip 1 and the input capacitor 2 can further reduce the fluctuation of the electrical signal of the input chip 1, improve the filtering effect of the input capacitor 2, and ensure the working reliability of the chip 1.

[0067] The output capacitor 4 is integrated into the first embedded frame 11 and is adjacent to the second embedded frame 12 containing the embedded inductor 3. This reduces the parasitic path from the output terminal of the inductor 3 and the output capacitor 4 to the motherboard (not shown in Figure 1), while improving the filtering effect of the output capacitor 4, reducing output voltage fluctuations, and improving the steady-state power supply output efficiency. Based on this, stable mode switching can be achieved, meeting the functional needs of different application scenarios and exhibiting good adaptability.

[0068] In this implementation scheme, chip 1, input capacitor 2, inductor 3, and output capacitor 4 are respectively centrally arranged in their respective layers, maximizing the utilization of the module architecture area and achieving high space utilization. Taking the chip 1 layout as an example, multiple chips 1 can be arranged within the chip packaging layer, increasing the current density per unit area, for example, but not limited to, increasing the current density by 85%. Taking inductor 3 as an example, the second embedded frame 12 can only accommodate inductor 3. In other words, the layout of the inductor layer does not need to consider other resistive and capacitive components, making full use of the layer area to arrange the inductor. Under the same inductance, the overall thickness of the inductor 3 can be reasonably controlled, for example, but not limited to, reducing the inductor thickness by 30%.

[0069] To clearly illustrate the basic architecture of this embedded package structure, the figure exemplifies two chips 1, four input capacitors 2, one inductor 3, and two output capacitors 4. It is understood that the number of chips 1, input capacitors 2, inductors 3, and output capacitors 4 can be determined based on the overall product design requirements, and is not limited to the example shown in the figure.

[0070] In other specific implementations, resistors or signal resistors / capacitors can be embedded in the first embedded frame 11, and resistors or signal resistors / capacitors can also be embedded in the third embedded frame 13 (not shown in the figure). To improve the current carrying and current sharing effects of the first embedded frame 11 and the third embedded frame 13, the resistors and capacitors embedded in the first embedded frame 11 and the third embedded frame 13 can be double-sided pin-out resistors / capacitors, providing more flexible wiring and connection methods, which is conducive to optimizing circuit design to achieve current carrying and current sharing. For example, but not limited to, the double-sided pin-out input capacitor 2 and the double-sided pin-out output capacitor 4 shown in the figure.

[0071] For the power module, the power path and signal line current carrying and interconnection can be achieved through the connecting side 5 on the outer periphery of the module architecture. This connecting side 5 is used to construct the power path and / or signal line between at least two embedded frames. In specific implementation, the connecting side 5 on the outer periphery of the module architecture can be formed using a copper plating process, which facilitates the rapid transmission of signals, heat, and current. The specific shape can be determined according to the functional requirements of the interconnecting links.

[0072] Furthermore, the internal structures of each embedded frame include, but are not limited to, resin-filled holes, solid through holes, and organic frames. This application does not limit the scope of the embodiments.

[0073] The power module 10 described in Figure 1 can be manufactured using a process flow shown in Figure 2.

[0074] Step S201: Mount inductor 3 and press and fill it.

[0075] Specifically, the inductor 3 is mounted on the mold material A; here, the inductor 3 can be integrally formed using processes such as copper-iron co-firing. Next, a filling and pressing operation is performed to assemble and fix the inductor 3. The filling material 121 can be Ajinomoto Build-up Film (ABF) dielectric material, which is pressed and filled to fill the entire internal groove and embedded cavity of the inductor, or the filling material can be selected according to the actual process conditions.

[0076] Step S202: Fabricate the interconnect layer to form the second embedded frame 12.

[0077] In a specific implementation, the filling material 121 can also form the dielectric layer of the interconnect layer 122 on both sides of the inductor 3, so as to interconnect with the stacked resistor-capacitor layers (first embedded frame 11 and third embedded frame 13) on both sides respectively.

[0078] Step S203: Create the third embedded frame 13.

[0079] On one side surface of the second embedded frame 12, a third embedded frame 13 is formed to form components such as the embedded input capacitor 2. The third embedded frame 13 includes a circuit layer and an interconnect layer 131 for interconnection with the chip package layer 14. A chip interface 1311 is formed on the side of the third embedded frame 13 away from the second embedded frame 12.

[0080] Step S204: The first embedded frame 11 is formed.

[0081] On the other side of the second embedded frame 12, a first embedded frame 11 is fabricated to form components such as the embedded output capacitor 4, including a circuit layer and an interconnect layer within the first embedded frame 11. In this process, the interconnection between the stacked layer structures is achieved through copper interconnects 6 formed based on blind trenches or blind vias.

[0082] Step S205: Fabricate the connected side 5 and form the chip packaging layer 14.

[0083] After the first embedded frame 11 (the input capacitor layer for embedded input capacitor 2), the second embedded frame 12 (the inductor layer for embedded inductor 3), and the third embedded frame 13 (the output capacitor layer for embedded output capacitor 4) are completed, a copper plating process is used to form a connecting side 5 on the sidewall of the module frame to establish vertical interconnections between the layers, including the current flow and interconnection of power paths and signal lines. Next, the chip 1 is surface-mounted on the third embedded frame 13 and soldered to the chip interface 1311 for interconnection. Then, it is fixed by a molding process, with the molding material covering the outer periphery of the chip 1 to form the chip package layer 14. Overall, a power module 10 with a multi-layer embedded four-layer stacked structure is constructed.

[0084] In specific implementations, other components can also be surface-mounted on the chip packaging layer 14 to achieve the corresponding set functions. This application does not limit the scope of the embodiments.

[0085] Optionally, the resistors and capacitors embedded in the first embedded frame 11 and the third embedded frame 13 can both be double-sided pin-out resistors and capacitors. Accordingly, the third embedded frame 13 formed in step 203 and the first embedded frame 11 formed in step 204 are provided with interconnect layers on both sides to improve current flow and current equalization.

[0086] In other possible implementations, the process sequence of steps 203 and 204 can be adjusted. This application does not limit the specific implementation.

[0087] The power module formed by the embedded packaging structure described in Figure 1 can also be implemented using other process flows. Please refer to Figure 3, which is a schematic diagram of another process flow for the power module formed based on the embedded packaging structure shown in Figure 1.

[0088] Step S301: Mount inductor 3 and press and fill it.

[0089] Step S302: Fabricate the interconnect layer to form the second embedded frame 12.

[0090] For the above steps S301 to S302, please refer to the process diagram of steps S201 to S202 in Figure 2.

[0091] Step S303: Mount input capacitor 2 and press and fill it.

[0092] Specifically, each input capacitor 2 is attached to the mold material A, and the input capacitor 2 is assembled and fixed by filling and pressing. The filling material can be ABF, which is pressed and filled into the embedded cavity, or the filling material can be selected according to the actual process conditions.

[0093] Step S304: Fabricate the interconnect layer to form the third embedded frame 13.

[0094] In a specific implementation, the filling material can also form the dielectric layer of the interconnect layer 131 on both sides of the input capacitor 2. The interconnect layer 131 may specifically include copper interconnects formed based on blind trenches or blind vias. The chip interface 1311 is formed on the side of the third embedded frame 13 away from the second embedded frame 12.

[0095] Step S305: Mount the output capacitor 4 and press it to fill.

[0096] Specifically, each output capacitor 4 is mounted on the mold material A, and a filling and pressing operation is performed to assemble and fix the output capacitor 4. The filling material can be ABF, which is pressed and filled into the embedded cavity, or the filling material can be selected according to the actual process conditions.

[0097] Step S306: Fabricate the interconnect layer to form the first embedded frame 11.

[0098] In a specific implementation, the filling material can also form the dielectric layer of the interconnect layer on both sides of the output capacitor 4. The interconnect layer can specifically include copper interconnects formed based on blind slots or blind vias.

[0099] In step S307, the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are stacked and interconnected in sequence.

[0100] In specific implementations, copper interconnects 6a can be achieved between the first embedded frame 11 and the second embedded frame 12, and between the second embedded frame 12 and the third embedded frame 13, using Cu paste, or silver interconnects 6b can be achieved using Ag paste. Overall, the interconnect interface material of the embedded frames has good high conductivity and does not affect the layout and routing of power paths.

[0101] Step S308: Fabricate the connected side 5 and form the chip packaging layer 14.

[0102] For the above step S308, please refer to the process diagram of step S202 in Figure 2.

[0103] In other possible implementation schemes, the process sequence of steps S301 to S302, steps S303 to S304 and steps S305 to S306 can be adjusted to each other, that is, the manufacturing order of the first embedded frame 11, the second embedded frame 12 and the third embedded frame 13 is not limited.

[0104] Please refer to Figure 4, which is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0105] Step S401: Mount inductor 3 and press and fill it.

[0106] Step S402: Fabricate the interconnect layer to form the second embedded frame 12.

[0107] Step S403: Mount input capacitor 2 and press and fill it.

[0108] Step S404: Fabricate the interconnect layer to form the third embedded frame 13.

[0109] Step S405: Mount the output capacitor 4 and press it to fill.

[0110] Step S406: Fabricate the interconnect layer to form the first embedded frame 11.

[0111] For the above steps S401 to S406, please refer to the process diagram of steps S301 to S306 in Figure 3.

[0112] In step S407, the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are stacked and interconnected in sequence.

[0113] In a specific implementation, the first embedded frame 11 and the second embedded frame 12, and the second embedded frame 12 and the third embedded frame 13 can be interconnected with solder 6c.

[0114] Step S408: Fabricate the connected side 5 and form the chip packaging layer 14.

[0115] For the above step S408, please refer to the process diagram of step S308 in Figure 3.

[0116] Please refer to Figure 5, which is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 1.

[0117] Step S501: Mount the input capacitor 2 and press it to fill.

[0118] In step S502, the inductor 3 is mounted onto the input capacitor 2 and then pressed and filled.

[0119] Specifically, step S501 can be referred to in the process diagram of step S303 in Figure 3. In step S502, the filling material can also be ABF, which is used to press and fill the internal groove and embedded cavity of the inductor 3, or the filling material can be selected according to the actual process conditions.

[0120] Step S503: Fabricate an interconnect layer to form a combined embedded frame of the second embedded frame 12 and the third embedded frame 13. Here, "combined embedded frame" means that two layers of stacked architecture components are embedded in one frame.

[0121] In a specific implementation, the filling material can also form the dielectric layer of the interconnect layers on both sides of the combined embedded frame. The interconnect layer can also include copper interconnects formed based on blind slots or blind vias, for interconnection with the stacked architecture layers (first embedded frame 11 and chip packaging layer 14) on both sides, respectively.

[0122] Based on the process flow shown in Figure 5, the fabrication of the first embedded frame 11 and the chip packaging layer 14 can be selected from any of the implementation methods shown in Figures 2 and 3. Further details will not be provided here.

[0123] In a specific implementation, the first embedded frame 11 and the second embedded frame 12 can be combined and processed, and then the third embedded frame 13 and the chip packaging layer 14 (not shown in the figure) can be stacked sequentially based on the combined embedded frame. This application does not limit the embodiments.

[0124] In other specific implementations, the resistors and capacitors of the first embedded frame 11 or the third embedded frame 13 can also be embedded in the body of the inductor 3. For example, the input capacitor 2 can be embedded in the body of the inductor 3 to form a combined embedded frame.

[0125] Please refer to Figure 6, which is a cross-sectional schematic diagram of another combined embedded frame provided in an embodiment of this application. As shown in Figure 6, the inductor 3 has a recessed portion 31, the input capacitor 2 is built into the recessed portion 31 and pressed and filled, and interconnect layers on both sides of the combined embedded frame are formed as needed. Please refer to Figure 7, which is a cross-sectional schematic diagram of yet another combined embedded frame provided in an embodiment of this application. As shown in Figure 7, the inductor 3 is prepared by processing materials such as magnetic film, magnetic slurry or magnetic encapsulant, and the input capacitor 2 and inductor 3 are integrally formed and pressed and filled based on the material process, and interconnect layers on both sides of the combined embedded frame are formed as needed.

[0126] In the four-layer stacked architecture described in the foregoing embodiments, the chip is stacked on a three-layer embedded frame in the form of a chip package layer. In a specific implementation, the chip can also be stacked on a three-layer embedded frame in the form of an embedded frame, forming a fully embedded four-layer stacked architecture. Please refer to Figure 8, which is a cross-sectional schematic diagram of another embedded package structure provided in this application embodiment. In order to clearly show the differences and connections between this embodiment and the embodiment described in Figure 1, the same functional components or structures are indicated by the same reference numerals in the figure.

[0127] As shown in Figure 8, the embedded packaging structure includes four embedded frames stacked sequentially. From bottom to top, as shown in the figure, they are the first embedded frame 11, the second embedded frame 12, the third embedded frame 13, and the chip embedded frame 14a, forming a fully embedded four-layer stacked power module 10. Chip 1, input capacitor 2, inductor 3, and output capacitor 4 are integrated into this four-layer stacked architecture.

[0128] The output capacitor 4 is located in the first embedded frame 11, the inductor 3 is located in the second embedded frame 12, the input capacitor 2 is located in the third embedded frame 13, and the chip 1 is located in the chip embedded frame 14a.

[0129] Other components and connections can be the same as those in the aforementioned embodiments, and will not be repeated here.

[0130] In this embodiment, chip 1 is exposed on the surface of power module 10. The heat dissipation path of chip 1 is not affected by other embedded layers, and the thermal resistance of the heat dissipation path is small. At the same time, in the vertical direction, chip embedded frame 14a and third embedded frame 13 are arranged adjacent to each other, and each input capacitor 2 is arranged vertically adjacent to chip embedded frame 14a. The vertical path for interconnection between the capacitor 2 and chip 1 is relatively short, which can reduce path parasitics and reduce the risk of electrical stress. Thus, the matching requirements of high current and high power density can be met.

[0131] In addition, the effective shortening of the connection path between chip 1 and input capacitor 2 can further reduce the fluctuation of the electrical signal of input chip 1, improve the filtering effect of input capacitor 2, and ensure the working reliability of chip 1.

[0132] Similarly, this implementation reduces the parasitic path from the output of inductor 3 and output capacitor 4 to the motherboard, while improving the filtering effect of output capacitor 4. Furthermore, it maximizes the utilization of the module architecture area, resulting in high space utilization.

[0133] The power module 10 described in Figure 8 can be manufactured using a process flow shown in Figure 9.

[0134] Step S901: Mount inductor 3 and press and fill it.

[0135] Step S902: Fabricate the interconnect layer to form the second embedded frame 12.

[0136] Step S903: The third embedded frame 13 is formed.

[0137] Step S904: The first embedded frame 11 is formed.

[0138] For the above steps S901 to S904, please refer to the process diagram of steps S201 to S204 in Figure 2.

[0139] Step S905: Fabricate the chip embedding frame 14a and the connected side portion 5.

[0140] After the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are completed, the stacking process continues to form the chip embedded frame 14a. In this process, the chip 1 is also connected to other stacked structures through embedding and copper interconnects. Next, on the sidewall of the overall module frame, a copper plating process is used to form the connecting side 5 to establish vertical interconnects between layers, including the current flow and interconnection of power paths and signal lines. Overall, a power module 10 with a fully embedded four-layer stacked structure is constructed, and the interconnect layers between the stacked architectures include copper interconnects formed based on blind slots or blind vias.

[0141] The power module formed by the embedded packaging structure described in Figure 8 can also be implemented using other process flows. Please refer to Figure 10, which is a schematic diagram of another process flow for the power module formed based on the embedded packaging structure shown in Figure 8.

[0142] Step S1001: Mount inductor 3 and press and fill it.

[0143] Step S1002: Fabricate the interconnect layer to form the second embedded frame 12.

[0144] Step S1003: Mount input capacitor 2 and press and fill it.

[0145] Step S1004: Fabricate the interconnect layer to form the third embedded frame 13.

[0146] Step S1005: Mount the output capacitor 4 and press it to fill.

[0147] Step S1006: Fabricate the interconnect layer to form the first embedded frame 11.

[0148] In step S1007, the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are stacked and interconnected in sequence. In a specific implementation, the first embedded frame 11 and the second embedded frame 12, and the second embedded frame 12 and the third embedded frame 13, are interconnected by copper paste 6a, or by silver paste 6b.

[0149] For steps S1001 to S1017 above, please refer to the process diagram of steps S301 to S307 in Figure 3.

[0150] Step S1008: Fabricate the chip embedding frame 14a and the connected side portion 5.

[0151] For the above step S1008, please refer to the process diagram of step S905 in Figure 9.

[0152] In other possible implementation schemes, the manufacturing order of the first embedded frame 11, the second embedded frame 12 and the third embedded frame 13 is not limited.

[0153] Please refer to Figure 11, which is a schematic diagram of another process flow for a power module formed based on the embedded packaging structure shown in Figure 8.

[0154] Step S1101: Mount inductor 3 and press and fill it.

[0155] Step S1102: Fabricate the interconnect layer to form the second embedded frame 12.

[0156] Step S1103: Mount input capacitor 2 and press and fill it.

[0157] Step S1104: Fabricate the interconnect layer to form the third embedded frame 13.

[0158] Step S1105: Mount the output capacitor 4 and press and fill it.

[0159] Step S1106: Fabricate the interconnect layer to form the first embedded frame 11.

[0160] For the above steps S1101 to S1106, please refer to the process diagram of steps S1001 to S1006 in Figure 3.

[0161] In step S1107, the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are stacked and interconnected in sequence.

[0162] In a specific implementation, the first embedded frame 11 and the second embedded frame 12, and the second embedded frame 12 and the third embedded frame 13 can be interconnected with solder 6c.

[0163] Step S1108: Fabricate the connected side 5 and form the chip packaging layer 14.

[0164] For the above step S1108, please refer to the process diagram of step S905 in Figure 9.

[0165] In the four-layer stacked architecture described in the foregoing embodiments, the chip package layer 14 and the chip embedding frame 14a are equipped with the chip 1. In other specific implementations, signal resistors and capacitors can also be arranged on the chip layer. Please refer to Figure 12, which is a cross-sectional schematic diagram of another embedded package structure provided by an embodiment of this application. In order to clearly show the differences and connections between this embodiment and the embodiment described in Figure 1, the same functional components or structures are indicated by the same reference numerals in the figure.

[0166] As shown in Figure 12, the embedded packaging structure includes a first embedded frame 11, a second embedded frame 12, and a third embedded frame 13 stacked sequentially. A chip packaging layer 14 is stacked on the third embedded frame 13, forming a multi-layer embedded four-layer stacked power module 10. Compared to the embedded packaging structure described in Figure 1, the difference in this embodiment is that the chip packaging layer 14 is equipped with a chip 1 and a signal capacitor 7. The signal capacitor 7 reduces the fluctuation or noise of the signal pins of the chip 1, improves the signal quality of the chip signal pins, and ensures the reliability of controls such as triggering (starting), switching modes, or adjusting the operating frequency.

[0167] In specific implementations, the number of signal capacitors 7 can be determined according to the overall product design requirements. This application embodiment does not impose any limitations. In this way, the layout space below the vertical dimension of chip 1 can be utilized to the maximum extent. The third embedded frame 13 below the vertical dimension of chip 1 is arranged as the input capacitor 2, which can increase the number of input capacitors by 40% per phase, thereby maximizing the number of input capacitors and further improving the stability of the power input signal of chip 1 and the module efficiency.

[0168] Other components and connections can be the same as those in the aforementioned embodiments, and will not be repeated here.

[0169] The power module 10 described in Figure 12 can be manufactured using a process flow shown in Figure 13.

[0170] Step S1301: Mount inductor 3 and press and fill it.

[0171] Step S1302: Fabricate the interconnect layer to form the second embedded frame 12.

[0172] Step S1303: The third embedded frame 13 is formed.

[0173] Step S1304: The first embedded frame 11 is formed.

[0174] Step S1305: Fabricate the connected side 5 and form the chip packaging layer 14.

[0175] After the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are completed, a copper plating process is used to form a connecting side 5 on the sidewall of the module frame to establish vertical interconnections between the layers, including the current flow and interconnection of power paths and signal lines. Next, the chip 1 and the signal capacitor 7 are surface-mounted on the third embedded frame 13 and soldered to the chip interface 1311 for interconnection. Then, they are fixed by a molding process to form the chip package layer 14. Overall, a power module 10 with a multi-layer embedded four-layer stacked structure is constructed.

[0176] Please refer to Figure 14, which is a cross-sectional schematic diagram of another embedded packaging structure provided in an embodiment of this application. In order to clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 8, the same functional components or structures are indicated by the same reference numerals in the figure.

[0177] As shown in Figure 14, the embedded packaging structure includes a first embedded frame 11, a second embedded frame 12, a third embedded frame 13, and a chip embedded frame 14a stacked sequentially to form a power module 10 with a fully embedded four-layer stacked architecture. Compared with the embedded packaging structure described in Figure 8, the difference in this embodiment is that the chip embedded frame 14a is equipped with a chip 1 and a signal capacitor 7.

[0178] Other components and connections can be the same as those in the aforementioned embodiments, and will not be repeated here.

[0179] The power module 10 described in Figure 14 can be manufactured using a process flow shown in Figure 15.

[0180] Step S1501: Mount inductor 3 and press and fill it.

[0181] Step S1502: Fabricate the interconnect layer to form the second embedded frame 12.

[0182] Step S1503: Create the third embedded frame 13.

[0183] Step S1504: The first embedded frame 11 is formed.

[0184] For the above steps S1501 to S1504, please refer to the process diagram of steps S201 to S204 in Figure 2.

[0185] Step S1505: Fabricate the chip embedding frame 14a and the connected side portion 5.

[0186] After the first embedded frame 11, the second embedded frame 12, and the third embedded frame 13 are completed, the stacking process continues to form the chip embedded frame 14a. In this process, the chip 1 and the signal capacitor 7 are also connected to other stacked structures through embedding and copper interconnects. Next, on the sidewall of the overall module frame, a copper plating process is used to form the connecting side 5 to establish vertical interconnects between layers, including the current flow and interconnection of power paths and signal lines. Overall, a power module 10 with a fully embedded four-layer stacked structure is constructed.

[0187] To further improve current carrying capacity, in specific implementations, power paths and signal lines can be connected and interconnected through the interconnected sidewalls within each layer of the embedded frame. Please refer to Figure 16, which is a cross-sectional schematic diagram of another embedded packaging structure provided in this application embodiment. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 8, components or structures with the same function are indicated by the same reference numerals in the figures.

[0188] As shown in Figure 16, the embedded packaging structure includes a first embedded frame 11, a second embedded frame 12, a third embedded frame 13, and a chip embedded frame 14a stacked sequentially to form a fully embedded four-layer stacked power module 10. Compared with the embedded packaging structure described in Figure 8, the difference in this embodiment is that the first embedded frame 11, the second embedded frame 12, the third embedded frame 13, and the chip embedded frame 14a each have a connecting sidewall 8. The connecting sidewall 8 inside each embedded frame enables the current flow and interconnection of power paths and signal lines between layers, improving current flow capacity while also ensuring good heat dissipation efficiency.

[0189] In a practical implementation, the connecting sidewalls 8 located inside the embedded frames of each layer can be formed using a copper plating process, and the specific shape can be determined according to the functional requirements of the conductive interconnection links. Other components and connection relationships can be the same as those in the aforementioned embodiments, and will not be repeated here.

[0190] In other specific implementations, the first embedded frame 11, the second embedded frame 12, the third embedded frame 13, and the chip embedded frame 14a may be provided with connecting sidewalls 8 according to product design requirements. This application does not limit the scope of the embodiments.

[0191] The power module 10 described in Figure 16 can be manufactured using a process flow shown in Figure 17.

[0192] Step S1701: Mount inductor 3 and press and fill it.

[0193] Step S1702: Fabricate the second embedded frame 12.

[0194] Step S1703: Create the third embedded frame 13.

[0195] Step S1704: The first embedded frame 11 and the chip embedded frame 14a, as well as the connecting side 5, are fabricated.

[0196] For steps S1701 to S174 above, please refer to the process diagram of steps S901 to S905 in Figure 9.

[0197] In practical implementation, the connecting sidewalls 8 of each embedded frame can be formed using a copper plating process to create vertical interconnections between layers, including power paths and signal lines for current flow and interconnection. Further details are omitted here.

[0198] Furthermore, for the first embedded frame 11 and the third embedded frame 13, the capacitors and / or resistors in each layer of the embedded frame are arranged as a single layer of components in the foregoing embodiments. In other specific implementations, the capacitors and / or resistors in the first embedded frame 11 and the third embedded frame 13 can also be arranged as a multi-layer stack of components, as shown in Figure 18, which is a cross-sectional schematic diagram of a double-layer stack of embedded frames provided in an embodiment of this application.

[0199] As shown in Figure 18, taking the third embedded frame 13 as an example, the input capacitor 2 and / or resistor elements are stacked in two layers. In other specific implementations, they can also be arranged as other multi-layer stacked elements.

[0200] Furthermore, in the embedded packaging structures described in Figures 1 and 12 above, the chips 1 of the chip packaging layer 14 are all flip chips (FC) and fixed by plastic encapsulation. In other specific implementations, the chips 1 of the chip packaging layer 14 can also be quad flat no-leads packages (QFN). Please refer to Figure 19, which is a schematic diagram of another chip packaging layer assembly relationship provided in an embodiment of this application.

[0201] As shown in Figure 19, all chips 1 in the chip packaging layer 14 are QFN chips and are soldered and fixed on the third embedded frame 13. In this way, the thermal resistance of the heat dissipation path of the exposed chip 1 is small, which can effectively control the heat dissipation risk. Other configurations and connections are the same as those in the previous embodiments, and will not be described again here.

[0202] Furthermore, the specific placement of chip 1 can be face up or face down, and this application embodiment does not limit the placement.

[0203] For the fabrication of inductor 3, the process described in the foregoing embodiments employs a copper-iron co-firing process for integral molding. In other specific implementations, it can also be fabricated using materials such as magnetic film, magnetic slurry, or magnetic encapsulant. Please refer to Figure 20, which is a schematic diagram of the process flow for another second embedded frame provided in an embodiment of this application.

[0204] Step S2001: Inductor 3 is manufactured by pressing together materials such as three-layer magnetic film, magnetic slurry or magnetic plastic sealant.

[0205] Step S2002: Mount the inductor 3 and press it to fill, thus forming the second embedded frame 12.

[0206] The fabrication of the circuit layer and interconnect layer structure of the second embedded frame 12 is the same as in other embodiments. Further details will not be provided here.

[0207] Furthermore, in possible implementations, the inductor 3 may include, but is not limited to, one, two, or multiple windings. Additionally, the inductor 3 may include horizontal, vertical, or irregularly shaped windings. This application does not limit the scope of the embodiments.

[0208] Please refer to Figure 21, which is a schematic diagram of the structure of seven types of inductor windings provided in the embodiments of this application. In Figure 21, (a) to (e) show horizontal windings, (f) shows irregular windings, and (g) shows vertical windings. Specifically, in Figure 21(a), the terminals 32a at both ends of the inductor 3 extend horizontally; in Figure 21(b), the terminals 32b at both ends of the inductor 3 extend horizontally and are bent into shape to extend vertically; in Figure 21(c), the terminals 32c at both ends of the inductor 3 are bent into shape and pressed into the inside of the magnet, extending vertically; in Figure 21(d), the terminals 32d at both ends of the inductor 3 are bent into shape and pressed into the inside of the magnet, with one end extending vertically and the other end extending downward; in Figure 21(e), the terminals 32e at both ends of the inductor 3 are bent into shape and pressed into the inside of the magnet, with both ends extending vertically.

[0209] For the fabrication of the second embedded frame 12, holes can first be formed in the filling material using laser drilling or mechanical drilling to expose the inductor 3 terminals. Then, a hole plating process can be used to achieve the vertical interconnection between the inductor terminals and the copper traces of the interconnect layer. Different process implementation methods can be selected as needed. Please refer to Figures 22 and 23 together. Figure 22 is a partial interconnection diagram of the terminals on one side of the inductor provided in an embodiment of this application, and Figure 23 is a structural schematic diagram of an inductor terminal provided in an embodiment of this application.

[0210] As shown in Figure 22, the terminals 32 of the inductor 3 are vertically interconnected with the copper traces of the interconnect layer through the interconnect structure 33. As shown in Figure 23, in order to reduce the parasitic resistance of the interconnect path on the side of the inductor terminal 32, the terminals 32 of the inductor are arranged in a sheet shape in the extended plane of the embedded frame to obtain the largest possible copper area of ​​the terminals 32.

[0211] In practical implementation, the interconnection structure 33 between the terminals 32 of the inductor 3 and the copper traces of the interconnection layer can be selected as needed. For example, but not limited to: through-hole (full electroplating or sidewall electroplating + resin plugging), blind slot (full electroplating or sidewall electroplating + resin plugging), and other interconnection structures. Please refer to Figure 24, which shows a schematic diagram of four interconnection structures for inductor terminals.

[0212] When the inductor 3 is relatively thin and the depth of the through-hole or blind trench is small, a fully electroplated through-hole 33a as shown in Figure 24(a) can be used, or a fully electroplated blind trench 33b as shown in Figure 24(b) can also be used. When the inductor 3 is relatively thick and the depth of the through-hole or blind trench is large, a resin-plugged through-hole 33c as shown in Figure 24(c) can be used, or a resin-plugged blind trench 33d as shown in Figure 24(d) can also be used to obtain good process feasibility and reliability.

[0213] It should be noted that the depth of laser drilling or mechanical drilling must ensure that the depth of the through hole or blind slot can effectively connect with the inductor terminal. Specifically, the drilling depth is related to factors such as the overall thickness of the inductor, the thickness of the inductor winding, and the tolerances of the drilling fixture. On the one hand, controlling the drilling depth requires consideration of the tolerance dimensional chain; on the other hand, the reliability of the filling process after drilling also needs to be considered. Preferably, the drilling depth can be controlled so that the depth of the through hole or blind slot is close to that of the inductor terminal.

[0214] The embedded packaging structure described in the foregoing embodiments can be widely applied to the packaging structures of different functional modules. In practical applications, the above-mentioned technical advantages are particularly significant in power module architecture scenarios. Based on the power module provided in the embodiments of this application, and using the typical embedded vertical power supply architecture described above as a comparative example, junction temperature simulation tests were conducted under the same boundary conditions, and the simulation results are shown in Figure 25.

[0215] The thermal pad is located at the top of the power module, and the motherboard (PCB) is located at the bottom. Figure 25(a) is a simulation diagram of the comparative example, and Figure 25(b) is a simulation diagram of the embodiment of this application. Compared with the comparative example architecture, the chip junction temperature of the power module described in this embodiment is reduced by approximately 29.5°C. By applying the relevant heat dissipation measures of this embodiment, the heat dissipation effect can be significantly improved.

[0216] In addition to the aforementioned embedded substrate, this embodiment also provides an electronic device. Please refer to FIG26, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0217] As shown in Figure 26, the electronic device 100 includes a housing 30 and a motherboard 20 and a power module 10 disposed within the housing 30. The power module 10 is electrically connected to the motherboard 20 and is used to supply power to the motherboard and the power devices on the motherboard. In specific implementations, the electronic device can be a server, a computer, or a high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router, or an edge device, etc., and the embodiments of this application are not limited thereto.

[0218] It should be understood that the other main functional components of this electronic device can be implemented using existing technologies, so they will not be described in detail here.

[0219] It should be noted that the directional terms "upper," "lower," "horizontal," "top," "bottom," "end," and "side" used in this document are defined based on the state of the embedded packaging structure shown in the figure. Embedded packaging structures used in actual assembly scenarios are not limited to the state shown in the figure. For example, in use, the motherboard of an electronic device may extend vertically, or the motherboard may extend at an angle to the vertical. It should be understood that the use of the above directional terms does not constitute a substantial limitation on the embedded packaging structure described in this application.

[0220] Furthermore, the ordinal numbers “first,” “second,” and “third,” etc., used herein are only for describing the composition or structure of the same function in the technical solution. It is understood that the use of these ordinal numbers does not constitute a limitation on the understanding of the technical solution for which protection is sought in this application.

[0221] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An embedded packaging structure, characterized in that, The embedded packaging structure includes a first embedded frame, a second embedded frame, and a third embedded frame stacked sequentially, as well as an input capacitor, an inductor, and an output capacitor embedded in the embedded packaging structure. The output capacitor is located in the first embedded frame, the inductor is located in the second embedded frame, the input capacitor is located in the third embedded frame, and the chip interface is provided on the side of the third embedded frame away from the second embedded frame.

2. The embedded packaging structure according to claim 1, characterized in that, It also includes a chip embedding frame, in which a chip is embedded and stacked on the third embedding frame.

3. The embedded packaging structure according to claim 2, characterized in that, The chip is exposed outside the chip embedding frame.

4. The embedded packaging structure according to claim 2 or 3, characterized in that, Signal capacitors are also embedded within the chip embedding frame.

5. The embedded packaging structure according to claim 1, characterized in that, It also includes a chip packaging layer, which includes a chip and is stacked on the third embedded frame.

6. The embedded packaging structure according to claim 5, characterized in that, The chip is a flip chip and is fixed by plastic encapsulation to form the chip packaging layer; or, the chip adopts a square flat leadless package.

7. The embedded packaging structure according to claim 5 or 6, characterized in that, The chip is exposed outside the chip packaging layer.

8. The embedded packaging structure according to any one of claims 5 to 7, characterized in that, The chip packaging layer also includes signal capacitors.

9. The embedded packaging structure according to any one of claims 1 to 8, characterized in that, At least one of the first embedded frame and the third embedded frame has a resistor embedded in it.

10. The embedded packaging structure according to any one of claims 1 to 9, characterized in that, Each embedded frame has a connecting side on its outer peripheral sidewall, which is used to construct a power path or signal line.

11. The embedded packaging structure according to any one of claims 1 to 10, characterized in that, Each embedded frame has a connected sidewall inside, which is used to construct power paths or signal lines.

12. The embedded packaging structure according to any one of claims 1 to 11, characterized in that, The interconnect layers of each embedded frame are interconnected by blind slots or blind vias, or by copper or silver paste, or by solder.

13. The embedded packaging structure according to any one of claims 1 to 12, characterized in that, The embedded elements in the first embedded frame and the third embedded frame are respectively arranged as a single-layer element stack or a multi-layer element stack.

14. The embedded packaging structure according to any one of claims 1 to 13, characterized in that, The terminals of the inductor are connected to the interconnect layer traces of the second embedded frame through an interconnect structure, and the terminals are arranged in a sheet shape.

15. The embedded packaging structure according to claim 14, characterized in that, The interconnect structure is a through hole or a blind groove. The through hole is a fully electroplated through hole or a resin-filled through hole, and the blind groove is a fully electroplated blind groove or a resin-filled groove.

16. A power supply module, characterized in that, It includes a chip, an inductor, an input capacitor, and an output capacitor, wherein the chip, the inductor, the input capacitor, and the output capacitor are packaged using the embedded packaging structure according to any one of claims 1 to 15.

17. An electronic device, characterized in that, It includes a motherboard and a power module, wherein the power module is disposed on the motherboard, and the power module is the power module as described in claim 16.

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