Dual-interface smart card substrate layer and dual-interface smart card

Abstract

A dual-interface smart card substrate layer and a dual-interface smart card. The dual-interface smart card substrate layer comprises: a bearing layer, an antenna winding, and a chip module; the antenna winding and the chip module are both supported by the bearing layer; a strip projection area, a chip module projection area, a magnetic stripe projection area, an embossed projection area, and antenna projection areas are formed on a target surface of the bearing layer; the chip module projection area does not overlap with the strip projection area; the positional area of the chip module projection area is an area not overlapping with the antenna projection areas and the strip projection area in an area defined by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the bearing layer. The mechanical reliability of a chip can be improved and the cost is reduced.

Description

A dual-interface smart card substrate layer, a dual-interface smart card Technical Field

[0001] This invention relates to the field of chip devices, and more specifically, to chip devices comprising contact or contactless communication interfaces. Background Technology

[0002] Dual-interface smart cards are multifunctional cards that combine both contact and contactless communication interfaces. Because they combine the ease of use of contactless IC cards with the security and reliability of contact IC cards, dual-interface smart cards have been widely used in urban public transportation, highway toll collection, e-wallets, financial services, e-commerce and other fields.

[0003] Existing dual-interface smart cards assemble the smart card module, antenna, and card body together through lamination, milling, spot welding, and hot pressing. The functional circuits of the dual-interface module are concentrated in the module packaging position, which causes the chip to be subjected to excessive heat, pressure, and deformation during the card sealing process. At the same time, the mechanical reliability of the chip is insufficient, and the cost is too high. Summary of the Invention

[0004] To address the above problems, this invention proposes a dual-interface smart card substrate layer and a dual-interface smart card. Attached Figure Description

[0005] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 is one of the top view schematic diagrams of the novel dual-interface smart card substrate structure of a specific embodiment of the present invention.

[0007] Figure 1A is one of the schematic diagrams of the strip module installation area structure of the new dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0008] Figure 1B is a schematic diagram of the strip module structure of the new dual-interface smart card according to a specific embodiment of the present invention.

[0009] Figure 1C is a second schematic diagram of the strip module mounting area structure of the new dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0010] Figure 1D is one of the schematic diagrams of the chip module structure of the novel dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0011] Figure 1E is a second schematic diagram of the chip module structure of the novel dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0012] Figure 1F is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 1D.

[0013] Figure 1G is a schematic cross-sectional view of the structure along the AA direction in Figure 1E.

[0014] Figure 2 is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna full-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0015] Figure 2A is a schematic diagram of the preferred positions of the substrate layer chip modules of the new dual-interface smart card in a specific embodiment of the present invention, where antennas 2 / 3 are wound around the corresponding layers.

[0016] Figure 2B is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to different / same layers of the new dual-interface smart card according to a specific embodiment of the present invention, where the antenna 3 / 4 is wound around the corresponding substrate layer chip module.

[0017] Figure 2C is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to the different layers of the antenna full-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0018] Figure 3 is one of the schematic diagrams of the substrate layer structure corresponding to the co-layer antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0019] Figure 3A is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the antenna half-wrap in the same layer of the new dual-interface smart card according to a specific embodiment of the present invention.

[0020] Figure 3B is a schematic diagram of the substrate layer structure corresponding to the co-layer antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0021] Figure 3C is the third schematic diagram of the substrate layer structure corresponding to the co-layer antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0022] Figure 4 is one of the schematic diagrams of the substrate layer structure corresponding to different layers of the antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0023] Figure 4A is one of the preferred positions of the substrate layer chip module corresponding to different layers of the antenna half-wrap in a new dual-interface smart card according to a specific embodiment of the present invention.

[0024] Figure 4B is the second schematic diagram of the substrate layer structure corresponding to different layers of the antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0025] Figure 4C is the second schematic diagram of the preferred positions of the substrate layer chip module corresponding to different layers of the antenna half-wrap in the new dual-interface smart card of the present invention.

[0026] Figure 4D is the third schematic diagram of the substrate layer structure corresponding to different layers of the antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0027] Figure 4E is the fourth schematic diagram of the substrate layer structure corresponding to different layers of the antenna half-wrap of the new dual-interface smart card in a specific embodiment of the present invention.

[0028] Figure 5 is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 1.

[0029] Figure 5A is the second schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0030] Figure 5B is one of the top views of a new dual-interface smart card according to a specific embodiment of the present invention.

[0031] Figure 5C is one of the schematic diagrams of the cross-sectional structure of Figure 5B along the AA direction.

[0032] Figure 5D is the third schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0033] Figure 5E is one of the deformed top views and one of the cross-sectional structural schematic diagrams along the AA direction.

[0034] Figure 5F is one of the two distorted top views, showing a cross-sectional structure along the AA direction.

[0035] Figure 5G is the second schematic diagram of the cross-sectional structure along the AA direction of Figure 5B.

[0036] Figure 5H is the third schematic diagram of the cross-sectional structure of Figure 5B along the AA direction.

[0037] Figure 6 is the fourth schematic diagram of the cross-sectional structure along the AA direction in Figure 1.

[0038] Figure 6A is the fifth of the cross-sectional structural diagrams along the AA direction in Figure 1.

[0039] Figure 6B is the fourth schematic diagram of the cross-sectional structure along the AA direction of Figure 5B.

[0040] Figure 6C is a top view of the new dual-interface smart card according to a specific embodiment of the present invention.

[0041] Figure 6D is a schematic diagram of the cross-sectional structure of Figure 6C along the AA direction.

[0042] Figure 6E is one of the cross-sectional structural diagrams along the AA direction of the third deformed top view of Figure 1.

[0043] Figure 6F is one of the cross-sectional structural diagrams along the AA direction of the fourth deformed top view of Figure 1.

[0044] Figure 6G is one of the sectional structural schematic diagrams along the AA direction of one of the deformed top views of Figure 4.

[0045] Figure 6H is one of the cross-sectional structural diagrams along the AA direction of the second deformed top view of Figure 4.

[0046] Figure 6I is the second of three cross-sectional structural diagrams along the AA direction of the top view of Figure 1, which has been modified.

[0047] Figure 6J is the second cross-sectional structural schematic diagram along the AA direction of the second deformed top view of Figure 1.

[0048] Figure 6K is the fifth schematic diagram of the cross-sectional structure along the AA direction of Figure 5B.

[0049] Figure 7 is a schematic diagram of the substrate layer strip module mounting area corresponding to the new dual-interface smart card of the present invention.

[0050] Figure 8 is one of the schematic diagrams of the cross-sectional structure along the AA direction in Figure 7.

[0051] Figure 8A is the second schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0052] Figure 8B is the third schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0053] Figure 8C is the fourth schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0054] Figure 8D is the fifth of the cross-sectional structural diagrams along the AA direction in Figure 7.

[0055] Figure 8E is the sixth of the cross-sectional structural diagrams along the AA direction in Figure 7.

[0056] Figure 9 is the seventh of the cross-sectional structural diagrams along the AA direction in Figure 7.

[0057] Figure 9A is the eighth schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0058] Figure 9B is the ninth schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0059] Figure 9C is the tenth schematic diagram of the cross-sectional structure along the AA direction in Figure 7.

[0060] Figure 9D is the eleventh of the cross-sectional structural diagrams along the AA direction in Figure 7.

[0061] Figure 9E is a schematic diagram of the cross-sectional structure along the AA direction in Figure 7. Detailed Implementation

[0062] In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. However, those skilled in the art will understand that embodiments of the invention can be practiced without some or all of these specific details. It should be understood that the terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention. In the drawings, the same reference numerals refer to the same or similar functions or features in several figures.

[0063] It should be understood that the terms "comprising," "including," and "having" are intended to be open-ended, meaning that there may be additional elements besides those listed. The use of reference numerals such as first, second, third, and fourth should not be construed as imposing any order of position or time among the multiple definitions. Furthermore, terms such as "top," "bottom," "side," "below," and "vertical" used herein are merely for descriptive convenience and refer to the orientation of the components as shown in the figures. It should be understood that any orientation of the components described herein is within the scope of this invention.

[0064] General Introduction to Separation:

[0065] Existing dual-interface smart cards concentrate the dual-interface module's functional circuitry at the module packaging location. This integration method, where the stripe module and chip are in the same area, exposes the chip to excessive heat, pressure, and deformation during card sealing and use. Furthermore, the chip's mechanical reliability is insufficient, and the cost is too high. To address this issue, this invention proposes a novel dual-interface smart card. The dual-interface smart card includes a substrate layer and a stripe module. The substrate layer includes a carrier layer, a first connection structure, an antenna, and a chip module. The first connection structure, antenna, and chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module.

[0066] The mounting areas of the chip module and the strip module of the dual-interface smart card do not overlap in the orthographic projection area of ​​the target surface of the bearing layer.

[0067] Wherein, the target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer, and the normal plane of the target surface refers to the plane in which the normal of the target surface is located.

[0068] Referring to Figure 1, which is a top view schematic diagram of one specific embodiment of the novel dual-interface smart card substrate layer of the present invention, the substrate layer 100 of this embodiment includes a carrier layer, a strip module mounting area 110, a chip module 120, an antenna 130, and a first connection structure. The first connection structure is a connection lead between the strip module mounting area 110 and the chip module 120, used to realize the electrical connection between the strip module and the chip. The antenna 130 includes an antenna winding (i.e., the coil in the figure) and an antenna lead (i.e., the connection line between the antenna winding and the chip module 120 in the figure). The antenna lead is the connection lead between the antenna and the chip module 120. The antenna and the first connection structure are collectively referred to as a conductive channel. The carrier layer can be a single-layer or multi-layer film structure, and the material can preferably be a flexible film such as PVC, PC, or PET. The carrier layer is used to support other structures of the substrate layer. The target surface of the substrate layer 100 is the surface with the largest area of ​​the substrate layer 100, and the normal plane of the target surface refers to the plane where the normal of the target surface is located. The antenna and the first connection structure can be generated by methods including but not limited to winding or etching. For the winding method, both the first connecting structure and the antenna are enameled conductive wires; for the etching method, both the first connecting structure and the antenna are conductive metal foils. In this embodiment of the invention, the enameled conductive wire is preferably made of copper, and the conductive metal foil is preferably made of aluminum or copper. However, it is worth noting that other suitable materials can also be used for the enameled conductive wire and the conductive metal foil, and this embodiment of the invention does not specifically limit their use.

[0069] The orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrier layer overlap. Specifically, this overlap means that, excluding the portion where the antenna and the first connecting structure are electrically connected to the chip module after the chip module is installed, the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrier layer are a single closed shape (hereinafter referred to as the first connecting structure and antenna being on the same layer). It is worth noting that if the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrier layer overlap, but the first connecting structure and the antenna are located in different layer structures (e.g., different sub-substrate layers), this is not within the scope of the same layer in this embodiment of the invention. It should be further explained that, since the diameter of the enameled conductive wire is much larger than the thickness of the conductive metal foil layer, and the diameter of the enameled conductive wire is comparable to the thickness of the substrate layer structure, for the winding method of the enameled conductive wire, as long as the first connecting structure and the antenna are carried by the same substrate layer structure, the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrying layer can overlap, which is the same layer setting defined in this invention; while for the etching and wiring method of the conductive metal foil, to satisfy the overlap of the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrying layer, the first connecting structure and the antenna must be located on the same plane.

[0070] The orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrier layer do not overlap. Specifically, this non-overlap means that, excluding the portion where the antenna and the first connecting structure are electrically connected to the chip module after the chip module is installed, the orthographic projection areas of the first connecting structure and the antenna on the normal plane of the target surface of the carrier layer are not a single closed shape (hereinafter referred to as the first connecting structure and antenna being on different layers). Even if they are a single closed shape, if the first connecting structure and the antenna are located in different layer structures (e.g., on different sub-substrate layers), this also constitutes a non-overlapping situation (hereinafter referred to as the first connecting structure and antenna being on different layers).

[0071] The strip module of this invention includes contact pads, a support layer, and conductive pads. The contact pads and conductive pads are located on both sides of the support layer. The contact pads include effective contacts conforming to the ISO7816 protocol. Referring to Figure 1A, which is one schematic diagram of the strip module mounting area structure of a novel dual-interface smart card substrate layer according to a specific embodiment of this invention, corresponding to the winding method, Figure 1B is a schematic diagram of the strip module structure of a novel dual-interface smart card according to a specific embodiment of this invention. As an example, only the 8-pin module scheme is shown in the figures; the same applies to the 6-pin module scheme, which will not be detailed here. As shown in Figure 1A, the strip module mounting area includes five closely wound first connection structure terminals (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each closely wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. As shown in Figure 1B, the strip module has conductive pads on the surface corresponding to the effective contacts, and the conductive pads are electrically connected to the corresponding effective contacts. The tightly wound first connection structure terminal can be electrically connected to the corresponding conductive pad of the strip module via conductive adhesive, thereby achieving an effective contact connection with the strip module. Preferably, the conductive pad is inclined, which increases the contact area with the tightly wound first connection structure terminal and improves the reliability of the electrical connection. It is worth noting that the conductive pad is actually a three-dimensional structure, and its height can be adjusted according to design requirements. The conductive pad can be made of metal materials such as copper or aluminum.

[0072] Referring to Figure 1C, which is the second schematic diagram of the strip module mounting area structure of the new dual-interface smart card substrate layer according to a specific embodiment of the present invention, corresponding to the etching method. As shown in Figure 1C, the strip module mounting area includes five first connection structure terminals in the form of etched pads (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each first connection structure terminal in the form of etched pads matches the projection area corresponding to the effective contact after the strip module is installed. The strip module still adopts the structure shown in Figure 1B. Each first connection structure terminal in the form of etched pads can be electrically connected to the corresponding conductive pad of the strip module by conductive glue or solder ball soldering, thereby realizing the electrical connection with the effective contact of the strip module.

[0073] Based on the above, the chip module 120 is mounted on the substrate layer using methods including but not limited to COB (chip on board) packaging and WLCSP (Wafer Level Chip Scale Packaging). Figure 1D is one of the structural schematic diagrams of the chip module 120 when using COB packaging, and Figure 1E is one of the structural schematic diagrams of the chip module 120 when using WLCSP packaging.

[0074] Referring to Figure 1D, the COB-packaged chip module 120 includes a substrate and a chip. The target surface of the substrate is used to mount the chip, and this target surface is one of the largest surfaces of the substrate. Preferably, the chip is mounted at the center of the target surface of the substrate, i.e., the line connecting the center point of the chip and the center point of the substrate is perpendicular to the target surface of the substrate. The target surface of the substrate also has multiple chip module contact pad groups to achieve electrical connection between the chip and the antenna and the first connection structure. Based on this, electrical connection between the chip and the strip module and the antenna can be achieved, thereby realizing contact communication and contactless communication of the dual-interface smart card. It is worth noting that, to ensure the basic contact and contactless functions of the smart card, the number of chip module contact pad groups includes at least 7 groups: 2 groups are used to achieve electrical connection between the two free ends of the chip and the antenna, and 5 groups are used to achieve electrical connection between the chip and the effective contact points of the strip module. The number of chip module contact pad groups in Figure 1D can be adjusted according to actual application needs; the number of chip module contact pad groups in Figure 1D is only an example. It is worth noting that each chip module contact pad group includes one chip contact pad and one conductive channel contact pad. The chip contact pad and the conductive channel contact pad can be integrally formed or are two independent contact pads electrically connected by wires or other conductive structures. The chip contact pad and the conductive channel contact pad are made of the same conductive material and can be manufactured using the same process. Refer to Figure 1F, which is one of the cross-sectional structural diagrams along the AA direction in Figure 1D. As shown in Figure 1F, the chip contact pad is used to connect chip pins via chip connection lines. After the connection is completed, the chip, chip connection lines, and chip contact pad are encapsulated with encapsulating adhesive, which can be applied using processes such as epoxy resin dispensing. The conductive channel contact pad is used to connect to the first connection structure terminal (i.e., the chip-side first connection structure terminal used to connect the chip module) or the antenna terminal (i.e., the terminal of the antenna lead). Based on the aforementioned embodiments, it is known that the other terminal of the first connection structure is electrically connected to the corresponding contact of the strip module. Therefore, through the chip module contact pad assembly of this embodiment, the electrical connection between the chip and the antenna and strip module can be achieved.

[0075] Preferably, the plurality of chip module contact pads are evenly distributed around the chip. This shortens the length of the chip connection lines and optimizes the first connection structure and antenna arrangement. Of course, depending on the actual application requirements, the plurality of chip module contact pads can also adopt other layouts, such as being arranged side by side on one side of the chip, or having the chip module contact pads connected to the antenna and the chip module contact pads connected to the strip module arranged separately. This embodiment of the invention does not specifically limit these arrangements.

[0076] Optionally, the chip can also be flip-chip mounted on the target surface of the substrate. When flip-chip mounted, the chip pins can be directly electrically connected to the chip contact pads on the substrate via solder balls. Based on this, compared to the method shown in Figure 1F, the embodiments of the present invention can achieve the electrical connection between the chip pins and the chip contact pads without setting chip connection lines.

[0077] It is worth noting that when the chip module 120 is installed, the terminals of the antenna and the first connection structure overlap with the matching conductive channel contact pads on the chip module in the projection direction. Based on this, in this embodiment of the invention, the terminals of the antenna and the first connection structure can be soldered to the matching conductive channel contact pads or bonded with conductive adhesive, thereby achieving electrical connection between the antenna and the first connection structure and the chip and strip module. Specifically, the soldering method can be spot welding or other methods, and this embodiment of the invention does not specifically limit this. The substrate can be a flexible PCB board or epoxy glass cloth, or a composite bearing material, such as a metal base plate supporting PVC or PE materials. Based on this, it can provide higher stress strength than PVC materials, ensuring the reliability of the chip installation and use process, while reducing costs.

[0078] Referring to Figure 1E, the WLCSP-packaged chip module 120 consists only of a chip and solder balls. The chip pins can be electrically connected to an external module via the solder balls. It is understood that the number and position of the solder balls in Figure 1E can be adjusted as needed in practical applications, and this embodiment of the invention does not impose specific limitations on this. Referring to Figure 1G, it is a schematic cross-sectional view along direction AA in Figure 1E. The WLCSP package size is only about 0%-20% larger than the bare chip size, and its thickness is relatively thin. This method can minimize the chip module's footprint while meeting the manufacturing process requirements of dual-interface smart cards. The solder ball array of the WLCSP-packaged chip is electrically connected to the antenna and the terminals (conductive metal foil etched wiring) of the first connection structure designed in the substrate layer through soldering or other conductive connection methods. Precise soldering processes, such as reflow soldering or ultrasonic soldering, are used to ensure the reliability and conductivity of the connection. The WLCSP package allows the chip module 120 to be embedded in the substrate layer with minimal footprint while maintaining excellent electrical performance and mechanical stability. Through precise positioning and reliable electrical connections, the WLCSP package ensures the overall performance of dual-interface smart cards while extending the chip's lifespan, meeting the dual requirements of high performance and high reliability for modern dual-interface smart cards.

[0079] Preferably, for the wire-wound method, the chip module 120 is packaged using COB packaging; for the etching wiring method, the chip module 120 can be packaged using either COB packaging or WLCSP packaging.

[0080] Based on the aforementioned substrate layer structure, this embodiment of the invention maximizes chip lifespan while ensuring the mechanical and electrical performance of the dual-interface smart card by optimizing the chip module's location. Specifically, this embodiment of the invention generates multiple corresponding constraints to determine the optimal location of the chip module based on a comprehensive consideration of mechanical performance, electrical performance, and chip lifespan.

[0081] Constraint diagram: Positional distribution of the strip module mounting area and the chip module

[0082] 1. First constraint figure

[0083] The first constraint diagram refers to the substrate layer antenna winding size method corresponding to the new dual-interface smart card in the specific implementation of the present invention, which is full winding, 2 / 3 winding, or 3 / 4 winding.

[0084] Referring to Figure 2, which is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna full-wrap of the new dual-interface smart card according to a specific embodiment of the present invention; referring to Figure 2A, which is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna 2 / 3 wrap of the new dual-interface smart card according to a specific embodiment of the present invention; and referring to Figure 2B, which is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna 3 / 4 wrap of the new dual-interface smart card according to a specific embodiment of the present invention. In conjunction with Figures 2-2B, to facilitate the description of the planar positional relationships in the process of determining the preferred positions of the chip modules, this embodiment of the present invention is based on the orthographic projection areas formed on the target surface of the substrate layer 100 by the strip module mounting area 110, the chip module 120, and the antenna 130, i.e., the strip projection area, the chip module projection area, and the antenna projection area. It can be understood that the orthographic projection area is the area obtained by projecting along the normal direction of the target surface of the substrate layer 100. It is worth noting that the antenna projection area refers to the orthographic projection area corresponding to the antenna winding, i.e., excluding the orthographic projection area corresponding to the antenna leads. Based on this, the specific process for determining the preferred location of the projection area of ​​the substrate layer chip module is as follows:

[0085] The determination of the preferred location of the chip module projection area includes strong constraint regions and weak constraint regions generated based on strong and weak constraint conditions. Optionally, the strong constraint regions may include, but are not limited to, magnetic stripe projection regions, embossed projection regions, and antenna projection regions. The magnetic stripe projection region is the orthographic projection region of the carrier layer corresponding to the smart card magnetic stripe mounting area, and the embossed projection region is the orthographic projection region of the carrier layer corresponding to the smart card embossing area. The weak constraint regions may include, but are not limited to, imprinting projection regions, resistance projection regions, and the central axis. The imprinting projection region is the area enclosed by the straight line containing the long side of the stripe projection region and the left and right edges of the target surface of the carrier layer. The resistance projection region is the target half-region where the stripe mounting area is located, among the two half-regions divided by the vertical central axis of the target surface of the carrier layer. Strong constraint regions are areas where the chip module projection area cannot be located or set, while weak constraint regions are areas where the chip module projection area preferably cannot be located or set. If the chip module projection area is set in a weak constraint region, the limitations of the weak constraint conditions need to be overcome by strengthening the chip module. The strong constraints of this invention embodiment are as follows: Considering the risk of chip damage during the installation of the magnetic stripe and the fabrication of the embossed printing during the dual-interface smart card manufacturing process, this invention embodiment generates a first strong constraint: the chip module projection area avoids the magnetic stripe projection area and the embossed printing projection area. Based on this, damage to the chip during the magnetic stripe and embossed printing processes can be avoided. Furthermore, this invention embodiment further considers the impact of chip placement on antenna performance. If the chip module projection area coincides with the antenna, the installation of the chip module 120 will affect antenna performance or even cause antenna damage. Based on this, this invention embodiment generates a second strong constraint: the chip module projection area avoids the antenna projection area. Based on this, the installation of the chip module 120 can be avoided from affecting antenna performance or damaging the antenna.

[0086] The weak constraints of this embodiment are as follows: Since the strip module requires a new dual-interface smart card imprinting test after installation, this test uses a three-wheel imprinting method. The three imprinting rollers move along the imprinting projection area shown in Figures 2-2B. If the chip is located in the imprinting projection area, it will be squeezed by the three imprinting rollers and will also face the risk of damage. Based on this, this embodiment generates a first weak constraint: the chip module projection area avoids the imprinting projection area. Therefore, damage to the chip can be avoided during the imprinting test after the strip module is installed. Furthermore, this embodiment considers that a torsion test will be performed after the dual-interface smart card is manufactured. During the torsion test, the torque is greatest on the central axis of the dual-interface smart card, as shown in Figures 2-2B, including the vertical and horizontal central axes. If the chip is located on the central axis of the dual-interface smart card, it will also face a significant risk of damage. Based on this, this embodiment generates a second weak constraint: the chip module projection area avoids the central axis. Therefore, damage to the chip can be avoided during the torsion test. Building upon the above, this invention further discovers through research that during the use of a dual-interface smart card, the chip is subjected to continuous compression after entering the card slot, increasing the resistance to card insertion and removal. Prolonged compression also affects the chip's lifespan. Positioning the chip module on the right side of the vertical central axis, compared to placing the chip on the left side (i.e., the resistance projection area shown in Figures 2-2B), significantly shortens the compression stroke, reducing insertion resistance and extending chip lifespan. Based on this, this invention further adds a third weak constraint: the chip module projection area avoids the left side of the vertical central axis (i.e., the resistance projection area). This reduces insertion resistance and maximizes chip lifespan while ensuring the electrical performance of the dual-interface smart card.

[0087] Based on the above five constraint conditions (the first strong constraint condition, the second strong constraint condition, the first weak constraint condition, the second weak constraint condition, and the third weak constraint condition), the embodiments of the present invention can determine the preferred position area of the chip module projection area, that is, the area that does not overlap with the antenna projection area, the imprint projection area, and the resistance projection area in the area formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer (the same applies to subsequent embodiments). To facilitate the characterization of the preferred position area, the embodiments of the present invention establish a plane rectangular coordinate system with the center point of the strip projection area as the origin (i.e., A0 in FIG. 2). The preferred position area of the chip module is the area 1 formed by A1(D1, H1), A2(D2, H1), A3(D1, H2), A4(D2, H2) and the area 2 formed by B1(D1, -H1), B2(D2, -H1), B3(D1, -H3), B4(D2, -H3). Where D1 is the vertical distance from the center point of the strip projection area to the vertical central axis, D2 is the vertical distance from the center point of the strip projection area to the rightmost inner loop antenna projection, H1 is the vertical distance from the center point of the strip projection area to the upper edge of the strip projection area, H2 is the vertical distance from the center point of the strip projection area to the lower edge of the magnetic stripe projection area, and H3 is the vertical distance from the center point of the strip projection area to the upper edge of the embossed projection area.

[0088] Optionally, the shape of the chip module 120 is preferably a rectangle, composed of four corner points C1(X1, Y1), C2(X2, Y2), C3(X3, Y3), C4(X4, Y4), and is completely located within area 1 or area 2. It is necessary to ensure that all four corner points satisfy the constraint conditions of this area. Based on this, the logical expression for the preferred position of the chip module 120 is:

[0089] [(D1 < X1 < D2) and (H1 < Y1 < H2)] and [(D1 < X2 < D2) and (H1 < Y2 < H2)] and [(D1 < X3 < D2) and (H1 < Y3 < H2)] and [(D1 < X4 < D2) and (H1 < Y4 < H2)] (representing that the chip module projection area is located within area 1), or, [(D1 < X1 < D2) and (-H3 < Y1 < -H1)] and [(D1 < X2 < D2) and (-H3 < Y2 < -H1)] and [(D1 < X3 < D2) and (-H3 < Y3 < -H1)] and [(D1 < X4 < D2) and (-H3 < Y4 < -H1)] (representing that the chip module projection area is located within area 2).

[0090] It is worth noting that the above five constraint schemes are the optimal implementation of this invention. In practical applications, only the first and second strong constraints can be considered, or only some weak constraints can be considered based on the first and second strong constraints. That is, the chip module projection area can also be located in at least one of the resistance projection area and the imprinting projection area, and can overlap with the central axis. However, when the chip module projection area is set in the resistance projection area, the imprinting projection area, and the central axis, a corresponding protective structure needs to be provided for the chip module 120 to avoid damage to the chip due to pressure. The drag projection area is region 3 formed by A3(D1, H2), A5(-D3, H2), B5(-D3, -H3), and B3(D1, -H3) in Figures 2-2B, where D3 is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna. The imprint projection area is region 4 formed by A2(D2, H1), B2(D2, -H1), B6(-D3, -H1), and A6(-D3, H1) in Figures 2-2B. The central axis is line segment 5 formed by A3(D1, H2) and B3(D1, -H3) and line segment 6 formed by B2(D2, -H1) and B6(-D3, -H1) in Figures 2-2B.

[0091] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module projection area also includes the resistance projection area, the embossing projection area, and the central axis. That is, the preferred location area of ​​the chip module projection area is the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossing projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the strip projection area. Specifically, these are the aforementioned areas 1, 2, 3, and 4, and the chip module projection area can overlap with the central axis.

[0092] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection region also includes the portion of the resistance projection region and the central axis that does not overlap with the imprinted projection region. Specifically, the preferred location area of ​​the chip module projection region is the region formed by the lower edge of the magnetic stripe projection region, the upper edge of the embossed projection region, and the left and right edges of the support layer, that does not overlap with the antenna projection region and the imprinted projection region. Specifically, this refers to the portion of regions 1, 2, and 3 that does not overlap with region 4, and the chip module projection region can overlap with the central axis.

[0093] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection region also includes the portions of the resistance projection region and the embossing projection region that do not overlap with the central axis. Specifically, the preferred location area of ​​the chip module projection region is the region formed by the lower edge of the magnetic stripe projection region, the upper edge of the embossing projection region, and the left and right edges of the carrier layer, which does not overlap with the antenna projection region and the stripe projection region. Specifically, this refers to regions 1, 2, 3, and 4 mentioned above, and the chip module projection region does not overlap with the central axis.

[0094] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion of the central axis and the imprinted projection area that does not overlap with the resistance projection area. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, that does not overlap with the antenna projection area and the resistance projection area. Specifically, this refers to the portion of regions 1, 2, and 4 that does not overlap with region 3, and the chip module projection area can overlap with the central axis.

[0095] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location of the chip module projection area also includes the portion of the resistance projection area that does not overlap with the central axis and the imprinted projection area. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, that does not overlap with the antenna projection area and the imprinted projection area. Specifically, this refers to the portion of regions 1, 2, and 3 that does not overlap with region 4, and the chip module projection area does not overlap with the central axis.

[0096] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion along the central axis that does not overlap with the drag projection area and the embossing projection area. Specifically, the preferred built-in area of ​​the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the support layer, which does not overlap with the antenna projection area, the embossed projection area, and the drag projection area. Specifically, this refers to the aforementioned areas 1 and 2, and the chip module projection area can overlap with the central axis.

[0097] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the portion of the imprint projection area that does not overlap with the resistance projection area and the central axis. Specifically, the preferred location of the chip module projection area is the region formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the resistance projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer. Specifically, this refers to the portion of regions 1, 2, and 4 that does not overlap with region 3, and the chip module projection area does not overlap with the central axis.

[0098] Referring to Figure 2C, this is a schematic diagram illustrating the preferred positions of the substrate layer chip module corresponding to different layers of the novel dual-interface smart card with fully wound antenna, according to a specific embodiment of the present invention. As shown in Figure 2C, when the antenna and the first connection structure are set on different layers, this embodiment of the present invention, while ensuring the preferred position of the chip module projection area, allows the antenna projection area to overlap with the stripe projection area without affecting the normal use of the antenna and stripe module. Furthermore, the methods for determining the preferred positions of the chip module projection areas corresponding to fully wound, 3 / 4 wound, and 2 / 3 wound antennas are all applicable to the corresponding determination methods in the case of wire winding.

[0099] 2. Second constraint graph

[0100] The second constraint diagram is the substrate layer antenna winding size method corresponding to the new dual-interface smart card of the present invention, which is half-winding.

[0101] Referring to Figure 3, this is one of the schematic diagrams of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-wrap in a specific embodiment of the present invention. Due to the large diameter of the winding wire, when the antenna is set in the same layer as the first connection structure, the antenna cannot pass under the strip module mounting area; otherwise, the thickness of the dual-interface smart card will be insufficient or its reliability will be reduced. Based on this, referring to Figure 3A, this is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the new dual-interface smart card winding-same-layer-antenna half-wrap in a specific embodiment of the present invention. Specifically, the process for determining the preferred position of the chip module projection area is as follows:

[0102] Considering that the installation of the magnetic stripe and the embossing process during the manufacturing of dual-interface smart cards still pose a risk of chip damage, the aforementioned first strong constraint condition is retained; considering the impact of chip settings on antenna performance, the aforementioned second strong constraint condition is retained; considering that the squeezing of the three-roll embossing rollers still poses a risk of chip damage, the aforementioned first weak constraint condition is retained; considering that the torsion test process poses a significant risk of chip damage, the aforementioned second weak constraint condition is retained; considering that during the use of dual-interface smart cards, the chip will still be subjected to continuous squeezing after entering the card slot, which will increase the resistance to card insertion and removal, the aforementioned third weak constraint condition is retained.

[0103] Based on the above five constraints, the preferred position area of the chip module projection area can be determined in the embodiments of the present invention. It should be noted that since the space of the upper edge area and the lower edge area of the dual-interface smart card is too small, the installation of the chip module cannot be realized. Therefore, the preferred position area of the chip module projection area is Area 1 formed by A1(D1, H1), A2(D2, H1), A3(D1, H2), A4(D2, H2), and Area 2 formed by B1(D1, -H1), B2(D3, -H1), B3(D1, -H3), B4(D3, -H3). Where D1 is the vertical distance from the center point of the strip projection area to the vertical central axis, D2 is the vertical distance from the center point of the strip projection area to the projection of the innermost right antenna, D3 is the vertical distance from the center point of the strip projection area to the right edge of the card, H1 is the vertical distance from the center point of the strip projection area to the upper edge of the strip projection area, H2 is the vertical distance from the center point of the strip projection area to the lower edge of the magnetic stripe projection area, and H3 is the vertical distance from the center point of the strip projection area to the upper edge of the embossed projection area.

[0104] Similarly to the foregoing embodiments, the shape of the chip module 120 is preferably a rectangle, composed of four corner points C1(X1, Y1), C2(X2, Y2), C3(X3, Y3), C4(X4, Y4), and is completely located within Area 1 or Area 2, and it is necessary to ensure that all four corner points satisfy the constraints of this area. Based on this, the logical expression for the preferred position of the chip module 120 is:

[0105] [(D1 < X1 < D2) and (H1 < Y1 < H2)] and [(D1 < X2 < D2) and (H1 < Y2 < H2)] and [(D1 < X3 < D2) and (H1 < Y3 < H2)] and [(D1 < X4 < D2) and (H1 < Y4 < H2)] (indicating that the chip module projection area is located within Area 1), or, [(D1 < X1 < D3) and (-H3 < Y1 < -H1)] and [(D1 < X2 < D3) and (-H3 < Y2 < -H1)] and [(D1 < X3 < D3) and (-H3 < Y3 < -H1)] and [(D1 < X4 < D3) and (-H3 < Y4 < -H1)] (indicating that the chip module projection area is located within Area 2).

[0106] It is worth noting that the above five constraint schemes are the optimal implementation of this invention. In practical applications, only the first and second strong constraint conditions can be considered, or only some weak constraint conditions can be considered based on the first and second strong constraint conditions. That is, the chip module projection area can also be located in at least one of the resistance projection area and the imprinting projection area, and can overlap with the central axis. However, when the chip module projection area is set in the resistance projection area, the imprinting projection area, and the central axis, a corresponding protective structure needs to be provided for the chip module 120 to avoid damage to the chip module due to pressure. Among them, considering that the antenna projection area partially overlaps with the resistance projection area and the imprinting projection area, the resistance projection area, the imprinting projection area, and the central axis described below are all usable resistance projection area, imprinting projection area, and central axis after removing the influence of the antenna projection area. Specifically, the drag projection area is region 3 formed by A3(D1, H2), A5(D4, H2), A6(D4, -H4), and A7(D1, -H4) in Figure 3A, and region 4 formed by B1(D1, -H1), B3(D1, -H3), B5(-D5, -H3), and B6(-D5, -H1). Here, D4 ​​is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna; D5 is the vertical distance from the center point of the strip projection area to the left edge of the card; and H4 is the vertical distance from the center point of the strip projection area to the projection of the straight line segment of the lower innermost antenna. The imprint projection area is region 5 formed by A6(D4, -H4), A9(D6, -H4), A10(D6, H1), and A8(D4, H1) in Figure 3A. Here, D6 is the lateral distance from the center point of the strip projection area to the right end point of the projection of the straight line segment of the lower innermost antenna. The central axis is line segment 6 formed by A3(D1, H2) and A7(D1, -H4) in Figure 3A, line segment 7 formed by B1(D1, -H1) and B3(D1, -H3), and line segment 8 formed by B2(D3, -H1) and B6(-D5, -H1). It is worth noting that the chip module 120 preferably avoids overlapping with the stripe projection area 110 to prevent excessive compression of the chip during use of the dual-interface smart card. Therefore, the area enclosed by the left antenna and the left edge of the card cannot be used to install the chip module.

[0107] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module also includes the resistance projection area, the imprint projection area, and the central axis. That is, the preferred location area of ​​the chip module is: area 1-5, which can overlap with the central axis.

[0108] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection area also includes the resistance projection area and the part of the central axis that does not overlap with the imprint projection area. That is, the preferred location area of ​​the chip module is: area 1-area 4, and it can overlap with the central axis.

[0109] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the parts of the resistance projection area and the imprinting projection area that do not overlap with the central axis. That is, the preferred location area of ​​the chip module is: area 1-area 5, which do not overlap with the central axis.

[0110] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the central axis and the imprint projection area that does not overlap with the resistance projection area. That is, the preferred location areas of the chip module are: area 1-2 and area 5, and can overlap with the central axis.

[0111] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the resistance projection area that does not overlap with the central axis and the imprint projection area. That is, the preferred location area of ​​the chip module is the part of region 1-3 and region 4 that does not overlap with region 5 and does not overlap with the central axis.

[0112] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection region also includes the part of the central axis that does not overlap with the resistance projection region and the imprint projection region. That is, the preferred location area of ​​the chip module is: region 1-2, which can overlap with the central axis.

[0113] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the imprint projection area that does not overlap with the resistance projection area and the central axis, that is, the part of region 1-2 and region 5 that does not overlap with region 3-4 and does not overlap with the central axis.

[0114] Referring to Figure 3B, this is the second schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Referring to Figure 3C, this is the third schematic diagram of the substrate layer structure corresponding to the new dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Referring to Figure 3B, when the chip module is located in area A (i.e., the area formed by A1, A2, A3, and A4 in Figure 3A), the first connection structure needs to connect to the chip module by crossing the antenna winding. Preferably, the crossing position is located in the antenna bend area to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card. Referring to Figure 3C, when the chip module is located in area B (i.e., the area formed by B1, B2, B3, and B4 in Figure 3A), the first connection structure can connect to the chip module without crossing the antenna winding, but some antenna leads will cross the antenna winding to achieve the connection between the antenna terminal and the chip module. When the first connecting structure does not cross the antenna winding and is located outside the antenna winding area, it should also not be placed in the embossed area to avoid damage from subsequent card manufacturing embossing. Of course, in special designs, such as conductive metal foil etching schemes, the damage from embossing can be overcome by widening the first connecting structure, and the first connecting structure can be placed in the embossed area. This solution is a mature technology and will not be described in detail in this invention.

[0115] Referring to Figure 4, one of the schematic diagrams of the substrate layer structure corresponding to the antenna half-wrap of different layers in a new dual-interface smart card according to a specific embodiment of the present invention corresponds to the case where the strip module is positioned close to the first connection structure. In this case, since the antenna and the first connection structure are on different layers, the antenna does not need to avoid the strip module; that is, the antenna projection area and the strip projection area can overlap. Based on this, referring to Figure 4A, one of the schematic diagrams of the preferred position of the substrate layer chip module corresponding to the antenna half-wrap of different layers in a new dual-interface smart card according to a specific embodiment of the present invention is shown. Considering subsequent product requirements, the antenna can avoid the strip module; that is, the antenna projection area and the strip projection area do not overlap. Based on this, referring to Figure 4B, another schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in a new dual-interface smart card according to a specific embodiment of the present invention is shown, corresponding to the case where the strip module is positioned close to the antenna. Correspondingly, referring to Figure 4C, another schematic diagram of the preferred position of the substrate layer chip module corresponding to the antenna half-wrap of different layers in a new dual-interface smart card according to a specific embodiment of the present invention is shown. It is worth noting that although Figure 4 and Figure 4B correspond to the cases where the antenna does not avoid the strip module and the cases where it does avoid the strip module, respectively, the method for determining the preferred position of the chip module is the same, that is, the corresponding constraints are the same. The only difference is that the area corresponding to the constraints is different.

[0116] Specifically, the process for determining the preferred location of the chip module projection area is as follows:

[0117] Considering that the installation of the magnetic stripe and the embossing process during the manufacturing of dual-interface smart cards still pose a risk of chip damage, the aforementioned first strong constraint condition is retained; considering the impact of chip settings on antenna performance, the aforementioned second strong constraint condition is retained; considering that the squeezing of the three-roll embossing rollers still poses a risk of chip damage, the aforementioned first weak constraint condition is retained; considering that the torsion test process poses a significant risk of chip damage, the aforementioned second weak constraint condition is retained; considering that during the use of dual-interface smart cards, the chip will still be subjected to continuous squeezing after entering the card slot, which will increase the resistance to card insertion and removal, the aforementioned third weak constraint condition is retained.

[0118] Based on the above five constraints, the preferred location area for the chip module projection region can be determined in the embodiments of the present invention. It is worth noting that the upper and lower edge areas of the dual-interface smart card are too small to accommodate the chip module installation. Therefore, under the condition that the above five constraints are simultaneously satisfied, for the situations shown in Figures 4A and 4C, the preferred location area for the chip module projection region is region 1 formed by A1(D1, H1), A2(D2, H1), A3(D1, H2), and A4(D2, H2), and region 2 formed by B1(D1, -H1), B2(D3, -H1), B3(D1, -H3), and B4(D3, -H3). Wherein, D1 is the vertical distance from the center point of the strip projection area to the vertical central axis, D2 is the vertical distance from the center point of the strip projection area to the projection of the innermost right antenna, D3 is the vertical distance from the center point of the strip projection area to the right edge of the card, H1 is the vertical distance from the center point of the strip projection area to the upper edge of the strip projection area, H2 is the vertical distance from the center point of the strip projection area to the lower edge of the magnetic strip projection area, and H3 is the vertical distance from the center point of the strip projection area to the upper edge of the embossed projection area.

[0119] Similarly to the aforementioned embodiments, the chip module 120 is preferably rectangular in shape, consisting of four corner points C1(X1,Y1), C2(X2,Y2), C3(X3,Y3), and C4(X4,Y4), completely located within region 1 or region 2. It is necessary to ensure that all four corner points satisfy the constraints of that region. Based on this, the logical expression for the preferred position of the chip module's projection area is:

[0120] [(D1 < X1 < D2) and (H1 < Y1 < H2)] and [(D1 < X2 < D2) and (H1 < Y2 < H2)] and [(D1 < X3 < D2) and (H1 < Y3 < H2)] and [(D1 < X4 < D2) and (H1 < Y4 < H2)] (indicating that the projection area of the chip module is located within area 1), or, [(D1 < X1 < D3) and (-H3 < Y1 < -H1)] and [(D1 < X2 < D3) and (-H3 < Y2 < -H1)] and [(D1 < X3 < D3) and (-H3 < Y3 < -H1)] and [(D1 < X4 < D3) and (-H3 < Y4 < -H1)] (indicating that the projection area of the chip module is located within area 2).

[0121] It should be noted that the solutions of the above five constraint conditions are the optimal implementation manners of the embodiments of the present invention. In the actual application process, only the first strong constraint condition and the second strong constraint condition can be considered, or on the basis of considering the first strong constraint condition and the second strong constraint condition, only some weak constraint conditions can be considered. That is, the projection area of the chip module can also be located in at least one of the resistance projection area and the imprint projection area, and can overlap with the central axis. However, when the projection area of the chip module is set in the resistance projection area, the imprint projection area and the central axis, a corresponding protection structure needs to be set for the chip module 120 to avoid damage to the chip module due to pressure. Among them, considering that there is partial overlap between the antenna projection area and the resistance projection area and the imprint projection area, therefore, the resistance projection area, the imprint projection area and the central axis described below are the available resistance projection area, the imprint projection area and the central axis excluding the influence of the antenna projection area.

[0122] Specifically, for the situation shown in Figure 4A, the drag projection area is region 3 formed by A3(D1, H2), A5(D4, H2), A8(D4, H1), and A1(D1, H1) in Figure 4A, region 4 formed by B1(D1, -H1), B3(D1, -H3), B5(-D5, -H3), and B6(-D5, -H1), and region 5 formed by A1(D1, H1), A11(D7, H1), A6(D7, -H4), and A7(D1, -H4). Here, D4 ​​is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna, D5 is the vertical distance from the center point of the strip projection area to the left edge of the card, D7 is the vertical distance from the center point of the strip projection area to the right edge of the strip, and H4 is the vertical distance from the center point of the strip projection area to the projection of the straight line segment of the lower innermost antenna. The imprinted projection area is region 6 in Figure 3C, consisting of A6(D7, -H4), A9(D6, -H4), A10(D6, H1), and A11(D7, H1). Here, D6 is the lateral distance from the center point of the strip projection area to the right endpoint of the projection of the innermost straight segment of the lower antenna. The central axis is line segment 7 (consisting of A3(D1, H2) and A7(D1, -H4), line segment 8 (consisting of B1(D1, -H1) and B3(D1, -H3), and line segment 9 (consisting of B2(D3, -H1) and B6(-D5, -H1)) in Figure 3C.

[0123] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module also includes the resistance projection area, the imprint projection area, and the central axis. That is, the preferred location area of ​​the chip module is: area 1-5, which can overlap with the central axis.

[0124] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection area also includes the resistance projection area and the part of the central axis that does not overlap with the imprint projection area. That is, the preferred location area of ​​the chip module is: area 1-area 4, and it can overlap with the central axis.

[0125] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the parts of the resistance projection area and the imprinting projection area that do not overlap with the central axis. That is, the preferred location area of ​​the chip module is: area 1-area 5, which do not overlap with the central axis.

[0126] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the central axis and the imprint projection area that does not overlap with the resistance projection area. That is, the preferred location areas of the chip module are: area 1-2 and area 5, and can overlap with the central axis.

[0127] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the resistance projection area that does not overlap with the central axis and the imprint projection area. That is, the preferred location area of ​​the chip module is the part of region 1-3 and region 4 that does not overlap with region 5 and does not overlap with the central axis.

[0128] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection region also includes the part of the central axis that does not overlap with the resistance projection region and the imprint projection region. That is, the preferred location area of ​​the chip module is: region 1-2, which can overlap with the central axis.

[0129] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the imprint projection area that does not overlap with the resistance projection area and the central axis, that is, the part of region 1-2 and region 5 that does not overlap with region 3-4 and does not overlap with the central axis.

[0130] For the situation shown in Figure 4C, the drag projection area is region 3 formed by A3(D1, H2), A5(D4, H2), A6(D4, -H4), and A7(D1, -H4) in Figure 4C, and region 4 formed by B1(D1, -H1), B3(D1, -H3), B5(-D5, -H3), and B6(-D5, -H1). Here, D4 ​​is the vertical distance from the center point of the strip projection area to the projection of the innermost left-side antenna, D5 is the vertical distance from the center point of the strip projection area to the left edge of the card, and H4 is the vertical distance from the center point of the strip projection area to the projection of the straight line segment of the lower innermost antenna. The imprinted projection area is region 5 in Figure 3A, consisting of A6(D4, -H4), A9(D6, -H4), A10(D6, H1), and A8(D4, H1). Here, D6 is the lateral distance from the center point of the strip projection area to the right endpoint of the projection of the innermost straight line segment of the lowermost antenna. The central axis is line segment 6 formed by A3(D1, H2) and A7(D1, -H4), line segment 7 formed by B1(D1, -H1) and B3(D1, -H3), and line segment 8 formed by B2(D3, -H1) and B6(-D5, -H1) in Figure 3A. It is worth noting that the chip module projection area should preferably avoid overlapping with the strip projection area 110 to prevent excessive compression of the chip during use of the dual-interface smart card. Therefore, the area enclosed by the left antenna and the left edge of the card cannot be used to install the chip module.

[0131] Based on this, considering only the first and second strong constraints, the preferred location area of ​​the chip module projection area also includes the resistance projection area, the imprinting projection area and the central axis. That is, the preferred location area of ​​the chip module projection area is: area 1-5, which can overlap with the central axis.

[0132] Considering the first strong constraint, the second strong constraint, and the first weak constraint, the preferred location area of ​​the chip module projection area also includes the resistance projection area and the part of the central axis that does not overlap with the imprint projection area. That is, the preferred location area of ​​the chip module projection area is: area 1-area 4, which can overlap with the central axis.

[0133] Considering the first strong constraint, the second strong constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the parts of the resistance projection area and the imprinting projection area that do not overlap with the central axis. That is, the preferred location area of ​​the chip module projection area is: area 1-area 5, which do not overlap with the central axis.

[0134] Considering the first strong constraint, the second strong constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the central axis and the imprint projection area that does not overlap with the resistance projection area. That is, the preferred location areas of the chip module projection area are: area 1-2 and area 5, which can overlap with the central axis.

[0135] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the second weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the resistance projection area that does not overlap with the central axis and the imprint projection area. That is, the preferred location area of ​​the chip module projection area is the part of region 1-3 and region 4 that does not overlap with region 5 and does not overlap with the central axis.

[0136] Considering the first strong constraint, the second strong constraint, the first weak constraint, and the third weak constraint, the preferred location of the chip module projection area also includes the part of the central axis that does not overlap with the resistance projection area and the imprinting projection area. That is, the preferred location of the chip module projection area is: region 1-2, which can overlap with the central axis.

[0137] Considering the first strong constraint, the second strong constraint, the second weak constraint, and the third weak constraint, the preferred location area of ​​the chip module projection area also includes the part of the imprint projection area that does not overlap with the resistance projection area and the central axis. That is, the preferred location area of ​​the chip module projection area is the part of region 1-2 and region 5 that does not overlap with region 3-4 and does not overlap with the central axis.

[0138] Referring to Figure 4D, this is the third schematic diagram of the substrate layer structure corresponding to different layers and antenna half-wrap of the new dual-interface smart card according to a specific embodiment of the present invention. Referring to Figure 4E, this is the fourth schematic diagram of the substrate layer structure corresponding to different layers and antenna half-wrap of the new dual-interface smart card according to a specific embodiment of the present invention. Referring to Figure 4D, when the chip module is located in area A (i.e., the area formed by A1, A2, A3, and A4 in Figure 4C), the first connection structure needs to connect to the chip module by crossing the antenna winding. Preferably, the crossing position is located in the area where the antenna bends, so as to reduce the mechanical stress damage caused by the overlap between the antenna and the first connection structure and improve the reliability of the smart card. Referring to Figure 4E, when the chip module is located in area B (i.e., the area formed by B1, B2, B3, and B4 in Figure 4C), the first connection structure can connect to the chip module without crossing the antenna winding, but some antenna leads will cross the antenna winding to realize the connection between the antenna terminal and the chip module. When the first connecting structure does not cross the antenna winding and is located outside the antenna winding area, it should also not be placed in the embossed area to avoid damage from subsequent card manufacturing embossing. Of course, in special designs, such as conductive metal foil etching schemes, the damage from embossing can be overcome by widening the first connecting structure, and the first connecting structure can be placed in the embossed area. This solution is a mature technology and will not be described in detail in this invention.

[0139] Positional relationship between the first connection structure, the antenna, and the substrate layer structure

[0140] Corresponding to the wire-winding method, the strip module mounting area includes five closely wound first connection structure terminals. The projection area corresponding to each closely wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved using anisotropic conductive adhesive. Corresponding to the etching method, the strip module mounting area includes five etched pad-type first connection structure terminals. The projection area corresponding to each etched pad-type first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved using anisotropic conductive adhesive or soldering. The chip module 120 is mounted on the substrate layer using methods including but not limited to COB (chip on board) packaging and WLCSP (Wafer Level Chip Scale Packaging). Preferably, for the wire-winding method, the chip module 120 is packaged using COB packaging.

[0141] Based on this, the structure of the substrate layer 100 of the dual-interface smart card in this embodiment of the invention will be different depending on the generation method of different antennas and the first connection structure.

[0142] Specifically, see Figure 5-5A, which is a cross-sectional view of Figure 1 along the AA direction. The first connection structure is on the same layer as the antenna. The conductive channel is made by winding. The strip module and the chip module are finally installed on the same side of the substrate layer, i.e., the chip module is installed upright.

[0143] Referring to Figure 5, for the case where the substrate layer 100 has a single carrier layer, the situation can be further subdivided into two sub-cases based on the positions of the first connecting structure and the antenna: The first sub-case is where the first connecting structure and the antenna are located near the same surface of the carrier layer. Based on their positional relationship within the carrier layer, this sub-case can be further divided into two sub-cases: the first connecting structure and the antenna are simultaneously near either the first or second surface of the carrier layer. The second sub-case is where the first connecting structure and the antenna are located near different surfaces of the carrier layer. Based on their positional relationship within the carrier layer, this sub-case can also be divided into two sub-cases: the first connecting structure and the antenna are respectively near either the first or second surface of the carrier layer. Figure 5 only shows one of these cases as an example.

[0144] Furthermore, as shown in Figure 5, when the chip module is mounted, the chip module is installed through the mounting holes provided in the carrier layer. The terminals of the first connection structure and the antenna are exposed in the mounting holes, so that the first surface of the chip module can be flush with the first surface or the second surface of the carrier layer. The terminals of the first connection structure and the antenna are electrically connected to the conductive channel contact pad of the chip module.

[0145] Referring to Figure 5A, for the case where the carrier layer of substrate layer 100 is formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), it can be further subdivided into the following two sub-cases based on the positions of the first connecting structure and the antenna: The first sub-case is where the first connecting structure and the antenna are simultaneously carried by the first sub-substrate layer. Based on the positional relationship between the first connecting structure and the antenna within the sub-substrate layer, the first sub-case can be further divided into four sub-cases: the first connecting structure and the antenna are simultaneously adjacent to either the first or second surface of the first sub-substrate layer; and the first connecting structure and the antenna are respectively adjacent to either the first or second surface of the first sub-substrate layer. The second sub-case is where the first connecting structure and the antenna are simultaneously carried by the second sub-substrate layer. Based on the positional relationship between the first connecting structure and the antenna within the sub-substrate layer, the second sub-case can also be divided into: the first connecting structure and the antenna are simultaneously adjacent to either the first or second surface of the second sub-substrate layer; and the first connecting structure and the antenna are respectively adjacent to either the first or second surface of the second sub-substrate layer. It is worth noting that the arrangement of the first connection structure on the first or second surface of the carrier layer and the sub-substrate layer can be either embedded or semi-embedded when the conductive channel is fabricated by wire winding. Figure 5A only shows one of the above scenarios as an example.

[0146] Referring to Figure 5B, which illustrates a novel dual-interface smart card according to a specific embodiment of the present invention, Figure 5C is a cross-sectional view of Figure 5B along the AA direction, showing the upright configuration of the chip module. The inverted configuration is similar, but not all embodiments of the present invention are shown.

[0147] As shown in Figure 5C, depending on the thickness and usage conditions, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer is pressed onto the first and second surfaces of the carrier layer, or the first sub-substrate layer and the second sub-substrate layer, or the first sub-substrate layer and the third sub-substrate layer, respectively. The supplementary support layer can be made of materials such as PVC, and other materials can be used to form the upper and lower surfaces of the smart card. This embodiment of the invention does not specifically limit this. It is worth noting that Figures 5B and 5C only show the dual-interface smart card structure corresponding to the case where the carrier layer consists of two sub-substrate layers, and the first connecting structure and the antenna are simultaneously adjacent to the first surface of the first sub-substrate layer. Based on the aforementioned embodiments, it is also applicable to the case where the carrier layer consists of one or three sub-substrate layers, the first connecting structure and the antenna are located in other positions, and the chip module is mounted upright or upside down and fits each other appropriately. For the sake of simplifying the illustration, this invention does not show them all.

[0148] After the supplementary support layer is laminated and supported onto the smart card substrate layer, the strip module will be installed. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding strip mounting area in the supplementary support layer and substrate layer, the terminals of the first connection structure are exposed, and the strip module is installed. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is on the same plane as the first surface of the supplementary support layer. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements. Based on the packaging form adopted by the chip module, it can be further subdivided into the following two scenarios: The first seed scenario is that the chip module adopts COB packaging. The second seed scenario is that the chip module adopts WLCSP packaging.

[0149] Specifically, see Figure 5D, which is a cross-sectional view of Figure 1 along the AA direction; Figure 5E, which is a distorted top view of Figure 1 (the first connecting structure and the antenna are both solid lines), showing a cross-sectional view along the AA direction; and Figure 5F, which is a distorted top view of Figure 1 (the chip module is dashed lines), showing a cross-sectional view along the AA direction. Corresponding to the first connecting structure and the antenna being on the same layer, the conductive channel is fabricated by etching. The final installed strip module and the chip module are installed on the same side of the substrate layer, i.e., the chip module is mounted upright.

[0150] As shown in Figure 5E, for the case where the substrate layer 100 has a single carrier layer, the chip module uses WLCSP packaging. Based on the positions of the first connection structure and the antenna, it can be further subdivided into the following two sub-cases: The first sub-case is where the first connection structure and the antenna are simultaneously supported on the first surface of the carrier layer; the second sub-case is where the first connection structure and the antenna are simultaneously supported on the second surface of the carrier layer. Figure 5E illustrates one of these cases as an example.

[0151] Referring to Figures 5D and 5F, when the carrier layer of substrate layer 100 is formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), corresponding to the chip packaging modes of COB and WLCSP respectively, it can be further subdivided into the following three sub-cases based on the positions of the first connection structure and the antenna: First sub-case: the first connection structure and the antenna are simultaneously carried by the first surface of the first sub-substrate layer; Second sub-case: the first connection structure and the antenna are simultaneously carried by the first surface of the second sub-substrate layer; Third sub-case: the first connection structure and the antenna are simultaneously carried by the second surface of the second sub-substrate layer. It is worth noting that when the antenna and the first connection structure are fabricated by etching, they can be carried by the substrate's layer structure using floating, embedded, or semi-embedded methods. For the cross-sectional structural diagrams shown in Figures 5D and 5F, the chip module can be mounted upright or flip-top.

[0152] When the chip module is COB packaged, the carrier layer is preferably formed by laminating the first sub-substrate layer (i.e., layer 1 in the figure) and the second sub-substrate layer (i.e., layer 2 in the figure), and the antenna and the first connection structure are carried on the first surface of the second sub-substrate layer.

[0153] As shown in Figure 5D, when the chip module is mounted upright, it is mounted through the first mounting hole (mounting hole 1) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the second mounting hole (mounting hole 2) in sub-substrate layer 2 (i.e., the second sub-substrate layer). As shown in Figure 5A, when the chip module is mounted flip-chip, it is mounted through the second mounting hole (mounting hole 2) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the first mounting hole (mounting hole 1) in sub-substrate layer 2 (i.e., the second sub-substrate layer).

[0154] Preferably, the size of the first mounting hole is the same as the size of the chip module substrate, and the size of the second mounting hole is larger than the size of the encapsulating adhesive to accommodate the protruding portion of the chip module encapsulation area. The size of the first mounting hole is larger than the size of the second mounting hole.

[0155] In one embodiment of the present invention, the orthographic projection area of ​​the conductive channel contact pads of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. That is, the second mounting hole exposes portions of each conductive channel contact pad disposed on the chip module substrate within the second mounting hole. Simultaneously, the second mounting hole overlaps with the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer, meaning the second mounting hole penetrates the second sub-substrate layer. Based on this, the stepped surface formed between sub-substrate layer 1 and sub-substrate layer 2 can support the conductive channel contact pads of the chip module. Furthermore, after the chip module is installed, the upper surface of the substrate (i.e., the first surface of the chip module) is flush with the upper surface of sub-substrate layer 1 (i.e., the first surface of the first sub-substrate layer), minimizing the impact on subsequent card manufacturing processes. Meanwhile, based on the aforementioned embodiments, when the chip module is installed, the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the electrical connection process between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad can be achieved through the second mounting hole, such as welding or conductive adhesive pressing.

[0156] Furthermore, for cases where the conductive channel contact pad is not exposed in the second mounting hole, or the conductive channel contact pad is partially exposed in the second mounting hole, but the second mounting hole and the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer do not overlap (the second mounting hole does not penetrate the second surface of the second sub-substrate layer, as shown in Figure 4C), embodiments of the present invention can also drill holes in the corresponding projection area of ​​the conductive channel contact pad in the corresponding sub-substrate layer, so that the first connection structure terminal and the antenna terminal are simultaneously exposed through the welding hole, and then the welding process of the first connection structure terminal and the antenna terminal with the matching conductive channel contact pad is realized through the welding hole, such as spot welding, wedge welding, reflow soldering, etc. When the first mounting hole is located in the first sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the second sub-substrate layer; when the first mounting hole is located in the second sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the first sub-substrate layer, this case is not shown. It is worth noting that in subsequent embodiments of the present invention, the second mounting hole or solder holes can be used to complete the soldering or conductive adhesive bonding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad. For the sake of simplifying the illustration, not all of them are shown in the embodiments of the present invention. It should be noted that for the case of etching process matching COB chip module, the setting of solder holes is not necessary, and the electrical connection between COB chip module and first connection structure and antenna terminal can be achieved by conductive adhesive bonding.

[0157] Based on the foregoing, it can be understood that the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be achieved through the aforementioned second mounting hole or welding hole. Based on this, the relative positional relationship between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad in the dual-interface smart card substrate layer has been clearly stated. Therefore, for the sake of simplified illustration, this embodiment of the invention only shows the first connection structure terminal and the antenna terminal electrically connected to the conductive channel contact pad in some cross-sectional views. Meanwhile, in the actual product structure, the orthographic projection area of ​​the first connection structure on the normal plane of the target surface of the carrier layer overlaps with the orthographic projection areas of the strip module and the chip module on the normal plane of the target surface of the carrier layer, respectively. Based on the foregoing, it can also be understood that since there are many first connection structures, showing them all would affect the representation of the relative positional relationship between the first connection structure and the antenna in the cross-sectional views. Therefore, this embodiment of the invention only shows one set of first connection structures in all cross-sectional views. However, it is understood that the dual-interface smart card substrate layer of this embodiment of the invention actually includes multiple sets of first connection structures, which is hereby declared in this embodiment of the invention.

[0158] As shown in Figures 5E-5F, when the chip module is WLCSP packaged, the carrier layer can be a single layer (as shown in Figure 5E), or it can include a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure) (as shown in Figure 5F). Regardless of whether the chip module is mounted upright or flip-chip, when the first connection structure and the antenna are located between the two sub-substrate layer structures, since the WLCSP packaged chip module is relatively thin, the flexible substrate layer can accommodate its thickness. Therefore, there is no need to set mounting holes in the substrate layer. The chip module is soldered to the terminals of the first connection structure and the antenna terminals by solder balls, or electrically connected to the terminals of the first connection structure and the antenna terminals by anisotropic conductive adhesive.

[0159] Referring to Figure 5B, which is a top view of the novel dual-interface smart card according to a specific embodiment of the present invention, Figures 5C, 5G, and 5H are schematic cross-sectional views of Figure 5B along the AA direction. Based on Figure 5G, it can be seen that, depending on variations in thickness and usage conditions, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer can be laminated to the first and second surfaces of the carrier layer, or the first and second sub-substrate layers, or the first and third sub-substrate layers, respectively. The supplementary support layer can be made of materials such as PVC to form the upper and lower surfaces of the smart card, or other materials may be used; this embodiment of the present invention does not specifically limit its application. It is worth noting that the figure only shows a dual-interface smart card structure in which the chip module is in a COB or WLCSP package and is mounted upright, and the first connection structure and the antenna are located between two sub-substrate layers. Based on the aforementioned embodiments, it is known that the same applies to reasonable combinations of situations where the carrier layer consists of one or three sub-substrate layers, or where the first connection structure and the antenna are located in other positions, or where the chip module is mounted upright or flipped. For the sake of simplifying the illustration, the present invention has not shown them all.

[0160] Specifically, see Figure 6-6A, which is a cross-sectional view of Figure 1 along the AA direction. Corresponding to the first connection structure being on a different layer from the antenna, the conductive channel is fabricated by a winding method. The final installed strip module and chip module are installed on the same side of the substrate layer, i.e., the chip module is installed upright.

[0161] Referring to Figure 6, for the case where the substrate layer 100 has a single-layer carrier layer, in the case of a wire-wound configuration, the first connecting structure is located on one surface of the carrier layer, and the antenna is located on the other surface. Based on the positions of the first connecting structure and the antenna, this can be further subdivided into two sub-cases: 1) The first connecting structure is adjacent to the first surface of the carrier layer, and the antenna is adjacent to the second surface of the carrier layer; 2) The first connecting structure is adjacent to the second surface of the carrier layer, and the antenna is adjacent to the first surface of the carrier layer. Figure 6 only shows one of these cases as an example. Furthermore, referring to Figure 6, when the chip module is mounted upright or flipped, it is installed through mounting holes provided in the carrier layer. The terminals of the first connecting structure and the antenna are exposed in the mounting holes, allowing the first surface of the chip module to be flush with either the first or second surface of the carrier layer. The terminals of the first connecting structure and the antenna are electrically connected to the conductive track contact pads of the chip module.

[0162] Referring to Figure 6A, when the carrier layer of substrate layer 100 is formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), the dual-interface smart card substrate layer includes a first connection structure, an antenna, a chip module, and the first and second sub-substrate layers. The carrier layer carries the first connection structure, the antenna, and the chip module. The first connection structure and the antenna are electrically connected to the chip module, respectively. The first connection structure includes an inner lead and an inner lead connecting line. The antenna includes an antenna winding and an antenna lead. The inner lead is electrically connected to the chip module and the inner lead connecting line, respectively. The antenna lead is electrically connected to the chip module and the antenna winding, respectively. For the winding wiring method, the inner lead and the inner lead connecting line are integrally formed and located on the same plane of the sub-substrate layer. The antenna lead and the antenna winding are integrally formed and located on the same plane of the sub-substrate layer. According to the inner lead / inner lead connecting line, Antenna leads / antenna windings located in different sub-substrate layers can be categorized as follows: The first seed case is: the inner lead and the inner lead connecting line are carried by the first sub-substrate layer, and the antenna winding and antenna lead are carried by the second sub-substrate layer. Based on the positional relationship between the inner lead / inner lead connecting line and the antenna lead / antenna winding within the sub-substrate layer, the first seed case can be further subdivided into four sub-cases: the inner lead and the inner lead connecting line are simultaneously adjacent to the first or second surface of the first sub-substrate layer, and the antenna winding and antenna lead are simultaneously adjacent to the first or second surface of the second sub-substrate layer. The second sub-case is as follows: the inner lead and the inner lead connecting line are carried by the second sub-substrate layer, and the antenna winding and the antenna lead are carried by the first sub-substrate layer. Based on the positional relationship of the inner lead / inner lead connecting line and the antenna lead / antenna winding within the sub-substrate layer, the second sub-case can be further divided into four sub-cases: the inner lead and the inner lead connecting line are simultaneously adjacent to the first or second surface of the second sub-substrate layer, and the antenna winding and the antenna lead are simultaneously adjacent to the first or second surface of the first sub-substrate layer. Figure 6A only shows a few of the above cases as examples. It is worth noting that the arrangement of the inner lead / inner lead connecting line and the antenna lead / antenna winding on the carrier layer and the first or second surface of the sub-substrate layer can be either embedded or semi-embedded when the conductive channel is fabricated as a winding.

[0163] Furthermore, referring to Figure 6A, when the chip module is mounted upright, it is mounted through the first mounting hole (mounting hole 1) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the second mounting hole (i.e., mounting hole 2) in sub-substrate layer 2 (i.e., the second sub-substrate layer). When the chip module is flip-chip mounted, it is mounted through the second mounting hole (i.e., mounting hole 2) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the first mounting hole (i.e., mounting hole 1) in sub-substrate layer 2 (i.e., the second sub-substrate layer). Preferably, the size of the first mounting hole is the same as the size of the chip module substrate, and the size of the second mounting hole is larger than the size of the encapsulating adhesive to accommodate the protruding portion of the chip module encapsulation area. The size of the first mounting hole is larger than the size of the second mounting hole.

[0164] In one embodiment of the present invention, the orthographic projection area of ​​the conductive channel contact pads of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. That is, the second mounting hole exposes portions of each conductive channel contact pad disposed on the chip module substrate within the second mounting hole. Simultaneously, the second mounting hole overlaps with the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer, meaning the second mounting hole penetrates the second sub-substrate layer. Based on this, the stepped surface formed between sub-substrate layer 1 and sub-substrate layer 2 can support the conductive channel contact pads of the chip module. Furthermore, after the chip module is installed, the upper surface of the substrate (i.e., the first surface of the chip module) is flush with the upper surface of sub-substrate layer 1 (i.e., the first surface of the first sub-substrate layer), minimizing the impact on subsequent card manufacturing processes. Meanwhile, based on the aforementioned embodiments, when the chip module is installed, the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the electrical connection process between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad can be realized through the second mounting hole, such as spot welding.

[0165] Furthermore, in cases where the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer does not overlap with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer, i.e., the conductive channel contact pad is not exposed in the second mounting hole, or the conductive channel contact pad is partially exposed in the second mounting hole, but the orthographic projection area of ​​the second mounting hole and the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer does not overlap, the present invention embodiment can drill holes in the corresponding projection area of ​​the conductive channel contact pad in the corresponding sub-substrate layer so that the first connection structure terminal and the antenna terminal are simultaneously exposed through the welding hole, and then the welding process, such as spot welding, is realized by the welding hole between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad. When the first mounting hole is located in the first sub-substrate layer, a plurality of welding holes matching the antenna terminal and the first connection structure terminal are provided in the second sub-substrate layer; when the first mounting hole is located in the second sub-substrate layer, a plurality of welding holes matching the antenna terminal and the first connection structure terminal are provided in the first sub-substrate layer, this case is not shown; it is worth noting that in subsequent embodiments of the present invention, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be completed by using the second mounting hole or welding holes. For the sake of simplifying the illustration, the embodiments of the present invention are not shown one by one.

[0166] Based on the foregoing, it can be understood that the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be achieved through the aforementioned second mounting hole or welding hole. Based on this, the relative positional relationship between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad in the dual-interface smart card substrate layer has been clearly stated. Therefore, for the sake of simplified illustration, this embodiment of the invention only shows the first connection structure terminal and the antenna terminal electrically connected to the conductive channel contact pad in some cross-sectional views. Meanwhile, in the actual product structure, the orthographic projection area of ​​the first connection structure on the normal plane of the target surface of the carrier layer overlaps with the orthographic projection areas of the strip module and the chip module on the normal plane of the target surface of the carrier layer, respectively. Based on the foregoing, it can also be understood that since there are many first connection structures, showing them all would affect the representation of the relative positional relationship between the first connection structure and the antenna in the cross-sectional views. Therefore, this embodiment of the invention only shows one set of first connection structures in all cross-sectional views. However, it is understood that the dual-interface smart card substrate layer of this embodiment of the invention actually includes multiple sets of first connection structures, which is hereby declared in this embodiment of the invention.

[0167] The dual-interface smart card substrate layer in this embodiment of the invention further includes a third sub-substrate layer. After the chip module and the antenna carried by the sub-substrate layer are electrically connected and assembled with the first connection structure, the third sub-substrate layer can be pressed together with the first sub-substrate layer or the second sub-substrate layer to provide better support for the substrate layer.

[0168] Based on Figures 4, 4D, and 4E in the aforementioned embodiments, when the first connecting structure is on a different layer from the antenna, the conductive channel is fabricated using a winding method, and the antenna winding is half-wound, in the top view of the dual-interface smart card substrate layer, there are three positional relationships between the first connecting structure and the antenna: The first is that the first connecting structure does not need to cross the antenna winding to connect to the chip module (as shown in Figure 4); the second is that the first connecting structure needs to cross the antenna winding through the antenna bend area to connect to the chip module (as shown in Figure 4D); the third is that the first connecting structure can connect to the chip module without crossing the antenna winding, but some antenna leads will cross the antenna winding to achieve the connection between the antenna terminal and the chip module (as shown in Figure 4E). For the above three scenarios, the cross-sectional structural diagram corresponding to the first scenario is similar to that of the full-winding, 3 / 4-winding, and 2 / 3-winding scenarios. For the other two scenarios, Figure 6C is a top view of the new dual-interface smart card of the present invention (corresponding to the scenario shown in Figure 4B), and Figure 6D is a cross-sectional structural diagram of Figure 6C along the AA direction. As can be seen from Figures 6C and 6D, the difference between the second and third scenarios of the dual-interface smart card substrate layer with half-wound antennas and the dual-interface smart card substrate layers with full-wound, 3 / 4-wound, or 2 / 3-wound antennas lies in the different areas where the antenna or the first connecting structure is located in the top view. Accordingly, the horizontal position of the cross-sectional structure corresponding to the antenna winding or the first connecting structure in the cross-sectional structural schematic diagram is different. It is worth noting that although Figure 6D only shows the dual-interface smart card substrate layer structure corresponding to the case where the carrier layer consists of two sub-substrate layers, and the first connecting structure is adjacent to the first surface of the second sub-substrate layer, and the antenna is adjacent to the first surface of the first sub-substrate layer, the one-layer, two-layer, or three-layer substrate layer structures involved in the aforementioned embodiments, the chip module mounting methods with mounting holes, the electrical connection methods of welding the first connecting structure terminals and antenna terminals to the matching conductive channel contact pads or solder balls using mounting holes or solder holes, and the vertical layout of the first connecting structure and antenna in the substrate layer are all applicable to dual-interface smart card substrate layers where the antenna winding is semi-wound. For the sake of simplifying the illustration, the present invention has not shown them all.

[0169] Referring to Figure 5B, which illustrates a novel dual-interface smart card according to a specific embodiment of the present invention, Figure 6B is a cross-sectional view of Figure 5B along the AA direction, showing the chip module in its upright position. As shown in Figure 6B, depending on variations in thickness and usage conditions, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer is laminated to the first and second surfaces of the carrier layer, or the first and second sub-substrate layers, or the first and third sub-substrate layers. The supplementary support layer can be made of materials such as PVC, and other materials can be used to form the upper and lower surfaces of the smart card; this embodiment of the present invention does not specifically limit this. It is worth noting that Figure 6B only shows the dual-interface smart card structure corresponding to the case where the carrier layer consists of two sub-substrate layers, and the first connection structure is adjacent to the second surface of the first sub-substrate layer, and the antenna is adjacent to the first surface of the second sub-substrate layer. Based on the aforementioned embodiments, it can be seen that the same applies to the case where the carrier layer consists of one or three sub-substrate layers, the first connection structure and the antenna are located in other positions, and the chip module is properly adapted to be mounted upright or upside down. For the sake of simplifying the illustration, the present invention has not shown them all.

[0170] After the supplementary support layer is laminated and supported onto the smart card substrate layer, the strip module will be installed. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. The terminals of the first connection structure are exposed by slotting in the corresponding strip mounting area of ​​the supplementary support layer and substrate layer, and then the strip module is installed. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is on the same plane as the first surface of the supplementary support layer. The contact surface of the contact pads refers to the surface where the contact pads physically contact an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

[0171] Specifically, see Figure 6E, a distorted top view of Figure 1 (the first connecting structure and antenna leads are both solid lines), showing a cross-sectional view along the AA direction. See Figure 6F, a distorted top view of Figure 1 (the antenna winding and inner lead connection lines are both solid lines), showing a cross-sectional view along the AA direction. Corresponding to the first connecting structure and the antenna being on different layers, the conductive channel is fabricated by etching. The final installed strip module and chip module are installed on the same side of the substrate layer, i.e., the chip module is mounted upright.

[0172] More specifically, referring to Figure 6E, for the case where the substrate layer 100 has a single carrier layer, it can be further subdivided into the following two sub-cases based on the position of the first connection structure and the antenna: The first sub-case is: the antenna lead and the inner lead are simultaneously carried on the first surface of the carrier layer, and at least one of the antenna winding and the inner lead connection line is carried on the second surface of the carrier layer; the second sub-case is: the antenna lead and the inner lead are simultaneously carried on the second surface of the carrier layer, and at least one of the antenna winding and the inner lead connection line is carried on the first surface of the carrier layer. Figure 6E only shows one of the above cases as an example.

[0173] Referring to Figure 6F, for the case where the carrier layer of substrate layer 100 is formed by laminating a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure), the following sub-cases can be further subdivided according to the positions of the inner lead / antenna lead, antenna winding, and inner lead connection line: The first sub-case is: the inner lead and the antenna lead are simultaneously carried by the first surface of the first sub-substrate layer, and at least one of the antenna winding and the inner lead connection line is carried by the second surface of the first sub-substrate layer, the first surface of the second sub-substrate layer, or the second surface of the second sub-substrate layer; The second sub-case is: the inner lead and the antenna lead are simultaneously carried by the first surface of the second sub-substrate layer, and at least one of the antenna winding and the inner lead connection line is carried by the first surface of the first sub-substrate layer or the second surface of the second sub-substrate layer; The third sub-case is: the inner lead and the antenna lead are simultaneously carried by the second surface of the second sub-substrate layer, and at least one of the antenna winding and the inner lead connection line is carried by the first surface of the first sub-substrate layer or the first surface of the second sub-substrate layer. Figure 6F only illustrates one of the above scenarios. It is worth noting that when the antenna and the first connection structure are fabricated using etching, they can be supported by the substrate's layer structure using floating, embedded, or semi-embedded methods. The chip module uses a COB (Chip-on-Board) package; the WLCSP (Wafer-Localized Panel) package is also applicable, but will not be shown here.

[0174] When the chip module is COB packaged, the carrier layer is preferably formed by laminating the first sub-substrate layer (i.e., layer 1 in the figure) and the second sub-substrate layer (i.e., layer 2 in the figure), and the antenna lead and the inner lead are carried on the first surface of the second sub-substrate layer.

[0175] Referring to Figure 6F, when the chip module is mounted upright, it is mounted through the first mounting hole (mounting hole 1) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the second mounting hole (mounting hole 2) in sub-substrate layer 2 (i.e., the second sub-substrate layer). When the chip module is mounted flip-chip, it is mounted through the second mounting hole (mounting hole 2) in sub-substrate layer 1 (i.e., the first sub-substrate layer) and the first mounting hole (mounting hole 1) in sub-substrate layer 2 (i.e., the second sub-substrate layer). Preferably, the size of the first mounting hole is the same as the size of the chip module substrate, and the size of the second mounting hole is larger than the size of the encapsulating adhesive to accommodate the protruding portion of the chip module encapsulation area. The size of the first mounting hole is larger than the size of the second mounting hole.

[0176] In one embodiment of the present invention, similar to the winding method, the orthographic projection area of ​​the conductive channel contact pads of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. That is, the second mounting hole exposes each conductive channel contact pad disposed on the chip module substrate to the second mounting hole. At the same time, the second mounting hole overlaps with the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer. That is, the second mounting hole penetrates the second sub-substrate layer. Based on this, the stepped surface formed between the sub-substrate layer 1 and the sub-substrate layer 2 can support the conductive channel contact pads of the chip module. After the chip module is installed, the upper surface of the substrate (i.e., the first surface of the chip module) is flush with the upper surface of the sub-substrate layer 1 (i.e., the first surface of the first sub-substrate layer), which can minimize the impact on subsequent card manufacturing processes. Meanwhile, based on the aforementioned embodiments, when the chip module is installed, the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the electrical connection process between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad can be achieved through the second mounting hole, such as welding or conductive adhesive pressing.

[0177] Furthermore, in cases where the conductive channel contact pad is not exposed in the second mounting hole, or the conductive channel contact pad is partially exposed in the second mounting hole, but the second mounting hole and the orthographic projection area of ​​the second surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer do not overlap, the embodiments of the present invention can also drill holes in the corresponding projection area of ​​the conductive channel contact pad in the corresponding sub-substrate layer, so that the first connection structure terminal and the antenna terminal are simultaneously exposed through the welding hole, and then the welding process of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad is realized through the welding hole, such as spot welding, wedge welding, reflow soldering, etc. When the first mounting hole is located in the first sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the second sub-substrate layer; when the first mounting hole is located in the second sub-substrate layer, multiple solder holes matching the antenna terminal and the first connection structure terminal are provided in the first sub-substrate layer, this case is not shown. It is worth noting that in subsequent embodiments of the present invention, the second mounting hole or solder holes can be used to complete the soldering or conductive adhesive bonding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad. For the sake of simplifying the illustration, not all of them are shown in the embodiments of the present invention. It should be noted that for the case of etching process matching COB chip module, the setting of solder holes is not necessary, and the electrical connection between COB chip module and first connection structure and antenna terminal can be achieved by conductive adhesive bonding.

[0178] Based on the foregoing, it can be understood that the first connection structure terminal and the antenna terminal overlap with the matching conductive channel contact pad in the vertical direction. Therefore, the welding of the first connection structure terminal and the antenna terminal to the matching conductive channel contact pad can be achieved through the aforementioned second mounting hole or welding hole. Based on this, the relative positional relationship between the first connection structure terminal and the antenna terminal and the matching conductive channel contact pad in the dual-interface smart card substrate layer has been clearly stated. Therefore, for the sake of simplified illustration, this embodiment of the invention only shows the first connection structure terminal and the antenna terminal electrically connected to the conductive channel contact pad in some cross-sectional views. Meanwhile, in the actual product structure, the orthographic projection area of ​​the first connection structure on the normal plane of the target surface of the carrier layer overlaps with the orthographic projection areas of the strip module and the chip module on the normal plane of the target surface of the carrier layer, respectively. Based on the foregoing, it can also be understood that since there are many first connection structures, showing them all would affect the representation of the relative positional relationship between the first connection structure and the antenna in the cross-sectional views. Therefore, this embodiment of the invention only shows one set of first connection structures in all cross-sectional views. However, it is understood that the dual-interface smart card substrate layer of this embodiment of the invention actually includes multiple sets of first connection structures, which is hereby declared in this embodiment of the invention.

[0179] When the chip module is WLCSP packaged, the carrier layer can be a single layer, or it can include a first sub-substrate layer (i.e., layer 1 in the figure) and a second sub-substrate layer (i.e., layer 2 in the figure). Regardless of whether the chip module is mounted upright or flip-chip, when the first connection structure and the antenna are disposed between the layer structures of the two sub-substrates, since the WLCSP packaged chip module is relatively thin, the flexible substrate layer can accommodate its thickness. Therefore, there is no need to set mounting holes in the substrate layer. The chip module is soldered to the terminals of the first connection structure and the antenna terminals by solder balls, or electrically connected to the terminals of the first connection structure and the antenna terminals by anisotropic conductive adhesive.

[0180] The dual-interface smart card substrate layer of this embodiment of the invention further includes a third sub-substrate layer, which can be laminated with the first sub-substrate layer or the second sub-substrate layer to provide better support for the substrate layer.

[0181] Figures 6G-6H show the cross-sectional views along the AA direction of the distorted top view in Figure 4, where the conductive channel is fabricated by etching and the antenna winding is half-wound. Figure 6G is a schematic cross-sectional view along the AA direction of one of the distorted top views of Figure 4 (the antenna winding is now a dashed line), and Figure 6H is a schematic cross-sectional view along the AA direction of another distorted top view of Figure 4 (the inner lead connecting line is now a solid line, and the antenna winding is now a dashed line). For the etching scheme, since the antenna winding and the first connecting structure are located on different layers, and the etched antenna is relatively thin, the antenna can be placed below the orthographic projection direction of the strip module mounting area on the substrate layer. That is, the strip module mounting area overlaps with the orthographic projection area of ​​the antenna winding on the target surface of the carrier layer. As shown in Figure 6H, the preferred implementation scheme has the antenna winding located on the second surface of the second sub-substrate layer and the inner lead connecting line located on the first surface of the first sub-substrate layer. At this time, the inner lead connecting line and the antenna winding are longitudinally separated by two sub-substrate layer thicknesses. This reduces the impact on the antenna winding during subsequent testing experiments. After the strip module is installed, there will be no interference between the strip module and the antenna below, thus improving the reliability of the card.

[0182] When the chip module is WLCSP, similar to Figure 6H, the strip module area of ​​the smart card overlaps with the orthographic projection area of ​​the antenna winding on the target surface of the carrier layer. At this time, the internal lead connection line and the antenna winding are longitudinally separated by 2 sub-substrate layer thicknesses. During subsequent testing experiments, the impact on the antenna winding is reduced. After the strip module is installed, there will be no interference between the strip module and the antenna below, thus improving the reliability of the card.

[0183] The embodiments of the present invention only show the half-wound method. It can be understood that the cases of full-wound, 3 / 4-wound, and 2 / 3-wound are similar when the etched antenna is wide (see Figure 2C). The reverse mounting of the chip module is similar to the forward mounting. For the sake of simplifying the illustration, the present invention has not shown them one by one.

[0184] Referring to Figure 6I, a distorted top view of Figure 1 (the antenna lead and the first connecting structure are solid lines), a cross-sectional view along the AA direction is shown. Figure 6J, a distorted top view of Figure 1 (the chip module is dashed lines), a cross-sectional view along the AA direction is shown. Corresponding to the first connecting structure and the antenna winding being on different layers, the conductive channel is fabricated by etching. The inner lead and the antenna lead are located on the same layer. The substrate layer includes an etched insulating layer. The inner lead and the antenna winding are located on different layers, respectively on the upper and lower surfaces of the etched insulating layer. The etched insulating layer is designed to meet electrical insulation properties and is not a substrate layer structure. Its thickness is much smaller than that of the substrate layer structure to meet the needs of future card application areas and scenarios. The material of the etched insulating layer can be epoxy resin, polyimide, ceramic materials, polytetrafluoroethylene film, or other commonly used insulating materials known to those skilled in the art.

[0185] Figure 6K is a schematic diagram of the cross-sectional structure along the AA direction of Figure 5B.

[0186] In this embodiment of the invention, to meet the thickness requirements of future cards, an etched insulating layer is set to replace the substrate layer in the aforementioned embodiments, as shown in Figures 6I-6J. The chip module is packaged in the form of a WLCSP upright structure. The internal leads, antenna windings, and etched insulating layer constitute an etched antenna body. The etched antenna body is supported by the carrier layer. When the carrier layer is a single-layer substrate layer, as shown in Figure 6I, the etched antenna body is located on the first surface of the carrier layer (or sub-substrate layer), that is, the etched antenna body and the first surface of the carrier layer overlap in the orthogonal projection area on the normal plane of the target surface of the carrier layer.

[0187] When the carrier layer is a multi-layer structure, as shown in Figure 6J, the etched antenna body is located between the carrier layer structures, that is, the etched antenna body and the second surface of the first sub-substrate layer overlap in the orthographic projection area of ​​the first surface of the second sub-substrate layer on the normal plane of the target surface of the carrier layer.

[0188] As shown in Figure 6K, depending on the changes in thickness and usage conditions, the dual-interface smart card of this embodiment of the invention also includes a supplementary support layer and a strip module, wherein the supplementary support layer is pressed together with the first sub-substrate layer and the second sub-substrate layer respectively.

[0189] The dual-interface smart card of this invention only shows the inner lead and antenna winding located on the upper and lower surfaces of the etched insulating layer, respectively. Based on the aforementioned embodiments, it is known that the invention is applicable to cases where the carrier layer is composed of one or three sub-substrate layers, and whether the orthogonal projection area of ​​the inner lead connection line and the etched insulating layer on the normal plane of the target surface of the carrier layer overlaps with the orthogonal projection area of ​​the inner lead on the normal plane of the target surface of the carrier layer, and to cases where the chip module is properly adapted to be mounted upright or flipped. For the sake of simplifying the illustration, this invention has not shown them all.

[0190] Test Structure

[0191] Referring to Figure 7, which is a schematic diagram of the substrate layer strip module mounting area corresponding to the new dual-interface smart card of this invention, it can be understood that after the chip module is electrically connected and integrated with the first connection structure and antenna, the electrical connectivity of the first connection structure needs to be tested to ensure that the terminals of the first connection structure in the form of tightly wound or etched pads in the strip module mounting area are electrically connected to the chip module, thereby ensuring the pass rate of the dual-interface smart card. To address this issue, this invention proposes an innovative connectivity testing scheme. As shown in Figure 7, this invention exposes the conductive parts in the terminals of the first connection structure by opening test holes in the strip projection area. Test probes can then be inserted into the test holes and contact the conductive parts in the terminals of the first connection structure to perform connectivity testing. Referring to Figure 7, it can be understood that the test holes can be integrated test holes similar to U-grooves, or conventional discrete test holes (i.e., one test hole for each first connection structure terminal). This invention does not specifically limit this. The opening method of the test holes in this invention also differs depending on the conductive channel generation method and the substrate layer structure.

[0192] For the test structure, when the first connection structure and the antenna are located on the same layer or different layers, the first connection structure and the strip module are electrically connected in the strip module mounting area. The connection position of the first connection structure and the strip module is on the same plane. For the test hole, when the first connection structure and the antenna are located on the same layer or different layers, the situation is the same. This invention will not describe them one by one here.

[0193] The first connection structure and antenna are in the case of a wire-wound configuration. Referring to Figures 8 to 8C, these are schematic cross-sectional views along the AA direction of the substrate layer strip module mounting area corresponding to the new dual-interface smart card of this invention, respectively corresponding to the cases where the first connection structure is disposed on the first surface of the first sub-substrate layer, the second surface of the first sub-substrate layer, the first surface of the second sub-substrate layer, and the second surface of the second sub-substrate layer. It is worth noting that the first connection structure corresponding to the wire-wound configuration is embedded or partially embedded within the substrate layer surface, while the first connection structure corresponding to the etching configuration can be floating, embedded, or partially embedded in the substrate layer surface. The layer structure of the substrate supports the first connection structure. It is understood that for the terminals of the tightly wound structure, the cross-section can be elliptical or circular; for simplicity, only a rectangle is used to illustrate the cross-section of the first connection structure terminal in the figures.

[0194] Referring to Figures 8 to 8C, the finished substrate layer preferably consists of two sub-substrate layers; the same applies to a single-layer structure. Based on this, the test holes can be configured in two ways: Method 1: Drilling through the sub-substrate layer structure from above the first connecting structure terminal (i.e., in the direction of the first surface of the substrate layer structure) to generate a first type of test hole corresponding to the terminal tightly wrapped around the first connecting structure; Method 2: Drilling through the sub-substrate layer from below the first connecting structure terminal (i.e., in the direction of the second surface of the substrate layer structure) to generate a second type of test hole corresponding to the terminal tightly wrapped around the first connecting structure. It is understood that either the first type of test hole or the second type of test hole can be selected for drilling testing (both cases are shown simultaneously in the figures). The shapes of the first type of test hole and the second type of test hole can be the same or different; this embodiment of the invention does not specifically limit this.

[0195] Specifically, referring to Figure 8, when the first connecting structure is supported on the first surface of the first sub-substrate layer, the first type of test hole penetrates a portion of the first sub-substrate layer, and the second type of test hole penetrates the second sub-substrate layer and a portion of the first sub-substrate layer. Referring to Figure 8A, when the first connecting structure is supported on the second surface of the first sub-substrate layer, the first type of test hole penetrates a portion of the first sub-substrate layer, and the second type of test hole penetrates the second sub-substrate layer and a portion of the first sub-substrate layer. Referring to Figure 8B, when the first connecting structure is supported on the first surface of the second sub-substrate layer, the first type of test hole penetrates the first sub-substrate layer and a portion of the second sub-substrate layer, and the second type of test hole penetrates a portion of the second sub-substrate layer. Referring to Figure 8C, when the first connecting structure is supported on the second surface of the second sub-substrate layer, the first type of test hole penetrates the first sub-substrate layer and a portion of the second sub-substrate layer, and the second type of test hole penetrates a portion of the second sub-substrate layer. It is worth noting that, regardless of whether it is the first type of test hole or the second type of test hole, the drilling depth into the first connection structure is only required to remove the insulating enamel coating on its surface to expose the internal metal wires. Preferably, the depth of the test hole into the first connection structure does not exceed the radius of the first connection structure.

[0196] When manufacturing the card, additional support layers need to be laminated onto the first and second surfaces of the substrate layer, and strip modules need to be installed in the strip module mounting area. To install the strip modules, holes need to be drilled in the strip module mounting area on the card structure surface (strip mounting holes). The size of the strip mounting holes is the same as the size of the strip projection area, and the additional support layer, carrier layer or sub-substrate layer (if any) in the corresponding area needs to be removed to expose the tightly wound terminals in the strip mounting area.

[0197] When the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, meaning that both the depth and area of ​​the strip mounting hole are larger than those of the test hole. Therefore, the finished dual-interface smart card will not include a test hole. However, it is worth noting that although the depth of the strip mounting hole is greater than the depth of the test hole, its depth into the first connection structure preferably does not exceed the radius of the first connection structure. This avoids reducing the exposed area of ​​the conductive parts of the terminals of the first connection structure, thereby ensuring the electrical connectivity between the finished smart card strip module and the first connection structure.

[0198] When the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Since the area of ​​the test hole is small, the use of the card will not be affected after the supplementary support layer is covered, so there is no need to backfill with filler. Based on this, the dual-interface smart card product will include a test hole. Of course, it is also possible to backfill the test hole with filler. Since the supplementary support layer and the bearing layer can be pressed together by hot pressing, there will be some melted material in the test hole, and it is not a complete through hole. For the sake of simplifying the drawings, this is not shown one by one. It is worth noting that the drilling depth of the strip mounting hole also needs to remove the enameled layer of the tightly wound terminal of the first connecting structure to expose more metal area. In order to establish electrical connection contact with the strip module, since the test hole on the opposite side of the strip mounting hole has entered the first test structure to a certain depth, the depth of the strip mounting hole into the first connecting structure should not be too deep, preferably not exceeding the radius of the conductor of the first connecting structure. On the one hand, this prevents the metal part of the first connecting structure from being penetrated and damaged, and on the other hand, it ensures that the exposed area of ​​the conductive metal part is as large as possible, thereby enhancing the conductive contact.

[0199] Referring to Figures 8D-8E, which are schematic cross-sectional views of the installation area of ​​the new dual-interface smart card strip module along the AA direction in a specific embodiment of the present invention, corresponding to the winding form, and as shown in Figures 8D-8E, if the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, that is, the depth of the strip mounting hole is greater than the depth of the test hole. Based on this, the finished dual-interface smart card will not include a test hole (as shown in Figure 8E). However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Based on this, the finished dual-interface smart card will include a test hole (as shown in Figure 8D). It is worth noting, however, that although the depth of the strip mounting hole is greater than the depth of the test hole, its depth into the first connecting structure preferably cannot exceed the radius of the first connecting structure. It is understood that in practical applications, embodiments of the present invention can also add a third sub-substrate layer according to the thickness of the card. The test opening can be set after the third sub-substrate layer is installed, or the third sub-substrate layer can be installed after the opening test is completed. The former may result in the presence of test hole structures in the third sub-substrate layer (if the test hole is located on the side where the third sub-substrate layer is installed), while the latter will result in a complete third sub-substrate layer structure. For better support, it is preferable to install the third sub-substrate layer after completing the hole testing.

[0200] The conductive channel is generated by etching. Referring to Figures 9 to 9A, these are schematic cross-sectional views of the substrate layer strip module mounting area along the AA direction of the new dual-interface smart card according to a specific embodiment of the present invention, respectively corresponding to the cases where the carrier layer is a single layer and the first connecting structure is located on the first surface of the carrier layer, and the carrier layer is two layers and the first connecting structure is supported between two sub-substrate layers.

[0201] As shown in Figure 9A, the finished substrate layer preferably consists of two sub-substrate layers. Based on this, the test holes can be configured in two ways: Method 1 involves drilling through the sub-substrate layer above the first connection structure terminal to create a first type of test hole corresponding to the etched pad-shaped first connection structure terminal; Method 2 involves drilling through the sub-substrate layer below the first connection structure terminal to create a second type of test hole corresponding to the etched pad-shaped first connection structure terminal. It is understood that either the first type or the second type of test hole can be selected for drilling and testing (both cases are shown simultaneously in the figure). The shapes of the first type and the second type of test holes can be the same or different; this embodiment of the invention does not impose specific limitations on this.

[0202] Specifically, referring to Figure 9, when the first connection structure is supported on the first surface of the first sub-substrate layer, the etched pad terminals of the first connection structure can be accessed for testing without the need for a first type of test hole. There are no first type of test holes in the substrate layer; only second type of test holes exist that penetrate the first sub-substrate layer. Referring to Figure 9A, when the first connection structure is supported between two sub-substrate layers, either the first type of test hole penetrates the first sub-substrate layer, or the second type of test hole penetrates the second sub-substrate layer. It is worth noting that, for the etching method, since the first connection structure in the form of etched pads is relatively thin, both the first and second type of test holes expose only the etched pads in the depth direction, avoiding penetration into the first connection structure as much as possible. This is to prevent the etched pad-type first connection structure from perforating or breaking and failing, thus affecting the electrical connectivity between the finished smart card strip module and the first connection structure.

[0203] When fabricating the card, additional support layers need to be laminated onto the first and second surfaces of the substrate layer, and strip modules need to be installed in the strip module mounting area. To install the strip modules, holes (strip mounting holes) need to be drilled in the strip module mounting area on the card structure surface. The size of the strip mounting holes is the same as the size of the strip projection area, and the additional support layer, carrier layer or sub-substrate layer (if any) in the corresponding area needs to be removed to expose the etched pad terminals of the first connection structure in the strip mounting area.

[0204] If the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, meaning the depth of the strip mounting hole is the same as the depth of the test hole. Therefore, the finished dual-interface smart card will not include a test hole.

[0205] However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Since the test hole area is small, the use of the card is not affected after the supplementary support layer is used, therefore backfilling is unnecessary. Because the supplementary support layer and the load-bearing layer can be bonded by hot pressing, some molten material will exist in the test hole, making it not a completely through hole. For the sake of simplicity, this is not shown in detail in the accompanying drawings. Therefore, the finished dual-interface smart card will include a test hole. Of course, backfilling the test hole with material is also possible.

[0206] Referring to Figures 9B-9E, which are schematic cross-sectional views of the mounting area of ​​the new dual-interface smart card strip module along the AA direction in a specific embodiment of the present invention, and corresponding to the etching pattern, as shown in Figures 9B-9E, if the opening direction of the strip mounting hole is the same as the opening direction of the test hole, the test hole will be covered by the strip mounting hole, that is, the depth of the strip mounting hole is the same as the depth of the test hole. Therefore, the finished dual-interface smart card will not contain a test hole (as shown in Figures 9B and 9D). However, if the opening direction of the strip mounting hole is different from the opening direction of the test hole, the test hole will not be covered by the strip mounting hole. Therefore, the finished dual-interface smart card will contain a test hole (as shown in Figures 9C and 9E).

Claims

1. A dual-interface smart card substrate layer, characterized in that, include: The carrier layer, antenna winding, and chip module; Both the antenna winding and the chip module are carried by the carrier layer; Multiple orthographic projection areas are formed on the target surface of the carrier layer. These multiple orthographic projection areas include a strip projection area, a chip module projection area, a magnetic strip projection area, an embossed projection area, and an antenna projection area. The strip projection area is the orthographic projection area corresponding to the strip mounting area of ​​the carrier layer, the magnetic strip projection area is the orthographic projection area corresponding to the magnetic strip mounting area of ​​the carrier layer, the embossed projection area is the orthographic projection area corresponding to the embossed fabrication area of ​​the carrier layer, and the antenna projection area is the orthographic projection area corresponding to the antenna winding. The chip module projection area and the strip projection area do not overlap; Wherein, the target surface of the carrier layer is one of the surfaces with the largest area of ​​the carrier layer; the position of the chip module projection area is determined based on the target constraint conditions in the preset constraint condition set; the target constraint conditions include a first strong constraint condition and a second strong constraint condition, the first strong constraint condition being: the chip module projection area avoids the magnetic stripe projection area and the embossed projection area; the second strong constraint condition being: the chip module projection area avoids the antenna projection area, and the position area of ​​the chip module projection area is: the area formed by the lower edge of the magnetic stripe projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the stripe projection area.

2. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint condition also includes a first weak constraint condition, which is: the chip module projection area avoids the imprinted projection area. The imprinted projection area is the area enclosed by the straight line where the long side of the strip projection area is located and the left and right edges of the target surface of the carrier layer. The location area of ​​the chip module projection area is the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the imprinted projection area.

3. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint condition also includes a second weak constraint condition, which is that the chip module projection area avoids the central axis of the target surface of the carrier layer, and the location area of ​​the chip module projection area is the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the strip projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer.

4. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint condition also includes a third weak constraint condition, which is: the chip module projection area avoids the resistance projection area. The resistance projection area is the target half-area where the strip installation area is located in the two half-areas obtained by dividing the target surface of the bearing layer by the vertical central axis. The location area of ​​the chip module projection area is the area that does not overlap with the antenna projection area and the resistance projection area in the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the bearing layer.

5. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint condition also includes a second weak constraint condition, which is: the chip module projection area avoids the central axis of the target surface of the carrier layer, and the location area of ​​the chip module projection area is: the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area and the imprinted projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer.

6. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint condition also includes a third weak constraint condition, which is: the chip module projection area avoids the resistance projection area. The resistance projection area is the target half-area where the strip installation area is located in the two half-areas obtained by dividing the target surface of the bearing layer by the vertical central axis. The location area of ​​the chip module projection area is the area that does not overlap with the antenna projection area, the imprinting projection area and the resistance projection area in the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area and the left and right edges of the bearing layer.

7. The dual-interface smart card substrate layer as described in claim 3, characterized in that, The target constraint condition also includes a third weak constraint condition, which is: the chip module projection area avoids the resistance projection area. The resistance projection area is the target half-area where the strip mounting area is located in the two half-areas obtained by dividing the target surface of the bearing layer by the vertical central axis. The location area of ​​the chip module projection area is the area that does not overlap with the resistance projection area in the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the bearing layer; and the chip module projection area does not overlap with the central axis of the target surface of the bearing layer.

8. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint conditions also include a second weak constraint condition and a third weak constraint condition. The second weak constraint condition is that the chip module projection area avoids the central axis of the target surface of the carrier layer. The third weak constraint condition is that the chip module projection area avoids the resistance projection area. The resistance projection area is the target half-area where the strip mounting area is located in the two half-areas divided by the vertical central axis of the target surface of the carrier layer. The location area of ​​the chip module projection area is the area formed by the lower edge of the magnetic strip projection area, the upper edge of the embossed projection area, and the left and right edges of the carrier layer, which does not overlap with the antenna projection area, the imprinted projection area, and the resistance projection area; and the chip module projection area does not overlap with the central axis of the target surface of the carrier layer.

9. The dual-interface smart card substrate layer as described in claims 1-8, characterized in that, The antenna winding uses a full-size coil, a 3 / 4-size coil, or a 2 / 3-size coil.

10. The dual-interface smart card substrate layer as described in claims 1-8, characterized in that, The antenna winding uses a half-size coil.

11. The dual-interface smart card substrate layer as described in claim 9, characterized in that, The antenna projection area does not overlap with the strip projection area.

12. The dual-interface smart card substrate layer as described in claim 9, characterized in that, The antenna and the first connection structure are arranged in different layers, and the antenna projection area overlaps with the strip projection area.

13. The dual-interface smart card substrate layer as described in claim 10, characterized in that, The antenna projection area overlaps with the strip projection area.

14. The dual-interface smart card substrate layer as described in claim 10, characterized in that, The plurality of orthographic projection regions also include a first connecting structure projection region, wherein the antenna projection region does not overlap with the strip projection region, and the first connecting structure projection region overlaps with the antenna projection region.

15. The dual-interface smart card substrate layer as described in claim 10, characterized in that, The plurality of orthographic projection regions also include a first connecting structure projection region and an antenna lead projection region. The antenna projection region does not overlap with the strip projection region, and the first connecting structure projection region does not overlap with the antenna projection region, while the antenna lead projection region overlaps with the antenna projection region.

16. A dual-interface smart card, characterized in that, Includes a strip module and a dual-interface smart card substrate layer as described in claims 1-15; The strip module is carried by the dual-interface smart card substrate layer.

Images