Service system, input / output box, device box, and box identification method

Abstract

The present application relates to the technical field of computers. Provided in the embodiments are a service system, an input / output box, a device box, and a box identification method. The service system comprises an input / output box and a device box, the input / output box comprising first pluggable connectors, the device box comprising second pluggable connectors, and the second pluggable connectors being coupled to the first pluggable connectors. The device box further comprises a plurality of identifier components, the identifier components being coupled to the second pluggable connectors. The identifier components are used to manage identification information of the second pluggable connectors coupled thereto, the identification information indicating the type and quantity of the device box. The input / output box scans the plurality of first pluggable connectors, reads the identification information managed by the identifier components, and identifies the type and quantity of the device box on the basis of the identification information. The system uses the identifier components to manage the identification information which represents the type and quantity of the device box, such that the input / output box can accurately identify the type and quantity of the device box.

Description

Service system, input / output chassis, equipment chassis, and chassis identification methods

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410921330.8, filed on July 10, 2024, entitled “Service System, Input / Output Chassis, Equipment Chassis and Chassis Identification Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a service system, an input / output chassis, a device chassis, and a chassis identification method. Background Technology

[0004] Converged architecture decouples the system into independent modules such as computing resource pools, memory resource pools, and I / O (Input / Output) device resource pools. This facilitates flexible configuration and rapid upgrades of key devices such as CPUs (Central Processing Units), memory, GPUs (Graphics Processing Units), and SSDs (Solid State Disks or Solid State Drives). In a converged architecture, all I / O resources within a rack are centralized in an I / O Box. End devices are mounted under the I / O Box via CDFP connectors (CDFP connectors, short for 400Gb / s (16 x 25Gb / s) Pluggable Transceivers, i.e., 16-way pluggable connectors). Management software can allocate I / O resources based on the actual device access situation. However, this completely decoupled multi-chassis design presents challenges for the overall system's ID (identifier) ​​recognition. Taking SSD resource pools as an example, within a converged architecture, SSD resource pools exist as independent boxes. In actual use, customers will selectively mount one, two, or more SSD boxes under the IO box according to their own needs. Since these SSD boxes have identical physical structures, the CDFP connector itself does not have any extra pins for ID identification, meaning it cannot identify two or more SSD boxes. Summary of the Invention

[0005] To solve the above-mentioned technical problems, or at least partially solve them, embodiments of this application provide a service system based on a converged architecture, an input / output chassis, a device chassis, and a chassis identification method.

[0006] In a first aspect, an embodiment of the present application provides a service system. The service system includes an input / output chassis and at least one device chassis. The input / output chassis includes a plurality of first pluggable connectors, and the device chassis includes a plurality of second pluggable connectors. At least one of the second pluggable connectors is coupled to at least one of the first pluggable connectors;

[0007] The device chassis further includes a plurality of identification components, which are coupled to the second pluggable connectors. The identification components are used to manage the identification information of the second pluggable connectors to which they are coupled. The identification information is used to indicate the type and quantity of the device chassis;

[0008] The input / output chassis scans the plurality of first pluggable connectors, reads the identification information managed by the identification components under the second pluggable connectors coupled to each of the first pluggable connectors, and identifies the type and quantity of the device chassis according to the identification information.

[0009] In some embodiments of the present application, in response to reading the identification information, the input / output chassis determines whether there is the same identification information;

[0010] In response to determining that there is the same identification information, the input / output chassis determines the target device chassis corresponding to the same identification information, and sends a change command to at least one target device chassis. The change command instructs at least one target device chassis to change the identification information managed by the identification components included therein;

[0011] In response to receiving the change command, the target device chassis changes the identification information managed by the identification components included therein;

[0012] The input / output chassis rescans the plurality of first pluggable connectors to read the changed identification information, and identifies the quantity of the device chassis of the same type according to the changed identification information.

[0013] In some embodiments of the present application, the data width of the identification information is N bits. Among them, the k-th to m-th bits of the identification information are type bits, and the type bits are used to indicate the type of the device chassis; N is a positive integer greater than 1, 1 < k < m < N, and k and m are integers;

[0014] The input / output chassis identifies the type of the device chassis according to the value of the type bits of the identification information.

[0015] In some embodiments of the present application, the (m + 1)-th to (N - 1)-th bits of the identification information are quantity bits, and the quantity bits are used to distinguish device chassis of the same type.

[0016] In some embodiments of the present application, the input / output chassis generates a change command according to the quantity of the same identification information. The change command instructs to change the value of the specified bit in the quantity bits.

[0017] In some embodiments of this application, in response to determining that the number of identical identification information is 2, the input / output chassis generates a first change command, the first change command indicating the value of a first specified bit in the change quantity bit; the input / output chassis determines a first target device chassis and a second target device chassis among two target device chassis with identical identification information, and sends the first change command to the first target device chassis;

[0018] or,

[0019] In response to determining that the number of identical identification information is 3, the input / output chassis generates a first change command and a second change command, wherein the second change command indicates the value of the second specified bit in the change quantity bit; the input / output chassis determines the first target device chassis, the second target device chassis and the third target device chassis among the three target device chassis with identical identification information, and sends the first change command to the first target device chassis and the second change command to the second target device chassis;

[0020] or,

[0021] In response to determining that the number of identical identification information is 4, the input / output chassis generates a first change command, a second change command, and a third change command. The third change command indicates that the values ​​of the first specified bit and the second specified bit in the quantity bits are changed simultaneously. The input / output chassis determines the first target device chassis, the second target device chassis, the third target device chassis, and the fourth target device chassis among the four target device chassis with identical identification information, and sends the first change command to the first target device chassis, the second change command to the second target device chassis, and the third change command to the third target device chassis.

[0022] In some embodiments of this application, the 0th to (k-1)th bits of the identification information are interface bits, which are used to indicate the number of the second pluggable connector.

[0023] In some embodiments of this application, the input / output chassis further includes an identification component and a two-wire serial bus expansion component. The identification component is coupled to the two-wire serial bus expansion component, and the two-wire serial bus expansion component is coupled to the identification component and a plurality of first pluggable connectors, respectively. The two-wire serial bus expansion component expands one I2C channel of the identification component into multiple I2C channels, and couples the multiple I2C channels to the plurality of first pluggable connectors.

[0024] The identification component scans its I2C channel, reads the identification information managed by the identification component under the second pluggable connector coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.

[0025] In some embodiments of this application, the input / output chassis further includes a storage component and a multiplexer; the storage component is coupled to the multiplexer, and the multiplexer is coupled to the identification component and the baseboard management controller of the input / output chassis;

[0026] Before the device chassis type identification is completed, the identification component controls the multiplexer to close the data interaction link between the storage component and the baseboard management controller, and opens the data interaction link between the identification component and the storage component; in response to the completion of device chassis type identification, the identification component generates the system interconnect configuration relationship and writes the system interconnect configuration relationship into the storage component;

[0027] In response to writing the system interconnect configuration relationship to the storage component, the identification component controls the multiplexer to open the data interaction link between the storage component and the baseboard management controller, and notifies the baseboard management controller that the system interconnect configuration relationship has been written.

[0028] The baseboard management controller, in response to a notification from the identification component, obtains the system interconnect configuration relationship from the storage component.

[0029] In some embodiments of this application, the identification component includes a first identification component and a second identification component, and each second pluggable connector includes an input port and an output port, the input port being coupled to the first identification component and the output port being coupled to the second identification component;

[0030] The input / output chassis scans multiple first pluggable connectors and reads the identification information managed by the second identification component; if the same identification information exists, the target device chassis corresponding to the same identification information is determined, and a change command is sent to the first identification component of at least one target device chassis. The change command is used to instruct the first identification component to change the identification information managed by its corresponding second identification component; the second identification component corresponding to the first identification component is the second identification component coupled to the same second pluggable connector.

[0031] Upon receiving a change command, the first identification component changes the identification information managed by its corresponding second identification component;

[0032] The input / output chassis rescans multiple first pluggable connectors to read the modified identification information and identifies the number of chassis of the same type based on the modified identification information.

[0033] In some embodiments of this application, the address of the first identification component is a first fixed address, and the address of the second identification component is a second fixed address.

[0034] Secondly, embodiments of this application provide an input / output chassis coupled to at least one device chassis. The input / output chassis includes a plurality of first pluggable connectors, and the device chassis includes a plurality of second pluggable connectors. At least one second pluggable connector is coupled to at least one first pluggable connector. The device chassis also includes a plurality of identification components coupled to the second pluggable connectors. The identification components are used to manage identification information of the coupled second pluggable connectors, and the identification information is used to indicate the type and quantity of the device chassis.

[0035] The input / output chassis scans multiple first pluggable connectors, reads the identification information managed by the identification components under the second pluggable connectors coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.

[0036] Thirdly, embodiments of this application provide a device chassis coupled to an input / output chassis; the input / output chassis includes a plurality of first pluggable connectors, the device chassis includes a plurality of second pluggable connectors, and at least one second pluggable connector is coupled to at least one first pluggable connector;

[0037] The equipment chassis also includes multiple identification components coupled to a second pluggable connector. The identification components manage identification information of the coupled second pluggable connector, which indicates the type and quantity of the equipment chassis.

[0038] Fourthly, embodiments of this application provide a chassis identification method, characterized in that the method is applied to a service system provided in any embodiment of this application. The service system includes an input / output chassis and at least one device chassis. The input / output chassis includes a plurality of first pluggable connectors, and the device chassis includes a plurality of second pluggable connectors and a plurality of identification components. At least one second pluggable connector is coupled to at least one first pluggable connector, and the identification components are coupled to the second pluggable connectors.

[0039] The methods include:

[0040] In response to the power-on of the service system, multiple first pluggable connectors are scanned, and the identification information managed by the identification components under the second pluggable connectors coupled to each first pluggable connector is read. The type and quantity of the equipment chassis are identified based on the identification information.

[0041] Fifthly, embodiments of this application provide a computer program product, including a computer program, characterized in that the computer program, when executed by a processor, implements the chassis identification method of embodiments of this application.

[0042] Sixthly, embodiments of this application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement the chassis identification method of embodiments of this application when executing the programs stored in the memory.

[0043] In a seventh aspect, embodiments of this application provide a computer non-volatile storage medium storing a computer program thereon, which, when executed by a processor, implements the chassis identification method of embodiments of this application.

[0044] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0045] The service system of this application embodiment manages identification information representing the type and quantity of device chassis through an identification component. Input / output chassis scan their CDFP interfaces, read the identification information managed by the identification component within the chassis, and identify the type and quantity of the chassis based on this identification information. This allows the input / output chassis to accurately identify the type and quantity of the coupled chassis, thereby enabling data commands to be precisely sent to the desired chassis. If identical identification information is found among the identification information read by the input / output chassis, it indicates the presence of identical chassis. In this case, the input / output chassis needs to distinguish between these identical chassis by sending a change command to the identical chassis to modify the quantity bits of the identification information of a particular chassis. The input / output chassis then distinguishes between identical chassis based on the modified quantity bits of the identification information. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0047] Figure 1 shows a schematic diagram of the structure of the service system based on the converged architecture provided in an embodiment of this application;

[0048] Figure 2 shows a schematic diagram of the input / output chassis in the service system based on converged architecture provided in an embodiment of this application.

[0049] Figure 3 shows a schematic diagram of the input / output chassis in a service system based on a converged architecture provided in another embodiment of this application;

[0050] Figure 4 shows a schematic diagram of the device chassis in the service system based on converged architecture provided in an embodiment of this application.

[0051] Figure 5A shows a schematic diagram illustrating the connection relationship between the input / output chassis and the GPU chassis according to an embodiment of this application;

[0052] Figure 5B shows a schematic diagram illustrating the connection relationship between the input / output chassis and the GPU chassis according to another embodiment of this application;

[0053] Figure 6 shows a schematic diagram of the identification information of all the identification components coupled to the CDFP interface of the GPUBox;

[0054] Figure 7A shows a schematic diagram of the structure of a service system based on a converged architecture provided in another embodiment of this application;

[0055] Figure 7B shows a schematic diagram of the structure of the GPU Box 0 provided in an embodiment of this application;

[0056] Figure 7C shows a schematic diagram of the structure of the GPU Box 1 provided in an embodiment of this application;

[0057] Figure 8 shows a flowchart of the chassis identification method provided in an embodiment of this application;

[0058] Figure 9 shows a schematic diagram of the structure of the electronic device provided in an embodiment of this application. Detailed Implementation

[0059] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of this application, including various details to aid understanding. These embodiments should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application.

[0060] Figure 1 shows a schematic diagram of the structure of a service system based on a converged architecture provided in an embodiment of this application. As shown in Figure 1, the service system 100 based on a converged architecture includes an input / output chassis (IO Box) 101 and a device box 102. The device box 102 may include, but is not limited to, a GPU (Graphics Processing Unit) Box, an SSD (Solid State Disk or Solid State Drive) Box, and a memory box.

[0061] The input / output chassis 101 includes multiple first pluggable connectors 103 (CDFP connectors, short for 400Gb / s (16 x 25Gb / s) Pluggable Transceivers, i.e., 16-way pluggable connectors, hereinafter referred to as first CDFP interfaces). The device chassis 102 includes multiple second pluggable connectors 104 (hereinafter referred to as second CDFP interfaces). The first CDFP interfaces 103 and the second CDFP interfaces 104 are coupled. The device chassis 102 is coupled to the I / O chassis 101 through the first CDFP interfaces 103 and the second CDFP interfaces 104. In some embodiments of this application, the device chassis coupled to the I / O chassis can be one or multiple. Further, the multiple device chassis coupled to the I / O chassis can be of the same type, such as two GPU Boxes, or they can be of different types, such as two GPU Boxes and one SSD Box.

[0062] The device chassis 102 further includes a plurality of identification components 105. The identification components 105 are coupled to the second CDFP interface 104. In some embodiments of the present application, the number of the identification components 105 is the same as the number of the second CDFP interfaces 104, and the identification components 105 and the second CDFP interfaces 104 correspond to each other one by one. The identification component 105 is used to manage the identification information of the second CDFP interface to which it is coupled, and the identification information is used to indicate the type and quantity of the device chassis. The identification information corresponding to different types of device chassis is different. In some embodiments of the present application, the identification component may be a chip that converts an I2C signal into an IO signal, and has programmable GPIO (General-Purpose Input / Output) pins, and manages the identification information by controlling the high and low levels output by the GPIO pins. I2C (Inter-Integrated Circuit) is a multi-master, two-wire, low-speed serial communication bus, and the data transmitted by it is simply referred to as an I2C signal. In some embodiments of the present application, the data width of the identification information is N bits, where the kth to mth bits of the identification information are type bits, and the type bits are used to indicate the type of the device chassis. The IO chassis can identify the type of the device chassis according to the value of the type bits in the identification information. The (m + 1)th to (N - 1)th bits of the identification information are quantity bits, and the quantity bits are used to distinguish device chassis of the same type. The IO chassis can distinguish the same device chassis according to the value of the quantity bits in the identification information. The 0th to (k - 1)th bits of the identification information are interface bits, and the interface bits are used to indicate the number of the second CDFP interface. N is a positive integer greater than 1, 1 < k < m < N, and k and m are integers. As an example in some embodiments of the present application, the identification component is a PCA9554 chip. The PCA9554 chip has 8 programmable GPIO pins, and the identification information it manages is 8bit (bit). The 4th to 5th bits are type bits, which are used to distinguish different types of chassis. For example, if the 4th to 5th bits of the identification information are 10, then the identification information indicates that the type of the device chassis is GPU Box. If the 4th to 5th bits of the identification information are 01, then the identification information indicates that the type of the device chassis is SSD Box. If the 4th to 5th bits of the identification information are 11, then the identification information indicates that the type of the device chassis is Memory Box. The 6th to 7th bits are quantity bits, which are used to distinguish the same device chassis. The values of the 6th to 7th bits include 4 cases, which are: 00, 01, 10, 11. By default, the values of the 6th to 7th bits are 00. Four same device chassis can be distinguished by the values of the 6th to 7th bits. The 0th - 3rd bits are interface bits, which are used to distinguish the CDFP interfaces in the device chassis.

[0063] The IO chassis 101 scans the first CDFP interface 103, reads the identification information managed by the identification component 105 under the second CDFP interface 104 coupled to each first CDFP interface 103, and identifies the type of the device chassis 102 based on the identification information.

[0064] In some embodiments of this application, multiple device chassis of the same type may be coupled to an I / O chassis. In this case, the identification information read by the I / O chassis contains identical identification information. In response to determining the existence of identical identification information, the I / O chassis identifies the target device chassis corresponding to the identical identification information and sends a change command to at least one target device chassis. The change command instructs the target device chassis to change the identification information managed by its included identification component. For example, the change command instructs the target device chassis to change the value of the quantity bit in the identification information. In response to receiving the change command, the target device chassis changes the identification information managed by its included identification component, for example, changing the value of the quantity bit in the identification information. The I / O chassis rescans multiple first CDFP interfaces to read the changed identification information and distinguishes device chassis of the same type based on the changed identification information.

[0065] The service system of this application embodiment manages identification information representing the type and quantity of device chassis through an identification component. The IO chassis scans its CDFP interface, reads the identification information managed by the identification component within the chassis, and identifies the type and quantity of the device chassis based on this identification information. This allows the IO chassis to accurately identify the type and quantity of the coupled device chassis, thereby enabling data commands to be accurately sent to the desired device chassis. If the identification information read by the IO chassis contains identical identification information, it indicates the presence of identical device chassis. In this case, the IO chassis needs to distinguish between these identical device chassis by sending a change command to the identical device chassis to modify the quantity bit of the identification information of a certain device chassis. The IO chassis distinguishes between identical device chassis based on the modified quantity bit of the identification information.

[0066] In some embodiments of this application, the IO chassis generates a change command based on the number of identical identification information bits. This change command indicates a change to a specified bit in the quantity bits. The number of identical identification information bits represents the number of identical device chassis in the service system. In cases with different numbers of identical device chassis, it is necessary to change the identification information of different numbers of device chassis. For example, if there are two identical device chassis, and the identification information of one device chassis needs to be changed, the IO chassis can generate a change command to change the identification information of one of the device chassis. Therefore, in response to determining that the number of identical identification information bits is 2, the IO chassis generates a first change command. This first change command indicates a change to the value of a first specified bit in the quantity bits of the identification information (e.g., by default, the default values ​​of bits 6 and 7 in the identification information are both 0, and the first change command indicates changing the value of bit 6 in the identification information to 1). The IO chassis identifies a first target device chassis and a second target device chassis among the two target device chassis with identical identification information, and sends the first change command to the first target device chassis. The first target device chassis can be any one of the two target device chassis, or the first target device chassis and the second target device chassis can be determined according to a specified strategy. For example, the first target device chassis and the second target device chassis can be determined according to the numbering order of the second CDFP interfaces (the numbering order of the CDFP interfaces can be determined according to the value of the interface bit of the identification information), and the target device chassis corresponding to the later second CDFP interface is used as the first target device chassis.

[0067] In some embodiments of this application, when the service system has three identical device chassis, it is necessary to change the identification information of two of the device chassis. The IO chassis needs to generate two different change commands to change the identification information of the two device chassis, so that the three identical device chassis have three different identification information. Therefore, in response to determining that the number of identical identification information is 3, the IO chassis generates a first change command and a second change command. The first change command indicates changing the value of a first specified bit in the number bits of the identification information (for example, the default value of bits 6 and 7 in the identification information is 0 by default, and the first change command indicates changing the value of bit 6 in the identification information to 1), and the second change command indicates changing the value of a second specified bit in the number bits of the identification information (for example, the default value of bits 6 and 7 in the identification information is 0 by default, and the second change command indicates changing the value of bit 7 in the identification information to 1). The IO chassis identifies a first target device chassis, a second target device chassis, and a third target device chassis among the three target device chassis with identical identification information, sends the first change command to the first target device chassis, and sends the second change command to the second target device chassis. In some embodiments of this application, the IO chassis can determine the first target device chassis, the second target device chassis, and the third target device chassis according to the numbering order of the second CDFP interfaces. The target device chassis coupled to the last second CDFP interface is designated as the first target device chassis, the target device chassis coupled to the first second CDFP interface is designated as the third target device chassis, and the target device chassis coupled to the middle second CDFP interface is designated as the second target device chassis.

[0068] For example, in a service system with four identical device chassis, the identification information of three of the chassis needs to be changed. The I / O chassis needs to generate three different change commands to modify the identification information of two of the chassis, so that the four identical chassis have four different identification information. Therefore, in response to determining that the number of identical identification information is four, the I / O chassis generates a first change command, a second change command, and a third change command. The first change command instructs the user to change the value of the first specified bit in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the first change command instructs the user to change the value of bit 6 in the identification information to 1). The second change command instructs the user to change the value of the second specified bit in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the second change command instructs the user to change the value of bit 7 in the identification information to 1). The third change command instructs the user to change the values ​​of both the first and second specified bits in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the third change command instructs the user to change the values ​​of both bits 6 and 7 in the identification information to 1). The IO chassis identifies a first target device chassis, a second target device chassis, a third target device chassis, and a fourth target device chassis among four target device chassis with the same identification information, and sends the first change command to the first target device chassis, the second change command to the second target device chassis, and the third change command to the third target device chassis.

[0069] Figure 2 shows a schematic diagram of the structure of the IO chassis in the service system provided in the embodiment of this application. As shown in Figure 2, the IO chassis 200 includes a first pluggable connector 201 (hereinafter referred to as the first CDFP interface), an identification component 202, and a two-wire serial bus expansion component 203 (hereinafter referred to as the I2C expansion component).

[0070] The identification component 202 is coupled to the I2C expansion component 203. The I2C expansion component 203 is coupled to the identification component 202 and multiple first CDFP interfaces 201. The I2C expansion component 203 expands one I2C channel of the identification component 202 into multiple I2C channels, and couples the multiple I2C channels to the multiple first CDFP interfaces 201. The first CDFP interfaces 201 are coupled to the second CDFP interface of the device chassis (refer to Figure 1).

[0071] In this embodiment, the identification component 202, acting as the task initiator of the ID identification process within the I / O chassis, scans its I2C channels, reads the identification information managed by each identification component, and identifies the type of the device chassis based on the identification information. As an example in some embodiments of this application, the identification component 202 is a CPLD. CPLD (Complex Programmable Logic Device) is short for Complex PLD, a type of digital integrated circuit where the logic functions are constructed by the user according to their own needs.

[0072] I2C expansion component 203 expands the CPLD's single I2C channel into multiple I2C channels, and connects each of these multiple I2C channels to a different first CDFP interface. To ensure that each first CDFP interface corresponds to a specific I2C channel, multiple I2C expansion components are required within the entire I / O chassis. This ensures that during installation, regardless of which first CDFP interface the device is plugged into or whether it is plugged in sequentially, it can be effectively recognized by the CPLD of the I / O chassis through a specific I2C channel.

[0073] In this embodiment, the type and number of device chassis coupled to the IO chassis are identified by the identification component, eliminating the need for the baseboard management controller inside the IO chassis to perform identification, thus improving the identification speed of the service system. In addition, the baseboard management controller does not participate in the process of identifying device chassis, which can avoid the problem of abnormal system configuration identification when the baseboard management controller fails.

[0074] Figure 3 shows a schematic diagram of the structure of the IO chassis of the service system provided in this application embodiment. As shown in Figure 3, based on the IO chassis shown in Figure 2, the IO chassis further includes a storage component 204, a multiplexer 205, and a baseboard management controller 206. The storage component 204 is coupled to the multiplexer 205, and the multiplexer 205 is coupled to the identification component 202 and the baseboard management controller 206 of the IO chassis.

[0075] Before the device chassis type identification is completed, the identification component 202 controls the multiplexer 205 to close the data interaction link between the storage component 204 and the baseboard management controller 206, and opens the data interaction link between the identification component 202 and the storage component 204. In response to the completion of device chassis type identification, the identification component 204 generates a system interconnect configuration relationship and writes it to the storage component 204. This system interconnect configuration relationship indicates the type and number of device chassis coupled to the I / O chassis, as well as the coupling relationship between the first CDFP interface and the second CDFP interface.

[0076] In response to writing the system interconnect configuration relationship to the storage component, the identification component 202 controls the multiplexer 205 to open the data interaction link between the storage component 204 and the baseboard management controller 206, and notifies the baseboard management controller 206 that the system interconnect configuration relationship has been written. For example, the identification component controls the MUX_SEL signal to open the data interaction link between the storage component and the baseboard management controller, and notifies the baseboard management controller to obtain the system interconnect configuration relationship of the storage component through the ID_READY signal.

[0077] In response to a notification from the identification component 202, the baseboard management controller 206 obtains the system interconnect configuration relationship from the storage component 204.

[0078] In this embodiment, before the chassis device identification is completed, the data interaction link between the baseboard management controller and the storage component is disconnected via a multiplexer, preventing the baseboard management controller from reading the system interconnect configuration relationship before the chassis device identification is complete. After the chassis device identification is completed, the data interaction link between the baseboard management controller and the storage component is reopened via a multiplexer, enabling the baseboard management controller to read the complete system interconnect configuration relationship, thus ensuring the integrity and accuracy of the system interconnect configuration relationship read by the baseboard management controller.

[0079] Figure 4 shows a schematic diagram of the equipment chassis of the service system according to an embodiment of this application. As shown in Figure 4, each second CDFP interface of the equipment chassis includes an input port and an output port. The input port is coupled to a first identification component, and the output port is coupled to a second identification component. The second identification component manages identification information representing the type and quantity of the equipment chassis, and the first identification component is used to configure the identification information managed by the second identification component.

[0080] The IO chassis scans multiple first CDFP interfaces and reads the identification information managed by the second identification component. If the same identification information exists, the IO chassis determines the target device chassis corresponding to the same identification information and sends a change command to the first identification component of at least one target device chassis. The change command is used to instruct the first identification component to change the identification information managed by its corresponding second identification component. The second identification component corresponding to the first identification component is the second identification component coupled to the same second CDFP interface.

[0081] Upon receiving a change command, the first identification component changes the identification information managed by its corresponding second identification component.

[0082] The IO chassis rescans multiple first CDFP interfaces, reads the identification information managed by the second identification component, and identifies the type of device chassis based on the identification information.

[0083] In some embodiments of this application, the address of the first identification component is a first fixed address, and the address of the second identification component is a second fixed address. Setting the first and second identification components to fixed addresses respectively ensures that the I / O chassis can read the identification information when the device chassis is coupled to any CDFP interface of the I / O chassis.

[0084] To facilitate understanding of the service system based on a converged architecture according to the embodiments of this application, the following description is provided with reference to the examples shown in Figures 5A, 5B, 6, 7, and 8. Figures 5A and 5B respectively illustrate a coupling relationship between the GPU Box and the IO Box. Figure 6 shows a schematic diagram of the identification information managed by the identification components coupled to all CDFP interfaces of the GPU Box. Figure 7 shows a schematic diagram of a service system based on a converged architecture. Figure 8 shows a flowchart illustrating the chassis identification method provided in the embodiments of this application.

[0085] In this embodiment, the IO Box serves as the IO resource management node for the entire service system. Its specific function is to expand, network, and allocate PCIe resources (high-speed serial computer expansion resources) from multiple different CPUs through eight PCIe Switch chips (high-speed serial computer expansion components) contained within the IO Box. The PCIe Switch chips provide expansion or aggregation capabilities, allowing more devices to connect to a single PCIe port. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect external devices. The entire IO Box ultimately provides 40 CDFP interfaces, each containing a set of high-speed PCIe 5.0 x16 IO signals.

[0086] A GPU Box is a container specifically designed to house standard PCIe GPUs. Each GPU Box can fully accommodate 16 standard PCIe GPUs. The GPU Box provides 16 CDFP interfaces, which are coupled to the IO Box. Figures 5A and 5B illustrate two different coupling relationships between the GPU Box and the IO Box. In Figure 5A, the CDFP0-0, CDFP0-1, CDFP0-2, and CDFP0-3 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP3 interfaces of GPU Box-1, respectively. Similarly, the CDFP4-0, CDFP4-1, CDFP4-2, and CDFP6-0 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of GPU Box-0, respectively. In Figure 5B, the CDFP0-2, CDFP0-3, CDFP0-4, and CDFP2-2 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of the GPU Box-1, respectively. Similarly, the CDFP4-2, CDFP4-3, CDFP4-4, and CDFP5-0 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of the GPU Box-0, respectively. As shown in Figures 5A and 5B, the 16 CDFP interfaces of the GPU Box can connect to any 16 of the 40 CDFP interfaces of the IO Box, without requiring a fixed connection order. The SSD Box is a container specifically designed to house NVMe U.2 hard drives. Each SSD Box can hold up to 24 drives. The SSD Box provides 6 CDFP interfaces, which are coupled to the IO Box. These 6 CDFP interfaces can connect to any 6 of the 40 CDFP interfaces of the IO Box, without requiring a fixed connection order. A Memory Box is a container specifically designed to hold memory. Inside, a CXL Controller chip (where CXL (Compute Express Link) is a high-speed serial protocol that allows for fast and reliable data transfer between different components within a computer system) converts CXL signals (the physical layer of the PCIe protocol) into memory signals, thus enabling memory sharing. Each Memory Box provides eight CDFP interfaces, which can interface with any eight of the 40 CDFP interfaces in the IO Box, without requiring a fixed insertion order.

[0087] In the service system of this embodiment, the IO Box provides 40 CDFP interfaces, which can couple up to 4 GPU Boxes. The 4 GPU Boxes can be distinguished using 2-bit quantity bits. The device chassis may include GPU Boxes, Memory Boxes, and SSD Boxes, which can be distinguished using 2-bit type bits. GPU Boxes include the most CDFP interfaces (16 CDFP interfaces), which can be distinguished using 4-bit interface bits. Therefore, the identification information can be 8 bits. In some embodiments of this application, the identification component inside the device chassis can be a PCA9554 chip. For example, bits 7 and 6 of the PCA9554 are used as quantity bits (i.e., Box Number) to distinguish identical Boxes; these two bits default to 00. By using these two bits, 4 identical Boxes can be distinguished. Bits 5 and 4 are type bits used to distinguish different types of Boxes, thus enabling the IO Box to identify the device chassis type after a single scan. In this embodiment, bits 5 and 4 being 10 indicates that the device chassis type is a GPU Box. Bits 5 and 4 being 01 indicates that the device chassis type is an SSD Box. Bits 5 and 4 are both 11, indicating that the device chassis type is a Memory Box. Bits 3, 2, 1, and 0 are interface bits (i.e., CDFP Number bits), used to distinguish each CDFP interface. As an example, the identification information for GPU Box is shown in Table 1 below, the identification information for SSD Box is shown in Table 2 below, and the identification information for Memory Box is shown in Table 3 below.

[0088] Table 1:

[0089] Table 2:

[0090] Table 3:

[0091] Figure 6 shows the identification information managed by the identification component coupled to all CDFP interfaces of the GPUBox. Different CDFP interfaces are distinguished by the values ​​of the 0th to 3rd bits of the identification information. In Figure 6, "**100000" represents the 0th CDFP interface of the GPUBox (CDFP-0), "**100001" represents the 1st CDFP interface of the GPUBox (CDFP-1), and "**100010" represents the 2nd CDFP interface of the GPUBox (CDFP-2). The meanings of other identification information in Figure 6 are similar and will not be repeated here to avoid repetition.

[0092] Figure 7A shows a schematic diagram of the service system where two GPU Boxes are coupled to an IO Box. Figure 7B shows a schematic diagram of the GPU Box 0 provided in an embodiment of this application. Figure 7C shows a schematic diagram of the GPU Box 1 provided in an embodiment of this application. Referring to Figure 7A, taking two GPU Boxes as an example, the chassis identification principle in a scenario with multiple identical device chassis is explained. This solution is also applicable to other types of device chassis.

[0093] In Figure 7A, the CPLD in the IO Box is the identification component, acting as the task initiator for the chassis identification process. The PCA9548 is a two-wire serial bus expansion component. The PCA9548 expands the CPLD's single I2C channel into multiple channels, each connected to a different CDFP interface. To ensure that each CDFP interface corresponds to a specific I2C channel, multiple PCA9548s are required within the entire IO Box. This ensures that during installation, regardless of which CDFP interface the device is plugged into within the IO Box or whether it is plugged in sequentially, it can be effectively identified by the CPLD of the IO Box through a specific I2C channel.

[0094] In Figure 7A, a storage unit (FRU) and a multiplexer (MUX) are introduced between the CPLD in the IO Box and the Baseboard Management Controller (BMC). After the service system powers on, the CPLD in the IO Box is responsible for the entire chassis identification process. Before identification is complete, the multiplexer always switches the I2C connection of the FRU to the CPLD; after identification is complete, the CPLD first stores the complete system interconnect configuration relationship into the FRU, then controls the MUX_SEL signal to switch the I2C connection to the Baseboard Management Controller, and finally notifies the Baseboard Management Controller that the system interconnect configuration relationship of the storage unit can be obtained through the ID_READY signal.

[0095] In Figures 7B and 7C, each GPU Box's CDFP interface includes an input port and an output port. Each input and output port is coupled to one PCA9554. The PCA9554 acts as an identification component, managing the identification information of its coupled CDFP interface. The configuration and identification of the identification information are achieved through two PCA9554s paired with their internal CPLDs. These two PCA9554s are connected to the corresponding I2C channel of the CDFP. Referring to Figure 7, the output port of the CDFP interface is coupled to PCA9554 (1-0), and the input port is coupled to PCA9554 (1-A). PCA9554 (1-0) is used to manage the identification information. The I2C address of this type of PCA9554 is a fixed value: 0100001X throughout the entire GPU Box. PCA9554(1-A) is used to configure the identification information managed by PCA9554(1-0), such as configuring bits 7 and 6 of PCA9554(1-0). The I2C address of this type of PCA9554 is a fixed value: 0100010X throughout the GPU Box.

[0096] After the service system powers on, the CPLD inside the IO Box sequentially scans each I2C channel of the multiple PCA9548 chips beneath it. If its CDFP interface is already interconnected with the GPU Box's CDFP interface, the CPLD can scan for a PCA9554 with address 0100001X on that I2C channel. After scanning all 40 I2C channels, an IO CDFP <--> GPU CDFP mapping relationship is established and stored in the FRU. This allows identification of which ports of the IO Box are connected to which GPU within the GPU Box. If the IO Box is connected to different types of device chassis, and no chassis of the same type exist, the chassis identification process can be completed based on the type bit in the identification information.

[0097] When there are two GPU Boxes in the service system, the CPLD in the IO Box scans each I2C channel in sequence and finds that the same 8-bit identification information is read from two channels. At this time, the CPLD cannot determine which BOX the coupled GPU belongs to based on these same identification information. Therefore, the CPLD in the IO BOX will execute the next step: if the same identification information is read from two channels, it will send a command to the PCA9554 with address 0100010X through the I2C channel with the later sequence (for example, the PCA9554 (1-A) coupled to CDFP2 of GPU Box1), so that its IO[6] outputs 1 to the CPLD in the GPU Box. After the CPLD in GPU Box1 detects the change in IO level, it needs to pull all the IO[6] of the corresponding PCA9554 (1-1) and PCA9554 (1-2) high, that is, set bit6 of the identification information managed by PCA9554 (1-1) and PCA9554 (1-2) to 1. Subsequently, the CPLD within the IO Box scans the 40 I2C channels again to obtain the modified identification information. One set of identification information has a count bit (bits 7-6) of 00, while the other set has a count bit (bits 7-6) of 01, thus distinguishing the two identical GPU Boxes. The IO Box can then establish a system configuration management relationship, namely, a mapping relationship between IO CDFP and GPU Box 0CDFP, and GPU Box 1CDFP. The information is then stored in the storage component again, and the MUX_SEL and ID_READY signals are set. After the baseboard management controller finishes loading, the system configuration association is retrieved from the storage component.

[0098] Similarly, when there are three or four identical chassis devices, the identification process of the IO Box is similar, and will not be repeated here to avoid repetition.

[0099] Figure 8 shows a flowchart illustrating the chassis identification method provided in an embodiment of this application. Referring to the service system shown in Figure 7A, the chassis identification method includes:

[0100] 1) Couple at least one GPU Box to the CDFP interface of the IO Box. When the service system is powered on, the CPLD in the IO Box begins to identify the device chassis (in some embodiments of this application, the CPLD in the IO Box begins to identify the device chassis after a 5-second delay).

[0101] 2) The identification component CPLD in the IO Box scans all I2C channels where CDFP interfaces are located, and identifies all identification components PCA9554(1-0) and PCA9554(1-1) with address 0100001X in the GPU Box. The identification information of the identified PCA9554(1-0) and PCA9554(1-1) is read and summarized into the FRU.

[0102] 3) The identification component CPLD in the IO Box determines the number of duplicate identification information.

[0103] 4) If there is no duplicate identification information, it indicates that the current IO Box CDFP–GPU BOX CDFP mapping relationship (i.e., system interconnection configuration relationship) is unique.

[0104] 5) The identification component CPLD in the IO Box controls the MUX_SEL signal to switch the I2C connection to the BMC, and then notifies the BMC via the ID_READY signal. Upon receiving the notification, the BMC obtains the system interconnect configuration relationship from the FRU.

[0105] 6) If duplicate identification information exists, it indicates that the current IO Box CDFP–GPU BOX CDFP mapping relationship is not unique. In this case, the next step should be based on the number of duplicate identification information.

[0106] 7) If the number of duplicate identification information is 1 (i.e. there are two identical identification information), then: select any group of duplicate identification information and sort them according to the order of the I2C channels. Send a command to PCA9554 at address 0100010X through the second sorted channel, so that its IO[6] outputs 1 to the CPLD in the GPU Box. After the CPLD detects the change in the IO level of PCA9554 at address 0100010X, it pulls up all the signals of the corresponding PCA9554(1-0) and PCA9554(1-1)IO[6], that is, sets the 6th bit of the identification information of the corresponding PCA9554(1-0) and PCA9554(1-1) to 1.

[0107] 8) The CPLD in the IO BOX scans the 40 I2C channels again in sequence, rebuilds the mapping table, and then executes the operation in step 5) again.

[0108] 9) If the current number of duplicate IDs is 2 (i.e. there are three identical identification information), send a command to PCA9554 at address 0100010X through the second sorting channel, so that its IO[6] outputs 1 to the CPLD in the GPU Box. After the CPLD detects the change in the IO level of PCA9554 at address 0100010X, it pulls up all the signals of the corresponding PCA9554(1-0) and PCA9554(1-1) IO[6], that is, sets the 6th bit in the identification information of the corresponding PCA9554(1-0) and PCA9554(1-1) to 1, and sends a command to PCA9554 at address 0100010X through the third sorting channel, so that its IO[7] outputs 1 to the GPU. Inside the Box, the CPLD detects a change in the IO level of PCA9554 at address 0100010X. It then pulls all the signals corresponding to PCA9554(1-0) and PCA9554(1-1)IO[7] high, setting the 7th bit of the identification information of PCA9554(1-0) and PCA9554(1-1) to 1. Then, step 8 is repeated.

[0109] 10) If the current number of duplicate IDs is 3 (i.e. there are four identical identification information), send a command to PCA9554 at address 0100010X through the second sorting channel, so that its IO[6] outputs 1 to the CPLD in the GPU Box. After the CPLD detects the change in the IO level of PCA9554 at address 0100010X, it pulls up all the signals of the corresponding PCA9554(1-0) and PCA9554(1-1) IO[6], that is, sets the 6th bit in the identification information of the corresponding PCA9554(1-0) and PCA9554(1-1) to 1, and sends a command to PCA9554 at address 0100010X through the third sorting channel, so that its IO[7] outputs 1 to the GPU. Inside the Box, the CPLD detects a change in the IO level of PCA9554 at address 0100010X. It then pulls all the corresponding PCA9554(1-0) and PCA9554(1-1)IO[7] signals high. This means setting the 7th bit of the identification information of PCA9554(1-0) and PCA9554(1-1) to 1, and sending a command to PCA9554 at address 0100010X through the 4th channel of the sequence, causing its IO[6] and IO[7] to output 1 to the GPU. Inside the box, the CPLD detects a change in the IO level of PCA9554 at address 0100010X. It then pulls all the corresponding PCA9554(1-0) and PCA9554(1-1) IO[6] and IO[7] signals high, setting the 6th and 7th bits of the identification information for PCA9554(1-0) and PCA9554(1-1) to 1. Then, step 8 is repeated.

[0110] The service system based on fusion state provided in this application embodiment features a novel hardware topology, identification information definition method, and identification process designed based on the identification component CPLD and the identification component PCA9554. This solves the problem of identifying multiple device chassis with identical physical structures, enabling data commands to be accurately sent to the target device chassis. It can more quickly identify multiple identical device chassis and provide system interconnection configuration relationships. Moreover, the baseboard management controller only reads the system interconnection configuration relationships as a user and does not participate in the identification process, reducing the burden on the baseboard management controller, improving the system identification speed, and avoiding the problem of abnormal system configuration identification when the baseboard management controller fails.

[0111] Figure 9 shows a schematic diagram of the structure of an electronic device according to an embodiment of this application. As shown in Figure 9, the electronic device includes:

[0112] The system includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904. The processor 901, communication interface 902, and memory 903 communicate with each other via the communication bus 904.

[0113] Memory 903 is used to store computer programs;

[0114] The processor 901, when executing the program stored in the memory 903, implements the chassis identification method provided in the embodiments of this application.

[0115] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0116] The communication interface is used for communication between the aforementioned terminal and other devices.

[0117] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. In some embodiments of this application, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0118] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0119] In another embodiment provided in this application, a computer non-volatile storage medium is also provided, which stores instructions that, when run on a computer, cause the computer to perform any of the methods described in the above embodiments.

[0120] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the methods described in the above embodiments.

[0121] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer non-volatile storage medium or transmitted from one computer non-volatile storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer non-volatile storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0122] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0123] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A service system, characterized in that, The service system includes an input / output chassis and at least one device chassis. The input / output chassis includes a plurality of first pluggable connectors, and the device chassis includes a plurality of second pluggable connectors. At least one of the second pluggable connectors is coupled with at least one of the first pluggable connectors; The device chassis further includes a plurality of identification components. The identification components are coupled with the second pluggable connectors, and the identification components are configured to manage the identification information of the second pluggable connectors they are coupled with. The identification information is configured to indicate the type and quantity of the device chassis; The input / output chassis scans the plurality of first pluggable connectors, reads the identification information managed by the identification components under the second pluggable connectors coupled to each of the first pluggable connectors, and identifies the type and quantity of the device chassis according to the identification information.

2. The service system according to claim 1, characterized in that, In response to reading the identification information, the input / output chassis determines whether there is identical identification information; In response to determining that there is identical identification information, the input / output chassis determines the target device chassis corresponding to the identical identification information, and sends a change command to at least one of the target device chassis. The change command instructs at least one of the target device chassis to change the identification information managed by the identification components it includes; In response to receiving the change command, the target device chassis changes the identification information managed by the identification components it includes; The input / output chassis re-scans the plurality of first pluggable connectors to read the changed identification information, and identifies the quantity of the device chassis of the same type according to the changed identification information.

3. The service system according to claim 2, characterized in that, The data width of the identification information is N bits. Among them, the k-th to m-th bits of the identification information are type bits, and the type bits are configured to indicate the type of the device chassis; N is a positive integer greater than 1, 1 < k < m < N, and k and m are integers; The input / output chassis identifies the type of the device chassis according to the value of the type bits of the identification information.

4. The service system according to claim 3, characterized in that, The (m + 1)-th to (N - 1)-th bits of the identification information are quantity bits, and the quantity bits are configured to distinguish the device chassis of the same type.

5. The service system according to claim 4, characterized in that, The input / output chassis generates a change command according to the quantity of the identical identification information, and the change command instructs to change the value of a specified bit in the quantity bits.

6. The service system according to claim 5, characterized in that, In response to determining that the quantity of the identical identification information is 2, the input / output chassis generates a first change command, and the first change command instructs to change the value of the first specified bit in the quantity bits; the input / output chassis determines the first target device chassis and the second target device chassis among the 2 target device chassis with the identical identification information, and sends the first change command to the first target device chassis; [[ID=...]]Or, In response to determining that the number of identical identification information is 3, the input / output chassis generates a first change command and a second change command, wherein the second change command indicates that the value of a second specified bit in the number bits is changed; the input / output chassis determines a first target device chassis, a second target device chassis, and a third target device chassis among the three target device chassis with the same identification information, and sends the first change command to the first target device chassis and the second change command to the second target device chassis; or, In response to determining that the number of identical identification information is 4, the input / output chassis generates a first change command, a second change command, and a third change command. The third change command indicates that the values ​​of the first specified bit and the second specified bit in the quantity bits are changed simultaneously. The input / output chassis determines a first target device chassis, a second target device chassis, a third target device chassis, and a fourth target device chassis among the four target device chassis with the same identification information, and sends the first change command to the first target device chassis, the second change command to the second target device chassis, and the third change command to the third target device chassis.

7. The service system according to claim 4, characterized in that, The 0th to (k-1)th bits of the identification information are interface bits, which are configured to indicate the number of the second pluggable connector.

8. The service system according to claim 1, characterized in that, The input / output chassis further includes an identification component and a two-wire serial bus expansion component. The identification component is coupled to the two-wire serial bus expansion component, and the two-wire serial bus expansion component is coupled to the identification component and the plurality of first pluggable connectors, respectively. The two-wire serial bus expansion component expands one I2C channel of the identification component into multiple I2C channels, and couples the multiple I2C channels to the plurality of first pluggable connectors. The identification component scans its I2C channel, reads the identification information managed by the identification component under each of the first pluggable connector coupled to the second pluggable connector, and identifies the type and quantity of the device chassis based on the identification information.

9. The service system according to claim 8, characterized in that, The input / output chassis also includes a storage component and a multiplexer; the storage component is coupled to the multiplexer, and the multiplexer is coupled to the identification component and the baseboard management controller of the input / output chassis; Before the type identification of the device chassis is completed, the identification component controls the multiplexer to close the data interaction link between the storage component and the baseboard management controller, and opens the data interaction link between the identification component and the storage component; in response to the completion of the type identification of the device chassis, the identification component generates a system interconnection configuration relationship and writes the system interconnection configuration relationship into the storage component; In response to writing the system interconnect configuration relationship into the storage component, the identification component controls the multiplexer to open the data interaction link between the storage component and the baseboard management controller, and notifies the baseboard management controller that the system interconnect configuration relationship has been written. The baseboard management controller, in response to a notification from the identification component, obtains the system interconnect configuration relationship from the storage component.

10. The service system according to claim 9, characterized in that, The system interconnection configuration relationship indicates the type and number of device chassis coupled to the input / output chassis, as well as the coupling relationship between the first pluggable connector and the second pluggable connector.

11. The service system according to any one of claims 2-10, characterized in that, Each of the second pluggable connectors includes an input port and an output port, and the identification component includes a first identification component and a second identification component, the input port being coupled to the first identification component and the output port being coupled to the second identification component; The input / output chassis scans the plurality of first pluggable connectors and reads the identification information managed by the second identification component; if the same identification information exists, it determines the target device chassis corresponding to the same identification information and sends a change command to at least one of the first identification components of the target device chassis. The change command is configured to instruct the first identification component to change the identification information managed by the second identification component corresponding to it; the second identification component corresponding to the first identification component is a second identification component coupled to the same second pluggable connector. In response to receiving the change command, the first identification component changes the identification information managed by the corresponding second identification component; The input / output chassis rescans the plurality of first pluggable connectors to read the modified identification information and identifies the number of the same type of device chassis based on the modified identification information.

12. The service system according to claim 11, characterized in that, The address of the first identification component is a first fixed address, and the address of the second identification component is a second fixed address.

13. The service system according to claim 1, characterized in that, The identification component includes pins, and the identification component manages the identification information by outputting the level of the pins. The number of identification components is the same as the number of the second pluggable connectors, and the identification components correspond to the second pluggable connectors.

14. The service system according to claim 1, characterized in that, The input / output chassis includes multiple high-speed serial computer expansion components, which are used to expand, network, and allocate high-speed serial computer expansion resources from multiple different central processing units.

15. An input / output chassis, characterized in that, The input / output chassis is coupled to at least one device chassis. The input / output chassis includes a plurality of first pluggable connectors, and the device chassis includes a plurality of second pluggable connectors. At least one second pluggable connector is coupled to at least one first pluggable connector. The device chassis also includes a plurality of identification components coupled to the second pluggable connectors. The identification components are configured to manage identification information of the coupled second pluggable connectors, and the identification information is configured to indicate the type and quantity of the device chassis. The input / output chassis scans the plurality of first pluggable connectors, reads the identification information managed by the identification component under the second pluggable connector coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.

16. A device chassis, characterized in that, The device chassis is coupled to an input / output chassis; the input / output chassis includes a plurality of first pluggable connectors, the device chassis includes a plurality of second pluggable connectors, and at least one second pluggable connector is coupled to at least one first pluggable connector; The device chassis also includes multiple identification components coupled to the second pluggable connector. The identification components are configured to manage identification information of the coupled second pluggable connector, and the identification information is configured to indicate the type and quantity of the device chassis.

17. A chassis identification method, characterized in that, The method shall be configured as a service system according to any one of claims 1-14, the service system comprising an input / output chassis and at least one device chassis, the input / output chassis comprising a plurality of first pluggable connectors, and the device chassis comprising a plurality of second pluggable connectors and a plurality of identification components; At least one of the second pluggable connectors is coupled to at least one of the first pluggable connectors, and the identification component is coupled to the second pluggable connector. The method includes: In response to the power-on of the service system, the plurality of first pluggable connectors are scanned, and the identification information managed by the identification component under the second pluggable connector coupled to each first pluggable connector is read. The type and quantity of the device chassis are identified based on the identification information.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 17.

19. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, configured to store computer programs; When a processor is configured to execute a program stored in memory, it implements the steps of the method as described in claim 17.

20. A non-volatile computer storage medium storing a computer program thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in claim 17.

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