Chip-identifier-variable bus interface circuit and implementation method therefor, and electronic device

Abstract

A chip-identifier-variable bus interface circuit and an implementation method therefor. The bus interface circuit comprises a master radio frequency front-end chip and a slave radio frequency front-end chip; the slave radio frequency front-end chip comprises a VIO detection module and an MIPI module; proper connection and swapping of a power signal and a data signal are performed between the VIO detection module and the master radio frequency front-end chip; the VIO detection module generates a corresponding VIO-SEL signal on the basis of the power signal and the data signal, and inputs the VIO-SEL signal to the MIPI module; when a default chip identifier needs to be changed, the VIO-SEL signal is used to trigger the swapping between the power signal and the data signal, and a USID_SEL signal is generated by means of the VIO_SEL signal and is input to the MIPI module; and the MIPI module responds to the USID_SEL signal to generate a different default chip identifier. By means of the bus interface circuit, the radio frequency front-end chip can flexibly change its default product identifier and slave identifier by means of software or firmware configurations, without adding additional hardware pins.

Description

A bus interface circuit with variable chip identifier and its implementation method, and electronic equipment. Technical Field

[0001] This invention relates to a bus interface circuit that can change the default identifier of a chip, and also to the corresponding implementation method, belonging to the field of digital bus technology. Background Technology

[0002] With the rapid development of wireless communication technology, radio frequency (RF) front-end chips are increasingly widely used in smartphones and mobile devices. RF front-end chips typically include key components such as power amplifiers, low-noise amplifiers, filters, and antenna switches, which work together to ensure effective transmission and reception of wireless signals. However, due to the high requirements for miniaturization and integration in mobile devices, RF front-end chips face the challenge of a limited number of pads in their design. Pads are crucial interfaces connecting the chip's internal circuitry to external circuitry, and their limited number means that implementing more functions and connections within a confined space becomes increasingly difficult.

[0003] In multi-chip applications, such as Multiple-Input Multiple-Output (MIMO) systems, multiple RF front-end chips may need to be connected on the same bus. Each chip requires independent control and identification to enable precise system management and operation. This necessitates that each chip possess a unique identifier, including a Product Identifier (PID) and a Subsidiary Identifier (USID). The PID is typically assigned during product design to distinguish different models or series of products; while the USID is a unique identifier at the bus level, used to distinguish different slave devices on the same bus. In existing technologies, implementing such unique identification often requires additional hardware support or complex software configuration, which not only increases design complexity but may also affect system performance and reliability.

[0004] To address this issue, the industry has proposed several solutions. For example, some systems employ complex pin configuration and initialization processes to distinguish between different RF front-end chips. Chinese invention patent CN103226536B discloses a system and method for a bus interface. It provides a mechanism for changing the bus interface circuit address when input identities are interchanged, but its configuration method is relatively complex and lacks flexibility. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a bus interface circuit that can change the default identifier of a chip.

[0006] Another technical problem to be solved by the present invention is to provide a method for changing the default identifier of a chip using the bus interface circuit.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] According to a first aspect of the present invention, a bus interface circuit with variable chip identifier is provided, comprising a master radio frequency front-end chip and a slave radio frequency front-end chip; wherein,

[0009] The RF front-end chip includes a VIO detection module and a MIPI module; wherein, the VIO detection module and the main RF front-end chip perform positive connection and exchange of power signals and data signals, and the VIO detection module generates a corresponding VIO_SEL signal based on the power signal and the data signal, and inputs it into the MIPI module;

[0010] When it is necessary to change the chip default identifier, the VIO_SEL signal is used to trigger the exchange between the power signal and the data signal, and the USID_SEL signal is generated by the VIO_SEL signal and input to the MIPI module; the MIPI module generates different chip default identifiers in response to the USID_SEL signal.

[0011] Preferably, the VIO detection module uses the VIO_SEL signal generation circuit therein to generate the VIO_SEL signal;

[0012] The VIO_SEL signal generation circuit includes two transistors; the drain of each transistor is connected to one of the power supply signal and the data signal respectively; the gate is grounded through a pull-down resistor on one side and connected to the USID_SEL signal on the other side; the sources are connected in parallel to output the VIO_SEL signal.

[0013] Preferably, in the initial state, the gate of the transistor is pulled low by a pull-down resistor; when the voltage of the power signal or the data signal exceeds the threshold voltage of the transistor, the corresponding transistor is turned on, generating a corresponding USID_SEL signal, thereby allowing the identification and response to the power signal or the data signal.

[0014] Preferably, the VIO detection module uses the USID_SEL signal generation circuit therein to generate the USID_SEL signal;

[0015] The USID_SEL signal generation circuit includes two D flip-flops and two AND gate circuits; wherein, the VIO_SEL signal generates a POR signal through a power-on reset circuit, triggering the D flip-flops and causing the state of the clear signal to change; the clear signal generates the corresponding USID_SEL signal through a logical AND operation.

[0016] Preferably, the USID_SEL signal includes a first signal USID1 and a second signal USID2; wherein the first signal USID1 is generated by a logical AND operation of the clear signal A_LATCH of the first D flip-flop and the inverted clear signal B_LATCHN of the second D flip-flop, and the second signal USID2 is generated by a logical AND operation of the clear signal B_LATCH of the second D flip-flop and the inverted clear signal A_LATCHN of the first D flip-flop.

[0017] Preferably, the D flip-flop is replaced by a latch, an SR flip-flop, or a JK flip-flop.

[0018] Preferably, for RF front-end chips requiring readback functionality, during a write operation on the MIPI bus, the Sdata_i signal is processed by a shaping circuit and transmitted to the slave RF front-end chip, while the Sdata_oen signal is set high as a write enable; during a read operation on the MIPI bus, the Sdata_oen signal is set low, the path of the Sdata_i signal is closed, and the output path of the Sdata_o signal is activated, allowing the slave RF front-end chip to directly send data to the master RF front-end chip through the readback circuit.

[0019] In a preferred embodiment, for RF front-end chips that do not require readback functionality, the Sdata_o signal line and Sdata_oen signal control logic are omitted, and Sdata_i is used as a unidirectional input signal, directly output to the RF front-end chip.

[0020] According to a second aspect of the present invention, a method for changing the default identifier of a chip using the above-described bus interface circuit is provided, comprising the following steps:

[0021] (1) When the system starts up, the power signal and data signal are initialized to low level;

[0022] (2) The VIO detection module starts monitoring the externally input power signal and data signal, and generates the corresponding VIO_SEL signal;

[0023] (3) If it is necessary to change the chip default identifier, the VIO_SEL signal is used to trigger the exchange between the power signal and the data signal; wherein, the VIO_SEL signal generates a POR signal through the power-on reset circuit, triggers the D flip-flop, and generates the USID_SEL signal;

[0024] (4) The MIPI module generates different chip default identifiers in response to different combinations of the USID_SEL signal.

[0025] Preferably, in step (3), the USID_SEL signal is dynamically generated by a D flip-flop and an AND gate circuit based on the VIO_SEL signal, the POR signal and its inverted signal PORN, and is divided into a first signal USID1 and a second signal USID2.

[0026] Preferably, in step (4), the MIPI module generates corresponding product identifiers and subordinate identifiers in response to different combinations of the first signal USID1 and the second signal USID2.

[0027] Compared with existing technologies, the bus interface circuit and its implementation method provided in this invention can achieve different product identifiers and slave identifiers for the same product while maintaining a small module area of ​​the RF front-end chip, thereby significantly improving the flexibility and scalability of the RF front-end system. Furthermore, this invention reduces design complexity, shortens the design and testing cycle, and lowers costs. Using this invention, the default product identifier and slave identifier of the RF front-end chip can be changed through flexible configuration in software or firmware, effectively meeting the need for independent addressing and control of the RF front-end chip in multi-chip application scenarios. Attached Figure Description

[0028] Figure 1 is a schematic diagram of the bus architecture specified by the MIPI protocol;

[0029] Figure 2 is a simplified architectural diagram of the bus interface circuit with variable chip identifier provided by the present invention;

[0030] Figure 3 is a detailed interface diagram of the bus interface circuit with variable chip identifier provided by the present invention;

[0031] Figure 4 is a schematic diagram of the VIO_SEL signal generation circuit in an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of the USID_SEL signal generation circuit in an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of the Sdata_Driver circuit in an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of the logical relationship determination area between the VIO signal and the Sdata signal;

[0035] Figure 8 is a flowchart of the implementation method of changing the default identifier of a chip using the above-mentioned bus interface circuit provided by the present invention.

[0036] Figure 9 is a schematic diagram of an electronic device using the bus interface circuit with variable chip identifier provided by the present invention. Detailed Implementation

[0037] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0038] Figure 1 illustrates the bus architecture defined by the MIPI protocol. This architecture includes a radio frequency integrated circuit (RF IC) 100 and multiple front-end modules (FEMs) 110. The RF IC 100 is the central component of the entire RF front-end system, responsible for handling the main transceiver tasks of wireless signals. Internally, the RF IC 100 integrates a master RF front-end chip (the master chip in a master-slave architecture), responsible for generating control commands and transmitting them via the bus architecture. This bus architecture includes clock and data lines, which serve as the bridge for communication between the RF IC and the front-end modules. The RF IC 100 provides the clock signal (Sclk) via the Sclk line to ensure data synchronization and transmits the data signal (Sdata) via the Sdata line to transmit specific control commands. Additionally, VIO is the power signal, through which the RF IC 100 provides power to each front-end module 110.

[0039] The front-end module 110, which works in conjunction with the master, integrates a slave RF front-end chip (as a slave chip in a master-slave architecture) to receive control commands from the master. Each front-end module 110 has a unique ID, namely a slave identifier (USID), which allows the RF integrated circuit 100 to identify and control the corresponding front-end module through a specific USID. In this way, even if multiple front-end modules are connected to the same bus, the master can independently address and control them through their respective USIDs.

[0040] In the bus architecture shown in Figure 1, communication between the RF integrated circuit 100 and the front-end module 110 is accomplished through control commands. These commands include the configuration and control of various components in the front-end module, such as adjusting the operating state of the power amplifier, switching antenna switches, or changing the frequency of the filter. This approach allows for flexible management of complex RF signal paths, meeting the high-performance and high-efficiency requirements of modern mobile communications. Furthermore, since each RF front-end chip acting as a Slave in the front-end module 110 has a different USID, the master RF front-end chip can precisely control each front-end module, achieving fine-grained management of the RF front-end network. However, the chip identifiers (including but not limited to PID, USID, etc.) in the MIPI protocol are fixed by default, which is not conducive to flexible use in multi-chip application scenarios.

[0041] To address this, the embodiments of the present invention innovatively change the default chip identifier by exchanging power and data signals, thereby meeting the needs of MIPI devices in certain special scenarios. Compared to remaking a MIPI device with identical functionality except for the chip identifier, the present invention can reduce the design and testing time and cost by half. The following is a detailed description of the embodiments shown in Figures 2 to 7.

[0042] Figure 2 is a simplified architectural diagram of the bus interface circuit with variable chip identifiers provided in an embodiment of the present invention. As can be seen from Figure 2, the architecture of this bus interface circuit is similar to the bus architecture specified by the MIPI protocol. The main difference is that the master RF front-end chip and each slave RF front-end chip communicate only through the power signal line (VIO) and data line (Sdata) for the positive connection and swapping of power and data signals. Here, positive connection means that the power signal VIO and the data signal Sdata are transmitted through their respective lines. Swap refers to interchangeing the lines of the two signals, so that the line that originally transmitted the power signal VIO now transmits the data signal Sdata, and the line that originally transmitted the data signal Sdata now transmits the VIO signal. By swapping these two signals, configuration and control of each slave RF front-end chip can be achieved, such as changing the default identifiers (e.g., PID and USID) of the slave RF front-end chips.

[0043] Figure 3 is a detailed interface diagram of the bus interface circuit with variable chip identifier provided in an embodiment of the present invention. Each slave RF front-end chip 121 includes a VIO detection module 111 and a MIPI module 112. Their connection to the master RF front-end chip 120 is shown in Figure 3. The main task of the VIO detection module 111 is to monitor externally input VIO and Sdata signals. It has detection capabilities, can identify VIO and Sdata signals, and generate a discrimination signal USID_SEL based on these signals and its own logical operation results. The USID_SEL signal is a control signal, which is then sent to the MIPI module 112 to instruct it to take appropriate action.

[0044] According to the MIPI protocol, after the VIO signal is powered on, at least 120 nanoseconds must pass before control commands can be sent. During this time window, the Sclk and Sdata signals remain low. The VIO detection module 111 uses this characteristic to determine which signal was powered on first, thus identifying the VIO signal. Once the VIO signal is identified, the VIO detection module 111 can correctly process the subsequent Sdata signal, ensuring that data is received and processed by the MIPI module 112 in the correct timing.

[0045] The MIPI module 112's functions extend beyond implementing the MIPI protocol and fulfilling product requirements. It can also modify its own ID information based on the USID_SEL signal received from the VIO detection module 111. This includes modifying the Product Identifier (PID) and Slave Identifier (USID), enabling the slave RF front-end chip to respond to specific instructions from the master RF front-end chip, achieving more flexible configuration and control. Furthermore, the VIO detection module 111 is responsible for transmitting the Sdata signal output from the MIPI module 112 to the master RF front-end chip 120 through an internal selection path. This allows the master RF front-end chip to send appropriate control commands based on the slave RF front-end chip's status and needs, achieving precise management of the RF front-end device. This entire process ensures consistent communication between the master and slave RF front-end chips, meeting the RF front-end module's requirements for efficient and flexible control.

[0046] Figure 4 is a schematic diagram of the VIO_SEL signal generation circuit of the VIO detection module 111 in an embodiment of the present invention. As shown in Figure 4, the VIO_SEL signal generation circuit includes: two PMOS transistors, labeled MPO and MP1, and two pull-down resistors R0 and R1, each with a resistance of 51KΩ. The drains of these two transistors are connected to signal A and signal B, respectively; the gates are grounded through pull-down resistors R0 and R1, respectively, and receive output signals USID1 and USID2, respectively; the sources are connected in parallel to output the VIO_SEL signal. In one embodiment of the present invention, signal A represents the VIO signal received from the outside, and signal B represents the Sdata signal received from the outside, but it is not limited to this; signal A can also represent the Sdata signal received from the outside, and signal B can represent the VIO signal received from the outside.

[0047] The VIO_SEL signal generation circuit is responsible for identifying the power signal VIO and the data signal Sdata, and generating the control signal USID_SEL accordingly. This signal includes two status bits, USID1 and USID2. The circuit uses logic-controlled transistors MPO and MP1 to distinguish between signal A (VIO signal) and signal B (Sdata signal), determining their respective identities by comparing their voltage levels. Once the VIO signal is identified, the corresponding transistor (such as MPO) will conduct, allowing current to flow and affecting the states of USID1 and USID2. Initially, the transistor's gate is pulled low through resistors R0 and R1, ensuring the transistor is off. When the voltage of signal A or B exceeds the transistor's threshold voltage, the corresponding transistor will conduct. This will change the level state of USID1 or USID2, thereby allowing the identification and response to the VIO and Sdata signals.

[0048] Figure 5 shows the schematic diagram of the USID_SEL signal generation circuit in the VIO detection module 111. The core of this circuit consists of two D flip-flops (DFF_A and DFF_B), triggered by clock signals (CP and CPN), and two reset signals (A_LATCH and B_LATCH). Additionally, the circuit includes two inverters (PORN and A_LATCHN / B_LATCHN) to provide the required inverted signals. VSS and VSS_DIG in this circuit represent analog ground and digital ground, respectively, ensuring stable circuit operation and a correct signal reference.

[0049] In the initial state, the USID_SEL signals (USID1 and USID2) are in a high-impedance state, meaning they are not yet activated. Signals A and B have an initial voltage of 0 volts, representing the VIO and Sdata signals from the main RF front-end chip 120.

[0050] When signal A (representing the VIO signal) rises to 1.8V, the VIO_SEL signal also rises. The VIO_SEL signal, through a power-on reset (POR) circuit, generates a rising edge trigger signal. This rising edge triggers the D flip-flop, causing a change in the states of A_LATCH and B_LATCH. Specifically, when VIO_SEL rises to the threshold voltage of the MOSFET in the D flip-flop, DFF_A and DFF_B are triggered, A_LATCH goes high and B_LATCH goes low, and vice versa.

[0051] The states of A_LATCH and B_LATCH determine the values ​​of USID1 and USID2. USID1 is generated by a logical AND operation between A_LATCH and B_LATCHN, while USID2 is generated by B_LATCH and A_LATCHN. This means that if A_LATCH is high and B_LATCHN (the inverted form of B_LATCH) is also high, USID1 will be high; if B_LATCH is low and A_LATCHN (the inverted form of A_LATCH) is also low, USID2 will be low.

[0052] In addition, the circuit includes two pull-down resistors R0 and R1 (51KΩ), which provide an initial low level to the gates of transistors MP0 and MP1, ensuring that the transistors are off when there is no signal. The on-state of transistors MP0 and MP1 determines the final voltage of the VIO_SEL signal, keeping it consistent with signal A.

[0053] It should be noted that the D flip-flop in the above circuit can also be replaced by a latch, SR flip-flop, or JK flip-flop. In some cases, this helps reduce circuit complexity and cost. USID1 and USID2 can be combined into a single USID signal. This simplification reduces the number of required circuit components while maintaining the necessary functionality.

[0054] In summary, the circuit design in Figure 5 achieves accurate identification and response to VIO and Sdata signals through precise logic control and signal processing, thereby generating the USID_SEL signal that controls the behavior of the MIPI module 112.

[0055] Figure 6 is a schematic diagram of the Sdata_Driver circuit in an embodiment of the present invention. This circuit enables the main RF front-end chip 120 to flexibly control the flow of data signals and send data to the correct path according to the state of the MIPI module 112 and the selection of the USID_SEL signal.

[0056] The Sdata_Driver circuit is responsible for selectively routing the Sdata_o signal based on the USID_SEL signal. In this circuit, the VIO_SEL signal controls the routing of the data signal, while the Sdata_oen signal acts as an enable signal, controlling the data output. Specifically, this circuit receives the Sdata_o signal from the MIPI module 112, which is generated in response to control commands from the main RF front-end chip 120. The Sdata_i signal in the circuit is the result of a logical AND operation between signals A and B, representing the data signal input to the MIPI module 112. When the MIPI module 112 outputs the Sdata_o signal based on the USID_SEL signal, it simultaneously outputs a low-level Sdata_oen signal to the Sdata_Driver circuit.

[0057] The core of the Sdata_Driver circuit is a multiplexer (or selector) that determines whether to output Sdata_o to signal A or signal B based on the combination of the USID_SEL and Sdata_oen signals. If Sdata_oen is low, it indicates that the MIPI module 112 is ready to send data, and the Sdata_Driver will select the output path based on the state of the USID_SEL signal. If the USID_SEL signal indicates output to signal A, then Sdata_o will be routed to signal A; if the USID_SEL signal indicates output to signal B, then Sdata_o will be routed to signal B.

[0058] Additionally, the Sdata_Driver circuitry includes a VSS_DIG ground line, which provides a common reference level for the bus interface circuitry. The VIO_SEL signal can also serve as an additional control signal to ensure proper routing between power and data signals.

[0059] Optionally, in one embodiment of the present invention, for RF front-end chips requiring readback functionality, bidirectional data transmission and flexibility must be guaranteed. Therefore, the design of the Sdata signal allows for bidirectional data transmission. During a write operation on the MIPI bus, Sdata_i serves as the data input signal, processed by the shaping circuit, and transmitted to the slave RF front-end chip. Simultaneously, the Sdata_oen signal is set high as a write enable, ensuring that data can be received by the slave RF front-end chip. Conversely, during a read operation, the Sdata_oen signal is set low, the path of the Sdata_i signal is closed, and the output path of the Sdata_o signal is activated, allowing the slave RF front-end chip to directly send data to the master RF front-end chip via the readback circuit. This mechanism requires the Sdata_Driver circuit to dynamically route the Sdata_o signal to the correct path based on the Sdata_oen and USID_SEL signals.

[0060] In another embodiment of the invention, a simplified technical solution can be adopted for RF front-end chips that do not require readback functionality. In this solution, the parts of the Sdata_Driver circuit related to the Sdata_o signal output are omitted, including the Sdata_o signal line and the Sdata_oen signal control logic. Thus, the Sdata_i signal no longer needs the Sdata_oen signal enable, but instead acts as a continuous unidirectional input signal, directly output to the slave RF front-end chip. This solution simplifies the circuitry and signal lines required for readback, simplifying circuit design and reducing costs. However, the above solution is only applicable to applications requiring only unidirectional data transmission. For products requiring bidirectional data transmission, the complete Sdata signal transmission mechanism must be retained.

[0061] Figure 7 shows the logical relationship determination area between the VIO signal and the Sdata signal, used to determine which of signals A and B is the VIO signal and which is the Sdata signal.

[0062] Initially, both signals A and B have a voltage of 0 volts. As signal A (representing the VIO signal) slowly rises to the 1.8V voltage range, the VIO_SEL signal also rises. The rise of the VIO_SEL signal triggers a power-on reset (POR) circuit, which generates a POR signal that indicates the system is powered on and ready to start operation.

[0063] The rise of the VIO_SEL signal is also associated with two key logic signals: A_LATCH and B_LATCH. A_LATCH captures the state of signal A, while B_LATCH captures the state of signal B. These two signals, along with their inverted counterparts (A_LATCHN and B_LATCHN), are used to generate two USID_SEL signals: USID1 and USID2. These signals then control the states of transistors MP0 and MP1, which in turn affect the final voltage of the VIO_SEL signal.

[0064] Specifically, when the VIO_SEL signal rises to the threshold voltage of the MOSFET in the D flip-flop, DFF_A and DFF_B are triggered. This causes the A_LATCH signal to go high and the B_LATCH signal to go low, or vice versa, depending on the relative timing of signals A and B. Then, USID1 is generated by a logical AND operation between the A_LATCH and B_LATCHN signals, while USID2 is generated by the B_LATCH and A_LATCHN signals. If the A_LATCH signal is high and the B_LATCHN signal is also high, USID1 will be high; if the B_LATCH signal is low and the A_LATCHN signal is also low, USID2 will be low.

[0065] The body diode of transistor MP0 turns on when signal A rises, thus keeping the voltage of the VIO_SEL signal consistent with that of signal A. As the VIO_SEL signal rises, the gate-to-source voltage (|VGS|) of MP0 increases, causing transistor MP0 to turn on further. Meanwhile, transistor MP1 is turned off because |VGS| is 0 volts, therefore the state of signal B (representing the Sdata signal) does not affect the output of the VIO_SEL signal.

[0066] Ultimately, the VIO_SEL signal ensures that the VIO and Sdata signals can be correctly identified and processed, providing the necessary signal status information for the subsequent operation of the MIPI module 112.

[0067] Based on the bus interface circuit described above, this embodiment of the invention further provides a method for changing the default identifier of a chip using the bus interface circuit. As shown in Figure 8, this method includes at least the following steps:

[0068] (1) When the system starts up, the power signal VIO and the data signal Sdata are initialized to low level;

[0069] (2) The VIO detection module 111 starts monitoring the externally input VIO signal and Sdata signal, and generates the corresponding VIO_SEL signal;

[0070] Specifically, once the VIO signal starts to rise, the VIO detection module 111 identifies the VIO signal and generates the corresponding VIO_SEL signal.

[0071] (3) If it is necessary to change the default identifier of the chip (such as PID and USID), use the VIO_SEL signal to trigger the switching operation, so that the line that originally transmitted the VIO signal now transmits the Sdata signal, and vice versa; among them, the VIO_SEL signal generates a rising edge trigger signal through the POR circuit, which triggers the D flip-flop to generate the USID_SEL signal.

[0072] (4) The MIPI module 112 generates different chip default identifiers according to different combinations of the USID_SEL signal.

[0073] Once the USID_SEL signal stabilizes, the master RF front-end chip and each slave RF front-end chip will operate according to the new configuration, at which point the chip's default identifier has been changed.

[0074] The following section, in conjunction with the interaction process between the main RF front-end chip 120, the VIO detection module 111, and the MIPI module 112 shown in Figures 2 to 7, details the specific steps of the above implementation method:

[0075] First, the main RF front-end chip 120 outputs VIO and Sdata signals. Here, we assume signal A represents the VIO signal and signal B represents the Sdata signal, both initially at 0 volts. The VIO_SEL signal is controlled by signal A; when signal A rises to 1.8V, the VIO_SEL signal also rises. The VIO_SEL signal generates a POR signal through a power-on reset (POR) circuit. In Figure 4, two transistors, MP0 and MP1, receive a low level through pull-down resistors R0 and R1. When the VIO signal (signal A) rises, transistor MP0 turns on, and the voltage of the VIO_SEL signal rises to match that of signal A. At this time, the USID_SEL signal is dynamically generated by a D flip-flop and AND gate circuit based on the VIO_SEL signal, the POR signal, and its inverted signal PORN, and is divided into two signals, USID1 and USID2. These signals control the on / off states of transistors MP0 and MP1, ultimately ensuring that the VIO_SEL voltage matches that of signal A.

[0076] Next, signals A and B are ANDed to generate the Sdata_i signal, which is then sent to the MIPI module 112. The MIPI module 112 responds to the corresponding read command based on the USID_SEL signal and generates the Sdata_o signal, which is output to the Sdata_Driver circuit. The Sdata_Driver circuit determines whether to output the Sdata_o signal to signal A or signal B based on the USID_SEL and Sdata_oen signals. When VIO is high, the Sdata signal is shaped to generate the Sdata_i signal so that the MIPI module 112 can correctly recognize and respond to it.

[0077] As the VIO signal (signal A) rises to 1.8V, the VIO_SEL signal also rises to the threshold voltage of the MOSFET in the D flip-flop, triggering DFF_A and DFF_B. This results in the generation of USID1 and USID2 signals, which are synchronized with the VIO_SEL signal and ground, respectively. USID1 is generated by a logical AND operation between A_LATCH and B_LATCHN, while USID2 is generated by B_LATCH and A_LATCHN. As long as signal A remains powered on, the POR signal will remain high, thus stabilizing the USID_SEL signal.

[0078] Next, the MIPI module 112 generates different PIDs and USIDs based on different combinations of the USID_SEL signal. As shown in Figure 7, when USID1 is 0 and USID2 is 1, the MIPI module 112 responds with a set of PIDs and USIDs; conversely, it does not. For example, if the PID consists of a 6-bit basic code and two bits, USID1 and USID2, then different PIDs and USIDs can be obtained based on different USID1 and USID2 states.

[0079] In one embodiment of the invention, it is assumed that the PID consists of a 6-bit basic code and a 2-bit USID status bit. Initially, both USID1 and USID2 are inactive. If USID1 becomes 0 and USID2 becomes 1, the MIPI module 112 will respond to this specific USID combination. For example, if the basic code is 100011, then combining USID1 = 0 and USID2 = 1, the final PID might be represented as 8'b100011, and the USID might be represented as 4'b00 (assuming the first two bits of the USID are fixed). If the states of USID1 and USID2 are interchanged, i.e., USID1 becomes 1 and USID2 becomes 0, the MIPI module 112 will recognize the different combination and respond to another set of PID and USID. In this case, the basic code 100011 combined with USID1 = 1 and USID2 = 0, the final PID might become 8'b100111, and the USID might become 4'b01.

[0080] In another application scenario, if more detailed differentiation between multiple RF front-end chips is required, more encoding bits may be used. For example, if the PID consists of an 8-bit code, with 6 bits being the basic code and the remaining 2 bits being the USID status bits, when both USID1 and USID2 are 1, combined with the basic code 101010, the PID might be represented as 8'b1010101, and the USID might be represented as 4'b11, suitable for a specific configuration of the RF front-end chip. For RF front-end chips with different hardware versions, different PID codes may be needed for differentiation. Assuming the basic code is 110100, when USID1 is 0 and USID2 is 1, a hardware version can be assigned PID 8'b1101000 and USID 4'b01; while when USID1 is 1 and USID2 is 0, another hardware version can be assigned PID 8'b1101100 and USID 4'b10.

[0081] The working principle of the variable chip identifier bus interface circuit and its implementation method provided by the present invention has been described in detail above. Based on the above-mentioned variable chip identifier bus interface circuit, embodiments of the present invention further provide an electronic device, including the above-mentioned variable chip identifier bus interface circuit. This bus interface circuit, as an important component of radio frequency communication components, is used to realize communication control in transmission and / or reception-related components. The electronic device referred to here refers to computer devices that can be used in mobile environments and support multiple communication standards such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, and NR, including mobile phones, laptops, tablets, and in-vehicle computers. Furthermore, the technical solution provided by the present invention is also applicable to other bus interface circuit applications, such as communication base stations and intelligent connected vehicles.

[0082] As shown in Figure 9, this electronic device includes at least a processor, a memory, and a communication component. It may further include a sensor component, a power supply component, a multimedia component, and an input / output interface, depending on actual needs. The memory, communication component, sensor component, power supply component, multimedia component, and input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can be implemented using general-purpose components and will not be specifically described here.

[0083] It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0085] The above provides a detailed description of the variable chip identifier bus interface circuit and its implementation method provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A bus interface circuit with variable chip identifier, comprising a master RF front-end chip and a slave RF front-end chip, characterized in that: The RF front-end chip includes a VIO detection module and a MIPI module; wherein, the VIO detection module and the main RF front-end chip perform positive connection and exchange of power signals and data signals, and the VIO detection module generates a corresponding VIO_SEL signal based on the power signal and the data signal, and inputs it into the MIPI module; When it is necessary to change the chip default identifier, the VIO_SEL signal is used to trigger the exchange between the power signal and the data signal, and the USID_SEL signal is generated by the VIO_SEL signal and input to the MIPI module; the MIPI module generates different chip default identifiers in response to the USID_SEL signal.

2. The bus interface circuit as described in claim 1, characterized in that, The VIO detection module uses its VIO_SEL signal generation circuit to generate the VIO_SEL signal; The VIO_SEL signal generation circuit includes two transistors; the drain of each transistor is connected to one of the power supply signal and the data signal respectively; the gate is grounded through a pull-down resistor on one side and connected to the USID_SEL signal on the other side; the sources are connected in parallel to output the VIO_SEL signal.

3. The bus interface circuit as described in claim 2, characterized in that: In the initial state, the gate of the transistor is pulled low by a pull-down resistor; when the voltage of the power signal or the data signal exceeds the threshold voltage of the transistor, the corresponding transistor turns on and generates the corresponding USID_SEL signal, thereby allowing the identification and response to the power signal or the data signal.

4. The bus interface circuit as described in claim 1, characterized in that, The VIO detection module uses its USID_SEL signal generation circuit to generate the USID_SEL signal. The USID_SEL signal generation circuit includes two D flip-flops and two AND gate circuits; wherein, the VIO_SEL signal generates a power-on reset (POR) signal through the power-on reset circuit, triggering the D flip-flops and causing the state of the clear signal to change; the clear signal generates the corresponding USID_SEL signal through a logical AND operation.

5. The bus interface circuit as described in claim 4, characterized in that: The USID_SEL signal includes a first signal (USID1) and a second signal (USID2); wherein, the first signal (USID1) is generated by a logical AND operation between the clear signal (A_LATCH) of the first D flip-flop and the inverted clear signal (B_LATCHN) of the second D flip-flop, and the second signal (USID2) is generated by a logical AND operation between the clear signal (B_LATCH) of the second D flip-flop and the inverted clear signal (A_LATCHN) of the first D flip-flop.

6. The bus interface circuit as described in claim 4, characterized in that: The D flip-flop can be replaced by a latch, an SR flip-flop, or a JK flip-flop.

7. The bus interface circuit as described in claim 1, characterized in that: During a write operation on the MIPI bus, the Sdata_i signal is processed by the shaping circuit and then transmitted to the slave RF front-end chip. At the same time, the Sdata_oen signal is set high as a write enable. During a read operation on the MIPI bus, the Sdata_oen signal is set low, the path of the Sdata_i signal is closed, and the output path of the Sdata_o signal is activated, allowing the slave RF front-end chip to send data directly to the master RF front-end chip through the readback circuit.

8. The bus interface circuit as described in claim 1, characterized in that: The Sdata_o signal line and Sdata_oen signal control logic are omitted, and the Sdata_i signal is used as a unidirectional input signal and directly output to the RF front-end chip.

9. A method for changing the default identifier of a chip using the bus interface circuit according to any one of claims 1 to 8, characterized in that, Includes the following steps: (1) When the system starts up, the power signal and data signal are initialized to low level; (2) The VIO detection module starts monitoring the externally input power signal and data signal, and generates the corresponding VIO_SEL signal; (3) If it is necessary to change the chip default identifier, the VIO_SEL signal is used to trigger the exchange between the power signal and the data signal; wherein, the VIO_SEL signal generates a power-on reset (POR) signal through the power-on reset circuit, triggers the D flip-flop, and generates the USID_SEL signal; (4) The MIPI module generates different chip default identifiers in response to different combinations of the USID_SEL signal.

10. The implementation method as described in claim 9, characterized in that: In step (3), the USID_SEL signal is dynamically generated by a D flip-flop and an AND gate circuit based on the VIO_SEL signal, the power-on reset (POR) signal, and the inverted signal (PORN) of the power-on reset signal, and is divided into a first signal (USID1) and a second signal (USID2).

11. The implementation method as described in claim 10, characterized in that: In step (4), the MIPI module generates corresponding product identifiers and subordinate identifiers in response to different combinations of the first signal (USID1) and the second signal (USID2).

12. An electronic device, characterized in that, Includes the bus interface circuit with variable chip identifier as described in any one of claims 1 to 8.

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