Assembly method for a manufacturable, ultra small, dual semiconductor die voltage and current optical transformer

Abstract

A method for manufacturing a device including forming at least a first sub-stack and a second sub-stack, respectively comprising: forming a carrier (260-1, 260-2) comprising a first plasma treatment (206-1, 206-2) of a first surface of the carrier; arranging an optical component (240-1, 240-2) on the first surface of the carrier; and performing a second plasma treatment (242-1, 242-2) of a second surface including at least a part of the first surface and of the optical component; and forming a stack (246, 248) by attaching the first sub-stack to the second sub-stack.

Description

[0001] ASSEMBLY METHOD FOR A MANUFACTURABLE, ULTRA SMALL, DUAL SEMICONDUCTOR DIE VOLTAGE AND CURRENT OPTICAL TRANSFORMER

[0002] Description

[0003] This disclosure generally relates to methods for manufacturing a voltage and current optical transformer.

[0004] Optical transformers are known from US 11757369 Bl, US 9391226 B2, US 11563137 B2, and US 5248931.

[0005] It is an objective of the invention to provide a method for manufacturing a voltage and current optical transformer having any one of an improved yield and resulting in a voltage and current optical transformer having an improved performance.

[0006] In one aspect, a method for manufacturing a device, e.g. a voltage and current optical transformer, is provided. The method including: forming at least a first sub-stack and a second sub-stack, respectively including: forming a carrier comprising a first plasma treatment of a first surface of the carrier; arranging an optical component on the first surface of the carrier; and performing a second plasma treatment of a second surface including at least a part of the first surface and of the optical component; and forming a stack by attaching the first sub-stack to the second sub-stack.

[0007] In another aspect, a method for manufacturing a device, e.g. a voltage and current optical transformer, is provided. The method including: forming a carrier comprising a first plasma treatment of a first surface of the carrier; forming a stack, the stack comprising a photovoltaic component arranged in an optical path of a surface emitting laser component; arranging the stack on the first surface of the carrier; and performing a second plasma treatment of a second surface comprising at least a part of the first surface and a part of the stack. Illustratively, the plasma treatment, e.g. plasma cleaning, before and after positioning a chip stack on a surface of a carrier improves the yield of the method and results in a voltage and current optical transformer having an improved performance, e.g. an improved encapsulation, e.g. of higher quality, formed in a subsequent process on the plasma treated surface .

[0008] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention.

[0009] In the following description, various aspects of the invention are described with reference to the following drawings, in which :

[0010] FIG.1A shows a schematic side view of a voltage and current optical transformer;

[0011] FIG. IB shows a schematic top-down view of a photovoltaic array of the voltage and current optical transformer;

[0012] FIG.2 shows a flow diagram of a method for manufacturing a voltage and current optical transformer;

[0013] FIG.3A to FIG.3E illustrate process steps of FIG.2;

[0014] FIG.4 shows a flow diagram of another method for manufacturing a voltage and current optical transformer;

[0015] FIG.5A to FIG.5B illustrate a process step of FIG.4; FIG.6 shows a flow diagram of another method for manufacturing a voltage and current optical transformer;

[0016] FIG.7 illustrates a process step of FIG.6;

[0017] FIG.8 shows a flow diagram of another method for manufacturing a voltage and current optical transformer;

[0018] FIG.9 illustrates a process step of FIG.8;

[0019] FIG.10 shows a flow diagram of another method for manufacturing a voltage and current optical transformer; and

[0020] FIG.11 illustrates a process step of FIG.10.

[0021] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the disclosure may be practiced. One or more aspects are described in sufficient detail to enable those skilled in the art to practice the disclosure. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the disclosure. The various aspects described herein are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods and various aspects are described in connection with devices. However, it may be understood that aspects described in connection with methods may similarly apply to the devices, and vice versa. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. Throughout the drawings, it should be noted that proportions are not necessary to scale and that the size of features may be emphasized for ease of illustration. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any example or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples or designs .

[0022] The words "plurality" and "multiple" in the description or the claims expressly refer to a quantity greater than one. The terms "group (of) ", "set [of] ", "collection (of) ", "series (of)", "sequence (of)", "grouping (of)", etc., and the like in the description or in the claims refer to a quantity equal to or greater than one, i.e. one or more. Any term expressed in plural form that does not expressly state "plurality" or "multiple" likewise refers to a quantity equal to or greater than one .

[0023] The term "connected" can be understood in the sense of a (e.g. mechanical, optical and / or electrical) , e.g. direct or indirect, connection and / or interaction. For example, several elements can be connected together mechanically such that they are physically retained (e.g., a plug connected to a socket) and electrically such that they have an electrically conductive path (e.g., signal paths exist along a communicative chain) .

[0024] In the following description, same reference numbers pertain to the same object throughout the figures, and thus once described a description of the object is omitted.

[0025] In various process steps, a plasma treatment process is used. The plasma treatment process may be a plasma cleaning process. The plasma process may be a wet chemical process that is used to remove organic matter from a surface. By doing this, improves the adhesion of wirebond on the die surface.

[0026] FIG.1A illustrates a schematic side view and FIG. IB illustrates a schematic top view of a voltage and current optical transformer (VCOT) 10. The VCOT 10 includes a photovoltaic (PV) array 12 and is arranged in an optical path of an array of vertical cavity surface emitting lasers (VCSEL) 14.

[0027] The PV array 12 is made of an array of individual PV cells connected electrically in a serial and parallel combination.

[0028] The VCSEL 14 includes one or more aperture elements, and each aperture element emits a beam of light 16, and each beam of light 16 has a divergence, as illustrated in FIG.1A.

[0029] Illustratively, the VCSEL 14 illuminates the PV array 12 using an input electrical current 24, and the PV array 12 outputs an electrical current 26 based on the light 16 received. Each of the VCSEL 14 and the PV array generates a thermal flow during operation 28, 30.

[0030] A dielectric material 18 is arranged between the PV array 12 and the VCSEL 14. The thickness of the dielectric material 18 defines a dielectric breakdown voltage gap 20.

[0031] All light 16 emitted by the VCSELs 14 should strike an active area of a corresponding PV cell 12 and not the areas outside the active areas, as illustrated in FIG. IB. Thus, there is an alignment 22 between the PV cell 12 and the VCSEL 14.

[0032] An optimized VCOT 10 requires a 1:1 correspondence between each PV array cell and a corresponding VCSEL array' s aperture element. Thus, there may be competing requirements for the 1:1 matched VCSEL to PV array cells:

[0033] • reducing VCSEL beam divergence

[0034] • reducing dielectric breakdown size

[0035] • maximize thermal conductivity

[0036] • maximize electrical conductivity

[0037] • maximize chip to chip alignment Some or all of the competing requirements may be addressed by the method for manufacturing the VCOT .

[0038] FIG.2 shows a flow diagram of a method for manufacturing a voltage and current optical transformer. FIG.3A to FIG.3E illustrate process steps of FIG.2.

[0039] In one aspect, also denoted as copper pillar design, the manufacturing method 100 includes a carrier level manufacturing 160, a chip level manufacturing 166, and a module level manufacturing 168.

[0040] The carrier level manufacturing 160 may include fabricating 102 of a carrier including a substrate, e.g. an aluminium nitride (AIN) substrate, and of dam walls, an attaching 104 of substrate and dam walls. The dam walls may 602 may be arranged to surround the substrate, as becomes apparent from FIG.3A. The carrier level manufacturing 160 may further include a plasma cleaning 106 of a first surface of the substrate.

[0041] The chip level manufacturing 166 may include a VCSEL manufacturing 162 and a PV array manufacturing 164.

[0042] The VCSEL manufacturing 162 may include producing the VCSEL 112, e.g. on a wafer-scale level, and a wafer dicing 114, e.g. to singulate VCSELs .

[0043] The PV array manufacturing 164 may include producing the PV array 122, e.g. on a wafer-scale level, and a wafer dicing 124, e.g. to singulate the PV arrays.

[0044] The chip level manufacturing 166 may further include producing 130 a chip stack by stacking the VCSEL and the PV array, e.g. in a flip chip configuration. The chip stack may have a tolerance of less than or equal about 5 pm, for example. The module level manufacturing 168 may include an attaching 140 of the formed chip stack on the plasma cleaned first surface of the substrate, e.g. using an adhesive. A resulting structure of the chip stack 604 on the substrate is illustrated in FIG.3A. The attached chip stack 604 with the substrate may have a tolerance of about 15 pm or less, for example.

[0045] The module level manufacturing 168 may further include a plasma cleaning 142 of the attached chip stack 604 on the substrate, e.g. defining a second surface, a wire bonding 144 of the chip stack 604 to the substrate. Further, an encapsulant 606, e.g. an epoxy resin, may be added 146 to fill the interspace (also denoted as void) between the dam walls 602 and the chip stack 604, as illustrated in FIG.3B. The encapsulant 606 may be cured, e.g. hardened.

[0046] The dam walls may be removed 148 after the curing of the encapsulant, as illustrated in FIG.3C, forming a wafer level VCOT 608 having a pluralitv of chip stacks embedded in the encapsulant on a shared substrate.

[0047] The encapsulated chip stacks may be diced 150, e.g. by a ceramic panel dicing, as illustrated in FIG.3D.

[0048] Thus, singulated VCOTs 10, as illustrated in FIG.3E, may be tested 152, e.g. regarding any one of optical properties, electrical properties, and safety conformity. The tested VCOTs 10 may than be prepared for shipping, e.g. in a tape and reel process 154.

[0049] FIG.4 shows a flow diagram of another method for manufacturing a voltage and current optical transformer. FIG.5A and FIG.5B illustrate a process step of FIG.4. FIG.4 illustrates another aspect, also denoted as multilayer lidded package-assembly design. Subsequently, only the differences to the method illustrated in FIG.2 are described. The chip level manufacturing 166 may include a first carrier level manufacturing 260-1 and a second carrier level manufacturing 260-2.

[0050] The first carrier level manufacturing 260-1 includes a first fabricating 202-1 of a carrier having a first substrate 708, as illustrated in FIG.5A to FIG.5B, and a first plasma cleaning 206-1 of a surface of at least the first substrate.

[0051] The second carrier level manufacturing 260-2 includes a second fabricating 202-2 of a carrier having second substrate 702 with holes 710, as illustrated in FIG.5A to FIG.5B, and a second plasma cleaning 206-2 of a surface of at least the second substrate.

[0052] The singulated VCSEL is arranged on the plasma cleaned surface of the first substrate forming a first chip stack, e.g. having a tolerance of less or equal to 5 pm to 15 pm.

[0053] The singulated PV array is arranged on the plasma cleaned surface of the second substrate forming a second chip stack, e.g. having a tolerance of less or equal to 5 pm to 15 pm.

[0054] The method may further include a plasma cleaning 242-1 of exposed surfaces of the chip stack having the VCSEL on the first carrier, and a plasma cleaning 242-2 of exposed surfaces of the chip stack having the PV array on the second carrier.

[0055] The method may further include a first wire bonding 244-1 process including a connecting, e.g. using a wiring 712, of electrically connecting contacts of the VCSEL chip with corresponding contacts of the first substrate.

[0056] The method may further include a second wire bonding 244-2 process including a connecting, e.g. using a wiring 714, of electrically connecting contacts of the PV array with corresponding contacts of the second substrate.

[0057] The plasma cleaning 242-1, 242-2 may improve the wire bonding 244-1, 244-2. For example, the plasma cleaning 242-1, 242-2 may promote a strong bond between the chip stack and the wire bond since the organic impurities on the surface of chip stack are removed via plasma cleaning.

[0058] A spacer panel, e.g. formed from AIN, may be formed in a separate process 250. The singulated VCSEL may be attached 246 to the spacer panel, and the singulated PV array may be attached 248 to another side of the spacer panel. The first chip stack and the second chip stack may be arranged such that the VCSEL 14 and the PV array 12 are facing each other, as illustrated in FIG.5A to FIG.5B.

[0059] The adhesive, e.g. an epoxy resin, may be the dielectric material 706 arranged between the first substrate 708 and the second substrate 702 acting as an encapsulant. The adhesive 706 may be dispensed through the hole(s) 710 into the void (also denoted as interspace) formed by the first and second substrates 702, 708 and the spacers 704 of the spacer panel. Alternatively, the adhesive is positioned at the interface between the second substrate and the first substrate or spacer. Thus, an encapsulant different from the adhesive may be deposited in to the void through the hole(s) 710.

[0060] FIG.6 shows a flow diagram of another method for manufacturing a voltage and current optical transformer. FIG.7 illustrates a process step of FIG.6. FIG.6 illustrates another aspect, also denoted as package with light pipe-assembly design. Subsequently, only the differences to the methods illustrated before are described.

[0061] The method may include an optical waveguide manufacturing 360 including producing an optical waveguide 302 in a pattern, metallize 304 the pattern of the optical waveguide, and dicing 306 the optical waveguide, e.g. corresponding to any one of the VCSEL and the PV array, e.g. to provide singulated optical waveguides .

[0062] Thus, in the process of forming 130 the chip stack, the PV array 12 and the VCSEL 14 may be arranged on the optical waveguide 802, as illustrated in FIG.7.

[0063] Then, this chip stack may be attached 140 to the first surface of the substrate 702 provided by the carrier level manufacturing 160, as illustrated in FIG.7. A thermal adhesive is applied 346 to a surface of any one of the substrate and the chip stack after forming 144 the electrical connection, e.g. using a wire bond 808, between the substrate 702 and the chip stack.

[0064] The method may further include a lid manufacturing 362 including producing 312 a lid, and a plasma cleaning 314 of the lid. Thus, after depositing 346 the adhesive, the lid 804 from the lid manufacturing 362 may be placed on the deposited adhesive, as illustrated in FIG.7.

[0065] FIG.8 shows a flow diagram of another method for manufacturing a voltage and current optical transformer. FIG.9 illustrates a process step of FIG.8. FIG.8 illustrates another aspect, also denoted as package with point coated / plated light pipe array-design. Subsequently, only the differences to the methods illustrated before are described.

[0066] The method may include an optical light pipe manufacturing 460 including producing 402 a light pipe in a pattern, also denoted as light condenser, metallize 404 the pattern, and dicing 406 the light pipe, e.g. to provide singulated optical light pipes. Thus, in the process of forming 130 the chip stack, the PV array 12 and the VCSEL 14 may be arranged on the optical light pipe 902, as illustrated in FIG.9.

[0067] Then, this chip stack is attached 140 to the substrate 702 provided in the carrier level manufacturing 160, as illustrated in FIG.9. The thermal adhesive is applied 346 to a surface of any one of the substrate and the chip stack after forming 144 the electrical connection, e.g. using a wire bond 808, between the substrate 702 and the chip stack, as illustrated in FIG.9.

[0068] The method may further include a lid manufacturing 362 including producing 312 a lid, and a plasma cleaning 314 of the lid. Thus, after depositing 346 the adhesive, the lid 804 from the lid manufacturing 362 may be placed on the deposited adhesive .

[0069] FIG.10 shows a flow diagram of another method for manufacturing a voltage and current optical transformer. FIG.11 illustrates process steps of FIG.10. FIG.10 illustrates another aspect, also denoted as wafer level package - assembly-design. Note, the wafer level package - assembly-design is explained for the example of the package with point coated / plated light pipe array-design illustrated in FIG.8 but is also applicable to the other methods described above.

[0070] Here, the PV array, the VCSEL may be provided on a wafer scale level, as illustrated in FIG.11, and the method may include a wafer stacking 500 and dicing 502. Illustratively, wafers including pluralities of VCSEL and PV array instead of singulated VCSEL and PV array may be stacked and diced afterwards .

[0071] An optical light pipe manufacturing 460 or waveguide manufacturing 360 may be optional, and optionally included in the wafer stack as illustrated in FIG.10 by the dashed arrow. FIG . 11 illustrates a PV wafer 1002 , a reflective light pipe array wafer 1004 , and a VCSEL wafer 1006 stacked above one another in the wafer stacking 500 process .

[0072] The carrier provided by the carrier level manufacturing 160 may include a substrate panel 1008 , and a substrate-spacer panel 1010 . The diced chip stacks may thus be attached to the substrate panel generating a chip stack on the substrate panel structure 1012 . Subsequently, a lid panel may be attached 1014 on the chip stack on the substrate panel structure 1012 , and the packages finally singulated to form singulated packages 1016 .

[0073] In the following some examples are described, which relate to what is described herein and shown in the figures .

[0074] Example 1 is a method for manufacturing a device , the method including forming at least a first sub-stack and a second substack, respectively including : forming a carrier including a first plasma treatment of a first surface of the carrier ; arranging an optical component on the first surface of the carrier ; and performing a second plasma treatment of a second surface including at least a part of the first surface and of the optical component ; and forming a stack by attaching the first sub-stack to the second sub-stack .

[0075] In Example 2 , the subj ect matter of Example 1 can optionally include that the stack is formed using an adhesive arranged between the first sub-stack and the second sub-stack .

[0076] In Example 3 , the subj ect matter of Example 1 or 2 can optionally include that the stack is formed such that the optical component of the first sub-stack is arranged in an optical path of the optical component of the second sub-stack . In Example 4 , the subj ect matter of any one of Examples 1 to

[0077] 3 can optionally include that the optical component of the first sub-stack is a photovoltaic component .

[0078] In Example 5 , the subj ect matter of any one of Examples 1 to

[0079] 4 can optionally include that the optical component of the second sub-stack is a surface emitting laser .

[0080] In Example 6 , the subj ect matter of any one of Examples 1 to 4 can optionally include that the surface emitting laser is a vertical cavity surface emitting laser .

[0081] In Example 7 , the subj ect matter of any one of Examples 1 or 2 can optionally include that the optical component of the first sub-stack is a photovoltaic component , wherein the optical component of the second sub-stack is a surface emitting laser, and that the photovoltaic component is arranged in an optical path of the surface emitting laser .

[0082] In Example 8 , the subj ect matter of any one of Examples 1 to

[0083] 7 can optionally include that the first plasma treatment of at least one of the forming of the first sub-stack and forming of the second sub-stack includes a wet chemical plasma

[0084] In Example 9 , the subj ect matter of any one of Examples 1 to

[0085] 8 can optionally include that the second plasma treatment of at least one of the forming of the first sub-stack and forming of the second sub-stack includes a wet chemical plasma

[0086] In Example 10 , the subj ect matter of any one of Examples 1 to

[0087] 9 can optionally include that the first plasma treatment di f fers in at least one characteristic from the second plasma treatment .

[0088] In Example 11 , the subj ect matter of any one of Examples 1 to 10 can optionally include that the first plasma treatment includes a first plasma means and the second plasma treatment includes a second plasma means , wherein the first plasma means di f fers in at least one characteristic from the second plasma means .

[0089] In Example 12 , the subj ect matter of any one of Examples 1 to 10 can optionally include that the first plasma treatment includes a first plasma means and the second plasma treatment includes a second plasma means , wherein the first plasma means is the same as the second plasma means .

[0090] In Example 13 , the subj ect matter of any one of Examples 1 to 12 can optionally include that at least one of the first substack and the second sub-stack includes one or more spacers defining a void in the stack between the carrier of the first sub-stack and the carrier of the second sub-stack, and that the carrier of at least one of the first sub-stack and the second sub-stack includes one or more holes , and that an encapsulant is disposed in to the void through the one or more hole ( s ) .

[0091] In Example 14 , the subj ect matter of Example 13 can optionally include that forming the carrier includes forming spacers on a substrate .

[0092] In Example 15 , the subj ect matter of any one of Examples 13 to 14 can optionally include that the spacers define a component area, wherein the surface of the substrate in the component area includes the first surface , and wherein one or more optical components are arranged in the component area on the substrate .

[0093] In Example 16 , the subj ect matter of any one of Examples 13 to 15 can optionally include that the disposed encapsulant forms an encapsulating structure on at least a part of the second surface , wherein the component area includes the second surface . In Example 17 , the subj ect matter of any one of Examples 1 to 16 can optionally include that forming the stack further includes forming a passive optical component , and arranging the first sub-stack and the second sub-stack on the passive optical component .

[0094] In Example 18 , the subj ect matter of Example 17 can optionally include that the passive optical component is an optical waveguide or an optical light pipe .

[0095] In Example 19 , the subj ect matter of any one of Examples 1 to 18 can optionally include that at least one of the carrier of the first sub-stack and the carrier of the second sub-stack includes a wafer including a plurality of optical components .

[0096] In Example 20 , the subj ect matter of Example 19 can optionally further include a dicing of the wafer to singulate the plurality of optical components before the second plasma treatment .

[0097] In Example 21 , the subj ect matter of any one of Examples 1 to 20 can optionally include that the device is a voltage and current optical trans former .

[0098] Example 22 is a method for manufacturing a device , the method including : forming a carrier including a first plasma treatment of a first surface of the carrier ; forming a stack, the stack including a photovoltaic component arranged in an optical path of a surface emitting laser component ; arranging the stack on the first surface of the carrier ; and performing a second plasma treatment of a second surface including at least a part of the first surface and a part of the stack .

[0099] In Example 23 , the subj ect matter of Example 22 can optionally further include : forming an encapsulating structure on at least a part of the second surface . In Example 24 , the subj ect matter of any one of Examples 22 to 23 can optionally include that the first plasma treatment includes a first plasma means and the second plasma treatment includes a second plasma means , wherein the first plasma means di f fers in at least one characteristic from the second plasma means .

[0100] In Example 25 , the subj ect matter of Example 24 can optionally include that at least one of the first plasma means and the second plasma means includes a wet chemical plasma .

[0101] In Example 26 , the subj ect matter of any one of Examples 22 to 25 can optionally include that the first plasma treatment includes a first plasma means and the second plasma treatment includes a second plasma means , wherein the first plasma means is the same as the second plasma means .

[0102] In Example 27 , the subj ect matter of Example 26 can optionally include that at least one of the first plasma means and the second plasma means includes a wet chemical plasma .

[0103] In Example 28 , the subj ect matter of any one of Examples 22 to

[0104] 27 can optionally include that the stack includes the photovoltaic component and the surface emitting laser component arranged in a flip chip configuration .

[0105] In Example 29 , the subj ect matter of any one of Examples 22 to

[0106] 28 can optionally include that forming the carrier includes a forming of dam walls on a substrate .

[0107] In Example 30 , the subj ect matter of Example 29 can optionally include that the dam walls define a stack area, wherein the surface of the substrate in the stack area includes the first surface , and wherein one or more stacks are arranged in the stack area on the substrate . In Example 31 , the subj ect matter of any one of Examples 22 to 30 can optionally further include : forming an encapsulating structure on at least a part of the second surface , wherein the stack area includes the second surface .

[0108] In Example 32 , the subj ect matter of Example 31 can optionally further include : a curing process of the encapsulating structure , and a removing of the dam walls after the curing process .

[0109] In Example 33 , the subj ect matter of any one of Examples 22 to 32 can optionally include that forming the stack further includes forming a passive optical component , and arranging the photovoltaic component and the surface emitting laser on the passive optical component .

[0110] In Example 34 , the subj ect matter of Example 33 can optionally include that the passive optical component is an optical waveguide or an optical light pipe .

[0111] In Example 35 , the subj ect matter of any one of Examples 33 to

[0112] 34 can optionally include that the passive optical component is arranged in an optical path between the photovoltaic component and the surface emitting laser .

[0113] In Example 36 , the subj ect matter of any one of Examples 22 to

[0114] 35 can optionally include that the surface emitting laser is a vertical cavity surface emitting laser .

[0115] In Example 37 , the subj ect matter of any one of Examples 22 to

[0116] 36 can optionally include that the device is a voltage and current optical trans former .

[0117] In Example 38 , the subj ect matter of any one of Examples 22 to

[0118] 37 can optionally include that at least one of the photovoltaic component and the surface emitting laser component is arranged on a wafer . In Example 39 , the subj ect matter of Example 38 can optionally further include a dicing of the wafer to singulate the respective one of the photovoltaic component and the surface emitting laser component before the second plasma treatment .

[0119] While the above descriptions and connected figures may depict optical device components as separate elements , skilled persons will appreciate the various possibilities to combine or integrate discrete optical functions into a single element . Such may include combining two or more components from a single component . Conversely, skilled persons will recogni ze the possibility to separate a single element into two or more discrete elements , such as splitting a single component into two or more separate component .

[0120] It is appreciated that implementations of methods detailed herein are exemplary in nature , and are thus understood as capable of being implemented in a corresponding device . Likewise , it is appreciated that implementations of devices detailed herein are understood as capable of being implemented as a corresponding method . It is thus understood that a device corresponding to a method detailed herein may include one or more components configured to perform each aspect of the related method .

[0121] All acronyms defined in the above description additionally hold in all claims included herein .

[0122] While the disclosure has been particularly shown and described with reference to speci fic embodiments , it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims . The scope of the disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced .

[0123] Reference Numeral List

[0124] 10 voltage and current optical trans former (VCOT )

[0125] 12 photovoltaic ( PV) array

[0126] 14 vertical cavity surface emitting laser (VCSEL )

[0127] 16 light

[0128] 18 dielectric material

[0129] 20 breakdown voltage of the dielectric material

[0130] 22 alignment between PV array and VCSEL

[0131] 24 input current to VCSEL

[0132] 26 output current from PV array

[0133] 28 thermal flow

[0134] 30 thermal flow

[0135] 100 manufacturing method

[0136] 102 fabricating substrate and dam walls

[0137] 104 attaching substrate and dam walls

[0138] 106 plasma cleaning

[0139] 112 produce VCSEL

[0140] 114 wafer dicing

[0141] 122 produce PV array

[0142] 124 wafer dicing

[0143] 130 produce chip stack

[0144] 140 attach chip stack to substrate

[0145] 142 plasma cleaning

[0146] 144 wire bonding

[0147] 146 encapsulation

[0148] 148 dam wall removal

[0149] 150 dicing

[0150] 152 testing

[0151] 154 tape and reel

[0152] 160 carrier level manufacturing

[0153] 162 VCSEL manufacturing

[0154] 164 PV array manufacturing

[0155] 166 chip level manufacturing

[0156] 168 module level manufacturing

[0157] 202 fabricating substrate and spacer

[0158] 202- 1 , 202-2 fabricating substrate 204 attaching substrate and spacer

[0159] 206 , 206- 1 , 206-2 plasma cleaning

[0160] 230- 1 , 230-2 produce chip stack

[0161] 240- 1 , 240-2 attach chip stack to substrate

[0162] 242- 1 , 242-2 plasma cleaning

[0163] 244- 1 , 244-2 wire bonding

[0164] 246 attaching spacer panel to VCSEL

[0165] 248 attaching PV on other side of spacer panel

[0166] 250 fabricate spacer panel

[0167] 260- 1 , 260-2 carrier level manufacturing

[0168] 302 produce optical waveguide

[0169] 304 metalli ze pattern

[0170] 306 dicing

[0171] 312 produce lid

[0172] 314 plasma cleaning

[0173] 360 optical waveguide manufacturing

[0174] 362 lid manufacturing

[0175] 346 depositing thermal adhesive

[0176] 348 attaching lid

[0177] 402 produce light pipe

[0178] 404 metalli ze pattern

[0179] 406 dicing

[0180] 460 optical light pipe manufacturing

[0181] 500 wafer stacking

[0182] 502 dicing

[0183] 602 wall

[0184] 604 chip stack

[0185] 606 encapsulant

[0186] 608 wafer level VCOT

[0187] 702 PV substrate

[0188] 704 spacer

[0189] 706 encpasulant

[0190] 708 VCSEL substrate

[0191] 710 through hole

[0192] 712 wire bond

[0193] 714 wire bond

[0194] 802 optical waveguide 804 lid

[0195] 808 wire bond

[0196] 902 light condenser

[0197] 904 PV array chip 1002 PV wafer

[0198] 1004 Reflective light pipe array wafer

[0199] 1006 VCSEL wafer

[0200] 1008 substrate panel

[0201] 1010 substrate-spacer panel 1012 chip stack to substrate panel

[0202] 1014 Attach lid panel

[0203] 1016 Final singulated package

Claims

CLAIMS1 . A method for manufacturing a device , the method comprising forming at least a first sub-stack and a second sub-stack, respectively comprising : forming a carrier comprising a first plasma treatment of a first surface of the carrier ; arranging an optical component on the first surface of the carrier ; and performing a second plasma treatment of a second surface including at least a part of the first surface and of the optical component ; and forming a stack by attaching the first sub-stack to the second sub-stack .2 . The method of claim 1 , wherein the optical component of the first sub-stack is a photovoltaic component , wherein the optical component of the second sub-stack is a surface emitting laser, and wherein the photovoltaic component is arranged in an optical path of the surface emitting laser .3 . The method of claim 1 or 2 , wherein at least one of the first plasma treatment and the second plasma treatment of at least one of the forming of the first sub-stack and forming of the second sub-stack comprises a wet chemical plasma .4 . The method of any one of claims 1 to 3 , wherein at least one of the first sub-stack and the second sub-stack comprises one or more spacers defining a void in the stack between the carrier of the first sub-stack and the carrier of the second sub-stack, and wherein the carrier of at least one of the first substack and the second sub-stack comprises one or more holes , andwherein an encapsulant is disposed in to the void through the one or more hole ( s ) .

5. The method of claim 4 , wherein forming the carrier comprises a forming the spacers on a substrate , wherein the spacers define a component area, wherein the surface of the substrate in the component area comprises the first surface , and wherein one or more optical components are arranged in the component area on the substrate .

6. The method of claim 4 or 5 , wherein the disposed encapsulant forms an encapsulating structure on at least a part of the second surface , wherein the component area comprises the second surface .7 . The method of any one of claims 1 to 6 , wherein forming the stack further comprises forming a passive optical component , and arranging the first sub-stack and the second sub-stack on the passive optical component , wherein the passive optical component is an optical waveguide or an optical light pipe .8 . The method of any one of claims 1 to 7 , wherein at least one of the carrier of the first sub-stack and the carrier of the second sub-stack comprises a wafer comprising a plurality of optical components , and further comprising a dicing of the wafer to singulate the plurality of optical components before the second plasma treatment .

9. The method of any one of claims 1 to 8 , wherein the device is a voltage and current optical trans former .10 . A method for manufacturing a device , the method comprising : forming a carrier comprising a first plasma treatment of a first surface of the carrier ; forming a stack, the stack comprising a photovoltaic component arranged in an optical path of a surface emitting laser component ; arranging the stack on the first surface of the carrier ; and performing a second plasma treatment of a second surface comprising at least a part of the first surface and a part of the stack .11 . The method of claim 10 , further comprising : forming an encapsulating structure on at least a part of the second surface .12 . The method of claim 10 or 11 , wherein at least one of the first plasma means and the second plasma means comprises a wet chemical plasma .13 . The method of any one of claims 10 to 12 , wherein the stack comprises the photovoltaic component and the surface emitting laser component arranged in a flip chip configuration .14 . The method of any one of claims 10 to 13 , wherein forming the carrier comprises a forming of dam walls on a substrate , wherein the dam walls define a stack area, wherein the surface of the substrate in the stack area comprises the first surface , and wherein one or more stacks are arranged in the stack area on the substrate ; and further comprising : forming an encapsulating structure on at least a part of the second surface , wherein the stack area comprises the second surface .15 . The method of claim 14 , further comprising a curing process of the encapsulating structure , and a removing of the dam walls after the curing process .16 . The method of any one of claims 10 to 15 , wherein forming the stack further comprises forming a passive optical component , and arranging the photovoltaic component and the surface emitting laser on the passive optical component , wherein the passive optical component is an optical waveguide or an optical light pipe , and wherein the passive optical component is arranged in an optical path between the photovoltaic component and the surface emitting laser .17 . The method of any one of claims 10 to 16 , wherein the surface emitting laser is a vertical cavity surface emitting laser .18 . The method of any one of claims 10 to 17 , wherein the device is a voltage and current optical trans former .19 . The method of any one of claims 1 to 18 , wherein at least one of the photovoltaic component and the surface emitting laser component is arranged on a wafer, and further comprising a dicing of the wafer to singulate the respective one of the photovoltaic component and the surface emitting laser component before the second plasma treatment .

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