Bias circuit and amplifier

Abstract

The present invention is a bias circuit including: an amplification transistor for amplifying a signal input to a bias output terminal; a feedback transistor for feeding back the output of the amplification transistor to the bias output terminal; and a constant current source connected to an input terminal of the feedback transistor. The bias circuit outputs a bias voltage from the bias output terminal to a common mode control impedance.

Description

Bias Circuit and Amplifier

[0001] This application claims priority from Japanese Patent Application No. 2024-111067, filed on July 10, 2024, the contents of which are incorporated herein by reference.

[0002] In recent years, wireless communications using high-frequency signals such as microwaves and millimeter waves have been gaining attention. Amplifiers included in wireless communications devices that transmit and receive such high-frequency signals are nonlinear circuits, and their performance can be degraded by intermodulation distortion. Intermodulation distortion occurs when signals of different frequencies are input to a nonlinear circuit and mixed. This increases the bit error rate of the transmitted signal and causes in-band distortion, which is measured by an index such as Error Vector Magnitude (EVM), and out-of-band distortion, which is measured by an index such as Adjacent Channel Power Ratio (ACPR), due to interference outside the target frequency band.

[0003] For example, Non-Patent Document 1 listed below discloses a differential common emitter RF amplifier that includes an input transformer, an output transformer, and a pair of cross-coupling capacitors, and that reduces second-order intermodulation waves and second harmonic waves by connecting a common-mode controlled impedance circuit having a desired common-mode controlled impedance to the input transformer and the output transformer, thereby reducing distortion.

[0004] MP van der Heijden, M. Spirito, LCN de Vreede, F. van Straten and JN Burghartz, "A 2 GHz high-gain differential InGaPHBT driver amplifier matched for high IP3," IEEE MTT-S International Microwave Symposium Digest, 2003, 2003, pp. 235-238 vol.1

[0005] However, the above-mentioned Non-Patent Document 1 does not mention a biasing method for a differential common-emitter RF amplifier. When a bias circuit is connected to a differential common-emitter RF amplifier, the bias circuit has a certain impedance to high-frequency signals, which may result in the common-mode controlled impedance circuit not having the desired common-mode controlled impedance. Therefore, it must be said that the technology in Non-Patent Document 1 is of little practical use.

[0006] The present invention has been made in view of the above circumstances, and has as its object to provide a bias circuit and an amplifier that can enable a common-mode controlled impedance circuit to function normally.

[0007] In order to achieve the above object, a first aspect of the present invention is a bias circuit comprising an amplifying transistor that amplifies a signal input to a bias output terminal, a feedback transistor that feeds back the output of the amplifying transistor to the bias output terminal, and a constant current source connected to the input terminal of the feedback transistor, and which outputs a bias voltage from the bias output terminal to a common mode controlled impedance circuit.

[0008] A second aspect of the present invention is the bias circuit according to the first aspect of the present invention, wherein a compensation capacitor is provided between the bias output terminal and the input terminal of the feedback transistor.

[0009] A third aspect of the present invention is the bias circuit according to the first or second aspect of the present invention, wherein the constant current source has a current output terminal electrically connected to the output terminal of the amplification transistor and the input terminal of the feedback transistor.

[0010] A fourth aspect of the present invention is a bias circuit according to any one of the first to third aspects of the present invention, wherein a cascode transistor is provided between the output terminal of the amplifying transistor and the current output terminal and the input terminal of the constant current source.

[0011] A fifth aspect of the present invention is a bias circuit according to any one of the first, third, and fourth aspects of the present invention, wherein a low-pass filter is provided between the output terminal of the amplifying transistor and the input terminal of the feedback transistor.

[0012] A sixth aspect of the present invention is an amplifier comprising a bias circuit according to any one of the first to fifth aspects of the present invention, an amplifier circuit, and a common-mode controlled impedance circuit provided between the bias circuit and the amplifier circuit.

[0013] A seventh aspect of the present invention is the amplifier according to the sixth aspect of the present invention, wherein the common mode controlled impedance circuit is composed of resistors only.

[0014] An eighth aspect of the present invention is the amplifier according to the sixth aspect of the present invention, wherein the common mode controlled impedance circuit is configured as a parallel connection circuit of a resistor and a capacitor.

[0015] According to the present invention, it is possible to provide a bias circuit and an amplifier that enable a common-mode controlled impedance circuit to function normally.

[0016] FIG. 1 is a circuit diagram showing the configuration of a bias circuit and an amplifier according to a first embodiment of the present invention; FIG. 2 is a first characteristic diagram showing the performance of the bias circuit and the amplifier according to the first embodiment of the present invention; FIG. 3 is a third characteristic diagram showing the performance of the bias circuit according to the first embodiment of the present invention; FIG. 4 is a circuit diagram showing the configuration of a bias circuit and an amplifier according to a second embodiment of the present invention; and FIG. 5 is a characteristic diagram showing the performance of the bias circuit and the amplifier according to the second embodiment of the present invention.

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] First, a first embodiment of the present invention will be described with reference to Figures 1 to 4. As shown in Figure 1, an amplifier AF according to the first embodiment includes a differential amplifier circuit A, a bias circuit B, and a common-mode controlled impedance circuit C.

[0018] The differential amplifier circuit A has a pair of input terminals T1 and T2 and a pair of output terminals T3 and T4. As shown in the figure, one input terminal T1 of this differential amplifier circuit A is connected to one output terminal of a signal source G, and the other input terminal T2 is connected to the other output terminal of the signal source G. Furthermore, one output terminal T3 of this differential amplifier circuit A is connected to one end of a load L, and the other output terminal T4 is connected to the other end of the load L.

[0019] Such a differential amplifier circuit A amplifies, by a predetermined amplification factor, a high-frequency signal (transmission signal) input from a signal source G to a pair of input terminals T1 and T2, and outputs an amplified output signal with increased amplitude from a pair of output terminals T3 and T4 to a load L. Note that the symbol Zs in FIG. 1 denotes the output impedance (signal source impedance) of the signal source G.

[0020] As shown in the figure, the differential amplifier circuit A includes a first transistor 1, a second transistor 2, a first resistor 3, a second resistor 4, a third transistor 5, a fourth transistor 6, a first capacitor 7, a second capacitor 8, an intermediate transformer 9, a fifth transistor 10, a sixth transistor 11, a seventh transistor 12, an eighth transistor 13, a third capacitor 14, a fourth capacitor 15, and an output transformer 16.

[0021] As shown in the figure, the first transistor 1 is an NPN bipolar transistor. The base terminal of this first transistor 1 is connected to one input terminal T1, one end of the first resistor 3, and one end of the second capacitor 8. The collector terminal of this first transistor 1 is connected to the emitter terminal of the third transistor 5 and one end of the first capacitor 7, and the emitter terminal is grounded.

[0022] The first transistor 1 is a differential amplification transistor that forms a pair with the second transistor 2. The first transistor 1 differentially amplifies a transmission signal input to its base terminal from one end of a signal source G together with the second transistor 2, which receives the transmission signal from the other end of the signal source G, and outputs the amplified signal after differential amplification to the emitter terminal of the third transistor 5.

[0023] The second transistor 2 is an NPN bipolar transistor, similar to the first transistor 1. The base terminal of this second transistor 2 is connected to the other input terminal T2, one end of the second resistor 4, and the other end of the first capacitor 7. The collector terminal of this second transistor 2 is connected to the emitter terminal of the fourth transistor 6 and the other end of the second capacitor 8, and the emitter terminal is grounded.

[0024] The second transistor 2 is a differential amplification transistor that forms a pair with the first transistor 1. The second transistor 2 differentially amplifies a transmission signal input to its base terminal from the other end of the signal source G together with the first transistor 1, to which the transmission signal is input from one end of the signal source G, and outputs the inverted amplified signal after differential amplification to the emitter terminal of the fourth transistor 6.

[0025] The first resistor 3 is a bias resistor having a predetermined resistance value (first resistance value). One end of the first resistor 3 is connected to the base terminal of the first transistor 1, one input terminal T1, and one end of the second capacitor 8, and the other end is connected to the first bias power supply V ＢＢ１ The first resistor 3 sets the base voltage of the first transistor 1 to a predetermined voltage.

[0026] The second resistor 4 is a bias resistor having a predetermined resistance value (second resistance value). One end of the second resistor 4 is connected to the base terminal of the second transistor 2, the other input terminal T2, and the other end of the first capacitor 7, and the other end is connected to the first bias power supply V ＢＢ１ That is, the other end of the second resistor 4 and the other end of the first resistor 3 are connected to the first bias power supply V ＢＢ１ The second resistor 4 has a second resistance value set to be equal to the first resistance value of the first resistor 3, and sets the base voltage of the second transistor 2 to be equal to the base voltage of the first transistor 1.

[0027] The third transistor 5 is an NPN bipolar transistor, similar to the first transistor 1. The emitter terminal of this third transistor 5 is connected to the collector terminal of the first transistor 1 and one end of the first capacitor 7, and the collector terminal is connected to one end of the primary winding of the intermediate transformer 9.

[0028] The base terminal of the third transistor 5 is connected to the second bias power supply V ｃａｓ１ The third transistor 5 is a cascode transistor that is cascode-connected to the first transistor 1. The third transistor 5 outputs the amplified signal input from the collector terminal of the first transistor 1 from the collector terminal to one end of the primary winding of the intermediate transformer 9.

[0029] The fourth transistor 6 is an NPN bipolar transistor, similar to the second transistor 2, etc. The emitter terminal of this fourth transistor 6 is connected to the collector terminal of the second transistor 2 and the other end of the second capacitor 8, and the collector terminal is connected to the other end of the primary winding of the intermediate transformer 9.

[0030] The fourth transistor 6 has a base terminal connected to the second bias power supply V ｃａｓ１ That is, the base terminal of the fourth transistor 6 and the base terminal of the third transistor 5 are connected to the second bias power supply V ｃａｓ１ The fourth transistor 6 is a cascode transistor that is cascode-connected to the second transistor 2. The fourth transistor 6 outputs the inverted amplified signal input from the collector terminal of the second transistor 2 from the collector terminal to the other end of the primary winding of the intermediate transformer 9.

[0031] The first capacitor 7 is a compensation capacitor having a predetermined capacitance (first capacitance). One end of the first capacitor 7 is connected to the collector terminal of the first transistor 1 and the emitter terminal of the third transistor 5, and the other end is connected to the base terminal of the second transistor 2, the other input terminal T2, and one end of the second resistor 4. The first capacitor 7 stabilizes the differential amplification operation of the second transistor 2.

[0032] The second capacitor 8 is a compensation capacitor having the same capacitance (second capacitance) as the first capacitance of the first capacitor 7. One end of the second capacitor 8 is connected to the base terminal of the first transistor 1, one input terminal T1, and one end of the first resistor 3, and the other end is connected to the collector terminal of the second transistor 2 and the emitter terminal of the fourth transistor 6. The second capacitor 8 stabilizes the differential amplification operation of the first transistor 1.

[0033] The intermediate transformer 9 is a transformer in which a primary winding and a secondary winding are magnetically coupled. As shown in the figure, the primary winding of this intermediate transformer 9 is formed by connecting a first winding 9a and a second winding 9b in series, with one end (one end of the first winding 9a) connected to the collector terminal of the third transistor 5 and the other end (one end of the second winding 9b) connected to the collector terminal of the fourth transistor 6.

[0034] In addition, the other end of the first winding 9a and the other end of the second winding 9b are connected to the first power source V as a primary center tap. ＣＣ１ Such a primary winding is connected to a first power supply V ＣＣ１ The output voltage (first power supply voltage) is applied via the primary center tap to the collector terminal of the third transistor 5 and the collector terminal of the fourth transistor 6. The primary winding also contactlessly transmits to the secondary winding a composite signal of the amplified signal and the inverted amplified signal input to both ends from the collector terminal of the third transistor 5 and the collector terminal of the fourth transistor 6.

[0035] As shown in the figure, the secondary winding of this intermediate transformer 9 is formed by connecting a third winding 9c and a fourth winding 9d in series, with one end (one end of the third winding 9c) connected to the base terminal of the fifth transistor 10 and one end of the fourth capacitor 15, and the other end (one end of the fourth winding 9d) connected to the base terminal of the sixth transistor 11 and the other end of the third capacitor 14.

[0036] In addition, the other end of the third winding 9c and the other end of the fourth winding 9d of the secondary winding are connected as secondary center taps to one end of the common mode controlled impedance circuit C. Such secondary windings are connected to one end of the common mode controlled impedance circuit C via the secondary center taps. Ｂ and a composite signal transmitted in a non-contact manner from the third transistor 5 and the fourth transistor 6 via the primary winding are output to the base terminal of the fifth transistor 10, and the bias voltage V Ｂ and the inverted composite signal are output to the base terminal of the sixth transistor 11 .

[0037] The fifth transistor 10 is an NPN bipolar transistor, similar to the first transistor 1, etc. The base terminal of this fifth transistor 10 is connected to one end of the secondary winding of the intermediate transformer 9 and one end of the fourth capacitor 15. The collector terminal of this fifth transistor 10 is connected to the emitter terminal of the seventh transistor 12 and one end of the third capacitor 14, and the emitter terminal is grounded.

[0038] The fifth transistor 10 is a differential amplification transistor that forms a pair with the sixth transistor 11. The fifth transistor 10 differentially amplifies a composite signal input to the base terminal from one end of the secondary winding of the intermediate transformer 9 together with the sixth transistor 11, to which an inverted composite signal is input from the other end of the secondary winding, and outputs the amplified composite signal after differential amplification to the emitter terminal of the seventh transistor 12.

[0039] The sixth transistor 11 is an NPN bipolar transistor, similar to the fifth transistor 10. The base terminal of this sixth transistor 11 is connected to the other end of the secondary winding of the intermediate transformer 9 and the other end of the third capacitor 14. The collector terminal of this sixth transistor 11 is connected to the emitter terminal of the eighth transistor 13 and the other end of the fourth capacitor 15, and the emitter terminal is grounded.

[0040] The sixth transistor 11 is a differential amplification transistor that forms a pair with the fifth transistor 10. The sixth transistor 11 differentially amplifies an inverted composite signal that is input to the base terminal from the other end of the secondary winding of the intermediate transformer 9, together with the fifth transistor 10 to which the composite signal is input, and outputs the amplified inverted composite signal after differential amplification to the emitter terminal of the eighth transistor 13.

[0041] The seventh transistor 12 is an NPN bipolar transistor, similar to the fifth transistor 10. The emitter terminal of the seventh transistor 12 is connected to the collector terminal of the fifth transistor 10 and one end of the third capacitor 14, and the collector terminal is connected to one end of the primary winding of the output transformer 16.

[0042] The seventh transistor 12 has a base terminal connected to the third bias power supply V ｃａｓ２ The seventh transistor 12 is a cascode transistor that is cascode-connected to the fifth transistor 10. The seventh transistor 12 outputs the amplified composite signal input from the collector terminal of the fifth transistor 10 from the collector terminal to one end of the primary winding of the output transformer 16.

[0043] The eighth transistor 13 is an NPN bipolar transistor, similar to the sixth transistor 11, etc. The emitter terminal of the eighth transistor 13 is connected to the collector terminal of the sixth transistor 11 and the other end of the fourth capacitor 15, and the collector terminal is connected to the other end of the primary winding of the output transformer 16.

[0044] The base terminal of the eighth transistor 13 is connected to the third bias power supply Vｃａｓ２ That is, the base terminal of the eighth transistor 13 and the base terminal of the seventh transistor 12 are connected to the third bias power supply V ｃａｓ２ The eighth transistor 13 is a cascode transistor that is cascode-connected to the sixth transistor 11. The eighth transistor 13 outputs the amplified and inverted composite signal input from the collector terminal of the sixth transistor 11 to the other end of the primary winding of the output transformer 16 from the collector terminal.

[0045] The third capacitor 14 is a compensation capacitor having a predetermined capacitance (third capacitance). One end of the third capacitor 14 is connected to the collector terminal of the fifth transistor 10 and the emitter terminal of the seventh transistor 12, and the other end is connected to the base terminal of the sixth transistor 11 and the other end of the secondary winding of the intermediate transformer 9. The third capacitor 14 stabilizes the differential amplification operation of the sixth transistor 11.

[0046] The fourth capacitor 15 is a compensation capacitor having the same capacitance (fourth capacitance) as the third capacitance of the third capacitor 14. One end of the fourth capacitor 15 is connected to the base terminal of the fifth transistor 10 and one end of the secondary winding of the intermediate transformer 9, and the other end is connected to the collector terminal of the sixth transistor 11 and the emitter terminal of the eighth transistor 13. The fourth capacitor 15 stabilizes the differential amplification operation of the fifth transistor 10.

[0047] The output transformer 16 is a transformer in which a primary winding and a secondary winding are magnetically coupled. As shown in the figure, the primary winding of the output transformer 16 is formed by connecting a fifth winding 16 a and a sixth winding 16 b in series, with one end (one end of the fifth winding 16 a) connected to the collector terminal of the seventh transistor 12 and the other end (one end of the sixth winding 16 b) connected to the collector terminal of the eighth transistor 13.

[0048] In addition, the other end of the fifth winding 16a and the other end of the sixth winding 16b of the primary winding of the output transformer 16 are connected to the first power supply V ＣＣ１Such a primary winding is connected to a first power supply V ＣＣ１ The output voltage (first power supply voltage) of the seventh transistor 12 is applied to the collector terminal of the seventh transistor 12 and the collector terminal of the eighth transistor 13 via the primary center tap. The primary winding also contactlessly transmits to the secondary winding a composite signal (second composite signal) of the amplified composite signal and the amplified inverted composite signal input to both ends from the collector terminal of the seventh transistor 12 and the collector terminal of the eighth transistor 13.

[0049] As shown in the figure, one end of the secondary winding in the output transformer 16 is connected to one end of the load L, and the other end is connected to the other end of the load L. Such a secondary winding outputs to the load L the second composite signal that is contactlessly transmitted from the seventh transistor 12 and the eighth transistor 13 via the primary winding.

[0050] In the differential amplifier circuit A, the first transistor 1, the second transistor 2, the first resistor 3, the second resistor 4, the third transistor 5, the fourth transistor 6, the first capacitor 7, the second capacitor 8, and the primary winding of the intermediate transformer 9 constitute a pre-amplifier (initial amplifier). In this pre-amplifier (initial amplifier), the first resistor 3, the second resistor 4, and the first bias power supply V ＢＢ１ The base voltages of the first transistor 1 and the second transistor 2, that is, the operating point of the differential amplifier, are set by this.

[0051] The secondary winding of the intermediate transformer 9, the fifth transistor 10, the sixth transistor 11, the seventh transistor 12, the eighth transistor 13, the third capacitor 14, the fourth capacitor 15, and the output transformer 16 constitute a post-stage amplifier (second-stage amplifier). In this post-stage amplifier (second-stage amplifier), a bias voltage V is supplied from a bias circuit B to a secondary center tap of the secondary winding of the intermediate transformer 9 via a common mode control impedance circuit C. Ｂ The base voltages of the fifth transistor 10 and the sixth transistor 11 (the operating point of the differential amplifier) ​​are set by this.

[0052] As shown in the figure, the bias circuit B according to the first embodiment includes a constant current source 17, a ninth transistor 18, a tenth transistor 19, an eleventh transistor 20, a third resistor 21, a fifth capacitor 22, and a sixth capacitor 23. The bias circuit B outputs a bias voltage V Ｂ to the common mode control impedance circuit C, a bias voltage V Ｂ It is intended to supply

[0053] The constant current source 17 has a current output terminal connected to the collector terminal of the ninth transistor 18, the base terminal of the eleventh transistor 20, and one end of the fifth capacitor 22. Such a constant current source 17 generates a highly accurate and stable reference current I ｒｅｆ is a reference current source that outputs from the current output terminal.

[0054] Such a constant current source 17 is connected to the collector terminal (output terminal) of a tenth transistor 19 via a ninth transistor 18 , and is also connected to the base terminal (input terminal) of an eleventh transistor 20 .

[0055] As shown in the figure, the ninth transistor 18 is an NPN bipolar transistor. The collector terminal of this ninth transistor 18 is connected to the current output terminal of the constant current source 17, the base terminal of the eleventh transistor 20, and one end of the fifth capacitor 22, and the emitter terminal is connected to the collector terminal of the tenth transistor 19.

[0056] The base terminal of the ninth transistor 18 is connected to the third bias power supply V ｃａｓ２ The ninth transistor 18 is a cascode transistor provided between the collector terminal (output terminal) of the tenth transistor 19 and the current output terminal of the constant current source 17 and the base terminal (input terminal) of the eleventh transistor 20.

[0057] The tenth transistor 19 is an NPN bipolar transistor, similar to the ninth transistor 18. The collector terminal (output terminal) of this tenth transistor 19 is connected to the emitter terminal of the ninth transistor 18, and the emitter terminal is grounded. In addition, the tenth transistor 19 has a base terminal connected to one end of the third resistor 21.

[0058] The tenth transistor 19 corresponds to an amplifying transistor of the present invention. That is, the tenth transistor 19 is an amplifying element that amplifies the composite signal (high-frequency signal) input from the secondary intermediate tap of the intermediate transformer 9 to the bias output terminal Tc.

[0059] The eleventh transistor 20 is an NPN bipolar transistor, similar to the ninth transistor 18. The base terminal (input terminal) of the eleventh transistor 20 is connected to the current output terminal of the constant current source 17, the collector terminal of the ninth transistor 18, and one terminal of the fifth capacitor 22, and the collector terminal is connected to the second power supply V ＣＣ２ The emitter terminal of the eleventh transistor 20 is connected to the other end of the third resistor 21, the other end of the fifth capacitor 22, one end of the sixth capacitor 23, and the bias output terminal Tc.

[0060] The eleventh transistor 20 corresponds to the feedback transistor of the present invention. That is, the eleventh transistor 20 is a feedback element that feeds back (negatively feeds back) the output of the tenth transistor 19 (amplifying transistor) to the bias output terminal Tc.

[0061] The third resistor 21 is a base resistor having a predetermined resistance value (third resistance value). One end of the third resistor 21 is connected to the base terminal of the tenth transistor 19, and the other end is connected to the emitter terminal of the eleventh transistor 20, the other end of the fifth capacitor 22, one end of the sixth capacitor 23, and the bias output terminal Tc. The third resistor 21 sets the base voltage of the tenth transistor 19 based on the emitter voltage of the eleventh transistor 20.

[0062] The fifth capacitor 22 is a compensation capacitor having a predetermined capacitance (fifth capacitance). One end of the fifth capacitor 22 is connected to the output terminal of the constant current source 17, the collector terminal of the ninth transistor 18, and the base terminal of the eleventh transistor 20, and the other end is connected to the emitter terminal of the eleventh transistor 20, the other end of the third resistor 21, one end of the sixth capacitor 23, and the bias output terminal Tc. The fifth capacitor 22 stabilizes the operation of the eleventh transistor 20.

[0063] The sixth capacitor 23 is a filter capacitor having a predetermined capacitance (sixth capacitance). One end of the sixth capacitor 23 is connected to the bias output terminal Tc, the other end of the third resistor 21, the emitter terminal of the eleventh transistor 20, and the other end of the fifth capacitor 22.

[0064] As shown in the figure, the bias output terminal Tc is connected to the emitter terminal of the eleventh transistor 20, the other end of the third resistor 21, the other end of the fifth capacitor 22, and one end of the sixth capacitor 23, and is also connected to the other end of the common mode controlled impedance circuit C.

[0065] Such a bias circuit B corresponds to the bias circuit of the present invention, and outputs a bias voltage V Ｂ That is, the bias circuit B generates a DC voltage based on the reference current I ｒｅｆ , the reference current I ｒｅｆ The bias voltage V Ｂ The bias circuit B sets such a bias voltage V Ｂ is output from the bias output terminal Tc to the other terminal of the common mode controlled impedance circuit C.

[0066] The bias circuit B also includes a feedback loop made up of a ninth transistor 18, a tenth transistor 19, an eleventh transistor 20, and a third resistor 21. As will be described in detail later, the bias circuit B includes this feedback loop, and therefore has circuit performance such that the output impedance (bias circuit impedance) seen from one end of the common mode controlled impedance circuit C is approximately zero.

[0067] As shown in the figure, the common mode controlled impedance circuit C is a two-terminal circuit including a fourth resistor 24 and a seventh capacitor 25, and is configured as a parallel-connected circuit of the fourth resistor 24 and the seventh capacitor 25. One end of this common mode controlled impedance circuit C is connected to the secondary center tap of the intermediate transformer 9, i.e., the other end of the third winding 9c and the other end of the fourth winding 9d of the secondary winding of the intermediate transformer 9, and the other end is connected to the bias output terminal Tc.

[0068] In this common mode controlled impedance circuit C, the fourth resistor 24 has a predetermined resistance value (fourth resistance value) and is connected in parallel to the seventh capacitor 25. One end of this fourth resistor 24 is connected to the secondary center tap of the intermediate transformer 9 and one end of the seventh capacitor 25, and the other end is connected to the bias output terminal Tc and the other end of the seventh capacitor 25.

[0069] The seventh capacitor 25 has a predetermined capacitance (seventh capacitance) and is connected in parallel to the fourth resistor 24. One end of the seventh capacitor 25 is connected to the secondary center tap of the intermediate transformer 9 and one end of the fourth resistor 24, and the other end is connected to the bias output terminal Tc and the other end of the fourth resistor 24.

[0070] Such a common mode controlled impedance circuit C has a common mode controlled impedance Zs(ω) obtained by combining in parallel the fourth resistance value of the fourth resistor 24 and the seventh capacitance of the seventh capacitor 25. When the fourth resistance value is "Rs" and the seventh capacitance is "Cs", this common mode controlled impedance Zs(ω) is expressed by the following equation (1): Zs(ω)=1 / (1 / Rs+1 / Cs) (1)

[0071] As described in Non-Patent Document 1, such a common mode controlled impedance circuit C suppresses intermodulation waves generated in the pre-amplifier section (first-stage amplifier section) of the differential amplifier circuit A, and reduces distortion of the output amplified signal output from the differential amplifier circuit A to the load L. In other words, the common mode controlled impedance circuit C has the function of improving the linearity of the differential amplifier circuit A.

[0072] Next, the operation and performance of the amplifier AF according to the first embodiment will be described in detail with reference to FIGS.

[0073] This amplifier AF amplifies a high-frequency signal input from a signal source G to a pair of input terminals T1 and T2 using a differential amplifier circuit A, and outputs the amplified signal from a pair of output terminals T3 and T4 to a load L. That is, the high-frequency signal is primarily amplified in a front-stage amplifier section (first-stage amplifier section) of the differential amplifier circuit A, and then secondarily amplified in a rear-stage amplifier section (second-stage amplifier section) before being supplied to the load L.

[0074] In the differential amplifier circuit A, the first stage amplifier (first stage amplifier) ​​includes a first resistor 3, a second resistor 4, and a first bias power supply V ＢＢ１ The operating point of the differential amplifier is set by the following: In the post-stage amplifier (second-stage amplifier), the bias voltage V supplied from the bias circuit B via the common mode control impedance circuit C is Ｂ The operating point of the differential amplifier is set by:

[0075] In such a differential amplifier circuit A, the common-mode controlled impedance circuit C can exhibit its inherent performance to reduce second-order intermodulation waves and second harmonic waves, thereby reducing distortion in the output amplified signal. That is, when the circuit impedance (output impedance) when the common-mode controlled impedance circuit C is viewed from the secondary center tap of the intermediate transformer 9 is the common-mode controlled impedance Zs(ω), the second-order intermodulation waves and second harmonic waves included in the output amplified signal are reduced.

[0076] That is, if the bias circuit B has a significant bias circuit impedance (output impedance) for the composite signal (high frequency signal), the composite impedance of the common mode control impedance Zs(ω) and the bias circuit impedance acts on the composite signal (high frequency signal). In this case, the common mode control impedance circuit C does not perform its original function of reducing second-order intermodulation waves and double waves.

[0077] In view of this situation, the bias circuit B according to the first embodiment has circuit performance such that the bias circuit impedance Zb(ω) seen from one end of the common mode controlled impedance circuit C is approximately zero, as will be described below.

[0078] That is, the composite signal input from the secondary intermediate tap of the intermediate transformer 9 to the bias output terminal Tc is inverted and amplified by the tenth transistor 19 (amplifying transistor), and is input as an inverted amplified composite signal from the collector terminal of the tenth transistor 19 to the emitter terminal of the ninth transistor 18 (cascode transistor).

[0079] The inverted amplified composite signal is then input from the collector terminal of the ninth transistor 18 (cascode transistor) to the base terminal (input terminal) of the eleventh transistor 20 (feedback transistor), buffered (current amplified) by the eleventh transistor 20, and output to the bias output terminal Tc.

[0080] In such bias circuit B, the gain in the feedback loop (loop gain) is 1. Therefore, the inverted amplified composite signal input from the emitter terminal of the eleventh transistor 20 to the bias output terminal Tc has the same amplitude but the opposite phase to the composite signal input from the secondary intermediate tap of the intermediate transformer 9 to the bias output terminal Tc.

[0081] Therefore, the composite signal input from the secondary intermediate tap of the intermediate transformer 9 to the bias output terminal Tc is canceled by the inverted amplified composite signal input from the emitter terminal of the eleventh transistor 20 to the bias output terminal Tc. As a result, the bias circuit impedance Zb(ω) of the bias circuit B becomes approximately zero.

[0082] Figure 2 shows the frequency characteristics of such bias circuit impedance Zb(ω). In Figure 2, the solid line shows the bias circuit impedance Zb(ω) of bias circuit B, and the dashed line shows the bias circuit impedance of a general bias circuit as a comparative example. Note that the general bias circuit does not have the above-mentioned feedback loop.

[0083] 2, the bias circuit impedance Zb(ω) of the bias circuit B according to the first embodiment is approximately zero in the frequency band of 0 GHz to approximately 1 GHz, and increases only slightly in the frequency band of approximately 1 GHz to 10 GHz. In contrast, the bias circuit impedance of the bias circuit of the comparative example is approximately 6 Ω in the frequency band of 0 GHz to approximately 1 GHz, and increases from approximately 6 Ω in the frequency band of approximately 1 GHz to 10 GHz.

[0084] 3 also shows the average power of the output power Pout_low of the third-order intermodulation wave 2ω1-ω2 and the output power Pout_high of the third-order intermodulation wave 2ω2-ω1 when two signals of frequencies ω1 and ω2 (ω2>ω1) are input. In this Fig. 3, the solid line shows the average power of the amplifier AF according to the first embodiment, and the dashed line shows the average power of the amplifier of the comparative example that uses the bias circuit of the comparative example instead of the bias circuit B.

[0085] 3, the average power of the third-order intermodulation waves in the amplifier AF according to the first embodiment is smaller than the average power of the third-order intermodulation waves in the amplifier of the comparative example. In other words, the amplifier AF according to the first embodiment has better linearity than the amplifier of the comparative example.

[0086] 4A and 4B show the effect of the fifth capacitor 22 (compensation capacitor) in the bias circuit B according to the first embodiment. In these figures, 4A shows the frequency characteristics of the bias circuit B, and 4B shows the frequency characteristics when the fifth capacitor 22 (compensation capacitor) is removed from the bias circuit B. In these figures, the solid line shows the frequency characteristics of gain, and the dashed line shows the frequency characteristics of phase.

[0087] 4A and 4B, by providing the fifth capacitor 22 (compensation capacitor) in the bias circuit B, the phase margin is improved from about 37° to about 65°. That is, the bias circuit B according to the first embodiment can operate in a stable state, and therefore a stable bias voltage V Ｂ It is possible to supply

[0088] As described above, the bias circuit B according to the first embodiment includes a tenth transistor 19 (amplifying transistor) that amplifies a high-frequency signal input to the bias output terminal Tc, an eleventh transistor 20 (feedback transistor) that feeds back the output of the tenth transistor 19 to the bias output terminal Tc, and a constant current source 17 connected to the base terminal (input terminal) of the eleventh transistor 20, and outputs a bias voltage V Ｂ is output to the common mode controlled impedance circuit C.

[0089] According to the first embodiment, the bias circuit impedance Zb(ω) of the bias circuit B is approximately zero, so it is possible to provide a bias circuit B that allows the common mode controlled impedance circuit C to function normally.

[0090] Furthermore, in the bias circuit B according to the first embodiment, a fifth capacitor 22 (compensation capacitor) is provided between the bias output terminal Tc and the base terminal (input terminal) of the eleventh transistor 20. According to the first embodiment, the bias circuit B can operate in a stable state, and therefore a stable bias voltage V is applied to the differential amplifier circuit A. Ｂ can be supplied.

[0091] In the bias circuit B according to the first embodiment, the current output terminal of the constant current source 17 is electrically connected to the collector terminal (output terminal) of the tenth transistor 19 (amplifying transistor) and the base terminal (input terminal) of the eleventh transistor 20. According to the first embodiment, the reference current I flowing from the current output terminal of the constant current source 17 to the collector terminal (output terminal) of the tenth transistor 19 (amplifying transistor) ｒｅｆ The output voltage of the eleventh transistor 20, i.e., the bias voltage V Ｂ is set.

[0092] In addition, in the bias circuit B according to the first embodiment, a ninth transistor 18 (cascode transistor) is provided between the collector terminal (output terminal) of the tenth transistor 19 (amplifying transistor) and the current output terminal of the constant current source 17 and the base terminal (input terminal) of the eleventh transistor 20.

[0093] According to the first embodiment, the ninth transistor 18 (cascode transistor) is cascode-connected to the tenth transistor 19 (amplification transistor), so a high bias voltage V Ｂ It is possible to set

[0094] Furthermore, the amplifier AF according to the first embodiment includes a bias circuit B, an amplifier circuit A, and a common-mode controlled impedance circuit C provided between the bias circuit B and the amplifier circuit A. According to the first embodiment, the common-mode controlled impedance circuit C can function normally, thereby suppressing distortion of the output amplified signal output to the load L and providing an amplifier AF with excellent linearity.

[0095] Furthermore, in the amplifier AF according to the first embodiment, the common-mode control impedance circuit C is configured as a parallel-connected circuit of the fourth resistor 24 and the seventh capacitor 25. According to the first embodiment, it is possible to effectively suppress distortion of the output amplified signal output to the load L, and therefore it is possible to provide an amplifier AF with excellent linearity.

[0096] 5, an amplifier AF1 according to a second embodiment includes a differential amplifier circuit A, a bias circuit B1, and a common-mode controlled impedance circuit C. That is, in this amplifier AF1, the bias circuit B in the first embodiment is replaced with the bias circuit B1.

[0097] The bias circuit B1 in the second embodiment includes a fifth resistor 26 and an eighth capacitor 27 instead of the fifth capacitor 22 in the first embodiment. The fifth resistor 26 has a predetermined resistance value (fifth resistance value) and forms a low-pass filter together with the eighth capacitor 27. One end of the fifth resistor 26 is connected to the output terminal of the constant current source 17 and the collector terminal of the ninth transistor 18, and the other end is connected to the base terminal of the eleventh transistor 20 and one end of the eighth capacitor 27.

[0098] The eighth capacitor 27 has a predetermined capacitance (eighth capacitance) and forms a low-pass filter together with the fifth resistor 26. One end of the eighth capacitor 27 is connected to the other end of the fifth resistor 26 and the base terminal of the eleventh transistor 20, and the other end is grounded.

[0099] That is, in the bias circuit B1 according to the second embodiment, the collector terminal of the ninth transistor 18 is not directly connected to the base terminal of the eleventh transistor 20, but a low-pass filter (first-order low-pass filter) consisting of the fifth resistor 26 and the eighth capacitor 27 is inserted between the output terminal of the constant current source 17 and the base terminal of the eleventh transistor 20.

[0100] In this bias circuit B1, the fifth capacitor 22 is not provided, but a low-pass filter consisting of a fifth resistor 26 and an eighth capacitor 27 is provided. The fifth resistance value of the fifth resistor 26 and the eighth capacitance of the eighth capacitor 27 are set so that the phase margin is equivalent to that of the bias circuit B according to the first embodiment. Therefore, similar to the bias circuit B according to the first embodiment, a stable bias voltage V Ｂ can be supplied to the differential amplifier circuit A.

[0101] 6 shows the average power of the output power Pout_low of the third-order intermodulation wave 2ω1-ω2 and the output power Pout_high of the third-order intermodulation wave 2ω2-ω1 when two signals of frequencies ω1 and ω2 (ω2>ω1) are input to the amplifier AF1 according to the second embodiment. In this Fig. 6, the solid line shows the average power of the amplifier AF1 according to the second embodiment, and the dashed line shows the average power of the amplifier of the comparative example in which the bias circuit of the comparative example is used instead of the bias circuit B1 according to the second embodiment.

[0102] 6, the average power of the third-order intermodulation waves in the amplifier AF1 according to the second embodiment is smaller than the average power of the third-order intermodulation waves in the amplifier of the comparative example. In other words, the amplifier AF1 according to the second embodiment, like the bias circuit B according to the first embodiment, has better linearity than the amplifier of the comparative example.

[0103] As described above, the bias circuit B1 according to the second embodiment includes the tenth transistor 19 (amplifying transistor) that amplifies the high-frequency signal input to the bias output terminal Tc, the eleventh transistor 20 (feedback transistor) that feeds back the output of the tenth transistor 19 to the bias output terminal Tc, and the constant current source 17 that is electrically connected to the base terminal (input terminal) of the eleventh transistor 20 via a low-pass filter. The bias voltage VB is output from the bias output terminal Tc to the common mode control impedance circuit C, and a low-pass filter consisting of the fifth resistor 26 and the eighth capacitor 27 is provided between the collector terminal (output terminal) of the tenth transistor 19 (amplifying transistor) and the base terminal (input terminal) of the eleventh transistor 20 (feedback transistor).

[0104] The second embodiment as described above provides the same effects as the bias circuit B and amplifier AF according to the first embodiment. That is, the second embodiment can provide a bias circuit B1 that allows the common mode controlled impedance circuit C to function normally, and can also provide an amplifier AF1 that suppresses distortion of the output amplified signal output to the load L and has excellent linearity.

[0105] The present invention is not limited to the above-described embodiment, and the following modifications are possible: (1) In the above-described embodiment, a differential amplifier circuit A is used as the amplifier circuit, but the present invention is not limited to this. The amplifier circuit in the present invention may be an amplifier circuit of a form other than the differential amplifier circuit A.

[0106] (2) In the above embodiment, the fifth capacitor 22 (compensation capacitor) is provided between the bias output terminal Tc and the base terminal (input terminal) of the eleventh transistor 20, or the low-pass filter consisting of the fifth resistor 26 and the eighth capacitor 27 is provided between the collector terminal (output terminal) of the tenth transistor 19 (amplification transistor) and the base terminal (input terminal) of the eleventh transistor 20 (feedback transistor). However, the present invention is not limited to this. The fifth capacitor 22 (compensation capacitor) or the low-pass filter may be omitted as necessary.

[0107] (3) In the above embodiment, the ninth transistor 18 (cascode transistor) is provided between the collector terminal (output terminal) of the tenth transistor 19 (amplifying transistor) and the current output terminal of the constant current source 17 and the base terminal (input terminal) of the eleventh transistor 20. However, the present invention is not limited to this. In other words, the ninth transistor 18 (cascode transistor) may be omitted as necessary.

[0108] (4) In the above embodiment, the amplifier transistor, feedback transistor, and cascode transistor are configured as NPN bipolar transistors, but the present invention is not limited to this. That is, the amplifier transistor, feedback transistor, and cascode transistor in the present invention may be transistors of a type other than NPN bipolar transistors, such as field effect transistors.

[0109] (5) In the above embodiment, the common-mode controlled impedance circuit C is configured as a parallel-connected circuit of the fourth resistor 24 and the seventh capacitor 25. However, the present invention is not limited to this. For example, the common-mode controlled impedance circuit C may be configured with only a resistor. According to such a modification, it is possible to suppress distortion of the output amplified signal output to the load L with a simple circuit configuration.

[0110] A differential amplifier circuit (amplifier circuit), AF, AF1 amplifier, B, B1 bias circuit, C common mode controlled impedance circuit, G signal source, L load, Tc bias output terminal, Zs(ω) output impedance, 1 first transistor, 2 second transistor, 3 first resistor, 4 second resistor, 5 third transistor, 6 fourth transistor, 7 first capacitor, 8 second capacitor, 9 intermediate transformer, 10 fifth transistor, 11 sixth transistor, 12 seventh transistor, 13 eighth transistor, 14 third capacitor, 15 fourth capacitor, 16 output transformer, 17 constant current source, 18 ninth transistor (cascode transistor), 19 tenth transistor (amplifying transistor), 20 eleventh transistor (feedback transistor), 21 third resistor, 22 fifth capacitor, 23 sixth capacitor, 24 fourth resistor, 25 seventh capacitor, 26 fifth resistor, 27 eighth capacitor

Claims

1. A bias circuit comprising: an amplifying transistor that amplifies a signal input to a bias output terminal; a feedback transistor that feeds back the output of the amplifying transistor to the bias output terminal; and a constant current source connected to the input terminal of the feedback transistor, wherein the bias circuit outputs a bias voltage from the bias output terminal to a common mode controlled impedance circuit.

2. The bias circuit of claim 1, further comprising a compensation capacitor provided between said bias output and said input of said feedback transistor.

3. The bias circuit according to claim 1 or 2, wherein the constant current source has a current output terminal electrically connected to the output terminal of the amplifier transistor and the input terminal of the feedback transistor.

4. The bias circuit according to any one of claims 1 to 3, wherein a cascode transistor is provided between the output terminal of the amplifying transistor and the current output terminal of the constant current source and the input terminal of the feedback transistor.

5. The bias circuit according to any one of claims 1, 3 and 4, wherein a low-pass filter is provided between the output terminal of the amplifying transistor and the input terminal of the feedback transistor.

6. An amplifier comprising: a bias circuit according to any one of claims 1 to 5; an amplifier circuit; and a common-mode controlled impedance circuit provided between the bias circuit and the amplifier circuit.

7. The amplifier of claim 6, wherein said common-mode controlled impedance circuit consists solely of resistors.

8. The amplifier of claim 6, wherein the common-mode controlled impedance circuit is configured as a parallel connection circuit of a resistor and a capacitor.

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