Light-emitting element, and display device and electronic device comprising same

Abstract

A display device according to one embodiment comprises: a substrate; pixel electrodes arranged on the substrate; and light-emitting elements arranged on the pixel electrodes, wherein each of the light-emitting elements includes: a semiconductor stack containing a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; light extraction patterns which are arranged on a light-emitting surface of the semiconductor stack, and which include recess parts spaced apart from an end of the light-emitting surface and protrusion parts that surround the recess parts; and a protective layer that encompasses side surfaces of the semiconductor stack, and the light-emitting elements include the light extraction patterns of the same shape.

Description

Light-emitting elements, and display devices and electronic devices including the same

[0001] Embodiments of the present invention relate to light-emitting elements, and display devices and electronic devices including the same.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. In response, various types of display devices, including light-emitting displays, are being developed.

[0003] The light-emitting display device may include light-emitting elements, such as organic light-emitting diodes (OLEDs), ultra-small light-emitting elements, such as micro light-emitting diodes (micro LEDs) or nano light-emitting diodes (nano LEDs). Ultra-small light-emitting elements are made of inorganic materials, and thus have the advantage of having a longer lifespan and less deterioration issues compared to organic light-emitting elements.

[0004] The problem to be solved by the present invention is to provide a light-emitting element with improved light emission characteristics, and a display device and electronic device including the same.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] A display device according to one embodiment includes a substrate; pixel electrodes disposed on the substrate; and light-emitting elements disposed on the pixel electrodes, each of the light-emitting elements including a semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; light-extracting patterns disposed on a light-emitting surface of the semiconductor stack and including groove portions spaced apart from an end of the light-extracting surface and protrusion portions surrounding the groove portions; and a protective film covering a side surface of the semiconductor stack, wherein the light-emitting elements may include light-extracting patterns having the same shape.

[0007] In one embodiment, the light extraction patterns may be arranged in the same structure on the light-emitting surface of each of the light-emitting elements.

[0008] In one embodiment, the light emitting elements may include the same number of light extraction patterns.

[0009] In one embodiment, the light extraction pattern disposed at the outermost edge of the light-emitting surface of each of the light-emitting elements may be disposed on the inner side of the light-emitting surface, spaced apart from an end of the light-emitting surface.

[0010] In one embodiment, the light extraction patterns may be arranged in a plurality of columns, including a first column and a second column, on the light-emitting surface of each of the light-emitting elements.

[0011] In one embodiment, the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row may be spaced apart from the first end of the light-emitting surface by the same distance.

[0012] In one embodiment, the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row may be spaced apart from the first end of the light-emitting surface by different distances.

[0013] In one embodiment, at least one of the light extraction patterns may be in contact with an end of the light-emitting surface.

[0014] In one embodiment, the at least one light extraction pattern may be in contact with an end of the light-emitting surface at the protrusion portion and may be covered with the protective film.

[0015] In one embodiment, the light extraction patterns can be formed on the upper surface of the second semiconductor layer.

[0016] A light-emitting device according to one embodiment may include a semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; a protective film surrounding a side surface of the semiconductor stack; and light extraction patterns disposed on a light-emitting surface of the semiconductor stack, the light-extracting patterns including groove portions spaced apart from an end of the light-extracting surface and protrusion portions surrounding the groove portions.

[0017] In one embodiment, the light extraction pattern disposed at the outermost end of the light extraction patterns may be disposed on the inner side of the light extraction surface, spaced apart from the end of the light extraction surface.

[0018] In one embodiment, the light extraction patterns can be arranged in a plurality of columns including a first column and a second column in the first direction.

[0019] In one embodiment, the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row may be spaced apart from the first end of the light-emitting surface by the same distance.

[0020] In one embodiment, the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row may be spaced apart from the first end of the light-emitting surface by different distances.

[0021] In one embodiment, at least one of the light extraction patterns may be in contact with an end of the light-emitting surface.

[0022] An electronic device for providing an image according to one embodiment includes a display device, the display device including: a substrate; pixel electrodes disposed on the substrate; and light-emitting elements disposed on the pixel electrodes, each of the light-emitting elements including: a semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; light-extracting patterns disposed on a light-emitting surface of the semiconductor stack and including groove portions spaced apart from an end of the light-extracting surface and protrusion portions surrounding the groove portions; and a protective film covering a side surface of the semiconductor stack, wherein the light-emitting elements may include light-extracting patterns having the same shape.

[0023] Specific details of other embodiments are included in the detailed description and drawings.

[0024] According to the light-emitting device according to the embodiments, and the display device and electronic device including the same, light extraction patterns can be uniformly arranged on the light-emitting surface of the light-emitting device, and the side surface of the semiconductor stack can be stably covered with a protective film. As a result, the light-emitting characteristics of the light-emitting device can be uniformized, the light-emitting ratio can be improved, and the electrical stability of the light-emitting device can be secured.

[0025] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0026] Figure 1 is a perspective view showing a display device according to one embodiment.

[0027] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0028] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0029] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0030] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0031] FIG. 6 is a layout diagram showing pixels of a display area according to one embodiment.

[0032] Fig. 7 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 6.

[0033] Figure 8 is a cross-sectional view showing in detail one embodiment of area A1 of Figure 7.

[0034] FIG. 9 is a cross-sectional view showing in detail one embodiment of area A1 of FIG. 7.

[0035] Fig. 10 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7.

[0036] Fig. 11 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7.

[0037] Fig. 12 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7.

[0038] Fig. 13 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7.

[0039] Fig. 14 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 6.

[0040] Figure 15 is a cross-sectional view showing in detail one embodiment of area A2 of Figure 14.

[0041] Fig. 16 is a layout diagram showing pixels of a display area according to one embodiment.

[0042] Fig. 17 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 16.

[0043] Fig. 18 is a cross-sectional view showing in detail one embodiment of area B1 of Fig. 17.

[0044] Fig. 19 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 16.

[0045] Fig. 20 is a cross-sectional view showing in detail one embodiment of area B2 of Fig. 19.

[0046] Fig. 21 is a plan view showing a light emitting element according to one embodiment.

[0047] Fig. 22 is a plan view showing a light emitting element according to one embodiment.

[0048] Fig. 23 is a plan view showing a light emitting element according to one embodiment.

[0049] Fig. 24 is a plan view showing a light emitting element according to one embodiment.

[0050] Fig. 25 is a plan view showing a light emitting element according to one embodiment.

[0051] Fig. 26 is a plan view showing a light emitting element according to one embodiment.

[0052] Fig. 27 is a plan view showing a light emitting element according to one embodiment.

[0053] Fig. 28 is a plan view showing a light emitting element according to one embodiment.

[0054] Fig. 29 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0055] Figures 30 to 34 are cross-sectional views showing a method for manufacturing light-emitting elements according to one embodiment.

[0056] Fig. 35 is a cross-sectional view showing a method of arranging light-emitting elements according to one embodiment.

[0057] FIG. 36 is a plan view showing a patterned semiconductor substrate according to one embodiment.

[0058] Fig. 37 is a plan view showing a semiconductor substrate on which a light-emitting element is formed according to one embodiment.

[0059] Figures 38 to 42 are cross-sectional views showing a method for manufacturing a light-emitting element according to one embodiment.

[0060] FIG. 43 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0061] FIGS. 44 and 45 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0062] FIG. 46 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0063] FIG. 47 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0064] FIG. 48 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0065] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0066] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0067] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0068] Specific embodiments are described below with reference to the attached drawings.

[0069] Figure 1 is a perspective view showing a display device according to one embodiment.

[0070] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and is included in various electronic devices (e.g., an electronic device for providing an image) such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc., and can be used as a display screen of the electronic devices.

[0071] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (for example, a micro light-emitting diode or a nano light-emitting diode). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0072] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply unit (500).

[0073] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0074] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0075] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light, but the embodiments of the present specification are not limited thereto.

[0076] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be disposed in the sub-area (SBA).

[0077] The display driving circuit (250) can generate signals and voltages for driving the display panel (100). The display driving circuit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) can be attached to the circuit board (300) using a COF (chip on film) method.

[0078] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0079] The power supply unit (500) can generate multiple panel driving voltages according to the power voltage supplied from the outside. The power supply unit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0080] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0081] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0082] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0083] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0084] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0085] The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) may be disposed on one side (for example, the left side) of the display panel (100), and the second scan driver (SDC2) may be disposed on the other side (for example, the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driver circuit (250) via scan fan out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0086] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0087] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0088] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0089] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0090] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0091] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0092] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0093] A plurality of pixels (PX) can be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) can extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) can extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0094] Each of the plurality of sub-pixels (SPX) may be connected to one of the plurality of write scan lines (GWL), one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of emission control lines (EL), and one of the plurality of data lines (DL). In describing the embodiments, the term "connection" may include a direct connection or an indirect connection, and may include the meaning of an electrical and / or physical connection. Each of the plurality of sub-pixels (SPX) may be supplied with a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0095] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0096] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and an emission control signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the emission control signal output unit (614) may receive a scan timing control signal (SCS) from the timing control unit (251).

[0097] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control unit (251) and sequentially output them to the write scan lines (GWL).

[0098] The initialization scan signal output unit (612) can generate initialization scan signals according to a scan timing control signal (SCS) and sequentially output them to initialization scan lines (GIL).

[0099] The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL).

[0100] The light emission control signal output unit (614) can generate light emission control signals according to a scan timing control signal (SCS) and sequentially output them to light emission control lines (EL).

[0101] The display driving circuit (250) includes a timing control unit (251) and a data driving unit (252).

[0102] The data driving unit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control unit (251). The data driving unit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0103] The timing control unit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control unit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control unit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control unit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving unit (252).

[0104] The power supply unit (500) can generate a plurality of panel driving voltages according to a power voltage supplied from an external source. For example, the power supply unit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), and a fourth driving voltage (VAINT) and supply them to the display panel (100).

[0105] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0106] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission control line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission control line (EL), and a data line (DL).

[0107] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a light-emitting element (LE). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0108] A driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode of the driving transistor (DT) according to a data voltage applied to the gate electrode of the driving transistor (DT).

[0109] The light emitting element (LE) may be a micro light emitting diode.

[0110] The light emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light emitting element (LE) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second driving voltage is applied.

[0111] A capacitor (C1) is formed between the gate electrode of the driving transistor (DT) and a first power line (VDL) to which a first driving voltage is applied. The first driving voltage may be a voltage of a higher level than the second driving voltage. One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0112] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0113] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). The gate electrode of the fifth transistor (ST5) and the gate electrode of the sixth transistor (ST6) may be connected to an emission control line (EL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission control signal of a gate low voltage are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission control line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third driving voltage (VINT of FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VAIL) to which a fourth driving voltage (VAINT of FIG. 3) is applied. The third driving voltage (VINT of FIG. 3) and the fourth driving voltage (VAINT of FIG. 3) may be different voltages. In addition, the third driving voltage (VINT of FIG. 3) and the fourth driving voltage (VAINT of FIG. 3) may be a voltage at a lower level than the first driving voltage (VDD) and a voltage at a higher level than the second driving voltage (VSS).

[0114] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors. In addition, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a scan signal of a gate high voltage is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In comparison, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and thus can be turned on when a scan signal of gate low voltage and a light emission control signal of gate low voltage are applied.

[0115] Alternatively, when the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed of an oxide semiconductor, and the active layers of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed of polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of a gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of a gate low voltage and a light emission control signal of a gate low voltage are applied.

[0116] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) are formed of an oxide semiconductor and can be turned on when a scan signal of a gate high voltage and a light emission control signal are applied.

[0117] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0118] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), it may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0119] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0120] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit first light, the second sub-pixel (SPX2) can emit second light, and the third sub-pixel (SPX3) can emit third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. For example, the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 370 nm to 460 nm.

[0121] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit a first light, the second and fourth sub-pixels may emit a second light, and the third sub-pixel may emit a third light. Alternatively, the first sub-pixel may emit a first light, the second sub-pixel may emit a second light, the third sub-pixel may emit a third light, and the fourth sub-pixel may emit a fourth light. In this case, the fourth light may be white light.

[0122] The first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LE), and a first light conversion layer (QDL1). The second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LE), and a second light conversion layer (QDL2). The third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LE), and a light-transmitting layer (or third light conversion layer) (TPL).

[0123] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0124] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). In addition, unlike the light transmitting layer (TPL) that directly transmits the light of the light emitting element (LE), the first light conversion layer (QDL1) must convert the light, so the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0125] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a first electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0126] A plurality of light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light emitting elements (LE) may emit a third light, for example, light in a blue wavelength band, but the embodiment of the present specification is not limited thereto. When the light emitting element (LE) of the first sub-pixel (SPX1) emits a first light, the light emitting element (LE) of the second sub-pixel (SPX2) emits a second light, and the light emitting element (LE) of the third sub-pixel (SPX3) emits a third light, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0127] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LE) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LE) of the first sub-pixel (SPX1) into first light.

[0128] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LE) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LE) of the second sub-pixel (SPX2) into second light.

[0129] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LE) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit the third light emitted from the plurality of light emitting elements (LE) of the third sub-pixel (SPX3).

[0130] Fig. 6 is a layout diagram showing pixels of a display area according to one embodiment. Fig. 6 shows an embodiment that is different from the embodiment of Fig. 4 with respect to light-emitting elements (LE) arranged in sub-pixels (SPX1, SPX2, SPX3).

[0131] Referring to FIG. 6, the sub-pixel (SPX) may include a single light-emitting element (LE) disposed on each pixel electrode (PXE1 / PXE2 / PXE3). In one embodiment, the light-emitting element (LE) may have a shape corresponding to the shape of each pixel electrode (PXE1 / PXE2 / PXE3), for example, a rectangular planar shape. For example, the light-emitting element (LE) may have a rectangular planar shape in which a length in a direction in which the long sides of the pixel electrodes (PXE1, PXE2, PXE3) extend, for example, a second direction (DR2), is longer than a length in the first direction (DR1).

[0132] However, the shape of the light emitting element (LE) is not limited thereto. For example, the light emitting element (LE) may have a circular planar shape as illustrated in Fig. 5, or may have a planar shape of a shape other than a circular or rectangular shape.

[0133] The light emitting element (LE) may have a size that can be appropriately or stably placed inside each pixel electrode (PXE1 / PXE2 / PXE3) or the light emitting area in which the pixel electrode (PXE1 / PXE2 / PXE3) is placed. The light emitting area of ​​each of the sub-pixels (SPX1, SPX2, SPX3) is an area in which the pixel electrode (PXE1 / PXE2 / PXE3) and the light emitting element (LE) of each of the sub-pixels (SPX1, SPX2, SPX3) are placed, and may be a light-transmitting area in which light generated from the light emitting element (LE) is emitted.

[0134] The type, number, shape, or size of the light emitting elements (LE) that may be arranged in each of the sub-pixels (SPX1, SPX2, SPX3) are not limited to the embodiments of FIGS. 5 and 6. For example, each of the sub-pixels (SPX1, SPX2, SPX3) may include light emitting elements (LE) of various types, numbers, shapes, and / or sizes according to embodiments. In addition, the sub-pixels (SPX1, SPX2, SPX3) may include the same or different numbers of light emitting elements (LE).

[0135] Fig. 7 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 6. Fig. 8 is a cross-sectional view showing in detail an embodiment of area A1 of Fig. 7.

[0136] Referring to FIGS. 7 and 8, the display panel (100) may include a thin film transistor layer (TFTL), pixel electrodes (PXE1, PXE2, PXE3) disposed on the thin film transistor layer (TFTL), light emitting elements (LE) disposed on the pixel electrodes (PXE1, PXE2, PXE3), and light conversion layers (QDL1, QDL2), a light transmitting layer (TPL), and color filters (CF1, CF2, CF3) disposed on the light emitting elements (LE).

[0137] A thin film transistor layer (TFTL) may include a substrate (SUB) and circuit elements and wirings arranged on the substrate (SUB). In Fig. 7, the substrate (SUB) is considered as a component included in the thin film transistor layer (TFTL), but the embodiments are not limited thereto. For example, the substrate (SUB) and the thin film transistor layer (TFTL) may be considered as separate elements, and the thin film transistor layer (TFTL) may be viewed as being arranged on the substrate (SUB). In Fig. 7, one thin film transistor (TFT1) included in each sub-pixel (SPX) is illustrated as representing the circuit elements of the thin film transistor layer (TFTL) (for example, circuit elements of the pixel circuit included in each of the sub-pixels (SPX1, SPX2, SPX3)).

[0138] The substrate (SUB) may be made of an insulating material such as glass or polymer resin. If the substrate (SUB) is made of polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0139] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film that protects the transistors of the thin film transistor layer (TFTL) and the light emitting elements (LE) disposed on the thin film transistor layer (TFTL) from moisture penetrating through the substrate (SUB) that is vulnerable to moisture permeation. The barrier film (BR) may be formed of a plurality of inorganic films that are alternately laminated.

[0140] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) illustrated in FIG. 7 may be either the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0141] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0142] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0143] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1).

[0144] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other, when the thin film transistor (TFT1) is the driving transistor (DT) of FIG. 4, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be electrically or physically connected to each other. Alternatively, when the thin film transistor (TFT1) is any one of the first to sixth transistors (ST1 to ST6) of FIG. 4, the first gate electrode (G1) and the first capacitor electrode (CAE1) may not be electrically or physically connected to each other.

[0145] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin film transistor (TFT1).

[0146] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0147] A first interlayer insulating film (141) may be placed on the second capacitor electrode (CAE2).

[0148] A first data metal layer may be disposed on an interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141).

[0149] A first planarization film (160) may be placed on the first source connection electrode (PCE1) to planarize the step caused by the thin film transistor (TFT1).

[0150] A second data metal layer may be disposed on the first planarization film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) penetrating the first planarization film (160).

[0151] A second planarization film (180) may be placed on the second source connection electrode (PCE2).

[0152] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0153] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0154] The first flattening film (160) and the second flattening film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0155] A light-emitting element layer may be arranged on the second planarization film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and an organic film (210, 211, 212).

[0156] A pixel electrode layer may be disposed on the second planarization film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a second source connection electrode (PCE2) through a pixel connection hole (CT1 / CT2 / CT3 of FIG. 5) penetrating the second planarization film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a first source region (S1) or a first drain region (D1) of a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin film transistor (TFT1) may be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0157] The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu) having a low surface resistance.

[0158] A first organic film (210) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The first organic film (210) serves to temporarily fix or adhere the plurality of light emitting elements (LE) to prevent the plurality of light emitting elements (LE) from tilting and falling over or tipping over during the process of transferring the plurality of light emitting elements (LE) to the display panel (100). That is, the first organic film (210) may be a film for temporarily adhering the plurality of light emitting elements (LE) to each of the pixel electrodes (PXE1, PXE2, PXE3). To facilitate the temporary adhering, the thickness of the first organic film (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3) and may be greater than the thickness of the contact electrode (CTE).

[0159] The first organic film (210) may be a photosensitive organic film such as a photoresist. Alternatively, the first organic film (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0160] A plurality of light emitting elements (LE) may be arranged on the first organic film (210). In Fig. 6, it is exemplified that each of the plurality of light emitting elements (LE) is a vertical type micro LED extending in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged in the third direction (DR3), which is a vertical direction.

[0161] Each of the plurality of light emitting elements (LE) may have a cross-sectional shape of a reverse taper. For example, each of the plurality of light emitting elements (LE) may have a cross-sectional shape of a trapezoid in which the width of the upper surface is wider than the width of the lower surface.

[0162] Each of the plurality of light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light-emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively. However, the size of each of the plurality of light-emitting elements (LE) may vary depending on the embodiments.

[0163] Each of the plurality of light emitting elements (LE) may be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LE) may be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) directly from the semiconductor substrate or via a transfer substrate. Alternatively, the plurality of light emitting elements (LE) may be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0164] The light emitting element (LE) may include at least a semiconductor stack (STC). For example, the light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), a contact electrode (CTE), and a passivation layer (INS). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) sequentially arranged in a third direction (DR3).

[0165] The conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). In Fig. 8, the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), but the embodiment of the present specification is not limited thereto. For example, the conductive layer (E1) may be disposed on a portion of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0166] The first semiconductor layer (SEM1) may be disposed on the conductive layer (E1). The first semiconductor layer (SEM1) may be formed of a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like, for example, gallium nitride (GaN).

[0167] The active layer (MQW) may be disposed on the first semiconductor layer (SEM1). The active layer (MQW) may include the same semiconductor material layer as the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). For example, when the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) include gallium nitride (GaN), the active layer (MQW) may also include gallium nitride (GaN). For example, the active layer (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0168] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials having a large band gap energy and semiconductor materials having a small band gap energy are alternately stacked, and may include other group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0169] When the active layer (MQW) includes indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0170] A second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn), for example, gallium nitride (GaN).

[0171] An electron blocking layer may be positioned between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0172] The superlattice layer may be positioned between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0173] The protective film (INS) can surround the side surface of the semiconductor stack (STC). For example, the protective film (INS) can be disposed on the side surface of the first semiconductor layer (SEM1), the side surface of the active layer (MQW), and the side surface of the second semiconductor layer (SEM2). The protective film (INS) can be a film for protecting the side surface of the light emitting element (LE). The protective film (INS) can be an inorganic film, for example, silicon nitride (SiN). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. In one embodiment, the protective film (INS) can also be disposed on the lower surface and side surfaces of the conductive layer (E1).

[0174] The contact electrode (CTE) may be disposed on the protective film (INS). The contact electrode (CTE) may be disposed between the first organic film (210) and the protective film (INS). The contact electrode (CTE) may be in contact with the first organic film (210).

[0175] In one embodiment, a plurality of contact electrodes (CTE) may be disposed on a passivation layer (INS). Each of the plurality of contact electrodes (CTE) may be disposed between a first organic film (210) and the passivation layer (INS). Each of the plurality of contact electrodes (CTE) may be in contact with the first organic film (210).

[0176] Although FIGS. 7 and 8 illustrate that the contact electrode (CTE) of each of the light-emitting elements (LE) is disposed on the first organic film (210), the embodiments of the present specification are not limited thereto. For example, the first organic film (210) may be disposed on the lower surface and a portion of the side surface of the contact electrode (CTE) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surface of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surface of the first semiconductor layer (SEM1), the side surface of the active layer (MQW), and the side surface of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the first organic film (210) may be disposed on a portion of the side surface of the second semiconductor layer (SEM2).

[0177] The contact electrode (CTE) can be connected to the exposed conductive layer (E1) without being covered by the protective film (INS). As a result, even if one of the contact electrodes (CTE) is not connected to the conductive layer (E1) due to a process error, the other contact electrode (CTE) is connected to the conductive layer (E1), thereby preventing a defect in which the light emitting element (LE) does not light up.

[0178] When the contact electrode (CTE) is formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light emitting element (LE) that propagates in the lateral direction of the light emitting element (LE) can be reflected by the contact electrode (CTE) and emitted to the upper surface of the light emitting element (LE). Therefore, since light loss of the light emitting element (LE) can be reduced, the light efficiency of the light emitting element (LE) can be increased. Therefore, in order to increase the light efficiency of the light emitting element (LE), it is preferable that the contact electrode (CTE) be arranged to cover most of the lateral surface of the semiconductor stack (STC).

[0179] The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the contact electrode (CTE) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0180] The connection electrode (BE) connects the contact electrode (CTE) of the light-emitting element (LE) and one of the pixel electrodes (PXE1, PXE2, PXE3). The connection electrode (BE) can be connected to one of the pixel electrodes (PXE1, PXE2, PXE3) exposed through a connection hole (BH) penetrating the first organic film (210). In addition, the connection electrode (BE) can be disposed on the upper surface of the first organic film (210) and the side surface of the contact electrode (CTE). In addition, the connection electrode (BE) can be disposed on a part of the side surface of the light-emitting element (LE). For example, the connection electrode (BE) can be disposed on a part of the passivation layer (INS) of the light-emitting element (LE).

[0181] The connecting electrode (BE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode (BE) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO), which can transmit light.

[0182] When the connecting electrode (BE) is made of a highly reflective metal material such as aluminum (Al), light emitted from the active layer (MQW) of the light emitting element (LE) that propagates in the lateral direction of the light emitting element (LE) can be reflected by the connecting electrode (BE) and propagate upwardly toward the light emitting element (LE). Accordingly, light loss from the light emitting element (LE) can be reduced, and thus the light efficiency of the light emitting element (LE) can be increased.

[0183] In embodiments, the light emitting element (LE) may include a patterned light-emitting surface. For example, the light emitting element (LE) may include light extraction patterns (LEP) arranged on the light-emitting surface of the semiconductor stack (STC), as illustrated in FIG. 8.

[0184] In one embodiment, the light-emitting surface of the semiconductor stack (STC) may be the upper surface of the semiconductor stack (STC), for example, the upper surface of the second semiconductor layer (SEM2). For example, the light extraction patterns (LEP) may be formed on the upper surface of the second semiconductor layer (SEM2).

[0185] In one embodiment, the light extraction patterns (LEP) are formed by etching the semiconductor stack (STC) and may be formed integrally with the semiconductor stack (STC). In this case, the light extraction patterns (LEP) may be considered a part of the semiconductor stack (STC). For example, when the light extraction patterns (LEP) are formed by etching the second semiconductor layer (SEM2), the light extraction patterns (LEP) may be considered a part of the second semiconductor layer (SEM2).

[0186] Light extraction patterns (LEP) may be patterns for increasing the emission efficiency of light passing through the light-emitting surface of the light-emitting element (LE). For example, the light extraction patterns (LEP) are micro-patterns formed to have a convex or concave shape on the light-emitting surface of the light-emitting element (LE), and may be formed in the form of a micro-lens array, a diffuse reflection structure, a diffuse refractive surface, etc. As long as they can have a shape or structure that can improve the light-emitting efficiency of the light-emitting element (LE), the shape, structure, size, etc. of the light extraction patterns (LEP) are not particularly limited. For example, the light extraction patterns (LEP) may be formed on the light-emitting surface of the light-emitting element (LE) to include regular or irregular curves or unevenness, and may have various shapes and / or sizes according to embodiments.

[0187] In one embodiment, the light extraction patterns (LEP) may include groove portions (GP) (e.g., portions including valleys of each of the light extraction patterns (LEP)) that are repeated along at least one of the first direction (DR1) and the second direction (DR2) and protrusion portions (PP) (e.g., portions including peaks of each of the light extraction patterns (LEP)) arranged around or around the groove portions (GP). The protrusion portions (PP) of each of the light extraction patterns (LEP) may surround the groove portions (GP). The groove portions (GP) and the protrusion portions (PP) of the light extraction patterns (LEP) may be regularly and / or periodically repeated in at least one direction, but are not limited thereto.

[0188] In one embodiment, the light extraction patterns (LEP) may include a plurality of groove portions (GP) having a hemispherical or semi-elliptical shape and protrusion portions (PP) arranged around the groove portions (GP). For example, the light extraction patterns (LEP) may include a plurality of groove portions (GP) having a semicircular or semi-elliptical cross-sectional shape and protrusion portions (PP) arranged around the groove portions (GP).

[0189] In one embodiment, the maximum length (Lmax) of the light extraction patterns (LEP) in the third direction (DR3) may be approximately several microns or less. In addition, the light extraction patterns (LEP) may be formed at a distance that can be sufficiently spaced from the active layer (MQW). For example, the maximum length (Lmax) of the light extraction patterns (LEP) in the third direction (DR3) may be less than or equal to half of the thickness of the second semiconductor layer (SEM2) (for example, the length of the second semiconductor layer (SEM2) in the third direction (DR3), but is not limited thereto). The size, shape, number, or arrangement interval of the light extraction patterns (LEP) may be appropriately set or changed in consideration of the size, shape, structure, light output efficiency, or stability of the light emitting element (LE).

[0190] Since the light emitting element (LE) includes light extraction patterns (LEP) formed on the light-emitting surface, the light-emitting efficiency of the light emitting element (LE) and the sub-pixel (SPX) including the LE can be improved.

[0191] In one embodiment, a semiconductor substrate for manufacturing a light emitting element (LE) may be patterned to form patterns corresponding to light extraction patterns (LEP) on a surface of the semiconductor substrate, and semiconductor material layers for forming a second semiconductor layer (SEM2), an active layer (MQW), and a first semiconductor layer (SEM1) may be sequentially formed (for example, grown) on the patterned semiconductor substrate, and then etched to manufacture the light emitting element (LE). Accordingly, the light emitting element (LE) may include light extraction patterns (LEP) on one surface on which the second semiconductor layer (SEM2) is disposed. In addition, the light emitting element (LE) may be disposed on each pixel electrode (PXE1 / PXE2 / PXE3) such that the light-emitting surface of the light emitting element (LE) on which the light extraction patterns (LEP) are disposed faces upward.

[0192] The shape, size, or process method or step for forming the light extraction patterns (LEP) included in the light emitting element (LE) may be varied in various ways depending on the embodiments. For example, in another embodiment, a patterning process for forming the light extraction patterns (LEP) may be additionally performed after manufacturing the light emitting element (LE) to form the light extraction patterns (LEP) on the light-emitting surface (e.g., the upper surface) of the light emitting element (LE).

[0193] In embodiments, the light emitting elements (LE) of the sub-pixels (SPX1, SPX2, SPX3) may include light extraction patterns (LEP) having the same shape. For example, the light extraction patterns (LEP) of the light emitting elements (LE) disposed on the pixel electrodes (PXE1, PXE2, PXE3) may be arranged with the same structure on the light-emitting surface of each of the light emitting elements (LE). In addition, the light emitting elements (LE) may include the same number of light extraction patterns (LEP). Accordingly, the light emission characteristics of the light emitting elements (LE) and the sub-pixels (SPX1, SPX2, SPX3) including the light emitting elements (LE) may be uniformized.

[0194] The second organic film (211) may be arranged to cover a portion of the side surface of the plurality of light-emitting elements (LE). In addition, the second organic film (211) may be arranged to cover the connection electrode (BE), but at least a portion of the connection electrode (BE) may be exposed without being covered by the second organic film (211).

[0195] The third organic film (212) may be disposed on the second organic film (211). The third organic film (212) may be disposed to cover a portion of a side surface of each of the plurality of light-emitting elements (LE). The third organic film (212) may be disposed on at least a portion of the connection electrode (BE) that is exposed and not covered by the second organic film (211). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the third organic film (212).

[0196] The second organic film (211) and the third organic film (212) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0197] The second organic film (211) and the third organic film (212) are layers for leveling the steps caused by the plurality of light-emitting elements (LE). If the height of the second organic film (211) is arranged to cover most of the side surfaces of each of the plurality of light-emitting elements (LE), the third organic film (212) may be omitted.

[0198] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the third organic film (212). The common electrode (CE) may be a common layer formed in common on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0199] The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0200] The first capping layer (CAP1) can be disposed on the common electrode (CE).

[0201] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in the first sub-pixel (SPX1), the first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in the second sub-pixel (SPX2), the second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in the third sub-pixel (SPX3), the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The light-shielding layer (BM) may overlap the second organic film (211) and the third organic film (212) in the third direction (DR3), and may not overlap the plurality of light-emitting elements (LE).

[0202] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0203] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). The second light conversion layer (QDL2) can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0204] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0205] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0206] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The length of the first light-blocking layer (BM1) in the first direction (DR1) or the length of the second direction (DR2) may be wider than the length of the second light-blocking layer (BM2) in the first direction (DR1) or the length of the second light-blocking layer (BM2) in the second direction (DR2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first shading layer (BM1) and the second shading layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0207] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-shielding layer (BM). The second capping layer (CAP2) may be disposed on the side surface and the upper surface of the light-shielding layer (BM). For example, the second capping layer (CAP2) may be disposed on the side surface of the first light-shielding layer (BM1) and the side surface and the upper surface of the second light-shielding layer (BM2).

[0208] A reflective film (RF) may be disposed between a light-shielding layer (BM) and a first light conversion layer (QDL1), between a light-shielding layer (BM) and a second light conversion layer (QDL2), and between a light-shielding layer (BM) and a light-transmitting layer (TPL). The reflective film (RF) may be disposed on a second capping layer (CAP2) disposed on a side surface of the first light-shielding layer (BM1) and a side surface of the second light-shielding layer (BM2). The reflective film (RF) serves to reflect light that propagates in a lateral direction in the first light-conversion layer (QDL1), the second light-conversion layer (QDL2), and the light-transmitting layer (TPL).

[0209] The reflective film (RF) may include a highly reflective metal material, such as aluminum (Al). The thickness of the reflective film (RF) may be approximately 0.1 μm.

[0210] Alternatively, the reflective film (RF) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to act as distributed Bragg reflectors (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be made of an inorganic film, for example, silicon nitride (SiN). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0211] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0212] The first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3) are inorganic films, for example, silicon nitride (SiN). x ), silicon nitride oxide (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) can be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0213] A fourth organic film (213) may be disposed on the third capping layer (CAP3). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0214] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0215] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the second light conversion layer (QDL2) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the second light conversion layer (QDL2). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0216] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0217] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap the light-blocking layer (BM) in the third direction (DR3).

[0218] A fifth organic film (214) for planarization may be placed on multiple color filters (CF1, CF2, CF3).

[0219] The fourth organic film (213) and the fifth organic film (214) can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0220] Fig. 9 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7. Fig. 10 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7.

[0221] FIGS. 9 and 10 show embodiments different from the embodiment of FIG. 8 with respect to the contact electrode (CTE) of the light emitting element (LE). In addition, FIGS. 9 and 10 show embodiments different from each other with respect to the connection structure of the contact electrode (CTE) of the light emitting element (LE) and the conductive layer (E1). In describing the embodiments below, any description overlapping with at least one embodiment described above will be omitted, and differences between the embodiments will be primarily described.

[0222] Referring to FIGS. 9 and 10, the light emitting element (LE) may include a single contact electrode (CTE) rather than multiple contact electrodes (CTE).

[0223] In one embodiment, the contact electrode (CTE) may be connected to the conductive layer (E1) in one or more regions of the conductive layer (E1). For example, as illustrated in FIG. 9, multiple regions of the conductive layer (E1) may be exposed without being covered by the protective film (INS). The contact electrode (CTE) may be connected to the conductive layer (E1) in each of the multiple regions of the conductive layer (E1). As a result, even if the contact electrode (CTE) is not connected to the conductive layer (E1) in one of the multiple regions due to a process error, the occurrence of a defect in which the light-emitting element (LE) does not light up can be prevented by connecting the contact electrode (CTE) to the conductive layer (E1) in another region.

[0224] In another embodiment, the protective film (INS) may include a single opening region on the lower surface of the conductive layer (E1), as illustrated in FIG. 10. A portion of the conductive layer (E1) exposed by the opening region of the protective film (INS) may be connected to the contact electrode (CTE).

[0225] Fig. 11 is a cross-sectional view showing in detail one embodiment of the A1 region of Fig. 7. Fig. 11 shows an embodiment different from the embodiment of Fig. 10 with respect to light extraction patterns (LEP) of a light emitting element (LE).

[0226] Although FIG. 11 discloses a modified embodiment of the embodiment of FIG. 10, the light extraction patterns according to the embodiment of FIG. 11 may also be applied to the light emitting element (LE) according to the embodiment of FIG. 8 or FIG. 9. For example, each embodiment disclosed herein may be applied or implemented alone or in combination with at least one other embodiment, and all possible combinations of the embodiments may fall within the scope of the present invention.

[0227] Referring to FIG. 11, the light extraction patterns (LEP) may include groove portions (GP) having a substantially "V" shaped cross-sectional shape and protrusion portions (PP) arranged around the groove portions (GP). For example, the groove portions (GP) of the light extraction patterns (LEP) may have a shape such as a cone with its apex pointing downward.

[0228] In one embodiment, the light extraction patterns (LEP) may be repeatedly arranged on the light-emitting surface of the light-emitting element (LE) with a gap (SP) as illustrated in FIG. 10, or may be repeatedly arranged on the light-emitting surface of the light-emitting element (LE) in a form that is in contact with each other as illustrated in FIG. 11.

[0229] In one embodiment, the outermost light extraction pattern (LEP) among the light extraction patterns (LEP) arranged on the light-emitting surface of the light-emitting element (LE) may be in contact with an end portion of the light-emitting surface (for example, a portion where the top surface and the side surface of the light-emitting element (LE) meet). In addition, the groove portions (GP) of the light extraction patterns (LEP) may not directly be in contact with the end portion of the light-emitting surface. For example, the outermost light extraction pattern (LEP) may meet the side end portion of the light-emitting element (LE) at the protrusion portion (PP).

[0230] In describing the embodiments, the protrusion portion (PP) of each of the light extraction patterns (LEP) may include a peak located at the highest height in each of the light extraction patterns (LEP), and the groove portion (GP) of each of the light extraction patterns (LEP) may include a valley located at the lowest height in each of the light extraction patterns (LEP). More broadly, the protrusion portion (PP) of each of the light extraction patterns (LEP) may refer to an upper portion of each of the light extraction patterns (LEP), and the groove portion (GP) of each of the light extraction patterns (LEP) may refer to a lower portion of each of the light extraction patterns (LEP). For example, the protrusion portion (PP) of each of the light extraction patterns (LEP) may include a portion located at a height greater than half of the highest height of each of the light extraction patterns (LEP), and the groove portion (GP) of each of the light extraction patterns (LEP) may include a portion located at a height less than half of the highest height of each of the light extraction patterns (LEP).

[0231] Since the outermost light extraction pattern (LEP) comes into contact with the side surface of the light emitting element (LE) at the portion where the protrusion portion (PP) is formed, the stability of the light emitting element (LE) can be ensured. For example, the protective film (INS) may not come into contact with the groove portions (GP) of the light extraction patterns (LEP). Accordingly, the protective film (INS) can stably wrap the side surface of the semiconductor stack (STC) to a height corresponding to the height of the protrusion portions (PP) of the light extraction patterns (LEP). Accordingly, a gap between electrodes (e.g., a contact electrode (CTE) and / or a connection electrode (BE)) arranged on the outside of the protective film (INS) and the semiconductor stack (STC) can be appropriately secured, and a short-circuit defect of the light emitting element (LE) can be prevented. In addition, by stably covering the side of the semiconductor stack (STC) by the protective film (INS), even when the light emitting element (LE) manufactured on the semiconductor substrate is placed on each pixel electrode (PXE1 / PXE2 / PXE3) using a laser in a process for placing the light emitting element (LE) on a transfer substrate or a display substrate, damage to the light emitting element (LE) at the interface between the semiconductor stack (STC) and the protective film (INS) can be prevented or minimized.

[0232] Fig. 12 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7. Fig. 13 is a cross-sectional view showing in detail one embodiment of area A1 of Fig. 7. Figs. 12 and 13 show embodiments different from the embodiments of Figs. 10 and 11, respectively, with respect to light extraction patterns of light-emitting elements (LEs).

[0233] Referring to FIGS. 12 and 13, the light extraction patterns (LEP) are positioned on the inner side of the light-emitting surface of the light-emitting element (LE) when viewed in plan view, and may be spaced apart from the side surface of the semiconductor stack (STC). For example, among the light extraction patterns (LEP) arranged on the light-emitting surface of the light-emitting element (LE), the outermost light extraction pattern (LEP) may be spaced apart from an end of the light-emitting surface (for example, a portion where the upper surface and the side surface of the semiconductor stack (STC) meet) by a distance. As the light extraction patterns (LEP) are arranged on the inner side of the light-emitting surface of the light-emitting element (LE), the physical and / or electrical stability of the light-emitting element (LE) can be further improved.

[0234] Fig. 14 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 6. Fig. 15 is a cross-sectional view showing in detail one embodiment of area A2 of Fig. 14.

[0235] FIGS. 14 and 15 show an embodiment different from the embodiment of FIGS. 7 and 8 with respect to a light emitting element layer including light emitting elements (LE). For example, FIGS. 14 and 15 show an embodiment of a display panel (100) in which light emitting elements (LE) are directly disposed on pixel electrodes (PXE1, PXE2, PXE3).

[0236] Referring to FIGS. 14 and 15, each of the light emitting elements (LE) may include a main body (CBD) and a bonding electrode (BDE) (also referred to as an “electrode” or a “bonding layer”) disposed on a lower surface of the main body (CBD). The light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3) (or bonding pads connected to the pixel electrodes (PXE1, PXE2, PXE3)) by the respective bonding electrodes (BDE). For example, the light emitting elements (LE) may be stably disposed or bonded on the pixel electrodes (PXE1, PXE2, PXE3) by a bonding method such as eutectic bonding.

[0237] When the light-emitting elements (LE) are directly disposed or bonded on the pixel electrodes (PXE1, PXE2, PXE3), the display panel (100) may not include the first organic film (210) and the connection electrodes (BE) of FIG. 7. In one embodiment, the pixel electrodes (PXE1, PXE2, PXE3) may be formed of multiple layers including a metal layer for appropriate connection with the light-emitting elements (LE), but are not limited thereto.

[0238] The main body (CBD) may be an LED chip body including a semiconductor stack (STC). For example, the main body (CBD) may include a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) sequentially arranged or laminated along one direction (for example, a third direction (DR3)). In one embodiment, the main body (CBD) may further include a conductive layer (E1) arranged on one surface (for example, a lower surface) of the first semiconductor layer (SEM1), and a protective film (INS) covering at least a side surface of the semiconductor stack (STC).

[0239] In one embodiment, the conductive layer (E1) may have a shape and / or size corresponding to the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2). For example, the conductive layer (E1) may be etched and patterned together with the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2) on a manufacturing substrate (e.g., a semiconductor substrate for growing semiconductor layers) for manufacturing light emitting elements (LE). Accordingly, the conductive layer (E1) may have a planar shape and size corresponding to the planar shape and size (e.g., area) of the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2). However, the shape or size of the conductive layer (E1) may vary depending on the embodiments.

[0240] In one embodiment, the protective film (INS) can further surround the conductive layer (E1). For example, the protective film (INS) can surround the side surfaces of the conductive layer (E1), the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2).

[0241] In one embodiment, the protective film (INS) may partially cover the lower surface of the conductive layer (E1). For example, the protective film (INS) may cover the edge portion of the lower surface of the conductive layer (E1) and may include an opening exposing the central portion of the conductive layer (E1). However, the embodiments are not limited thereto. For example, the protective film (INS) may only cover the side surfaces of the conductive layer (E1) or may not cover the conductive layer (E1).

[0242] In one embodiment, the main body (CBD) may have a rectangular cross-sectional shape, such as a square, rectangular, or trapezoidal shape. For example, the main body (CBD) may be a vertical micro LED chip having a square or rectangular cross-sectional shape. Alternatively, the main body (CBD) may have a trapezoidal cross-sectional shape. The type, shape, or size of the main body (CBD) may vary depending on the embodiments.

[0243] The bonding electrode (BDE) may include a conductive material suitable for bonding (e.g., a bonding metal). In one embodiment, the bonding electrode (BDE) may be disposed on a lower surface of a passivation layer (INS) and may be electrically connected to a conductive layer (E1) exposed by an opening in the passivation layer (INS). The bonding electrode (BDE) may be bonded onto each pixel electrode (e.g., a first pixel electrode (PXE1), a second pixel electrode (PXE2), or a third pixel electrode (PXE3)) and may be electrically connected to the pixel electrodes. In one embodiment, the bonding electrode (BDE) may be formed of a multilayer including a bonding metal layer and a capping layer disposed on at least one surface of the bonding metal layer. In one embodiment, the bonding electrode (BDE) may further include a reflective layer disposed between the bonding metal layer and the main body (CBD). The reflective layer may be formed of a metal layer including a metal having high light reflectivity, or may be formed of a distributed Bragg reflector.

[0244] In one embodiment, the light emitting element (LE) may further include a side reflector disposed on a side of the protective film (INS). In one embodiment, the side reflector may be formed of a metal layer including a metal having high light reflectivity, or may be formed of a distributed Bragg reflector.

[0245] The light emitting element (LE) may include light extraction patterns (LEP) formed on a light-emitting surface. For example, the light emitting element (LE) may include light extraction patterns (LEP) formed on an upper surface of a semiconductor stack (STC).

[0246] Fig. 16 is a layout diagram showing pixels of a display area according to one embodiment. The embodiment of Fig. 16 differs from the embodiment of Fig. 6 in that the light emitting elements (LEs) are arranged on pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3).

[0247] Referring to FIG. 16, pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3) may be arranged in the second direction (DR2) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape, but the embodiment of the present specification is not limited thereto. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiment of the present specification is not limited thereto.

[0248] When the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the second common electrode (CE2) may be larger than the area of ​​the first common electrode (CE1). In addition, while the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), the first light conversion layer (QDL1) must convert the light, and therefore, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3), and the area of ​​the first common electrode (CE1) may be larger than the area of ​​the third common electrode (CE3).

[0249] The first common electrode (CE1) can be connected to a second power line (VSL) to which a second driving voltage (VSS) is applied through a first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power line (VSL) through a third common connection hole (CT6). Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, and CE3).

[0250] In each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3), the light-emitting element (LE) may be disposed on the pixel electrode (PXE1 / PXE2 / PXE3) and the common electrode (CE1 / CE2 / CE3). For example, a part of the light-emitting element (LE) may be disposed on the pixel electrode (PXE1 / PXE2 / PXE3), and another part of the light-emitting element (LE) may be disposed on the common electrode (CE1 / CE2 / CE3). The length of the light-emitting element (LE) in the second direction (DR2) may be longer than the length in the first direction (DR1).

[0251] Fig. 17 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 16. Fig. 18 is a cross-sectional view showing in detail one embodiment of area B1 of Fig. 17. The embodiments of Figs. 17 and 18 differ from the embodiments of Figs. 7 and 8 in that the light-emitting element (LE) is a flip-type micro LED.

[0252] Referring to FIGS. 17 and 18, a pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) can be placed on a second planarization film (180).

[0253] The light emitting element (LE) may be a flip-type micro LED. A flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one surface (e.g., the lower surface) of the light emitting element (LE).

[0254] In one embodiment, the second semiconductor layer (SEM2) may include a heavily doped layer (SEM21) and a lightly doped layer (SEM22) having different doping concentrations. The heavily doped layer (SEM21) may be a portion of the second semiconductor layer (SEM2) in which the n-type dopant is greater than a predetermined threshold value and may be adjacent to the active layer (MQW). The lightly doped layer (SEM22) may be another portion of the second semiconductor layer (SEM2) in which the n-type dopant is less than a predetermined threshold value and may include or be adjacent to the light-emitting surface. For example, the lightly doped layer (SEM22) may include indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN) having an n-type dopant lower than a predetermined threshold value. In Fig. 18, the lightly doped layer (SEM22) is described as a part of the second semiconductor layer (SEM2), but the embodiments are not limited thereto. For example, the heavily doped layer (SEM21) may be referred to as the second semiconductor layer (SEM2), and the lightly doped layer (SEM22) may be referred to as an undoped semiconductor layer. The lightly doped layer (SEM22) may be disposed on the heavily doped layer (SEM21). In this case, light extraction patterns (LEP) can be formed on the upper surface of the low-concentration doping layer (SEM22).

[0255] However, the embodiments are not limited thereto. For example, the n-type dopant may be present at a predetermined threshold value or higher throughout the entire second semiconductor layer (SEM2). In this case, the entire second semiconductor layer (SEM2) may be a high-concentration doping layer, and light extraction patterns (LEPs) may be formed on the upper surface of the high-concentration doping layer.

[0256] A hole (LEH) can be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of the present specification are not limited thereto. For example, the hole (LEH) may have a polygonal planar shape, such as an ellipse or a square.

[0257] Additionally, the protective film (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed in the hole (LEH) without being covered by the protective film (INS).

[0258] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective film (INS). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0259] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). In this case, the first contact electrode (CTE1) may be disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), while the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0260] The second contact electrode (CTE2) can be disposed on the passivation layer (INS) disposed in the hole (LEH) and the second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the passivation layer (INS). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0261] Although FIGS. 17 and 18 disclose an embodiment in which the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light-emitting elements (LE) are disposed on the first organic film (210), the embodiment of the present specification is not limited thereto. For example, the first organic film (210) may be disposed on a portion of the lower surface and the side surface of the first contact electrode (CTE1) of each of the light-emitting elements (LE) and a portion of the lower surface and the side surface of the second contact electrode (CTE2) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surfaces of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the first organic film (210) may be disposed on a portion of each of the side surfaces of the second semiconductor layer (SEM2).

[0262] On each of the sides of the semiconductor stack (STC), an area adjacent to the upper surface of the semiconductor stack (STC) may be covered by a protective film (INS), but may be exposed without being covered by the first contact electrode (CTE1) or the second contact electrode (CTE2). For example, a separation distance (or height difference) between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3) may be approximately 100 nm or more. In one embodiment, the separation distance (or height difference) between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3). In this way, when the first contact electrode (CTE1) is spaced apart from the upper surface of the semiconductor stack (STC), the first contact electrode (CTE1) can be prevented from being peeled off by a chemical solution or the like during a manufacturing process. In addition, the separation distance (or height difference) between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3) may be approximately 100 nm or more. In addition, the separation distance (or height difference) between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3) may be greater than the maximum length (Lmax) of the light extraction pattern in the third direction (DR3). In this way, when the second contact electrode (CTE2) is spaced apart from the upper surface of the semiconductor stack (STC), the second contact electrode (CTE2) can be prevented from being peeled off by a chemical solution or the like during the manufacturing process.

[0263] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be disposed on three sides of the semiconductor stack (STC). For example, when the semiconductor stack (STC) includes first to fourth sides, the first contact electrode (CTE1) may be disposed on the first side, the second side, and the third side, and the second contact electrode (CTE2) may be disposed on the second side, the third side, and the fourth side.

[0264] The first connection electrode (BE1) connects the first contact electrode (CTE1) of the light emitting element (LE) and each pixel electrode (PXE1 / PXE2 / PXE3). The first connection electrode (BE1) can be connected to the pixel electrode (PXE1 / PXE2 / PXE3) exposed through the first connection hole (BH1) penetrating the first organic film (210). In addition, the first connection electrode (BE1) can be disposed on the upper surface of the first organic film (210) and the first contact electrode (CTE1).

[0265] The second connection electrode (BE2) connects the second contact electrode (CTE2) of the light emitting element (LE) and each common electrode (CE1 / CE2 / CE3). The second connection electrode (BE2) may be connected to the common electrode (CE1 / CE2 / CE3) exposed through the second connection hole (BH2) penetrating the first organic film (210). In addition, the second connection electrode (BE2) may be disposed on the upper surface of the first organic film (210) and the second contact electrode (CTE2).

[0266] The first connecting electrode (BE1) and the second connecting electrode (BE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the first connecting electrode (BE1) and the second connecting electrode (BE2) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0267] The conductive layer (E1) of the light emitting element (LE) can be connected to the pixel electrode (PXE1 / PXE2 / PXE3) via the first contact electrode (CTE1) and the first connection electrode (BE1). In addition, the second semiconductor layer (SEM2) of the light emitting element (LE) can be connected to the common electrode (CE1 / CE2 / CE3) via the second contact electrode (CTE2) and the second connection electrode (BE2).

[0268] In addition, on each of the sides of the semiconductor stack (STC), an area adjacent to the upper surface of the semiconductor stack (STC) may be exposed without being covered by the first connection electrode (BE1) or the second connection electrode (BE2). For example, a distance (or height difference) between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3), and a distance (or height difference) between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may each be greater than 100 nm. In this way, when the first connection electrode (BE1) and the second connection electrode (BE2) are spaced apart from the upper surface of the semiconductor stack (STC), the first connection electrode (BE1) and the second connection electrode (BE2) can be prevented from being peeled off by a chemical solution or the like during the manufacturing process.

[0269] Although FIG. 18 discloses an embodiment in which the first connection electrode (BE1) and the second connection electrode (BE2) are formed at a lower height than the first contact electrode (CTE1) and the second contact electrode (CTE2) to expose the upper surfaces of the first contact electrode (CTE1) and the second contact electrode (CTE2), the embodiments are not limited thereto. For example, the first connection electrode (BE1) and the second connection electrode (BE2) may be formed at a lower height than the first contact electrode (CTE1) and the second contact electrode (CTE2), or may be formed at a height higher than the height of the first contact electrode (CTE1) and the second contact electrode (CTE2).

[0270] Fig. 19 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 16. Fig. 20 is a cross-sectional view showing in detail an embodiment of area B2 of Fig. 19. The embodiments of Figs. 19 and 20 differ from the embodiments of Figs. 14 and 15 in that the light-emitting elements (LEs) are flip-type micro LEDs. In addition, the embodiments of Figs. 19 and 20 differ from the embodiments of Figs. 17 and 18 in that the light-emitting elements (LEs) are directly disposed on each pixel electrode (PXE1 / PXE2 / PXE3) and each common electrode (CE1 / CE2 / CE3).

[0271] Referring to FIGS. 19 and 20, the light emitting element (LE) may include a first bonding electrode (BDE1) (also referred to as a “first electrode” or a “first bonding layer”) instead of the first contact electrode (CTE1) and the first connection electrode (BE1) of FIGS. 17 and 18. In addition, the light emitting element (LE) may include a second bonding electrode (BDE2) (also referred to as a “second electrode” or a “second bonding layer”) instead of the second contact electrode (CTE2) and the second connection electrode (BE2) of FIGS. 17 and 18. In the embodiment of FIGS. 19 and 20, the display panel (100) may not include the first organic film (210) of FIGS. 17 and 18.

[0272] The first bonding electrode (BDE1) may be directly disposed or bonded on the pixel electrode (PXE1 / PXE2 / PXE3) and electrically connected to the pixel electrode (PXE1 / PXE2 / PXE3). The first bonding electrode (BDE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective film (INS) and may be electrically connected to the conductive layer (E1). Therefore, the pixel electrode (PXE1 / PXE2 / PXE3) and the conductive layer (E1) of the light-emitting element (LE) may be electrically connected through the first bonding electrode (BDE1).

[0273] The second bonding electrode (BDE2) may be directly disposed or bonded on the common electrode (CE1 / CE2 / CE3) and electrically connected to the common electrode (CE1 / CE2 / CE3). The second bonding electrode (BDE2) may be disposed on the second semiconductor layer (SEM2) that is exposed and not covered by the protective film (INS) in the hole (LEH) and may be electrically connected to the second semiconductor layer (SEM2). Therefore, the common electrode (CE1 / CE2 / CE3) and the second semiconductor layer (SEM2) of the light-emitting element (LE) may be electrically connected through the second bonding electrode (BDE2).

[0274] Fig. 21 is a plan view showing a light emitting element according to one embodiment. Fig. 22 is a plan view showing a light emitting element according to one embodiment. For example, Figs. 21 and 22 show different embodiments with respect to light extraction patterns (LEP) that can be arranged on a light-emitting surface (SF1) of a light emitting element (LE).

[0275] FIGS. 21 and 22 illustrate a rough planar shape of a light emitting element (LE) based on a light-emitting surface (SF1) of the light emitting element (LE). The light-emitting surface (SF1) of the light emitting element (LE) illustrated in FIGS. 21 and 22 may be an upper surface of a semiconductor stack (STC). Although FIGS. 21 and 22 disclose embodiments in which the light-emitting surface (SF1) of the light emitting element (LE) has a rectangular planar shape, the planar shape of the light emitting element (LE) may vary depending on the embodiments.

[0276] Referring to FIGS. 21 and 22, the light emitting element (LE) may include light extraction patterns (LEP) arranged or formed on the light-emitting surface (SF1). In one embodiment, the light extraction patterns (LEP) may have a planar shape that is approximately circular, but is not limited thereto. For example, the light extraction patterns (LEP) may have a planar shape that is oval, polygonal, or other shapes.

[0277] The light extraction patterns (LEP) may be repeatedly arranged on the light-emitting surface (SF1) of the light-emitting element (LE) along at least one direction. For example, the light extraction patterns (LEP) may be arranged in a plurality of columns in the first direction (DR1) and the second direction (DR2). In one embodiment, the light extraction patterns (LEP) may be arranged in a smaller number of columns in a short-side direction of the light-emitting element (LE), for example, in the first direction (DR1), and in a larger number of columns in a long-side direction of the light-emitting element (LE), for example, in the second direction (DR2). For example, the light extraction patterns (LEP) may be arranged in two or three columns in the first direction (DR1), and in four or more columns in the second direction (DR2).

[0278] The number, shape, size, arrangement interval, and / or arrangement structure of the light extraction patterns (LEP) may vary depending on embodiments. For example, depending on the length (e.g., the short side length) of the light-emitting surface (SF1) of the light-emitting element (LE) in the first direction (DR1) and the length (e.g., the diameter) of the light extraction patterns (LEP) in the first direction (DR1), the light extraction patterns (LEP) may be arranged in one column or two or more columns in the first direction (DR1). For example, as the length of each of the light extraction patterns (LEP) in the first direction (DR1) with respect to the short side length of the light-emitting surface (SF1) of the light-emitting element (LE) decreases, the light extraction patterns (LEP) may be arranged in a greater number of columns in the first direction (DR1). Alternatively, as the length of each of the light extraction patterns (LEP) in the first direction (DR1) with respect to the short side length of the light-emitting surface (SF1) of the light-emitting element (LE) decreases, the light extraction patterns (LEP) may be arranged at larger intervals in the first direction (DR1). Similarly, depending on the length (e.g., long side length) of the light-emitting surface (SF1) of the light-emitting element (LE) in the second direction (DR2) and the length (e.g., diameter) of the light extraction patterns (LEP) in the second direction (DR2), the light extraction patterns (LEP) may be arranged in one column or in two or more columns in the second direction (DR2).

[0279] In one embodiment, the light extraction patterns (LEP) may be arranged spaced apart from each other in at least one of the first direction (DR1) and the second direction (DR2). For example, the light extraction patterns (LEP) may be arranged with a first spacing (SP1) in the first direction (DR1) and with a second spacing (SP2) in the second direction (DR2). The lengths (or distances) of the first spacing (SP1) and the second spacing (SP2) may be the same or different. In one embodiment, the light extraction patterns (LEP) may be arranged with a uniform spacing in at least one of the first direction (DR1) and the second direction (DR2), but the embodiments are not limited thereto. When the light extraction patterns (LEP) are arranged with a uniform spacing, the light emission characteristics of the light emitting element (LE) can be more uniform.

[0280] Although FIGS. 21 and 22 disclose embodiments in which the light extraction patterns (LEPs) are arranged spaced apart from each other, the embodiments are not limited thereto. For example, the light extraction patterns (LEPs) may be arranged to contact each other in at least one of the first direction (DR1) and the second direction (DR2).

[0281] In one embodiment, the light extraction patterns (LEP) may be arranged on the inner side of the end portion (EDG) of the light-emitting surface (SF1) of the light-emitting element (LE) and spaced apart from the end portion (EDG). For example, the light extraction patterns (LEP) may not be arranged on the end portion (EDG) of the light-emitting surface (SF1).

[0282] In one embodiment, the light extraction patterns (LEP) may be arranged at positions spaced apart from a first end (EDG1) and a second end (EDG2) of the light exit surface (SF1) by a first distance (d1) and a second distance (d2), respectively. The first end (EDG1) and the second end (EDG2) of the light emitting element (LE) may be ends that extend in the first direction (DR1) and are located at opposite ends of the light exit surface (SF1) in the second direction (DR2). The first distance (d1) and the second distance (d2) may be the same as or different from each other. In addition, the light extraction patterns (LEP) may be arranged at positions spaced apart from a third end (EDG3) and a fourth end (EDG4) of the light exit surface (SF1) by a third distance (d3) and a fourth distance (d4), respectively. The third end (EDG3) and the fourth end (EDG4) of the light emitting element (LE) may be ends that extend in the second direction (DR2) and are located at opposite ends of the light-emitting surface (SF1) in the first direction (DR1). The third distance (d3) and the fourth distance (d4) may be the same or different from each other.

[0283] As the light extraction patterns (LEP) are arranged spaced apart from the end portion (EDG) of the light-emitting surface (SF1) of the light-emitting element (LE), the stability of the light-emitting element (LE) can be secured or improved. For example, as the groove portions (GP) of the light extraction patterns (LEP) having a relatively low height are spaced apart from the end portion (EDG) of the light-emitting surface (SF1), the side surface of the semiconductor stack (STC) can be stably covered by the passivation layer (INS). Accordingly, the short-circuit defect of the light-emitting element (LE) can be prevented and the electrical stability can be improved. In addition, even if the light-emitting element (LE) is irradiated with a laser during a transfer process of the light-emitting element (LE), the end portion of the light-emitting element (LE), for example, at the interface between the semiconductor stack (STC) and the passivation layer (INS) can be prevented from being damaged, causing changes in characteristics or defects in the light-emitting element (LE). Accordingly, it is possible to prevent or reduce the luminance dispersion of the light emitting element (LE) and improve the image quality of the display device (10) including the light emitting elements (LE).

[0284] In one embodiment, the light extraction patterns (LEP) can be spaced apart from at least one end (EDG) of the light emitting element (LE) by the same distance. For example, with respect to the first direction (DR1), the light extraction pattern (LEP) closest to the first end (EDG1) of the light exit surface (SF1) among the light extraction patterns (LEP) arranged in the first row of the light exit surface (SF1) and the light extraction pattern (LEP) closest to the first end (EDG1) of the light exit surface (SF1) among the light extraction patterns (LEP) arranged in the second row of the light exit surface (SF1) can be spaced apart from the first end (EDG1) of the light exit surface (SF1) by the same distance (for example, the first distance (d1)). Since the light extraction patterns (LEP) are arranged at equal distances from at least one end (EDG) of the light emitting element (LE), the light emission characteristics at the end (EDG) of the light emitting element (LE) can be made more uniform.

[0285] Fig. 23 is a plan view showing a light emitting element according to one embodiment. Fig. 24 is a plan view showing a light emitting element according to one embodiment. Fig. 25 is a plan view showing a light emitting element according to one embodiment. For example, Figs. 23 to 25 show embodiments that are different from the embodiments of Figs. 21 and 22 in relation to light extraction patterns (LEP) that can be arranged on a light-emitting surface (SF1) of a light emitting element (LE).

[0286] Referring to FIGS. 23 to 25, the light extraction patterns (LEP) arranged in different columns in at least one direction may be spaced apart from at least one end (EDG) of the light exit surface (SF1) by different distances. In one embodiment, as illustrated in FIGS. 23 and 24, the distance (d12, d11') between the light extraction patterns (LEP) arranged in odd columns in the first direction (DR1) and the first end (EDG1) of the light exit surface (SF1) may be different from the distance (d11, d12') between the light extraction patterns (LEP) arranged in even columns in the first direction (DR1) and the first end (EDG1) of the light exit surface (SF1). In another embodiment, as illustrated in FIG. 25, the distance (d41) between the light extraction patterns (LEP) arranged in odd columns in the second direction (DR2) and the fourth end (EDG4) of the light exit surface (SF1) may be different from the distance (d42) between the light extraction patterns (LEP) arranged in even columns in the second direction (DR2) and the fourth end (EDG4) of the light exit surface (SF1).

[0287] When the distance between the light extraction patterns (LEP) and the end portion (EDG) of the light-emitting surface (SF1) is differentiated in at least one of the first direction (DR1) and the second direction (DR2), the space utilization of the light-emitting surface (SF1) can be increased. Accordingly, when necessary, the light extraction patterns (LEP) can be arranged more densely to increase the light emission rate of the light-emitting element (LE).

[0288] Although FIGS. 23 to 25 disclose embodiments in which the distance between the light extraction patterns (LEP) and at least one end (EDG) of the light-emitting surface (SF1) of the light-emitting element (LE) is differentiated in a periodic manner of two columns in at least one of the first direction (DR1) and the second direction (DR2), the embodiments are not limited thereto. For example, the arrangement shape or period of the light extraction patterns (LEP) may be varied in various ways depending on the embodiments.

[0289] Fig. 26 is a plan view showing a light emitting element according to one embodiment. Fig. 27 is a plan view showing a light emitting element according to one embodiment. Fig. 28 is a plan view showing a light emitting element according to one embodiment. For example, Figs. 26 to 28 show embodiments that are different from the embodiments of Figs. 21 to 25 in relation to light extraction patterns (LEP) that can be arranged on a light-emitting surface (SF1) of a light emitting element (LE).

[0290] Referring to FIGS. 26 to 28, at least one of the light extraction patterns (LEP) may be in contact with an end portion (EDG) of the light exit surface (SF1). For example, the light extraction patterns (LEP) located at the outermost end portion in at least one of the first direction (DR1) and the second direction (DR2) among the light extraction patterns (LEP) may be in contact with an adjacent end portion (EDG) of the light exit surface (SF1). Accordingly, the area where the light extraction patterns (LEP) are arranged may be expanded, so that the light extraction patterns (LEP) may be arranged more efficiently on the light exit surface (SF1) of the light emitting element (LE). For example, by arranging the light extraction patterns (LEP) up to the end portion of the light exit surface (SF1), a greater number of light extraction patterns (LEP) may be arranged on the light exit surface (SF1) of the light emitting element (LE). Accordingly, the light emission characteristics (e.g., light emission rate and / or light emission uniformity) of the light emitting element (LE) can be further improved.

[0291] In one embodiment, each of the light extraction patterns (LEP) in contact with the end portion (EDG) of the light exit surface (SF1) may be in contact with the end portion (EDG) of the light exit surface (SF1) at a protrusion portion (PP). Accordingly, even when the light extraction patterns (LEP) are in contact with the end portion (EDG) of the light exit surface (SF1), the groove portions (GP) of the light extraction patterns (LEP) may be located inward of the end portion (EDG) of the light exit surface (SF1). In addition, the protrusion portions (PP) of the light extraction patterns (LEP) may be covered with a protective film (INS). Accordingly, damage, defects, or changes in characteristics of the light emitting element (LE) may be prevented.

[0292] In embodiments, the size, number, and / or spacing of the light extraction patterns (LEP) arranged on the light exit surface (SF1) of the light emitting element (LE) may vary depending on the size of the light emitting element (LE) and / or the size of the light extraction patterns (LEP). For example, when the light emitting element (LE) includes a light exit surface (SF1) of a specific size, as the size of each of the light extraction patterns (LEP) decreases, the number and / or density of the light extraction patterns (LEP) that can be arranged on the light exit surface (SF1) may increase. On the other hand, when each of the light extraction patterns (LEP) has a specific size, as the size of the light emitting element (LE) decreases, the number and / or density of the light extraction patterns (LEP) that can be arranged on the light exit surface (SF1) of the light emitting element (LE) may decrease.

[0293] In embodiments, by controlling the size, shape, number, and / or arrangement density of the light extraction patterns (LEP) by considering at least one of the size and shape of the light exit surface (SF1), the light extraction patterns (LEP) can be efficiently arranged on the light exit surface (SF1). Accordingly, the light emission characteristics of the light emitting element (LE) can be appropriately controlled or optimized. For example, the light extraction patterns (LEP) can be densely arranged on the light exit surface (SF1) so as to reduce or minimize the area of ​​the entire area of ​​the light exit surface (SF1) where the light extraction patterns (LEP) are not arranged. Accordingly, the light emission rate of the light emitting element (LE) can be improved.

[0294] Fig. 29 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. For example, Fig. 29 schematically illustrates manufacturing steps of a display device (10) including light-emitting elements (LE) including light extraction patterns (LEP) as in the embodiments described above.

[0295] Referring to FIG. 29, a method for manufacturing a display device (10) according to one embodiment may include a step (S110) of forming light-emitting elements (LE) including light extraction patterns (LEP), a step (S120) of arranging the light-emitting elements (LE) on a display substrate, and a step (S130) of performing a subsequent pixel process.

[0296] In one embodiment, the step (S110) of forming light-emitting elements (LE) including light extraction patterns (LEP) may include a step of forming light-emitting elements (LE) on a semiconductor substrate including patterns corresponding to the light extraction patterns (LEP). In another embodiment, the step (S110) of forming light-emitting elements (LE) including light extraction patterns (LEP) may include a step of forming light-emitting elements (LE) on a light-emitting surface (SF1) of each of the light-emitting elements (LE) after transferring the light-emitting elements (LE) formed on the semiconductor substrate onto a transfer substrate. A detailed description regarding a method of forming light-emitting elements (LE) including light extraction patterns (LEP) will be described later.

[0297] The step (S120) of arranging light-emitting elements (LE) on the display substrate may include a step of preparing a display substrate including pixel electrodes (PXE1, PXE2, PXE3) and arranging the light-emitting elements (LE) on the pixel electrodes (PXE1, PXE2, PXE3). In one embodiment, the step of preparing the display substrate may include a step of forming a thin film transistor layer (TFTL) including a substrate (SUB) and a thin film transistor (TFT1), as illustrated in FIG. 7, FIG. 14, FIG. 17, or FIG. 19, and forming at least one of the pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (for example, CE1, CE2, CE3 of FIG. 17 or 19) on the thin film transistor layer (TFTL). When arranging light emitting elements (LE) on the first organic film (210) as in the embodiment of FIG. 7 or FIG. 17, the first organic film (210) can be formed on a pixel electrode layer including at least one of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3).

[0298] The step (S130) of performing a subsequent pixel process may include a step of forming elements disposed on and / or around the light emitting elements (LE) after the light emitting elements (LE) are disposed in the display panel (100). For example, the step (S130) of performing a subsequent pixel process may include a step of forming the second organic film (211) and the third organic film (212) illustrated in FIG. 7, FIG. 14, FIG. 17, or FIG. 19 around the light emitting elements (LE), and forming a first capping layer (CAP1) on the light emitting elements (LE) and the third organic film (212). In addition, when manufacturing a display panel (100) including a common electrode (CE) disposed on the light emitting elements (LE) as illustrated in FIG. 7 or FIG. 14, the common electrode (CE) and the first capping layer (CAP1) may be sequentially formed on the third organic film (212).

[0299] Additionally, when manufacturing a display panel (100) in which a light control layer for changing or controlling the characteristics (e.g., color or wavelength of light) of light emitted from sub-pixels (SPX1, SPX2, SPX3) is disposed on a light emitting element layer including light emitting elements (LE) as illustrated in FIG. 7, FIG. 14, FIG. 17, or FIG. 19, the step (S130) of performing a subsequent pixel process may further include a step of forming a light control layer on the first capping layer (CAP1). For example, a light-shielding layer (BM), light conversion layers (QDL1, QDL2), a light-transmitting layer (TPL), etc. may be formed on the first capping layer (CAP1), and a color filter layer including color filters (CF1, CF2, CF3) may be formed.

[0300] FIGS. 30 to 34 are cross-sectional views showing a method for manufacturing light-emitting elements according to one embodiment. For example, FIGS. 30 to 34 sequentially show a method for manufacturing light-emitting elements (LE) including light extraction patterns (LEP) according to one embodiment. The manufacturing steps of FIGS. 30 to 34 may be included in step S110 of FIG. 29.

[0301] Fig. 35 is a cross-sectional view showing a method of arranging light-emitting elements according to one embodiment. For example, Fig. 35 schematically shows a method of arranging light-emitting elements (LE) including light extraction patterns (LEP) on pixel electrodes (PXE) of a display substrate (DSB).

[0302] Fig. 36 is a plan view showing a patterned semiconductor substrate according to one embodiment. For example, Fig. 36 is a plan view showing a semiconductor substrate (SSB) including the patterns (PTN) of Fig. 31.

[0303] Fig. 37 is a plan view showing a semiconductor substrate on which light-emitting elements are formed according to one embodiment. For example, Fig. 37 is a plan view showing a semiconductor substrate (SSB) on which light-emitting elements (LE) of Fig. 33 are formed.

[0304] Referring to Figure 30, a semiconductor substrate (SSB) is first prepared. The semiconductor substrate (SSB) may be a manufacturing substrate for manufacturing a light-emitting element (LE). For example, the semiconductor substrate (SSB) may be a growth substrate suitable for epitaxial growth.

[0305] In one embodiment, the semiconductor substrate (SSB) may include a material such as GaAs, silicon (Si), sapphire, SiC, GaN, or ZnO. For example, the semiconductor substrate (SSB) may be a silicon wafer or a sapphire substrate. As long as the epitaxial growth of a semiconductor material layer (e.g., a semiconductor material layer (SEML) of FIG. 32) for manufacturing a light emitting element (LE) can be smoothly performed, the type or material of the semiconductor substrate (SSB) is not particularly limited. Hereinafter, a case in which the semiconductor substrate (SSB) is a sapphire substrate will be described as an example.

[0306] In embodiments, a plurality of light-emitting elements (LE) may be formed simultaneously on a single semiconductor substrate (SSB). For example, the semiconductor substrate (SSB) may include a plurality of light-emitting element areas (LEAs) for forming a plurality of light-emitting elements (LEs). For convenience, FIGS. 30 to 37 illustrate a portion of a semiconductor substrate (SSB) including two light-emitting element areas (LEAs).

[0307] Referring to FIG. 31, a semiconductor substrate (SSB) may be patterned to form patterns (PTN) on the upper surface of the semiconductor substrate (SSB). As illustrated in FIG. 36, the patterns (PTN) may be formed in the light-emitting element areas (LEA). For example, the patterns (PTN) may be formed only inside the light-emitting element areas (LEA) and not in other areas.

[0308] The patterns (PTN) are for forming light extraction patterns (LEP) of the light emitting elements (LE), and may be formed in each light emitting element area (LEA) to match the size, shape, and / or arrangement structure of the light extraction patterns (LEP) to be formed on the light-emitting surface (SF1) of each of the light emitting elements (LE). For example, the patterns (PTN) may be formed in each light emitting element area (LEA) to match a predetermined size, shape, and / or arrangement structure. In one embodiment, the patterns (PTN) may be formed by a patterning process including a photolithography process. For example, the patterns (PTN) may be formed by etching the semiconductor substrate (SSB) after arranging a mask pattern on the semiconductor substrate (SSB) through a photolithography process. However, the method of forming the patterns (PTN) is not limited thereto, and the patterns (PTN) may be formed in another manner.

[0309] The patterns (PTN) can be aligned with the light emitting element areas (LEAs). For example, by aligning the mask pattern for forming the patterns (PTN) with the respective light emitting element areas (LEAs) using an alignment key, patterns (PTN) having a uniform shape can be formed inside the light emitting element areas (LEAs). For example, patterns (PTN) having the same shape, size, number, and / or arrangement can be formed in the light emitting element areas (LEAs). Accordingly, the light emitting elements (LE) formed in each of the light emitting element areas (LEAs) in a subsequent process can include light extraction patterns (LEP) having substantially the same shape. In one embodiment, the patterned semiconductor substrate (SSB) can be a patterned sapphire substrate (PSS) patterned to include patterns (PTN) according to embodiments.

[0310] Referring to FIG. 32, a semiconductor material layer (SEML) can be formed on a semiconductor substrate (SSB) including patterns (PTN). The semiconductor material layer (SEML) is for forming a semiconductor stack (STC) of each of the light emitting elements (LE), and may be formed of multiple layers for forming each layer of the semiconductor stack (STC). For example, the semiconductor material layer (SEML) may include a first semiconductor material layer (SEM2L) for forming a second semiconductor layer (SEM2) of the semiconductor stack (STC), a second semiconductor material layer (MQWL) for forming an active layer (MQW) of the semiconductor stack (STC), and a third semiconductor material layer (SEM1L) for forming the first semiconductor layer (SEM1) of the semiconductor stack (STC). A first semiconductor material layer (SEM2L), a second semiconductor material layer (MQWL), and a third semiconductor material layer (SEM1L) may be sequentially formed on a semiconductor substrate (SSB). The first semiconductor material layer (SEM2L), the second semiconductor material layer (MQWL), and the third semiconductor material layer (SEM1L) may each include semiconductor materials for forming a second semiconductor layer (SEM2), an active layer (MQW), and a first semiconductor layer (SEM1) of a semiconductor stack (STC), respectively.

[0311] In embodiments, the semiconductor material layer (SEML) may have a shape corresponding to the patterns (PTN) of the semiconductor substrate (SSB). For example, the lower surface of the first semiconductor material layer (SEM2L) may have a curvature corresponding to the patterns (PTN) of the semiconductor substrate (SSB).

[0312] The semiconductor material layer (SEML) can be formed by an epitaxial growth method using each semiconductor material. Here, the method for forming the semiconductor material layer (SEML) may be, but is not limited to, electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, or metal-organic chemical vapor deposition (MOCVD).

[0313] In one embodiment, when manufacturing light emitting elements (LE) including a conductive layer (E1), a conductive material layer (E1L) may be further formed on the semiconductor material layer (SEML). The conductive material layer (E1L) may include a conductive material for forming the conductive layer (E1). In one embodiment, the conductive material layer (E1L) may be formed by depositing a conductive material on the semiconductor material layer (SEML).

[0314] Referring to FIG. 33, by etching the semiconductor material layer (SEML) and the conductive material layer (E1L), light emitting elements (LE) can be formed in each light emitting element area (LEA). For example, as illustrated in FIG. 37, the light emitting elements (LE) may be formed only in each light emitting element area (LEA) including the patterns (PTN), and may not be formed in other areas.

[0315] In one embodiment, light emitting elements (LE) can be formed by etching a semiconductor material layer (SEML) and a conductive material layer (E1L) by a patterning process including a photolithography process, but the method of forming the light emitting elements (LE) is not limited thereto. The light emitting elements (LE) can include light extraction patterns (LEP) having a shape corresponding to the patterns (PTN) of the semiconductor substrate (SSB). The light emitting elements (LE) can include light extraction patterns (LEP) having substantially the same size, shape, and arrangement structure.

[0316] The light emitting elements (LE) may have various shapes and / or structures according to embodiments. When the light emitting elements (LE) further include a protective layer (INS) and at least one electrode (for example, at least one contact electrode (CTE) or bonding electrode (BDE)) according to the embodiments described above, an additional process for forming the protective layer (INS) and the electrode may be performed after etching the semiconductor material layer (SEML) and the conductive material layer (E1L).

[0317] Referring to FIG. 34, the light emitting elements (LE) can be transferred onto a first transfer substrate (TSB1), and the light emitting elements (LE) can be separated from the semiconductor substrate (SSB). In one embodiment, the first transfer substrate (TSB1) can include an adhesive layer formed on an upper surface, and the light emitting elements (LE) can be transferred onto the adhesive layer on the first transfer substrate (TSB1) to stably place the light emitting elements (LE) on the first transfer substrate (TSB1).

[0318] In one embodiment, the light emitting elements (LE) can be separated from the semiconductor substrate (SSB) by a laser lift-off (LLO) process that irradiates a laser onto the semiconductor substrate (SSB), but the method of separating the light emitting elements (LE) and the semiconductor substrate (SSB) is not limited thereto.

[0319] Referring to FIG. 35, after the light emitting elements (LE) are transferred from the first transfer substrate (TSB1) to the second transfer substrate (TSB2), they can be placed on the display substrate (DSB). In one embodiment, the second transfer substrate (TSB2) can include a laser separation layer formed on an upper surface, and after the light emitting elements (LE) are transferred onto the laser separation layer on the second transfer substrate (TSB2), the second transfer substrate (TSB2) can be placed on the display substrate (DSB) so that the light emitting elements (LE) face the display substrate (DSB). Each of the light emitting elements (LE) can be placed so that its lower surface, which is opposite to the upper surface on which the light extraction patterns (LEP) are placed, faces the display substrate (DSB).

[0320] The second transfer substrate (TSB2) may be formed of a transparent material that allows light to pass through. For example, the second transfer substrate (TSB2) may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The laser separation layer is a layer that can be separated by laser irradiation and may include, for example, a transparent polymer such as polyimide.

[0321] While the light emitting elements (LE) are arranged on the first transfer substrate (TSB1), one surface of each of the light emitting elements (LE) can be brought into contact with the laser separation layer of the second transfer substrate (TSB2) and heat can be applied. Accordingly, each of the light emitting elements (LE) can be adhered or fixed to the laser separation layer, and as the adhesive strength of the adhesive layer is weakened, each of the plurality of light emitting elements (LE) can be separated from the adhesive layer of the first transfer substrate (TSB1).

[0322] The display substrate (DSB) may include pixel electrodes (PXE). For example, the display substrate (DSB) may include pixel electrodes (PXE) disposed on a thin film transistor layer (TFTL). In one embodiment, each of the pixel electrodes (PXE) may be one of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) described above. The display substrate (DSB) may have various shapes according to embodiments. Accordingly, only a schematic form of the display substrate (DSB) is illustrated in FIG. 35.

[0323] Thereafter, the light emitting elements (LE) may be directly placed or connected on the pixel electrodes (PXE) by a eutectic bonding method, or the light emitting elements (LE) may be placed or connected on the pixel electrodes (PXE) by utilizing at least one connecting electrode (for example, the connecting electrode (BE) of FIG. 8, or the first connecting electrode (BE1) and the second connecting electrode (BE2) of FIG. 18). The method of placing or connecting the light emitting elements (LE) on the pixel electrodes (PXE1, PXE2, PXE3), or the connection structure between the light emitting elements (LE) and the pixel electrodes (PXE1, PXE2, PXE3) may vary depending on the embodiments.

[0324] After the light-emitting elements (LE) are arranged on the pixel electrodes (PXE), a subsequent pixel process can be performed to manufacture the display device (10). For example, a display panel (100) of the display device (10) can be manufactured by performing a subsequent pixel process including a process of forming a second organic film (211) and a third organic film (212) that surround the light-emitting elements (LE), and a first capping layer (CAP1) that covers the light-emitting elements (LE).

[0325] According to the above-described embodiment, light extraction patterns (LEP) can be uniformly formed on the light-emitting surfaces (SF1) of the light-emitting elements (LE). For example, the light-emitting elements (LE) manufactured according to the embodiment can include light extraction patterns (LEP) having substantially the same size, shape, and / or number. Accordingly, the light-emitting characteristics of the light-emitting elements (LE) and the sub-pixels (SPX) including the same can be improved. For example, by arranging the light-emitting elements (LE) including light extraction patterns (LEP) of a uniform shape in the sub-pixels (SPX), the light-emitting ratio of the light-emitting elements (LE) and the sub-pixels (SPX) including the same can be increased while the light-emitting characteristics can be made uniform. In addition, as the light-emitting characteristics of the sub-pixels (SPX) become uniform, the viewing angle of the display device (10) can become uniform. For example, it is possible to prevent or reduce a viewing angle deviation between a plurality of display devices (10) including light-emitting elements (LE) according to embodiments, and to improve or uniformize the operating characteristics of the display devices (10).

[0326] FIGS. 38 to 42 are cross-sectional views showing a method for manufacturing a light-emitting element according to one embodiment. For example, FIGS. 38 to 42 sequentially show a method for manufacturing a light-emitting element (LE) including light extraction patterns (LEP) according to one embodiment. It may be included in step S110 of FIG. 29 of FIGS. 38 to 42.

[0327] FIGS. 38 to 42 show embodiments that differ from the embodiments of FIGS. 30 to 35 in terms of the formation steps or methods of light extraction patterns (LEPs). In describing the embodiments of FIGS. 37 to 41, any overlapping descriptions with the embodiments of FIGS. 38 to 42 will be omitted, and the differences between the embodiments will be primarily described.

[0328] Referring to FIGS. 30 and 38, a semiconductor substrate (SSB) including light emitting element areas (LEAs) may be prepared, and a semiconductor material layer (SEML) may be formed on the semiconductor substrate (SSB). In one embodiment, a conductive material layer (E1L) may further be formed on the semiconductor material layer (SEML). The patterning process of the semiconductor substrate (SSB) for forming the patterns (PTN) of FIG. 31 may be omitted. For example, the upper surface of the semiconductor substrate (SSB) may not include the patterns (PTN) of FIG. 31 and may be substantially flat.

[0329] Referring to FIG. 39, light-emitting elements (LE) can be formed by etching a semiconductor material layer (SEML) and a conductive material layer (E1L). The light-emitting elements (LE) can be arranged in respective light-emitting element areas (LEA).

[0330] Referring to FIGS. 40 to 42, the light emitting elements (LE) can be separated from the semiconductor substrate (SSB), and thus light extraction patterns (LEP) can be formed on the light-emitting surface (SF1) of each of the exposed light emitting elements (LE). For example, after coating a polymer on the semiconductor substrate (SSB) and the light emitting elements (LE) of FIG. 39, the light emitting elements (LE) can be transferred onto the first transfer substrate (TSB1) of FIG. 40, and the semiconductor substrate (SSB) can be separated from the light emitting elements (LE). Accordingly, the light emitting elements (LE) and the polymer layer (PL) can be disposed on the first transfer substrate (TSB1). The polymer layer (PL) may include polyimide (PI) or glue, but the material of the polymer layer (PL) is not limited thereto. The first transfer substrate (TSB1) may include an adhesive layer formed on its upper surface, thereby stably positioning the light-emitting elements (LE) on the first transfer substrate (TSB1). Thereafter, as illustrated in FIG. 41, a mask (MK) may be positioned on the light-emitting elements (LE) and the polymer layer (PL).

[0331] The mask (MK) is used to form light extraction patterns (LEP) of the light emitting elements (LE), and may be formed in a shape that matches the size, shape, and / or arrangement structure of the light extraction patterns (LEP) to be formed on the light-emitting surface (SF1) of each of the light emitting elements (LE). For example, the mask (MK) may include openings that expose an area where light extraction patterns (LEP) having a fine size (for example, having a diameter of several nanometers to several hundred nanometers) are to be formed on the light-emitting surface (SF1) of each of the light emitting elements (LE), and may have a shape that covers other areas. In one embodiment, the mask (MK) may include a photoresist material, but is not limited thereto.

[0332] The mask (MK) can be aligned to match the alignment of the light emitting elements (LE). In addition, the mask (MK) can have a uniformly shaped pattern corresponding to the light-emitting surfaces (SF1) of the light emitting elements (LE). For example, the mask (MK) can be appropriately aligned on the light emitting elements (LE) so that light extraction patterns (LEP) of uniform size, shape, and number are formed on the light emitting surfaces (SF1) of the light emitting elements (LE).

[0333] By etching the light emitting elements (LE) through a patterning process using a mask (MK), light extraction patterns (LEP) can be formed on the light-emitting surface (SF1) of each of the light emitting elements (LE), as illustrated in FIG. 42. For example, after the light extraction patterns (LEP) are formed by etching the light emitting surfaces (SF1) of the light emitting elements (LE) using the mask (MK), the mask (MK) and the polymer layer (PL) can be removed. In one embodiment, the light extraction patterns (LEP) can be formed by a photolithography process, a nano-imprint process, or another type of patterning process. The patterning method of the light emitting elements (LE) is not particularly limited as long as the light extraction patterns (LEP) of a desired shape and size can be formed.

[0334] Thereafter, as described with reference to FIGS. 34 and 35, the light emitting elements (LE) can be transferred to the second transfer substrate (TSB2) and placed on the display substrate (DSB), and the light emitting elements (LE) can be placed on each pixel electrode (PXE). The light emitting elements (LE) can be appropriately connected to each pixel electrode (PXE). Thereafter, a subsequent pixel process can be performed to manufacture the display panel (100) of the display device (10).

[0335] As described above, according to the embodiments, light extraction patterns (LEP) can be uniformly formed on the light-emitting surfaces (SF1) of the light-emitting elements (LE). For example, the light-emitting elements (LE) can include light extraction patterns (LEP) having the same size, shape, and number. According to the embodiments, the light-emitting efficiency of the light-emitting elements (LE) can be improved by the light extraction patterns (LEP), and the light-emitting characteristics of the light-emitting elements (LE) and the sub-pixels (SPX) including the same can be uniformized. Accordingly, the light-emitting characteristics of the sub-pixels (SPX) and the display device (10) including the same can be improved, and the viewing angle can be uniformized.

[0336] In addition, according to embodiments, the groove portions (GP) of the light extraction patterns (LEP) may be arranged on the inner side of the light-emitting surface (SF1) spaced apart from the passivation film (INS). For example, the light extraction patterns (LEP) may be arranged on the inner side of the light-emitting surface (SF1) of each of the light-emitting elements (LE) so as not to come into contact with the passivation film (INS), or the outermost light extraction pattern (LEP) may come into contact with the passivation film (INS) at the protrusion portion (PP). Accordingly, the side surface of the semiconductor stack (STC) is more stably wrapped by the passivation film (INS), and a distance between the electrode around the passivation film (INS) and the second semiconductor layer (SEM2) is appropriately secured, thereby effectively preventing a short-circuit defect of the light-emitting element (LE) and improving the efficiency of the light-emitting element (LE). In addition, even if the light emitting elements (LE) are irradiated with a laser during the process of separating the light emitting elements (LE) from the semiconductor substrate (SSB) or the transfer substrate (for example, the first transfer substrate (TSB1) or the second transfer substrate (TSB2)), damage to the light emitting elements (LE) at the interface between the semiconductor stack (STC) and the protective film (INS) of each of the light emitting elements (LE) can be prevented or reduced. Accordingly, the luminance dispersion of the light emitting elements (LE) can be reduced or prevented, and the image quality and reliability of the display device (10) including the light emitting elements (LE) can be improved. Additionally, when the light emitting elements (LE) are bonded onto the pixel electrodes (PXE1, PXE2, PXE3) by irradiating the light emitting elements (LE) with a laser using a bonding method, the light emitting elements (LE) include light extraction patterns (LEP) of a uniform shape, thereby increasing the incidence uniformity of the laser, and stably bonding the light emitting elements (LE) onto the pixel electrodes (PXE1, PXE2, PXE3).

[0337] FIG. 43 is an exemplary drawing showing a smart watch including a display device according to one embodiment. Referring to FIG. 43, the display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of smart devices.

[0338] FIGS. 44 and 45 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0339] Referring to FIGS. 44 and 45, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0340] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0341] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0342] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0343] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0344] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0345] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 44 and 45, the first eyepiece (1210) and the second eyepiece (1220) are exemplified as being arranged separately, but the embodiments of the present specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0346] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0347] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1100) is implemented in a lightweight and compact form, the head-mounted display device (1000_2) may be equipped with a glasses frame as shown in FIG. 46 instead of the head-mounted band (1300).

[0348] In addition, the head-mounted display device (1000_2) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0349] Fig. 46 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 46 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0350] Referring to FIG. 46, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0351] In Fig. 46, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 46, and can be applied in various forms in various other electronic devices.

[0352] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0353] In FIG. 46, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0354] Fig. 47 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. Fig. 47 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0355] Referring to FIG. 47, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0356] FIG. 48 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0357] Referring to FIG. 48, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also view an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0358] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; pixel electrodes arranged on the substrate; and It includes light emitting elements arranged on the above pixel electrodes, Each of the above light emitting elements, A semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; Light extraction patterns arranged on the light-emitting surface of the semiconductor stack, including groove portions spaced from the end of the light-emitting surface and protrusion portions surrounding the groove portions; and A protective film is included that covers the side of the semiconductor stack, A display device wherein the light emitting elements include light extraction patterns having the same shape.

2. In paragraph 1, A display device in which the above light extraction patterns are arranged in the same structure on the light-emitting surface of each of the light-emitting elements.

3. In paragraph 1, A display device wherein the light emitting elements include the same number of light extraction patterns.

4. In paragraph 1, A display device, wherein the light extraction pattern disposed at the outermost end of the light-emitting surface of each of the light-emitting elements is disposed on the inner side of the light-emitting surface, spaced apart from the end of the light-emitting surface.

5. In paragraph 4, A display device wherein the above light extraction patterns are arranged in a plurality of columns, including a first column and a second column, on the light-emitting surface of each of the light-emitting elements.

6. In paragraph 5, A display device, wherein the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first column and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second column are spaced apart from the first end of the light-emitting surface by the same distance.

7. In paragraph 5, A display device, wherein the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row are spaced apart from the first end of the light-emitting surface by different distances.

8. In paragraph 1, A display device, wherein at least one of the light extraction patterns is in contact with an end of the light-emitting surface.

9. In paragraph 8, A display device wherein at least one light extraction pattern is in contact with an end of the light-emitting surface at a protrusion portion and is covered with the protective film.

10. In paragraph 1, A display device wherein the above light extraction patterns are formed on the upper surface of the second semiconductor layer.

11. A semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; A protective film covering the side of the semiconductor stack; and A light emitting element, which is arranged on the light-emitting surface of the semiconductor stack and includes light extraction patterns including groove portions spaced from an end of the light-emitting surface and protrusion portions surrounding the groove portions.

12. In paragraph 11, A light emitting element in which the outermost light extraction pattern among the above light extraction patterns is disposed on the inner side of the light emitting surface and spaced apart from the end of the light emitting surface.

13. In paragraph 12, A light emitting element wherein the above light extraction patterns are arranged in a plurality of columns including a first column and a second column in a first direction.

14. In paragraph 13, A light emitting element, wherein the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row are spaced apart from the first end of the light-emitting surface by the same distance.

15. In paragraph 13, A light emitting element, wherein the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the first row and the light extraction pattern closest to the first end of the light-emitting surface among the light extraction patterns arranged in the second row are spaced apart from the first end of the light-emitting surface by different distances.

16. In paragraph 11, A light emitting element, wherein at least one of the above light extraction patterns is in contact with an end of the light-emitting surface.

17. As an electronic device for providing images, A display device is included, wherein the display device comprises: substrate; pixel electrodes arranged on the substrate; and including light emitting elements arranged on the pixel electrodes, Each of the above light emitting elements, A semiconductor stack including a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; Light extraction patterns arranged on the light-emitting surface of the semiconductor stack, including groove portions spaced from the end of the light-emitting surface and protrusion portions surrounding the groove portions; and A protective film is included that covers the side of the semiconductor stack, An electronic device wherein the light emitting elements include light extraction patterns having the same shape.

Images