Display device, electronic device, and method for producing display device

Abstract

A display device according to an embodiment comprises: a lower substrate; light-emitting elements disposed on the lower substrate; a protective layer surrounding the sides of the light-emitting elements; an insulating layer disposed on the protective layer and comprising grooves surrounding the light-emitting elements; and a reflective layer disposed on the grooves and surrounding the sides of the light-emitting elements.

Description

Display devices and electronic devices, and methods for manufacturing display devices

[0001] Embodiments of the present invention relate to a display device, an electronic device, and a method for manufacturing a display device.

[0002] As the information society develops, demand for display devices capable of displaying images is increasing in various forms. To meet this demand, various types of display devices, including light-emitting displays, are being developed. Light-emitting displays contain pixels containing light-emitting elements.

[0003] The problem to be solved by the present invention is to provide a display device and an electronic device capable of improving the light efficiency of pixels, and a method for manufacturing the display device.

[0004] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment may include a lower substrate, light-emitting elements disposed on the lower substrate, a protective film surrounding side surfaces of the light-emitting elements, an insulating layer disposed on the protective film and including a groove surrounding the light-emitting elements, and a reflective film disposed on the groove and surrounding side surfaces of the light-emitting elements.

[0006] In one embodiment, the reflective film may have a mesh shape including openings that expose the light-emitting elements when viewed on a planar surface.

[0007] In one embodiment, the reflective film includes a surface having a textured pattern and may have a surface roughness according to the textured pattern.

[0008] In one embodiment, the depth of the groove may be greater than or equal to the thickness of the light emitting elements, and the bottom surface of the reflective film may be positioned at a height less than or equal to the height of the light emitting elements.

[0009] In one embodiment, the reflective film may comprise a metal or a distributed Bragg reflector.

[0010] In one embodiment, the display device further includes bonding electrodes disposed on the lower substrate, and the light emitting elements can be disposed on the bonding electrodes.

[0011] In one embodiment, each of the bonding electrodes may include a bonding layer and a reflective layer on the bonding layer.

[0012] In one embodiment, the reflective layer of each of the bonding electrodes can completely cover the lower surface of each of the light-emitting elements.

[0013] In one embodiment, the display device may further include a common electrode disposed on the insulating layer and electrically connected to the light emitting elements.

[0014] In one embodiment, the display device further includes a power wire disposed on the reflective film and filled in the groove, and the common electrode may be disposed on the power wire.

[0015] In one embodiment, the display device may further include a cover layer disposed on the common electrode, and lenses disposed on the cover layer and overlapping the light emitting elements.

[0016] A method for manufacturing a display device according to one embodiment may include the steps of preparing a lower substrate including pixel circuits, forming light-emitting elements electrically connected to the pixel circuits on the lower substrate, forming a protective film covering the light-emitting elements on the lower substrate, forming an insulating layer including a groove surrounding the light-emitting elements on the protective film, forming a reflective film surrounding side surfaces of the light-emitting elements on the groove, and forming a common electrode electrically connected to the light-emitting elements on the insulating layer.

[0017] In one embodiment, the step of forming the insulating layer may include the step of forming the insulating layer on the protective film to a height greater than the height of the light emitting elements so as to completely cover the light emitting elements, and the step of etching the insulating layer in a non-overlapping portion with the light emitting elements to form the groove in the insulating layer.

[0018] In one embodiment, the method for manufacturing the display device may further include a step of forming a textured pattern on the surface of the reflective film after forming the reflective film.

[0019] An electronic device according to one embodiment includes a display device for displaying an image, wherein the display device may include a lower substrate, light-emitting elements disposed on the lower substrate, a protective film surrounding side surfaces of the light-emitting elements, an insulating layer disposed on the protective film and including a groove surrounding the light-emitting elements, and a reflective film disposed on the groove and surrounding side surfaces of the light-emitting elements.

[0020] In one embodiment, the reflective film may have a mesh shape including openings that expose the light-emitting elements when viewed on a planar surface.

[0021] In one embodiment, the reflective film and the light-emitting elements may not overlap each other when viewed in a plane.

[0022] In one embodiment, the reflective film includes a surface having a textured pattern and may have a surface roughness according to the textured pattern.

[0023] In one embodiment, the depth of the groove may be greater than or equal to the thickness of the light-emitting elements, and the bottom surface of the reflective film may be positioned at a height less than or equal to the height of the light-emitting elements.

[0024] In one embodiment, the reflective film can completely surround a side surface of each of the light-emitting elements.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to the display device and electronic device according to the embodiments, and the manufacturing method of the display device, the light efficiency of light-emitting elements and pixels including the same can be increased. In addition, light leakage or light interference between pixels can be prevented, and the electrical stability of the light-emitting elements can be secured.

[0027] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0028] Figure 1 is a perspective view showing a display device according to one embodiment.

[0029] Figure 2 is a plan view showing a display area according to one embodiment.

[0030] FIG. 3 is a cross-sectional view showing a display panel according to one embodiment.

[0031] FIG. 4 is a cross-sectional view showing a display panel according to one embodiment.

[0032] FIGS. 5 to 7 are perspective views showing a method of manufacturing a display device according to one embodiment.

[0033] FIGS. 8 to 20 are cross-sectional views showing a method of manufacturing a display device according to one embodiment.

[0034] FIG. 21 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0035] FIGS. 22 and 23 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0036] FIG. 24 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0037] FIG. 25 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0038] FIG. 26 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0039] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0040] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0041] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0042] Specific embodiments are described below with reference to the attached drawings.

[0043] Figure 1 is a perspective view showing a display device according to one embodiment.

[0044] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen of various products (e.g., electronic devices). For example, the display device (10) can be used as a display screen of not only portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), but also various electronic devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT). In addition, the display device (10) can be applied to virtual reality (VR) devices or augmented reality (AR) devices. For example, the display device (10) can be included in at least one of the electronic devices exemplified above, or can be included in another type of electronic device.

[0045] A display device (10) according to one embodiment may include a display panel (DPN) including a display area (DA) and a non-display area (NDA).

[0046] The display panel (DPN) may have a rectangular planar shape having a long side in a first direction (DR1) and a short side in a second direction (DR2). In FIG. 1, the first direction (DR1) may refer to the horizontal direction of the display panel (DPN), and the second direction (DR2) may refer to the vertical direction of the display panel (DPN). The third direction (DR3) may refer to the thickness direction or the height direction of the display panel (DPN). However, the planar shape of the display panel (DPN) is not limited thereto, and the display panel (DPN) may have a different shape. For example, the display panel (DPN) may have a polygonal, circular, oval, or irregular planar shape other than the rectangular shape.

[0047] The display area (DA) may be an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. In one embodiment, the planar shape of the display area (DA) may follow the planar shape of the display panel (DPN). FIG. 1 illustrates an embodiment in which the planar shape of the display area (DA) is a rectangle. The display area (DA) may be arranged at the center of the display panel (DPN). The non-display area (NDA) may be arranged around the display area (DA). For example, the non-display area (NDA) may be arranged at the edge of the display panel (DPN) to surround the display area (DA).

[0048] The display panel (DPN) may include pixels (PX) arranged in a display area (DA). For example, the display panel (DPN) may include first pixels (PX1) emitting light of a first color, second pixels (PX2) emitting light of a second color, and third pixels (PX3) emitting light of a third color. In one embodiment, the first color may be red, the second color may be green, and the third color may be blue, but is not limited thereto. At least one first pixel (PX1), at least one second pixel (PX2), and at least one third pixel (PX3) adjacent to each other may constitute a unit pixel (UPX) capable of emitting light of various colors. For example, a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) sequentially or continuously arranged along a first direction (DR1) in the display area (DA) may constitute one unit pixel (UPX). The number, type, and / or arrangement structure of pixels (PX) constituting a unit pixel (UPX) may vary depending on the embodiments.

[0049] Pixels (PX) may have a planar shape such as a rectangle or a rhombus, but are not limited thereto. For example, pixels (PX) may have a planar shape of another polygonal shape (e.g., a hexagonal shape or a rhombus shape), a circle, an ellipse, or any other shape.

[0050] The pixels (PX) may be arranged in a display area (DA) in a matrix form, a stripe form, or any other form. The sizes of the pixels (PX) may be the same or different.

[0051] In one embodiment, the display device (10) may be a light-emitting display device including light-emitting elements. For example, each of the pixels (PX) of the display device (10) may include at least one light-emitting element.

[0052] The non-display area (NDA) may include a pad area (PDA) and a peripheral area (PHA). In one embodiment, the non-display area (NDA) may further include a common voltage supply area arranged around the display area (DA). In the non-display area (NDA), wires (or a portion of the wires) connected to the pixels (PX) and pads (PD) may be arranged. In describing the embodiments, the term "connection" may include the meaning of electrical connection and / or physical connection.

[0053] Pads (PD) may be arranged in a pad area (PDA). The pads (PD) may be connected to an external circuit board. For example, the pads (PD) may be electrically connected to circuit pads on the circuit board via conductive connecting members such as wires. Driving signals and driving voltages for driving pixels (PX) may be supplied from the circuit board to the display device (10) (or display panel (DPN)) via the pads (PD).

[0054] The peripheral area (PHA) may be the remaining area of ​​the non-display area (NDA) excluding the pad area (PDA). The peripheral area (PHA) may surround the display area (DA).

[0055] In one embodiment, the display device (10) may include a common electrode (CME) disposed across the entire display area (DA). The common electrode (CME) may be electrically connected to at least one pad (PD) disposed in the pad area (PDA) and may receive a second driving voltage for driving light-emitting elements through the pad (PD). In one embodiment, the second driving voltage may be a common voltage such as a low-potential pixel voltage or a cathode voltage. For example, the common electrode (CME) may be electrically connected to a plurality of pads (PD) disposed at both ends of the pad area (PDA) and may receive a common voltage from a circuit board through the plurality of pads (PD). The shape, structure, and / or position of the common electrode (CME) are not limited to the embodiment of FIG. 1 and may vary depending on the embodiments.

[0056] In one embodiment, the display device (10) may further include a power line (e.g., a power line (PL) of FIG. 2) disposed between the pixels (PX) and electrically connected to the common electrode (CME). Accordingly, a common voltage can be supplied more smoothly to the pixels (PX).

[0057] The pixels (PX) can be supplied with a common voltage through the common electrode (CME). In addition, the pixels (PX) can also be connected to other pads (PD) and driving circuits (not shown) of the pad area (PDA). For example, the pixels (PX) include circuit elements formed on a semiconductor circuit board or the like (for example, circuit elements constituting a pixel circuit of each pixel (PX)), and can be electrically connected to other pads of the pad area (PDA) and / or driving circuits through wires connected to the circuit elements. The shape or position of each wire or electrode (for example, the common electrode (CME)) for supplying each driving signal or each driving voltage to the pixels (PX) can be variously changed according to embodiments. The driving circuit can be arranged within the display panel (DPN) or provided outside the display panel (DPN) and electrically connected to a plurality of pads (PD) arranged in the pad area (PDA).

[0058] The pixels (PX) can receive driving signals (e.g., a scan signal or a control signal, and a data signal) and a first driving voltage from the other pads (PD) and / or the driving circuit. In one embodiment, the first driving voltage can be a pixel voltage such as a high-potential pixel voltage or an anode voltage. The pixels (PX) can emit light in response to the driving signals and driving voltages (e.g., a first driving voltage and a second driving voltage).

[0059] Fig. 2 is a plan view showing a display area according to one embodiment. For example, Fig. 2 schematically shows a portion of the display area (DA) according to the embodiment of Fig. 1.

[0060] Referring to FIGS. 1 and 2, each pixel (PX) may include a light emitting element (LE). Although FIG. 2 discloses an embodiment in which each pixel (PX) includes a single light emitting element (LE), embodiments are not limited thereto. For example, at least one of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include two or more light emitting elements (LE).

[0061] The light emitting elements (LE) may have a circular shape, a rectangular shape, a polygonal shape other than a rectangular shape, or a planar shape other than a rectangular shape. For example, the shape of the light emitting elements (LE) may be varied in various ways depending on the embodiments.

[0062] In one embodiment, the light emitting elements (LE) may be micro light emitting diodes (micro LEDs) having a small size in the micrometer (μm) range. For example, each of the light emitting elements (LE) may be a micro LED having a length in a first direction (DR1) (e.g., a horizontal length), a length in a second direction (DR2) (e.g., a vertical length), and a length in a third direction (DR3) (e.g., a thickness or height) of several micrometers to several hundred micrometers, respectively. In one embodiment, the length in the first direction (DR1), the length in the second direction (DR2), and the length in the third direction (DR3) of each of the light emitting elements (LE) may be, but is not limited to, 100 μm or less.

[0063] In one embodiment, the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may include respective light-emitting elements (LE) that emit light of a first color, light of a second color, and light of a third color, respectively. In another embodiment, the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may include light-emitting elements (LE) that emit light of the same color, and light conversion patterns (for example, wavelength conversion patterns including quantum dots) and / or color filters may be arranged in the light-emitting areas of the first pixels (PX1), the second pixels (PX2), and / or the third pixels (PX3) to convert the color or wavelength of light emitted from the light-emitting elements (LE) arranged in each of the pixels (PX).

[0064] In one embodiment, the pixels (PX) may be arranged in the display area (DA) in a matrix form, a stripe form, or another form. The sizes of the pixels (PX) (or the light-emitting areas of the pixels (PX)) may be substantially the same or different from each other.

[0065] In one embodiment, the pixels (PX) may have a planar shape such as a rectangle or a rhombus, but is not limited thereto. For example, the pixels (PX) may have a planar shape of another polygonal shape (e.g., a hexagonal shape or a rhombus shape), a circle, an ellipse, or any other shape.

[0066] The display device (10) may include a reflective film (RFL) disposed between the light emitting elements (LE). For example, the reflective film (RFL) may have a mesh shape when viewed on a plane (for example, a plane defined by the first direction (DR1) and the second direction (DR2)) and may surround each of the light emitting elements (LE). The reflective film (RFL) may be disposed between the pixels (PX) so as not to overlap with the pixels (PX). Alternatively, a portion of the reflective film (RFL) may overlap an edge portion of the pixels (PX).

[0067] In one embodiment, the reflective film (RFL) may not overlap the light-emitting elements (PX) when viewed from a planar perspective. For example, the reflective film (RFL) may be opened by an area greater than the area of ​​each light-emitting element (LE) on the upper portion of each light-emitting element (LE) and may not cover the upper surfaces of the light-emitting elements (PX). Accordingly, the light emission angle of the light emitted from the light-emitting elements (PX) can be sufficiently secured or widened.

[0068] In one embodiment, the display device (10) may further include a power line (PL) arranged between the light emitting elements (LE). For example, the power line (PL) may have a mesh shape when viewed from a plan view and may overlap with the reflective film (RFL). In one embodiment, the power line (PL) may be electrically connected to the common electrode (CME). By arranging the power line (PL) between the light emitting elements (LE), the voltage drop of the common voltage applied to the common electrode (CME) can be reduced or minimized, and the image quality and power consumption of the display device (10) can be improved.

[0069] Fig. 3 is a cross-sectional view showing a display panel according to one embodiment. For example, Fig. 3 shows one embodiment of a cross-section of a display panel (DPN) corresponding to the line X1-X1' of Fig. 2, and shows a schematic cross-section of a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) located in a unit pixel area (UPA) of a display area (DA).

[0070] Fig. 4 is a cross-sectional view showing a display panel according to one embodiment. Fig. 4 shows an embodiment that is different from the embodiment of Fig. 3 with respect to a reflective film (RFL).

[0071] FIGS. 3 and 4 illustrate an embodiment in which a display device (10) includes a display panel (DPN) having a Light Emitting Diode on Silicon (LEDoS) structure in which light emitting diodes (LEs) are arranged as light emitting elements (LE) on a semiconductor circuit board (PCL) formed by a semiconductor process using a silicon wafer. However, the structure or type of devices to which the embodiments can be applied are not limited thereto. For example, the embodiments can be applied to display devices of other types and / or structures, or to devices of other types and / or structures, such as lighting devices.

[0072] Referring to FIGS. 1 to 4, the display panel (DPN) may include a semiconductor circuit board (PCL) (or a thin film transistor substrate), connection electrodes (CNE) and a first cover layer (CVL1) disposed on the semiconductor circuit board (PCL), bonding electrodes (BDE) disposed on the connection electrodes (CNE) and the first cover layer (CVL1), and light emitting elements (LE) disposed on the bonding electrodes (BDE). In one embodiment, the display panel (DPN) may further include at least one of contact electrodes (CTE1, CTE2) disposed on at least one surface of the light emitting elements (LE), a protective film (PSV) covering the side surfaces of the light emitting elements (LE), an insulating layer (INS), a reflective film (RFL), and a power line (PL) disposed around the light emitting elements (LE), and a common electrode (CME) and a second cover layer (CVL2) disposed on the light emitting elements (LE). In one embodiment, the display panel (DPN) may further include optical structures, for example, lenses (LS), disposed on the second cover layer (CVL2).

[0073] A semiconductor circuit board (PCL) may include a display area (DA) in which pixel circuits (PXC) of pixels (PX) are formed. The semiconductor circuit board (PCL) may further include a non-display area (NDA) of FIG. 1. For example, the semiconductor circuit board (PCL) may further include pads (PD) located in the non-display area (NDA).

[0074] A semiconductor circuit board (PCL) may include a base substrate (SB), pixel circuits (PXC) arranged or formed on the base substrate (SB), and pixel electrodes (PXE) (or connection wires) electrically connected to each of the pixel circuits (PXC). The semiconductor circuit board (PCL) may further include wires electrically connected to the pixels (PX).

[0075] In one embodiment, the semiconductor circuit board (PCL) may be formed by a semiconductor process using a silicon wafer. For example, the base substrate (SB) may be a silicon wafer. In one embodiment, the base substrate (SB) may be made of single-crystal silicon.

[0076] Pixel circuits (PXC) may be arranged on a semiconductor circuit board (PCL) corresponding to respective pixel areas in which each pixel (PX) is arranged. In one embodiment, each pixel circuit (PXC) may include a complementary metal-oxide semiconductor (CMOS) circuit formed using a semiconductor process. In one embodiment, each pixel circuit (PXC) may include at least one transistor and at least one capacitor formed using a semiconductor process. FIG. 3 schematically illustrates locations of pixel circuits (PXC) included in a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) as examples of elements arranged inside the semiconductor circuit board (PCL).

[0077] Pixel electrodes (PXE) may be disposed on respective pixel circuits (PXC). The pixel electrodes (PXE) may be connected to respective pixel circuits (PXC). For example, the pixel circuit (PXC) of each pixel (PX) may be electrically connected to the pixel electrode (PXE) of the corresponding pixel (PX). The pixel electrodes (PXE) may receive a first driving voltage (for example, a first pixel voltage or an anode voltage) from each pixel circuit (PXC).

[0078] In one embodiment, the pixel electrodes (PXE) may be formed integrally with each pixel circuit (PXC). For example, the pixel electrodes (PXE) may be electrodes (or wires) that protrude and are exposed from the upper surface of each pixel circuit (PXC).

[0079] The pixel electrodes (PXE) may include at least one conductive material. For example, the pixel electrodes (PXE) may include, but are not limited to, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof.

[0080] The pixel electrodes (PXE) may be electrically connected to the respective light-emitting elements (LE) through respective connection electrodes (CNE) and respective bonding electrodes (BDE). For example, the pixel electrode (PXE) of each pixel (PX) may be electrically connected to the light-emitting element (LE) on the bonding electrode (BDE) through the connection electrode (CNE) and the bonding electrode (BDE) of the corresponding pixel (PX). In one embodiment, at least one electrode may be further disposed between the bonding electrode (BDE) and the light-emitting element (LE), and the bonding electrode (BDE) and the light-emitting element (LE) may be electrically connected to each other via the at least one electrode. For example, a first contact electrode (CTE1) and a light-emitting element (LE) may be sequentially disposed on the bonding electrode (BDE) along the third direction (DR3), and the bonding electrode (BDE) may be electrically connected to the light-emitting element (LE) via the first contact electrode (CTE1).

[0081] A first cover layer (CVL1) may be disposed on the pixel circuits (PXC) and the pixel electrodes (PXE). The first cover layer (CVL1) may cover a semiconductor circuit board (PCL) including the base substrate (SB), the pixel circuits (PXC), and the pixel electrodes (PXE). The first cover layer (CVL1) may also be referred to as a "first passivation layer" or a "first insulating layer."

[0082] The first cover layer (CVL1) may include openings (e.g., contact holes or via holes) that expose portions of the pixel electrodes (PXE). The openings may be filled with connection electrodes (CNE). For example, the first cover layer (CVL1) may surround the connection electrodes (CNE).

[0083] The first cover layer (CVL1) includes at least one insulating material and may have a single-layer or multi-layer structure. In one embodiment, the first cover layer (CVL1) includes an inorganic insulating material (for example, silicon oxide (SiO x ), silicon nitride (SiNx ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ), or other inorganic insulating materials, but are not limited thereto.

[0084] The connecting electrodes (CNE) can connect the semiconductor circuit board (PCL) and the bonding electrodes (BDE). For example, the connecting electrodes (CNE) can be electrically connected between the pixel electrode (PXE) of each pixel (PX) and the bonding electrode (BDE).

[0085] In one embodiment, the connecting electrodes (CNE) may include a conductive metal. For example, the connecting electrodes (CNE) may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag).

[0086] A semiconductor circuit board (PCL), connection electrodes (CNE), and a first cover layer (CVL1) may constitute a lower substrate (110) (e.g., a backplane substrate) of a display panel (DPN). Light-emitting elements (LE) may be disposed on the lower substrate (110). In one embodiment, the display panel (DPN) further includes bonding electrodes (BDE) disposed on the lower substrate (110), and the light-emitting elements (LE) may be disposed on the bonding electrodes (BDE). The lower substrate (110) and the light-emitting elements (LE) may be coupled or connected by the bonding electrodes (BDE).

[0087] Bonding electrodes (BDE) may be disposed on the first cover layer (CVL1). The bonding electrodes (BDE) may be disposed separately from each other in each pixel area where pixels (PX) are disposed. Accordingly, the light emitting elements (LE) of the pixels (PX) may be individually driven. Each bonding electrode (BDE) may be connected to a connection electrode (CNE) of the corresponding pixel (PX). In one embodiment, the bonding electrode (BDE) may function as an anode electrode of the light emitting element (LE) or the pixel (PX). The bonding electrode (BDE) may also be referred to as an "electrode" or a "first electrode."

[0088] Each of the bonding electrodes (BDE) may be formed of a single layer or multiple layers including a bonding layer (BMTL) (also referred to as a "bonding metal layer"). For example, each of the bonding electrodes (BDE) may include a bonding layer (BMTL) and first and second barrier layers (BRL1, BRL2) disposed on both sides of the bonding layer (BMTL).

[0089] In one embodiment, each of the bonding electrodes (BDE) may further include a reflective layer (RMTL) disposed on the bonding layer (BMTL). For example, the reflective layer (RMTL) may be disposed on the second barrier layer (BRL2).

[0090] In one embodiment, each of the bonding electrodes (BDE) may further include a third barrier layer (BRL3) disposed on the reflective layer (RMTL). For example, the third barrier layer (BRL3) may be disposed between each of the reflective layers (RMTL) and the first contact electrode (CTE1).

[0091] The bonding layer (BMTL) may include a conductive material suitable for bonding, such as a bonding metal. For example, the bonding layer (BMTL) may include a metal or metal alloy with excellent electrical and thermal conductivity.

[0092] In one embodiment, the bonding layer (BMTL) may have a thickness sufficient to appropriately or easily perform the bonding process. For example, the bonding layer (BMTL) may have the largest thickness among the layers constituting the bonding electrode (BDE). For example, the bonding layer (BMTL) may have a thickness of approximately several hundred nanometers (for example, a thickness in the range of approximately 200 nm to 500 nm), but is not limited thereto.

[0093] In one embodiment, the bonding layer (BMTL) may include a gold (Au)-tin (Sn) alloy. The gold (Au)-tin (Sn) alloy has excellent bonding strength and a low melting point, thereby lowering the temperature of the bonding process (e.g., a wafer-to-wafer bonding process utilizing the bonding layer (BMTL)) while allowing the light-emitting elements (LE) (or an epitaxial layer to be formed with the light-emitting elements (LE)) to be properly bonded to the lower substrate (110). Accordingly, the light-emitting elements (LE) or peripheral elements can be prevented from being damaged or deteriorated by the bonding process. In addition, the gold (Au)-tin (Sn) alloy has low resistance change depending on temperature and electrically stable characteristics. Therefore, the pixel electrode (PXE) and the light-emitting element (LE) can be electrically and / or physically stably connected by the bonding layer (BMTL) including a gold (Au)-tin (Sn) alloy, and the reliability and operating characteristics of the light-emitting element (LE) and the pixel (PX) including the same can be improved. However, the material of the bonding layer (BMTL) is not limited to the gold (Au)-tin (Sn) alloy. For example, the bonding layer (BMTL) may include a metal or alloy having a low risk of foreign matter generation due to an etching process, etc., such as titanium (Ti), or may include another highly reliable bonding metal such as zirconium (Zr), nickel (Ni), or chromium (Cr).

[0094] The first barrier layer (BRL1) may be disposed under the bonding layer (BMTL). For example, the first barrier layer (BRL1) may be disposed between the connection electrode (CNE) and the bonding layer (BMTL), and may cover the lower surface of the bonding layer (BMTL).

[0095] The second barrier layer (BRL2) may be disposed on top of the bonding layer (BMTL). For example, the second barrier layer (BRL2) may be disposed between the bonding layer (BMTL) and the reflective layer (RMTL), and may cover the upper surface of the bonding layer (BMTL) and the lower surface of the reflective layer (RMTL).

[0096] Each of the first barrier layer (BRL1) and the second barrier layer (BRL2) may include a material suitable for diffusion prevention (e.g., intermetallic diffusion prevention) and may include the same or different materials. Each of the first barrier layer (BRL1) and the second barrier layer (BRL2) may be formed of a material and / or a thickness capable of ensuring conductivity of the bonding electrode (BDE). In one embodiment, each of the first barrier layer (BRL1) and the second barrier layer (BRL2) may include a material having a high intermetallic diffusion prevention effect, for example, titanium (Ti), titanium nitride (TiN), nickel (Ni), or other diffusion prevention material, and may be formed to a thickness less than or equal to the thickness of the reflective layer (RMTL) and / or the bonding layer (BMTL). For example, each of the first barrier layer (BRL1) and the second barrier layer (BRL2) may be formed as a thin film including a material suitable for preventing diffusion of a metal included in the bonding layer (BMTL) and / or the reflective layer (RMTL).

[0097] The reflective layer (RMTL) may be disposed on the bonding layer (BMTL). The lower and upper surfaces of the reflective layer (RMTL) may be covered with a second barrier layer (BRL2) and a third barrier layer (BRL3), respectively.

[0098] The reflective layer (RMTL) may include a conductive material (e.g., a metal) having high light reflectivity. For example, the reflective layer (RMTL) may include aluminum (Al) or another metal having high light reflectivity (e.g., molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), or chromium (Cr)).

[0099] In one embodiment, the reflective layer (RMTL) can completely cover the lower surface of each of the light-emitting elements (LE). For example, when viewed in a plan view, the reflective layer (RMTL) of the bonding electrode (BDE) disposed in each pixel (PX) can have a larger size than the light-emitting element (LE) disposed in the corresponding pixel (PX) and can overlap the light-emitting element (LE) and the surrounding area of ​​the light-emitting element (LE). Since the reflective layer (RMTL) completely covers the lower surface of each of the light-emitting elements (LE), light propagating downward from the light-emitting elements (LE) can be effectively reflected. Accordingly, the light efficiency of the light-emitting elements (LE) and the pixels (PX) including the light-emitting elements (LE) can be increased.

[0100] The third barrier layer (BRL3) may be disposed on top of the reflective layer (RMTL). For example, the third barrier layer (BRL3) may be disposed between the reflective layer (RMTL) and the first contact electrode (CTE1) and may cover the upper surface of the reflective layer (RMTL).

[0101] The third barrier layer (BRL3) may include a material suitable for diffusion prevention (e.g., intermetallic diffusion prevention) and may be formed with a material and / or thickness capable of ensuring conductivity of the bonding electrode (BDE). In one embodiment, the third barrier layer (BRL3) may include titanium (Ti), titanium nitride (TiN), nickel (Ni), or other diffusion-preventing material. For example, the third barrier layer (BRL3) may be formed as a thin film (e.g., a thin film having a thickness of approximately 20 nm or less) including titanium nitride (TiN). Accordingly, diffusion of the metal included in the reflective layer (RMTL) can be prevented while ensuring conductivity of the bonding electrode (BDE).

[0102] In one embodiment, a light emitting element (LE) may be disposed on each bonding electrode (BDE). For example, a first contact electrode (CTE1) may be disposed on each bonding electrode (BDE), and a light emitting element (LE) may be disposed on the first contact electrode (CTE1). In FIGS. 3 and 4, the first contact electrode (CTE1) is illustrated as a separate configuration from the light emitting element (LE), but the embodiments are not limited thereto. For example, the first contact electrode (CTE1) may be considered as a configuration included in the light emitting element (LE). The first contact electrode (CTE1) may be formed or etched together with the light emitting element (LE), or may be formed or etched separately from the light emitting element (LE).

[0103] In another embodiment, the light emitting element (LE) or pixel (PX) may not include a first contact electrode (CTE1). In this case, the light emitting element (LE) may be placed directly on the bonding electrode (BDE) of the pixel (PX).

[0104] In addition, although FIGS. 3 and 4 illustrate a display panel (DPN) having a structure in which bonding electrodes (BDE) are arranged on a lower substrate (110) including a semiconductor circuit board (PCL) and light-emitting elements (LE) are bonded to the lower substrate (110) by the bonding electrodes (BDE), the structure of the display panel (DPN) according to the embodiments is not limited thereto. For example, the light-emitting elements (LE) may be appropriately arranged on the lower substrate (110) by utilizing other connecting electrodes or wires without using a bonding method.

[0105] The first contact electrode (CTE1) may be disposed on the bonding electrode (BDE). For example, the first contact electrode (CTE1) may be disposed between the bonding electrode (BDE) and the light emitting element (LE).

[0106] The first contact electrode (CTE1) may be disposed on one surface (e.g., the lower surface) of the first semiconductor layer (SEM1) included in the light-emitting element (LE). The first contact electrode (CTE1) protects the first semiconductor layer (SEM1) and can smoothly connect the light-emitting element (LE) to the bonding electrode (BDE).

[0107] In one embodiment, the first contact electrode (CTE1) may be disposed entirely on one surface of the first semiconductor layer (SEM1). For example, the first contact electrode (CTE1) may be disposed entirely on the lower surface of the first semiconductor layer (SEM1). Accordingly, the first semiconductor layer (SEM1) may be appropriately or stably protected. However, the embodiments are not limited thereto, and the first contact electrode (CTE1) may be disposed only on a portion of the first semiconductor layer (SEM1).

[0108] The first contact electrode (CTE1) may include a metal, a metal oxide, or other conductive material. In one embodiment, the first contact electrode (CTE1) may include, but is not limited to, a transparent conductive material (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive material).

[0109] Each of the light emitting elements (LE) can be disposed on the first contact electrode (CTE1) (or bonding electrode (BDE)) of the corresponding pixel (PX).

[0110] Each of the light emitting elements (LE) may include a first semiconductor layer (SEM1), a light emitting layer (EML), and a second semiconductor layer (SEM2) sequentially disposed on a first contact electrode (CTE1). For example, the first semiconductor layer (SEM1), the light emitting layer (EML), and the second semiconductor layer (SEM2) may be sequentially disposed or stacked on the first contact electrode (CTE1) along a third direction (DR3). The first semiconductor layer (SEM1), the light emitting layer (EML), and the second semiconductor layer (SEM2) may be formed from a semiconductor epitaxial stack or epi-layers formed by epitaxial growth on a semiconductor substrate.

[0111] The first semiconductor layer (SEM1) may include a semiconductor material doped with a first conductivity type dopant. For example, the first semiconductor layer (SEM1) may be a first conductivity type semiconductor layer including a nitride-based semiconductor material, a phosphide-based semiconductor material, or another semiconductor material, and further including a first conductivity type dopant. In one embodiment, the first semiconductor layer (SEM1) may be a p-type semiconductor layer (e.g., p-GaN) doped with a p-type dopant such as Mg, Zn, Ca, Se, Ba, etc., but is not limited thereto.

[0112] The light-emitting layer (EML) can be disposed on the first semiconductor layer (SEM1). For example, the light-emitting layer (EML) can be disposed between the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). The light-emitting layer (EML) can emit light by recombination of electron-hole pairs generated in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0113] The emission layer (EML) may include a nitride-based semiconductor material, a phosphide-based semiconductor material, or other semiconductor material, and may have a single or multiple quantum well structure. In one embodiment, the emission layer (EML) may have a multiple quantum well structure including, but not limited to, a quantum well layer including InGaN, and a barrier layer including GaN, AlGaN, or GaAlN. In one embodiment, when the emission layer (EML) includes InGaN, the color of light emitted from the emission layer (EML) can be controlled or changed by controlling the content of indium (In).

[0114] The light emitting layer (EML) can emit light in the visible light wavelength range, for example, light in the wavelength range of about 400 nm to 900 nm. For example, the light emitting layer (EML) can emit blue light having a peak wavelength in the range of about 440 nm to 480 nm, green light having a peak wavelength in the range of about 510 nm to 550 nm, or red light having a peak wavelength in the range of about 610 nm to 650 nm. The light emitting layer (EML) may also emit light in a color or wavelength range other than the colors or wavelength ranges exemplified above.

[0115] The second semiconductor layer (SEM2) may include a semiconductor material doped with a second conductivity type dopant. For example, the second semiconductor layer (SEM2) may be a second conductivity type semiconductor layer including a nitride-based semiconductor material, a phosphide-based semiconductor material, or another semiconductor material, and further including a second conductivity type dopant. In one embodiment, the second semiconductor layer (SEM2) may be an n-type semiconductor layer (e.g., n-GaN) doped with an n-type dopant such as Si, Ge, Sn, etc., but is not limited thereto.

[0116] In one embodiment, a second contact electrode (CTE2) may be disposed on each light emitting element (LE), and a common electrode (CME) may be disposed on the second contact electrode (CTE2). For example, the second semiconductor layer (SEM2) of the light emitting element (LE) may be electrically connected to the common electrode (CME) via the second contact electrode (CTE2).

[0117] Although the second contact electrode (CTE2) is illustrated as a separate configuration from the light emitting element (LE) in FIGS. 3 and 4, the embodiments are not limited thereto. For example, the second contact electrode (CTE2) may also be viewed as a configuration included in the light emitting element (LE). The second contact electrode (CTE2) may be formed or etched together with the light emitting element (LE), or may be formed or etched separately from the light emitting element (LE).

[0118] In other embodiments, the light emitting element (LE) or pixel (PX) may not include a second contact electrode (CTE2). In this case, the common electrode (CME) may be directly connected to or in contact with the light emitting element (LE).

[0119] The second contact electrode (CTE2) may be disposed on one surface (e.g., the upper surface) of the second semiconductor layer (SEM2). The second contact electrode (CTE2) protects the second semiconductor layer (SEM2) and can smoothly connect the light emitting element (LE) to the common electrode (CME).

[0120] In one embodiment, the second contact electrode (CTE2) may be disposed over the entire surface of one side of the second semiconductor layer (SEM2). For example, the second contact electrode (CTE2) may be disposed over the entire surface of the upper surface of the second semiconductor layer (SEM2). Accordingly, the second semiconductor layer (SEM2) may be stably protected. However, the embodiments are not limited thereto, and the second contact electrode (CTE2) may be disposed over only a portion of the second semiconductor layer (SEM2).

[0121] The second contact electrode (CTE2) may include a metal, a metal oxide, or other conductive material. In one embodiment, the second contact electrode (CTE2) may be formed of a transparent electrode layer including a transparent conductive material (for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or other transparent conductive material). Accordingly, light generated from the light-emitting element (LE) may transmit through the second contact electrode (CTE2) and be emitted to the upper portion of the light-emitting element (LE).

[0122] The light emitting elements (LE) may be surrounded by a protective film (PSV), etc. For example, each side of the light emitting elements (LE) may be surrounded by a protective film (PSV) and a reflective film (RFL).

[0123] The protective film (PSV) can surround the side surfaces of the light emitting elements (LE). In one embodiment, the protective film (PSV) can further surround the side surfaces of at least one of the bonding electrodes (BDE), the first contact electrode (CTE1), and the second contact electrode (CTE2). For example, the protective film (PSV) can be entirely disposed in the display area (DA) to surround the side surfaces of the light emitting elements (LE), the bonding electrodes (BDE), the first contact electrode (CTE1), and the second contact electrode (CTE2).

[0124] The protective film (PSV) may include an opening that exposes a portion, for example, a top surface, of each of the light-emitting elements (LE). For example, the protective film (PSV) may include an opening (for example, an opening (OPN) of FIG. 18) that exposes a portion (for example, a portion of a top surface) of each of the light-emitting elements (LE) or the second contact electrode (CTE2). In the portion of the protective film (PSV) where the opening occurs, the light-emitting element (LE) or the second contact electrode (CTE2) may be connected to the common electrode (CME).

[0125] The protective film (PSV) is silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ) and hafnium oxide (HfO x ) may include at least one insulating material, or other insulating material. The protective film (PSV) protects the light emitting element (LE) and may increase the electrical stability of the light emitting element (LE).

[0126] An insulating layer (INS) may be disposed on the protective film (PSV). The insulating layer (INS) may be disposed around the light emitting elements (LE). For example, the insulating layer (INS) may be disposed around the light emitting elements (LE) so as to surround each of the light emitting elements (LE). For example, the insulating layer (INS) may be disposed around each of the light emitting elements (LE) and between the light emitting elements (LE), and may be disposed over the entire display area (DA) except for a portion that is opened for connection between the light emitting elements (LE) and the common electrode (CME).

[0127] The insulating layer (INS) may include an opening that exposes a portion, for example, an upper surface, of each of the light emitting elements (LE). In one embodiment, the insulating layer (INS) may be formed to a height greater than or equal to the height of the light emitting elements (LE) and may be opened at an upper portion of each of the light emitting elements (LE). For example, the insulating layer (INS) may include an opening (for example, an opening OPN of FIG. 18) that exposes a portion of an upper surface of each of the light emitting elements (LE) and may cover the remaining portion of each of the light emitting elements (LE).

[0128] The insulating layer (INS) may be formed of a single layer or multiple layers including at least one insulating material. For example, the insulating layer (INS) may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ), or other inorganic insulating materials.

[0129] In one embodiment, the insulating layer (INS) may include a groove (GRV) surrounding the light emitting elements (LE) around the light emitting elements (LE). In one embodiment, the groove (GRV) may be arranged in a mesh shape surrounding the light emitting elements (LE) when viewed from a plan view. For example, the groove (GRV) may have a mesh shape corresponding to the reflective film (RFL) and the power wiring (PL) of FIG. 2 when viewed from a plan view.

[0130] In one embodiment, the groove (GRV) may be formed to a depth greater than or equal to the thickness of the light emitting elements (LE). For example, the depth of the groove (GRV) may be greater than or equal to the thickness of the light emitting elements (LE), and the bottom surface of the groove (GRV) may be positioned below the height of the light emitting elements (LE). However, the embodiments are not limited thereto. For example, the groove (GRV) may be formed to a depth greater than or equal to the thickness of the insulating layer (INS). For example, the insulating layer (INS) may define a side wall of the groove (GRV), and another insulating layer (for example, a protective film (PSV) or a first cover layer (CVL1)) under the insulating layer (INS) may define the bottom surface of the groove (GRV).

[0131] The reflective film (RFL) may be disposed on the groove (GRV) of the insulating layer (INS). The reflective film (RFL) has a shape corresponding to the shape of the groove (GRV) of the insulating layer (INS) and may surround a side surface of each of the light emitting elements (LE). For example, the reflective film (RFL) may be disposed around and between the light emitting elements (LE), and may face a side surface of each of the light emitting elements (LE). For example, the reflective film (RFL) may have a mesh shape including openings exposing the light emitting elements (LE) as shown in FIG. 2 when viewed in plan view, and may face a side surface of the light emitting elements (LE) as shown in FIGS. 3 and 4 when viewed in cross section.

[0132] The reflective film (RFL) can reflect and recycle light generated from each of the light emitting elements (LE) and directed in a lateral direction, etc. The light emission efficiency (e.g., the ratio of light that passes through the second contact electrode (CTE2) and the common electrode (CME) and is emitted from the upper portion of the light emitting element (LE)) of each of the light emitting elements (LE) can be increased by the reflective film (RFL).

[0133] In one embodiment, the lowest height of the reflective film (RFL) may be less than or equal to the height of the light emitting elements (LE). For example, the bottom surface of the reflective film (RFL) positioned on the bottom surface of the groove (GRV) may be positioned at a height less than or equal to the height of the light emitting elements (LE). In addition, the highest height (for example, the height of the upper surface) of the reflective film (RFL) may be greater than or equal to the height of the light emitting elements (LE). Accordingly, the reflective film (RFL) may entirely or completely surround the side surface of each of the light emitting elements (LE). This allows light emitted from the light emitting elements (LE) in a lateral direction to be more effectively reflected.

[0134] In one embodiment, the reflective film (RFL) may include a highly reflective metal, such as aluminum (Al). When the reflective film (RFL) includes a conductive material such as a metal, the reflective film (RFL) may be electrically connected to the power line (PL). Accordingly, the reflective film (RFL) may function as an auxiliary power line, thereby reducing the resistance of the power line (PL).

[0135] In another embodiment, the reflective film (RFL) may include distributed Bragg reflectors (DBR). For example, the reflective film (RFL) may include at least one pair (e.g., two or more pairs) of first and second layers having different refractive indices and arranged alternately or sequentially. One of the first and second layers may be a low-refractive-index layer, and the other may be a high-refractive-index layer having a higher refractive index than the low-refractive-index layer. The first and second layers may be inorganic films, for example, silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (Ti x O y ), or aluminum oxide (Al x O y ) can be formed.

[0136] In one embodiment, the reflective film (RFL) may have a substantially smooth surface, as illustrated in FIG. 3. In another embodiment, the reflective film (RFL) may include a surface having a textured pattern (TXP) of a regular or irregular shape, as illustrated in FIG. 4, and may have surface roughness according to the textured pattern (TXP). As the reflective film (RFL) has surface roughness, light reflectance by the reflective film (RFL) may be increased. For example, light reflectance of the reflective film (RFL) may be increased due to diffuse reflection by the textured pattern (TXP), and thus, light output ratio of the pixels (PX) may be further increased.

[0137] In the embodiments, since the reflective film (RFL) is formed while the light emitting elements (LE) are stably covered with a protective film (PSV) and an insulating layer (INS), a short-circuit defect (e.g., a short-circuit defect of the light emitting elements (LE) due to a by-product) that may occur during an etching process of the reflective film (RFL) or the like can be effectively prevented.

[0138] The power wiring (PL) can be placed on the reflective film (RFL) and can be placed within the groove (GRV) of the insulating layer (INS). For example, the power wiring (PL) can be placed directly on the reflective film (RFL) and can fill the groove (GRV) of the insulating layer (INS).

[0139] In one embodiment, the reflective film (RFL) comprises a conductive material, such as metal, and the power line (PL) may be positioned directly on the reflective film (RFL). In this case, the reflective film (RFL) and the power line (PL) may be electrically connected to each other. Accordingly, the reflective film (RFL) may also function as an auxiliary power line, thereby preventing or reducing a voltage drop in the common voltage applied to the power line (PL).

[0140] The power wiring (PL) may have a shape corresponding to the groove (GRV) and the reflective film (RFL) of the insulating layer (INS). For example, the power wiring (PL) may have a mesh shape including openings exposing the light emitting elements (LE) as shown in FIG. 2 when viewed in plan view, and may completely fill the groove (GRV) of the insulating layer (INS) as shown in FIGS. 3 and 4 when viewed in cross section.

[0141] The common electrode (CME) may be disposed on the light emitting elements (LE), the second contact electrodes (CTE2), the reflective film (RFL), the power wiring (PL) and / or the insulating layer (INS).

[0142] In one embodiment, the common electrode (CME) may be disposed over the entire display area (DA). For example, the common electrode (CME) may be a common layer shared by the light-emitting elements (LE) of the display area (DA) and the pixels (PX) including the LE.

[0143] The common electrode (CME) can be electrically connected to the light emitting elements (LE). For example, openings can be formed in the passivation layer (PSV) and the insulating layer (INS) on top of each of the light emitting elements (LE), and the common electrode (CME) can be connected to the second contact electrodes (CTE2) (or the light emitting elements (LE)) within the openings.

[0144] In one embodiment, the common electrode (CME) may be electrically connected to the second contact electrodes (CTE2) and may be electrically connected to the second semiconductor layer (SEM2) of the light emitting elements (LE) through the second contact electrodes (CTE2). In another embodiment, the pixels (PX) may not include the second contact electrodes (CTE2), and the common electrode (CME) may be directly connected to the second semiconductor layer (SEM2) of each of the light emitting elements (LE). For example, the common electrode (CME) may be in contact with the second contact electrodes (CTE2) or the light emitting elements (LE) at a portion where the passivation layer (PSV) and the insulating layer (INS) are opened.

[0145] Additionally, the common electrode (CME) may be electrically connected to the power wiring (PL). For example, the common electrode (CME) may be placed directly on the power wiring (PL) and may be in contact with the power wiring (PL).

[0146] The common electrode (CME) may include a transparent conductive material that can transmit light. For example, the common electrode (CME) may be made of indium tin oxide (ITO), indium zinc oxide (IZO), or another transparent conductive material. In one embodiment, the common electrode (CME) may function as a cathode electrode of the light-emitting elements (LE) or pixels (PX).

[0147] The second cover layer (CVL2) may be disposed on the common electrode (CME). In one embodiment, the second cover layer (CVL2) may be disposed over the entire display area (DA) to cover the common electrode (CME). In one embodiment, the second cover layer (CVL2) may also be disposed in a peripheral area (for example, the peripheral area (PHA) of FIG. 1). The second cover layer (CVL2) may also be referred to as a "second passivation layer" or a "second insulating layer."

[0148] In one embodiment, the upper surface of the second cover layer (CVL2) may be substantially flat. For example, the second cover layer (CVL2) may be formed of a material and / or thickness suitable for having a substantially flat upper surface, or may be flattened by a planarization process performed after film deposition.

[0149] The second cover layer (CVL2) includes at least one insulating material and may have a single-layer or multi-layer structure. In one embodiment, the second cover layer (CVL2) includes an inorganic insulating material (for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ), or other inorganic insulating materials, but are not limited thereto.

[0150] The lens (LS) may be disposed on the second cover layer (CVL2). For example, lenses (LS) overlapping each of the light emitting elements (LE) may be disposed on the second cover layer (CVL2). In one embodiment, each lens (LS) may have a size corresponding to a light emitting area of ​​each pixel (PX) and may completely overlap the light emitting element (LE) disposed in each pixel (PX). For example, the lens (LS) may be a micro lens corresponding to the size of each of the light emitting elements (LE). In one embodiment, each lens (LS) may have a size larger than each light emitting element (LE) when viewed in a plan view and may cover the light emitting element (LE) and the periphery of the light emitting element (LE).

[0151] In one embodiment, the lens (LS) may be a micro lens in the form of a convex lens provided on top of the light emitting elements (LE), but the type, shape, and / or size of the lens (LS) is not limited thereto. By arranging the lens (LS) on top of the light emitting elements (LE), the light emission characteristics of the pixels (PX) can be adjusted and / or improved.

[0152] The lens (LS) may be formed of a transparent material to allow light incident from the light-emitting elements (LE) to pass through. For example, the lens (LS) may be formed of glass, plastic, ceramic, or other materials, and may be formed of an optical material with a high refractive index.

[0153] In one embodiment, the display panel (DPN) or the display device (10) including the same may further include additional components. For example, the display panel (DPN) or the display device (10) including the same may further include a light conversion layer or a color filter, etc., arranged on top of the pixels (PX) (or the light emitting elements (LE)).

[0154] According to the above-described embodiments, since the reflective film (RFL) is disposed on the groove (GRV) of the insulating layer (INS), the reflective film (RFL) can appropriately reflect light emitted in the lateral direction of the light emitting elements (LE) without covering the upper surface of the light emitting elements (LE). Accordingly, the light emission angles (θ1, θ2) at which light can be emitted upward from the light emitting elements (LE) increase, so that the amount of light emitted from the light emitting elements (LE) can increase. For example, according to the embodiments, the amount of light emitted upward from the light emitting elements (LE) and reaching the lens (LS) can increase. Accordingly, the light efficiency of the light emitting elements (LE) and the pixels (PX) including the light emitting elements (LE) can be increased.

[0155] In addition, according to the embodiments described above, light leakage or light interference between pixels (PX) can be prevented by the reflective film (RFL). Accordingly, color mixing of light emitted from pixels (PX) can be prevented.

[0156] Additionally, according to the embodiments described above, the light-emitting elements (LE) and the reflective film (RFL) can be appropriately spaced or separated by the protective film (PSV) and the insulating layer (INS). Accordingly, electrical stability between the light-emitting elements (LE) and the reflective film (RFL) can be secured, and short-circuit failure can be prevented.

[0157] FIGS. 5 to 7 are perspective views illustrating a method for manufacturing a display device according to one embodiment. For example, FIGS. 5 to 7 illustrate manufacturing steps of preparing a first substrate (100) and a second substrate (200) for manufacturing a display panel (DPN) according to one embodiment, and placing the second substrate (200) on the first substrate (100).

[0158] In one embodiment, the first substrate (100) and the second substrate (200) of FIGS. 5 to 7 may include a plurality of cell regions for simultaneously manufacturing a plurality of display panels (DPN). However, the embodiments are not limited thereto. For example, the first substrate (100) and the second substrate (200) may have a size corresponding to a single display panel (DPN).

[0159] Referring to FIG. 5, a first substrate (100) can be prepared. The first substrate (100) can include a lower substrate (110) of a display panel (DPN), a first barrier material layer (120), and a first bonding material layer (130) (also referred to as a “first bonding metal layer”). The first barrier material layer (120) and the first bonding material layer (130) can be sequentially arranged or formed on the lower substrate (110) along a third direction (DR3).

[0160] In one embodiment, the lower substrate (110) may include a semiconductor circuit board (PCL) as illustrated in FIGS. 3 and 4. The lower substrate (110) may further include connection electrodes (CNE) and a first cover layer (CVL1) on the semiconductor circuit board (PCL). For example, as illustrated in FIGS. 3 and 4, a semiconductor circuit board (PCL) including a base substrate (SB), pixel circuits (PXC), and pixel electrodes (PXE) may be prepared, and the first cover layer (CVL1) and the connection electrode (CNE) may be formed on the semiconductor circuit board (PCL) to prepare the lower substrate (110). The lower substrate (110) may include a cell region for forming at least one display panel (DPN). For example, the lower substrate (110) of FIG. 5 may be prepared in a size and shape that includes a plurality of cell regions for simultaneously manufacturing a plurality of display panels (DPN). Each of the above cell regions may include pixel circuits (PXC), pixel electrodes (PXE), connection electrodes (CNE), and a first cover layer (CVL).

[0161] The first barrier material layer (120) and the first bonding material layer (130) are for forming bonding electrodes (BDE) of pixels (PX), and the lower layers of each of the bonding electrodes (BDE) may be formed from the first barrier material layer (120) and the first bonding material layer (130). For example, the lower layers of the first barrier layer (BRL1) and the bonding layer (BMTL) of FIGS. 3 and 4 may be formed from the first barrier material layer (120) and the first bonding material layer (130), respectively.

[0162] The first barrier material layer (120) may be formed using a material, such as the material previously exemplified as the material of the first barrier layer (BRL1). The first barrier material layer (120) may be patterned as the first barrier layer (BRL1) of each of the bonding electrodes (BDE) by an etching process performed after the bonding process.

[0163] The first bonding material layer (130) may be formed using a material previously exemplified as a material of the bonding layer (BMTL), etc. For example, the first bonding material layer (130) may be formed of a gold (Au)-tin (Sn) alloy, titanium (Ti), zirconium (Zr), nickel (Ni), chromium (Cr), or other bonding metal. The first bonding material layer (130) may be formed to a thickness suitable for the bonding process. For example, the first bonding material layer (130) may be formed to a thickness of 100 nm to 300 nm (for example, 200 nm), but is not limited thereto. The first bonding material layer (130) may be patterned into a bonding layer (BMTL) of each of the bonding electrodes (BDE) (for example, a lower portion of the bonding layer (BMTL)) through a bonding process and a subsequent etching process.

[0164] Referring to FIG. 6, a second substrate (200) for forming light emitting elements (LE) of a display panel (DPN) can be prepared. The second substrate (200) can include a semiconductor substrate (210), an epi-layer (220), a first contact material layer (230), a third barrier material layer (240), a reflective material layer (250), a second barrier material layer (260), and a second bonding material layer (270) (also referred to as a “second bonding metal layer”). The epi-layer (220), the first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), and the second bonding material layer (270) can be sequentially arranged or formed on the semiconductor substrate (210).

[0165] The semiconductor substrate (210) may be a manufacturing substrate for manufacturing light emitting elements (LEs). For example, the semiconductor substrate (210) may be a growth substrate suitable for epitaxial growth.

[0166] In one embodiment, the semiconductor substrate (210) may include a material such as GaAs, silicon (Si), sapphire, SiC, GaN, or ZnO. For example, the semiconductor substrate (210) may be a silicon or sapphire substrate. As long as the epitaxial growth of the epi layer (220) for manufacturing the light emitting elements (LE) can be smoothly performed, the type or material of the semiconductor substrate (210) is not particularly limited.

[0167] The epilayer (220) may be for forming semiconductor layers of each of the light-emitting elements (LE). For example, the first semiconductor layer (SEM1), the light-emitting layer (EML), and the second semiconductor layer (SEM2) of each of the light-emitting elements (LE) illustrated in FIGS. 3 and 4 may be formed from the epilayer (220). In this case, the epilayer (220) may include a third epilayer (the third epilayer (221) of FIG. 8) for forming the second semiconductor layers (SEM2) of the light-emitting elements (LE), a second epilayer (the second epilayer (222) of FIG. 8) for forming the light-emitting layers (EML) of the light-emitting elements (LE), and a first epilayer (the first epilayer (223) of FIG. 8) for forming the first semiconductor layers (SEM1) of the light-emitting elements (LE). For example, an epi layer (220) can be formed on a semiconductor substrate (210) by epitaxial growth using the materials previously exemplified as the materials of the second semiconductor layer (SEM2), the light-emitting layer (EML), and the first semiconductor layer (SEM1) of the light-emitting element (LE).

[0168] The first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), and the second bonding material layer (270) may be used to form the first contact electrodes (CTE1) and the bonding electrodes (BDE) of the pixels (PX). For example, the first contact electrodes (CTE1) may be formed from the first contact material layer (230). The upper layers of each of the bonding electrodes (BDE), for example, the upper portions of the third barrier layer (BRL3), the reflective layer (RMTL), the second barrier layer (BRL2), and the bonding layer (BMTL), may be formed from the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), and the second bonding material layer (270), respectively.

[0169] The first contact material layer (230) may be formed using a material (e.g., ITO, etc.) previously exemplified as a material of the first contact electrodes (CTE1). In one embodiment, the first contact material layer (230) may be formed to a thickness suitable for functioning as a contact electrode for smoothly connecting the light emitting elements (LE) to each of the bonding electrodes (BDE). For example, the first contact material layer (230) may be formed to a thickness of approximately 100 nm, but is not limited thereto. The first contact material layer (230) may be patterned into the first contact electrode (CTE1) of each of the pixels (PX) by an etching process performed after the bonding process.

[0170] The third barrier material layer (240) may be formed using a material (e.g., TiN, etc.) previously exemplified as a material of the third barrier layer (BRL3). In one embodiment, the third barrier material layer (240) may be a thin film formed with a limited thickness, for example, a thickness of 20 nm or less, but is not limited thereto. The third barrier material layer (240) may be patterned as the third barrier layer (BRL3) of each of the bonding electrodes (BDE) by an etching process performed after the bonding process.

[0171] The reflective material layer (250) may be formed using a material (e.g., Al, etc.) previously exemplified as a material of the reflective layer (RMTL). In one embodiment, the reflective material layer (250) may be formed to a thickness capable of appropriately reflecting light emitted from the light emitting elements (LE) (e.g., a thickness capable of securing a target range of light reflectance). For example, the reflective material layer (250) may be formed to a thickness of 100 nm to 200 nm, but is not limited thereto. The reflective material layer (250) may be patterned into a reflective layer (RMTL) of each of the bonding electrodes (BDE) by an etching process performed after the bonding process.

[0172] The second barrier material layer (260) may be formed using a material (e.g., Ti, etc.) previously exemplified as a material of the second barrier layer (BRL2). The second barrier material layer (260) may be patterned as a second barrier layer (BRL2) of each of the bonding electrodes (BDE) by an etching process performed after the bonding process.

[0173] The second bonding material layer (270) may be formed using a material previously exemplified as a material of the bonding layer (BMTL), etc. For example, the second bonding material layer (270) may be formed using a gold (Au)-tin (Sn) alloy, titanium (Ti), zirconium (Zr), nickel (Ni), chromium (Cr), or other bonding metal. In one embodiment, the first bonding material layer (130) and the second bonding material layer (270) may include the same material. The second bonding material layer (270) may be formed to a thickness suitable for the bonding process. For example, the second bonding material layer (270) may be formed to a thickness of 100 nm to 300 nm (for example, 200 nm), but is not limited thereto. The second bonding material layer (270) can be patterned into a bonding layer (BMTL) (for example, an upper portion of the bonding layer (BMTL)) by an etching process performed after the bonding process.

[0174] Referring to FIG. 7, the first substrate (100) and the second substrate (200) can be arranged to face each other. For example, after aligning the first substrate (100) and the second substrate (200) so that the first bonding material layer (130) of the first substrate (100) and the second bonding material layer (270) of the second substrate (200) face each other, the first bonding material layer (130) and the second bonding material layer (270) can be brought into contact or close contact with each other.

[0175] Thereafter, the first bonding material layer (130) and the second bonding material layer (270) can be melted to bond (or join) the first substrate (100) and the second substrate (200). For example, after placing the second substrate (200) on the first substrate (100), heat and pressure can be applied to join the first substrate (100) and the second substrate (200).

[0176] FIGS. 8 to 20 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment. For example, FIGS. 8 to 20 illustrate a pixel process performed after bonding a first substrate (100) and a second substrate (200). The pixel process may include a process of forming pixels (PX) including light-emitting elements (LE) in each cell area on a lower substrate (110).

[0177] FIGS. 8 to 20 show only a portion of one cell area, for example, a unit pixel area (UPA) located within one cell area. The unit pixel areas (UPAs) of FIGS. 8 to 20 may correspond to the unit pixel areas (UPAs) of FIG. 3. The display panel (DPN) according to the embodiment of FIG. 4 can be manufactured in a similar manner to the display panel (DPN) according to the embodiment of FIG. 3. For example, the display panel (DPN) according to the embodiment of FIG. 4 can be manufactured in substantially the same manner as the display panel (DPN) according to the embodiment of FIG. 3, except that a process for forming a textured pattern (TXP) on the surface of the reflective film (RFL) is added.

[0178] In addition, although FIGS. 8 to 20 disclose embodiments in which the light emitting elements (LE) of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) are formed from epi layers (220) formed on one semiconductor substrate (210), the embodiments are not limited thereto. For example, the light emitting elements (LE) of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be formed from different epi layers (220) and disposed on bonding electrodes (BDE) or the lower substrate (110).

[0179] Referring to FIGS. 7 and 8, a second substrate (200) can be bonded to a first substrate (100) by bonding a first bonding material layer (130) and a second bonding material layer (270) to form a bonding layer (300). For example, a bonding process can be performed by applying heat and pressure while the second substrate (200) is placed on the first substrate (100) so that the first bonding material layer (130) and the second bonding material layer (270) are in contact. Accordingly, the first bonding material layer (130) and the second bonding material layer (270) can be melted to form one bonding layer (300). The bonding layer (300) can be patterned into a bonding layer (BMTL) of each of the bonding electrodes (BDE) by an etching process performed after the bonding process.

[0180] FIG. 8 shows the structure of the epilayer (220) in more detail. For example, the epilayer (220) may include a first epilayer (223) (e.g., a p-type semiconductor layer) for forming first semiconductor layers (SEM1) of the light-emitting elements (LE), a second epilayer (222) (e.g., a multi-quantum well layer including a quantum well layer and a barrier layer) for forming light-emitting layers (EML) of the light-emitting elements (LE), and a third epilayer (221) (e.g., an n-type semiconductor layer) for forming second semiconductor layers (SEM2) of the light-emitting elements (LE).

[0181] Referring to FIGS. 8 and 9, after forming the bonding layer (300), the semiconductor substrate (210) can be separated from the epi layer (220). Accordingly, the semiconductor substrate (210) can be removed from the epi layer (220).

[0182] Referring to FIG. 10, a second contact material layer (310) can be formed (for example, deposited) on an epi layer (220). The second contact material layer (310) is for forming second contact electrodes (CTE2) of the pixels (PX), and the second contact electrodes (CTE2) of each of the pixels (PX) can be formed from the second contact material layer (310).

[0183] The second contact material layer (310) may be formed using a material (e.g., ITO, etc.) previously exemplified as a material of the second contact electrodes (CTE2). In one embodiment, the second contact material layer (310) may be formed to a thickness suitable for functioning as a contact electrode for smoothly connecting the light emitting elements (LE) to the common electrode (CME). In addition, the second contact material layer (310) may be formed so that light emitted from the light emitting elements (LE) may be transmitted therethrough. For example, the second contact material layer (310) may include a transparent conductive material and may be formed to a thickness of approximately 100 nm, but is not limited thereto. In one embodiment, when manufacturing a display panel (DPN) that does not include the second contact electrodes (CTE2) (e.g., a display panel (DPN) in which the common electrode (CME) is directly disposed on the light emitting elements (LE)), a process step for forming the second contact material layer (310) may be omitted.

[0184] Referring to FIGS. 10 and 11, the second contact material layer (310) and the epi layer (220) may be etched to form the second contact electrode (CTE2) and the light emitting element (LE) of each of the pixels (PX). In one embodiment, the second contact material layer (310) and the epi layer (220) may be etched by an etching process using one mask. For example, the second contact material layer (310) and the epi layer (220) may be etched simultaneously and / or continuously by an etching process using a first mask. As a result, the second contact electrode (CTE2) and the light emitting element (LE) of each of the pixels (PX) may be formed.

[0185] In an etching process using the first mask, the type and ratio of the etching gas may vary depending on the material of each layer being etched. For example, the type and ratio of the etching gas may be adjusted or changed so that each layer being etched can be appropriately etched.

[0186] Referring to FIGS. 11 and 12, the first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), the bonding layer (300), and the first barrier material layer (120) may be etched to form a first contact electrode (CTE1) and a bonding electrode (BDE) of each of the pixels (PX). In one embodiment, the first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), the bonding layer (300), and the first barrier material layer (120) may be etched by an etching process using one mask. For example, the first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), the bonding layer (300), and the first barrier material layer (120) can be etched simultaneously and / or continuously by an etching process using a second mask. As a result, the first contact electrode (CTE1) and the bonding electrode (BDE) of each of the pixels (PX) can be formed.

[0187] In an etching process using a second mask, the type and ratio of etching gas may vary depending on the material of each layer being etched. For example, the type and ratio of etching gas may be adjusted or changed to appropriately etch each layer being etched.

[0188] Although FIGS. 11 and 12 disclose an embodiment in which an additional mask process is performed to etch the first contact electrode (CTE1) and the bonding electrode (BDE) after forming the light emitting elements (LE), the embodiments are not limited thereto. For example, the number of times the mask process is performed for etching the second contact material layer (310), the epi layer (220), the first contact material layer (230), the third barrier material layer (240), the reflective material layer (250), the second barrier material layer (260), the bonding layer (300), and the first barrier material layer (120), and / or the shape or size of the second contact electrode (CTE2), the light emitting element (LE), the first contact electrode (CTE1), and the bonding electrode (BDE) according to the embodiments may be variously changed.

[0189] Additionally, in FIGS. 5 to 12, an embodiment is disclosed in which a second substrate (200) including an epi layer (220) and a second bonding material layer (270) is bonded on a first substrate (100) including a lower substrate (110) and a first bonding material layer (130), and then the epi layer (220) and the bonding layer (300) are etched to form light-emitting elements (LE) and bonding electrodes (BDE). However, the method of arranging or forming the light-emitting elements (LE) on the lower substrate (110) is not limited thereto. For example, after etching the epi layer (220) on a semiconductor substrate (210) to form the light-emitting elements (LE), the light-emitting elements (LE) may be arranged on the lower substrate (110).

[0190] Referring to Fig. 13, a protective film (PSV) can be formed to cover the side surfaces of the light emitting elements (LE). The protective film (PSV) is formed of the material of the protective film (PSV) exemplified above (for example, Al). x O y (for example, Al2O3) or other insulating materials) can be formed.

[0191] In one embodiment, a protective film (PSV) may first be formed over the entire display area (DA) and may be etched in a subsequent process to expose a portion of each of the light emitting elements (LE). For example, the protective film (PSV) may entirely cover the bonding electrodes (BDE), the first contact electrodes (CTE1), the light emitting elements (LE), and the second contact electrodes (CTE2).

[0192] Referring to FIG. 14, an insulating layer (INS) may be formed on the protective film (PSV). In one embodiment, the insulating layer (INS) may be formed over the entire surface of the lower substrate (110) or the like to fill the space between the light emitting elements (LE). For example, the insulating layer (INS) may first be formed over the entire surface of the display area (DA).

[0193] In one embodiment, the insulating layer (INS) can be formed to a height greater than the height of the light emitting elements (LE) so as to completely cover the light emitting elements (LE). For example, the insulating layer (INS) can cover the bonding electrodes (BDE) of the pixels (PX), the light emitting elements (LE), and the passivation layer (PSV), and can also fill the space between the light emitting elements (LE). The insulating layer (INS) can be formed using the materials exemplified above, or other insulating materials.

[0194] In one embodiment, the insulating layer (INS) may be formed to be substantially flat. For example, the insulating layer (INS) may be formed of a material and / or thickness suitable for having a flat upper surface, or may be flattened by a planarization process (e.g., a chemical mechanical polishing (CMP) process) performed after film deposition.

[0195] For example, SiO x After forming an insulating layer (INS) higher than the height of the light emitting elements (LE) using an inorganic insulating material such as (for example, SiO2), the upper surface of the insulating layer (INS) can be planarized by a planarization process (for example, a CMP process, etc.). Alternatively, the insulating layer (INS) can be formed using an inorganic insulating material, and the insulating layer (INS) can be formed to a sufficient thickness so that the upper surface of the insulating layer (INS) is substantially planar. However, the embodiments are not limited thereto. For example, the insulating layer (INS) can include at least one organic insulating layer including an organic insulating material, and thus the insulating layer (INS) can be formed to be substantially planar.

[0196] However, the embodiments are not limited thereto. For example, the insulating layer (INS) may be formed to have a step according to the light emitting elements (LE).

[0197] Referring to FIG. 15, a groove (GRV) surrounding the light emitting elements (LE) can be formed by etching the insulating layer (INS). For example, the insulating layer (INS) can be etched to a certain thickness so as to surround each of the light emitting elements (LE) in a non-overlapping portion (e.g., between and / or around the light emitting elements (LE)) when viewed in a plan view (or in a third direction (DR3)). Accordingly, a groove (GRV) can be formed in the insulating layer (INS) in a shape surrounding the light emitting elements (LE). For example, the groove (GRV) can have a mesh shape surrounding the light emitting elements (LE) when viewed in a plan view.

[0198] In one embodiment, the insulating layer (INS) can be etched to a depth (or level) lower than the height at which the light emitting elements (LE) are arranged. Accordingly, the height of the bottom surface of the groove (GRV) can be arranged lower than the height of the light emitting elements (LE). For example, the bottom surface of the groove (GRV) can be arranged at a height similar to the height of the reflective layer (RMTL) of each of the bonding electrodes (BDE), or can be arranged at a height lower than the height of the reflective layer (RMTL).

[0199] In FIGS. 14 and 15, an embodiment is disclosed in which an insulating layer (INS) is formed to a height greater than the height of the light emitting elements (LE) so as to completely fill the space between the light emitting elements (LE), and then the insulating layer (INS) is etched to form a groove (GRV), but the embodiments are not limited thereto. For example, the insulating layer (INS) may be formed to a thickness less than the thickness of the bonding electrodes (BDE) or the light emitting elements (LE) using an inorganic insulating material. Accordingly, the insulating layer (INS) may be formed to have a curve including a groove (GRV) between the light emitting elements (LE) from the film deposition step. In this case, the process for forming the groove (GRV) in the insulating layer (INS) may be omitted. Alternatively, even if the insulating layer (INS) is formed to include a groove (GRV) between the light emitting elements (LE), an etching process may be performed to adjust or change the shape or depth of the groove (GRV) before forming the reflective layer (RFL) in order to form the reflective layer (RFL) and / or the power wiring (PL) in a desired shape.

[0200] In addition, although FIGS. 14 and 15 disclose an embodiment in which the insulating layer (INS) is etched only to a portion of its thickness to form the groove (GRV), the embodiments are not limited thereto. For example, in another embodiment, the groove (GRV) may be formed by etching the insulating layer (INS) to its entire thickness around the light emitting elements (LE). In this case, the insulating layer (INS) may define the sidewall of the groove (GRV), and the protective film (PSV) or the first cover layer (CVL1) may define the bottom surface of the groove (GRV).

[0201] Referring to Fig. 16, a reflective film (RFL) can be formed on a groove (GRV) of an insulating layer (INS). Accordingly, a reflective film (RFL) having a shape corresponding to the shape of the groove (GRV) can be formed at a position where the groove (GRV) is arranged. The reflective film (RFL) can surround the side surfaces of the light-emitting elements (LE). For example, the reflective film (RFL) can have a mesh shape surrounding the light-emitting elements (LE) when viewed from a plan view, and can face the side surfaces of the light-emitting elements (LE) when viewed from a cross-section.

[0202] In addition to the reflective layer (RMTL) of each of the bonding electrodes (BDE), the light traveling in the downward and lateral directions of the light emitting elements (LE) is appropriately reflected by the reflective film (RFL) disposed on the groove (GRV) of the insulating layer (INS), thereby increasing the amount of light emitted in the upward direction of each of the light emitting elements (LE). Accordingly, the light efficiency of the light emitting elements (LE) and the pixels (PX) including the light emitting elements (LE) can be improved.

[0203] In one embodiment, when forming a reflective film (RFL) including a textured pattern (TXP) as in the embodiment of FIG. 4, an additional process may be performed to form the textured pattern (TXP) on the surface of the reflective film (RFL). For example, after forming the reflective film (RFL), the surface roughness may be imparted by forming the textured pattern (TXP) on the surface of the reflective film (RFL) through annealing or the like. Accordingly, the light reflectivity of the reflective film (RFL) can be further increased.

[0204] Referring to FIG. 17, a power line (PL) can be formed on a reflective film (RFL). In one embodiment, after forming a conductive film with a height higher than the insulating layer (INS) and the reflective film (RFL) so that the groove (GRV) in which the reflective film (RFL) is formed is completely filled, a planarization process such as an etching process or a polishing process such as CMP (Chemical Mechanical Polishing) is performed to form a mesh-shaped power line (PL) including openings that expose the light-emitting elements (LE). Accordingly, a power line (PL) having a shape corresponding to the shape of the groove (GRV) can be formed at a position where the groove (GRV) is arranged. For example, the power line (PL) may have a mesh shape that surrounds the light-emitting elements (LE) when viewed in a planar manner. The formation method or shape of the power line (PL) is not limited to the above-described embodiment and may be variously changed according to embodiments.

[0205] Referring to FIG. 18, a protective film (PSV) and an insulating layer (INS) may be etched on the upper portion of each of the light emitting elements (LE) to form an opening (OPN) exposing a portion of each of the second contact electrodes (CTE2) (or the light emitting elements (LE)). In one embodiment, the protective film (PSV) and the insulating layer (INS) may include materials having different etching selectivities and may include openings of different sizes.

[0206] Referring to FIG. 19, a common electrode (CME) can be formed on the light emitting elements (LE), an insulating layer (INS), a reflective film (RFL), and power wiring (PL). The common electrode (CME) can be formed over the entire surface of the light emitting elements (LE) using the materials exemplified above. For example, the common electrode (CME) can be formed over the entire surface of the display area (DA).

[0207] The common electrode (CME) may also be positioned or formed within the opening (OPN) of FIG. 18. Accordingly, the common electrode (CME) and the light-emitting elements (LE) may be electrically connected to each other. For example, the common electrode (CME) may be electrically connected to the light-emitting elements (LE) by contacting each second contact electrode (CTE2) (or light-emitting element (LE)) within each opening (OPN).

[0208] In one embodiment, the common electrode (CME) may be positioned or formed directly on the power line (PL). Accordingly, the common electrode (CME) and the power line (PL) may be electrically connected to each other.

[0209] Referring to FIG. 20, a second cover layer (CVL2) can be formed on the common electrode (CME). The second cover layer (CVL2) can be formed using a material suitable for protecting the light emitting elements (LE) and the pixels (PX) including the same. For example, the second cover layer (CVL2) can be formed over the entire surface of the common electrode (CME) using the inorganic insulating material or organic insulating material exemplified above.

[0210] In one embodiment, when the display panel (DPN) includes an additional element disposed on the second cover layer (CVL2), a process for forming or disposing the element may follow. For example, when manufacturing a display panel (DPN) (or display device (10)) including a lens (LS) as illustrated in FIGS. 3 and 4, the lens (LS) may be formed or disposed on the second cover layer (CVL2). The lens (LS) may be formed integrally with the display panel (DPN) or may be formed separately from the display panel (DPN) and disposed on the display panel (DPN).

[0211] By the above-described process, the display panel (DPN) according to the embodiment of Fig. 3 can be manufactured. In addition, by forming a textured pattern (TXP) on the surface of the reflective film (RFL) during the formation step of the reflective film (RFL) or immediately after the formation of the reflective film (RFL), the display panel (DPN) according to the embodiment of Fig. 4 can be manufactured.

[0212] As described above, the display device (10) according to the embodiments may include a reflective film (RFL) disposed on the groove (GRV) of the insulating layer (INS) and surrounding the side surfaces of the light-emitting elements (LE). According to the display device (10) and the manufacturing method thereof according to the embodiments, the light efficiency of the light-emitting elements (LE) and the pixels (PX) including the light-emitting elements (LE) can be increased. In addition, light leakage or light interference between the pixels (PX) can be prevented, and the electrical stability of the light-emitting elements (LE) and the reflective film (RFL) can be secured.

[0213] FIG. 21 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0214] Referring to FIG. 21, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of smart devices.

[0215] FIGS. 22 and 23 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0216] Referring to FIGS. 22 and 23, a virtual reality device according to one embodiment may be a head-mounted display device (1000_2). The head-mounted display device (1000_2) includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0217] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye.

[0218] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0219] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0220] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into video data and transmit the video data to the first display device (10_2) and the second display device (10_3) via the connectors.

[0221] The control circuit board (1600) can transmit video data corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and video data corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same video data to the first display device (10_2) and the second display device (10_3).

[0222] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 22 and 23, the first eyepiece (1210) and the second eyepiece (1220) are separately arranged, but the embodiment of the present specification is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0223] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0224] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1100) is implemented in a lightweight and compact form, the head-mounted display device (1000_2) may be equipped with a glasses frame as shown in FIG. 24 instead of the head-mounted band (1300).

[0225] In addition, the head-mounted display device (1000_2) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0226] FIG. 24 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0227] Referring to FIG. 24, a virtual reality device (1000_3) (or an augmented reality device) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0228] In FIG. 24, the virtual reality device (1000_3) is expected to be a glasses-type display device including glasses frame legs (30a, 30b), but the embodiments are not limited thereto. For example, the virtual reality device (1000_3) can be applied in various forms to other electronic devices.

[0229] The display device housing (50) may include a display device (10_4) and a reflective member (40) (or an optical path conversion member). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye. For example, the user may view an augmented reality image that is a combination of a virtual image displayed on the display device (10_4) through the right eye and a real image viewed through the right eye lens (10b).

[0230] In Fig. 24, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0231] Fig. 25 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. Fig. 25 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0232] Referring to FIG. 25, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0233] FIG. 26 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0234] Referring to FIG. 26, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also view an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0235] At least one of the display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_a, 10_b, 10_c, 10_d, 10_e) according to the embodiments of FIGS. 21 to 26 may be a display device (for example, the display device (10) of FIG. 1) to which at least one of the embodiments described above is applied. For example, at least one of the display devices (10_1, 10_2, 10_3, 10_4, 10_5, 10_a, 10_b, 10_c, 10_d, 10_e) according to the embodiments of FIGS. 21 to 26 may include a reflective film (RFL) disposed on a groove (GRV) of an insulating layer (INS) and surrounding a side surface of the light emitting elements (LE).

[0236] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Lower substrate; Light-emitting elements arranged on the lower substrate; A protective film covering the side surfaces of the above light-emitting elements; An insulating layer disposed on the protective film and including a groove surrounding the light-emitting elements; and A display device comprising a reflective film disposed on the above home and surrounding the side surfaces of the light-emitting elements.

2. In paragraph 1, A display device in which the above reflective film has a mesh shape including openings that expose the light-emitting elements when viewed on a flat surface.

3. In paragraph 1, A display device, wherein the reflective film includes a surface having a textured pattern and has a surface roughness according to the textured pattern.

4. In paragraph 1, The depth of the above groove is greater than the thickness of the light emitting elements, A display device in which the bottom surface of the above reflective film is positioned at a height lower than the height of the light-emitting elements.

5. In paragraph 1, The above reflective film is a display device including a metal or a distributed Bragg reflector.

6. In paragraph 1, Further comprising bonding electrodes arranged on the lower substrate, A display device in which the light emitting elements are arranged on the bonding electrodes.

7. In paragraph 6, A display device, wherein each of the above bonding electrodes includes a bonding layer and a reflective layer on the bonding layer.

8. In paragraph 7, A display device in which the reflective layer of each of the bonding electrodes completely covers the lower surface of each of the light-emitting elements.

9. In paragraph 1, A display device further comprising a common electrode disposed on the insulating layer and electrically connected to the light emitting elements.

10. In paragraph 9, Further comprising a power wire disposed on the reflective film and filled in the groove, The above common electrode is a display device arranged on the power wiring.

11. In paragraph 9, a cover layer disposed on the common electrode; and A display device further comprising lenses disposed on the cover layer and overlapping the light emitting elements.

12. Step of preparing the lower substrate including pixel circuits; A step of forming light emitting elements electrically connected to the pixel circuits on the lower substrate; A step of forming a protective film covering the light-emitting elements on the lower substrate; A step of forming an insulating layer including a groove surrounding the light emitting elements on the protective film; A step of forming a reflective film surrounding the side surfaces of the light-emitting elements on the above-mentioned home; and A method for manufacturing a display device, comprising the step of forming a common electrode electrically connected to the light-emitting elements on the insulating layer.

13. In paragraph 12, The step of forming the above insulating layer is: A step of forming the insulating layer on the protective film to a height greater than the height of the light emitting elements so as to completely cover the light emitting elements; and A method for manufacturing a display device, comprising the step of forming a groove in the insulating layer by etching the insulating layer in a non-overlapping portion with the light-emitting elements.

14. In paragraph 12, A method for manufacturing a display device, further comprising the step of forming a textured pattern on the surface of the reflective film after forming the reflective film.

15. A display device for displaying an image is included, wherein the display device comprises: lower substrate; Light-emitting elements arranged on the lower substrate; A protective film covering the side surfaces of the above light-emitting elements; An insulating layer disposed on the protective film and including a groove surrounding the light-emitting elements; and An electronic device comprising a reflective film disposed on the above home and surrounding the side surfaces of the light-emitting elements.

16. In paragraph 15, An electronic device wherein the reflective film has a mesh shape including openings that expose the light-emitting elements when viewed on a flat surface.

17. In paragraph 16, An electronic device in which the reflective film and the light-emitting elements do not overlap each other when viewed on a plane.

18. In paragraph 15, An electronic device wherein the reflective film includes a surface having a textured pattern and has a surface roughness according to the textured pattern.

19. In paragraph 15, The depth of the above groove is greater than the thickness of the light emitting elements, An electronic device in which the bottom surface of the above reflective film is positioned at a height lower than the height of the light-emitting elements.

20. In paragraph 19, An electronic device wherein the reflective film completely surrounds each side of the light-emitting elements.

Images