Photonic article and making a photonic article

Abstract

A method of making a photonic article with a photonic packaging assembly, the method comprising the steps of: making a bonding solution; aligning an optical fiber v-groove array with at least one integrated photonic passive component on a chip using the photonic packaging assembly; dispensing the bonding solution to an interface area between the v-groove array and the at least one integrated photonic passive component on the chip; bringing the v-groove array into physical contact with the chip at a temperature elevated above ambient; and removing the photonic article from the photonic packaging assembly.

Description

[0001] PHOTONIC ARTICLE AND MAKING A PHOTONIC ARTICLE

[0002] Related Applications

[0003] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 669,291 (filed July 10, 2024), which is herein incorporated by reference in its entirety.

[0004] Federally-Sponsored Research and Development

[0005] This invention was made with United States Government support from the National Institute of Standards and Technology (NIST), an agency of the United States Department of Commerce. The Government has certain rights in this invention.

[0006] Copyright Notice

[0007] This patent disclosure may contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves any and all copyright rights.

[0008] Field of Invention

[0009] The present invention relates generally to integrated photonic sensors, and more particularly to improved bonding processes for integrated photonic sensors.

[0010] Background

[0011] Integrated photonic sensors have advanced significantly in the past decade, driven by a combination of the inherent scalability of integrated photonics combined with precision nanofabrication as well as an ever-increasing range of applications. Such integrated sensors offer advantages in size, weight, and power compared to traditional sensor form-factors. Conventional technology for fiber-to-chip bonding is applying polymer-based UV curable adhesives to the bond interface. UV curable adhesives have been used successfully for photonic packaging with tapered as well as angle polished fibers for cryogenic operation as well as operation between 233 K to 373 K.

[0012] Summary of Invention

[0013] These polymeric adhesives are limited by their working temperature range (less than 150°C) and can be unstable in under radiation and chemical environment. UV curable adhesives are typically incompatible with elevated temperatures above 150 °C, are not stable under humidity and harsh chemical environment, and quickly degrade under extreme radiation. Meanwhile, the radiation hardness of unpackaged silicon photonic devices has been investigated both theoretically as well as in experiments with radiation doses above 1 MGy. From a system perspective, the key concerns of usage of common adhesive in photonic packaging are bond mechanical strength failure, insertion loss degradation and aging-related performance reduction with changing operating environments.

[0014] The photonic bonding method described herein overcomes the technical limitations of conventional technologies and is compatible with various harsh environments and can enable various integrated photonic applications for extreme environments such as high- and ultra-high vacuum (HV&UHV), extreme radiation, harsh chemical conditions, extreme temperature environment (both deep cryogenic and extreme high temperatures), and space.

[0015] Embodiments of the invention include a process for making a photonic article that includes a chemically-assisted optical bond between photonic interfaces, such as optical fibers, optical fiber arrays, integrated photonic chips, optical elements with small contact surface areas, and the like. The photonic bond is polymer-adhesive-free and is mechanically and optically stable. It provides efficient and robust light coupling between optical fibers and photonic chip, from a photonic chip to another photonic chip, and between optical elements with very small contact surface areas. The photonic bond is compatibly stable with harsh environments and can operate in integrated photonic applications for extreme environments such as high- and ultra-high vacuum (HV&UHV), extreme radiation, harsh chemical conditions, extreme temperature environment (e.g., deep cryogenic, extreme high temperatures, and the like), space, and the like. This new photonic bonding method can be used for a wide spectrum of photonics application, including applications that benefit from a robust, polymer-free photonic bonding method.

[0016] Embodiments of the invention include a method to couple light between photonic interfaces, such as optical fibers, optical fiber arrays, photonic integrated circuits (PICs) chips, as well as optical elements with small contact surface areas, so the bonded interface is mechanically and optically stable under extreme conditions. The bond can be formed between fiber or fiber array and a PIC chip, and / or between separate PIC chips. The bonding method can enable various integrated photonic applications for extreme environments such as highland ultra-high vacuum (HV&UHV), extreme ionizing radiation, harsh chemical conditions, extreme temperature environment (both deep cryogenic and extreme high temperatures), and spaceflight projects.

[0017] The foregoing and other features of the invention are hereinafter described in greater detail with reference to the accompanying drawings.

[0018] Brief Description of the Drawings

[0019] FIG.1 shows a process flow of making an exemplary photonic chip with integrated waveguides and surface grating couplers.

[0020] FIG. 2 shows a process flow of patterning chip surface to facilitate optical bonding.

[0021] FIG. 3 shows a top view of an exemplary chip with patterned microfluidic channels to deliver bonding agent.

[0022] FIG. 4 shows a top view of an exemplary chip with patterned microfluidic channels to deliver bonding agent and bonded v-groove fiber array.

[0023] FIG. 5 shows a side view of an exemplary chip with patterned microfluidic structure to deliver bonding agent and bonded v-groove fiber array.

[0024] FIG. 6 shows a top view of an exemplary chip with patterned microfluidic structure to deliver bonding agent.

[0025] FIG. 7 shows a top view of an exemplary chip with patterned microfluidic structure to deliver bonding agent with boded v-groove array. FIG. 8 shows a side view of an exemplary chip with the v-groove fiber array aligned to the surface grating couplers and bonded to the chip.

[0026] FIG. 9 shows a side view of an exemplary chip and v-groove array prealigned to the chip’s grating couplers, where the bonding agent is applied directly to the facet of the v-groove array before bonding.

[0027] FIG. 10 shows a side view of an exemplary chip and v-groove array prealigned to the chip’s grating couplers, where the bonding agent is applied directly on chip’s surface over the of grating couplers area before bonding.

[0028] FIG. 11 shows a side view of an exemplary chip and v-groove array prealigned to the chip’s grating couplers, where the bonding agent is applied directly on chip’s surface in the immediate proximity of v-groove to chip alignment area.

[0029] FIG. 12 shows a side view of an exemplary chip with the v-groove fiber array aligned to chip’s waveguides at a chip’s facet and bonded to the chip.

[0030] FIG. 13 shows a side view of an exemplary chip and v-groove array prealigned to chip’s waveguides at a chip’s facet, where the bonding agent is applied directly to the facet of the v-groove array before bonding.

[0031] FIG. 14 shows a side view of an exemplary chip and v-groove array prealigned to chip’s waveguides at a chip’s facet, where the bonding agent is applied directly on chip’s facet before bonding.

[0032] FIG. 15 shows a side view of an exemplary chip and v-groove array prealigned to chip’s waveguides at a chip’s facet, where the bonding agent is applied directly on chip’s surface in the immediate proximity of v-groove to chip alignment area.

[0033] FIG. 16 shows a schematic of an exemplary aligning method and device.

[0034] FIG. 17 shows a schematic of an exemplary optical setup for a photonic article 200 under test.

[0035] FIG. 18 shows a schematic of an exemplary aligning and optical setup for a photonic article 200 under test.

[0036] FIG. 19 shows a procedure of making photonic article.

[0037] FIG. 20 shows a schematic of an exemplary computer system to perform calculations of light coupling efficiency. Detailed Description

[0038] While photonic packaging is well established for many applications, robust and ruggedized photonic packaging is indispensable to field-deployable photonic sensors that must operate under extreme environments. One of the great challenges for integrated photonic applications is robust and efficient light coupling to PICs. The common practice of optical fiber attachment is gluing with ultra-violet (UV) light curable adhesives, which has several fundamental limitations that drastically reduce the application range of photonic chips for photonic applications. Specifically, conventional UV curable adhesives have a very limited temperature range (nominally not higher than 150°C), are not stable under humidity and harsh chemical environments, induce local stress on a PIC, and quickly degrade under ionizing radiation.

[0039] Here, we describe a method for photonic packaging that can operate at cryogenic temperatures, high temperature, HV / UHV, as well as in high radiation environments. Using low temperature hydroxide catalysis bonding and a novel packaging station to actively align and attach optical fiber v-groove arrays to a silicon photonic chip, exemplary chips are suitable across a wide temperature range from 360 K down to 3.8 K, and are thus suitable for cryogenic operation. Exemplary chips demonstrate no change in mechanical bond strength before and after annealing at high temperature (e.g., 973 K). Exemplary packaging methodology can be readily adapted to different photonics applications, ranging from cryogenic circuits to deployable extreme-environment sensors.

[0040] Embodiments of the invention improve upon hydroxide catalysis bonding (HCB) that was initially developed for astronomical instrumentation applications and that involve space-environment-compatible bonding of large optical components, e.g. lens, prisms, mirrors, etc. Hydroxide catalysis bonding has been widely used to bond macroscopic objects that have a characteristic length scale of a centimeter. On the other hand, coupling photonic interfaces with midsize surface areas, where photonic interfaces are to be aligned on a micrometerlevel precision, is challenging.

[0041] HCB is a chemical process during which a strong bond is formed between two flat surfaces. The bonding process forms a silicate-like network through hydroxide-catalyzed hydration and dehydration. Materials that can be bonded include fused silica, SiC, silicon, sapphire, glass, and aluminum, for example. The hydroxide compositions that can be used for HCB include potassium hydroxide (KOH), sodium hydroxide (NaOH), sodium silicate composition (NaOH with SiO2 nanoparticles), and lithium, rubidium and cesium hydroxide compositions. HCB is used to bond relatively large materials (with surface areas on the order of cm2or more). Examples include optical prisms, lenses, and mirrors. Embodiments of the invention include bonding small photonic interfaces by HCB, wherein an alkali-based hydroxide compositions (optionally including silica nanoparticles) can bond photonic interfaces with surface areas on the order few mm2.

[0042] Local microfluidic surface structure patterning on top of the photonic chip (on PIC’s surface or facet, fiber arrays, or both) is used to increase an effective surface area for bonding. The microfluidic pattern can be comprised of pillars, trenches, blocked out regions (to protect optical fiber coupling ports), microfluidic channels, microfluidic fill ports, or a combination of such elements. Such structured patterns are shown in FIG. 3 and FIG. 6.

[0043] The benefits of this structured surface patterning include:

[0044] • providing fast and spatially localized delivery of alkali-based hydroxide composition directly to the interface via capillary forces or positive pressure applied to microfluidic channels;

[0045] • applying a controlled amount of alkali-based hydroxide composition to the interface;

[0046] • providing facile removal of water from hydroxide composition via capillary structure;

[0047] • provide a faster curing time;

[0048] • minimizing a local stress at the interface;

[0049] • mitigating a coefficient of thermal expansion (CTE) mismatch of dissimilar materials;

[0050] • controlling a selected portion of the surface area at the bonding interfaces that is in contact with (or blocked by) alkali-based hydroxide composition and can minimize optical light coupling losses (from optical fiber to PIC) due to type and amount of hydroxide bonding composition at the interface; or

[0051] • increasing mechanical stability of the bond that is exposed to large thermal variations.

[0052] In an embodiment, with reference to FIG. 1 and FIG. 2, a process for making a photonic article 200 with a microfluidic structure 150 includes forming of a photonic chip 100 with integrated photonic passive components such as waveguides 130 and surface grating couplers 135.

[0053] Referring first to FIG. 1 , photonic chip 100 can include substrate 105, buried oxide 110, and device layer 115 at (A).

[0054] At (B), first photo- / ebeam-resist 120 is spin-coated on top of device layer 115.

[0055] At (C), after exposing resist 120 to photo- or ebeam lithography, designs for waveguides 130 and grating couplers 135 are transferred into the resist forming resist etched mask 125.

[0056] At (D), etch mask 125 is used to selectively etch the device layer 115 in reactive ion plasma (RIE) etch process. During REI etch the designed pattern of waveguides 130 and grating couplers 135 is transferred into device layer 115, forming waveguides 130 and grating couplers 135.

[0057] After dissolving the resist mask 125 in solvents at (F), oxide layer 140 is deposited on top of the chip 100 surface at (G).

[0058] Following waveguides and grating couplers fabrication, microfluidic structure 150 including microfluidic trenches 151 or pillars 154, microfluidic fill ports 157, microfluidic connection channels 155 is formed in oxide layer 140 (FIGs. 2, 3, 6). The fabrication process flow is shown in FIG. 2.

[0059] Here, a photo- / ebeam resist layer 145 is spin-coated on top of the photonic chip 100 at (A).

[0060] After exposing the photoresist layer 145 to photo- / ebeam lithography a design for microfluidic structures is transferred into resist layer 145 forming an etch mask 147 at (B).

[0061] Then the microfluidic structure 150 is etched into top-surface oxide layer 140 using RIE etch. After RIE etch the resist mask 147 is dissolved in solvents. The patterned microfluidic structure can include microfluidic fill ports 157, microfluidic connection lines 155, microfluidic trenches 151 , or inter-pillar microfluidic area 152 (FIGs. 3 and 6).

[0062] The microfluidic structure 150 delivers hydroxide catalysis composition to specific area on the chip and ensures that no hydroxide catalysis composition is delivered over the grating coupler area 159, so that no light is attenuated from optical fibers 166 to grating couplers 135.

[0063] To improve bonding strength between v-grove array 160 and photonic chip, a thin (100 nm to 200 nm) layer 170 of silicon dioxide (or other oxide that is transpired to light that is being coupled to the chip) can be deposited on the v- groove array facet.

[0064] Application of Bonding Agent, and Fast Aligning of Bonding Interfaces

[0065] After device fabrication, it can be fiber-coupled to, e.g., a commercially available 4-channel v-groove fiber array using the HCB process. The v-groove array has (e.g., four) single mode (SM) optical fibers that are positioned in v- shape grooves (at, e.g., 250 pm fiber-to-fiber spacing). The spacing between the surface grating couplers on a chip are configured to match the v-groove array inter-channel spacing. Both aligning and bonding of the v-groove to the chip may be performed on a photonic packaging assembly 300 shown in FIGs. 16 and 17.

[0066] Some key components of the packaging assembly 300 are (i) a hexapod 310 for chip mounting and micro-positioning, (ii) fiber array holder 360 configured to hold a v-groove array 340 relative to the chip 330, (iii) a hexapod thermal control unit (e.g., a Peltier module) 350 for chip temperature control, (iv) microdispenser unit 380 for application of the bonding agents or adhesives, (v) digital microscope cameras 390 (preferably 4) for visual control of the bonding process at different view angles, and (vi) optical interrogation setup 400, for monitoring light coupling to the chip.

[0067] Referring now to FIG. 19 along with FIG. 16, an exemplary method for bonding optical elements is shown at 500.

[0068] At block 510, a liquid sodium silicate (41 %) composition of sodium and silica particles additionally diluted in water (1 :6 vol) is made.

[0069] At block 520, optical element alignment is completed as shown with respect to an optical fiber in FIG. 16. The PIC 330 may be secured on a hexapod 310 via a vacuum chuck 370. V-groove fiber array 340 is held, for example via vacuum provided from fiber array holder 360. First, the fiber array and PIC are pre-aligned to allow a light from a laser source to couple via optical fiber to PIC, and then out of the PIC via optical fiber to photodetector. During the prealignment, a small air gap (on the order of a few micrometers) is maintained between the coupling interfaces. Once the alignment is achieved (light is coupled to and out of the PIC as verified by optical interrogation setup 400), the fiber array and PIC are brought in contact (a fiber array is moved down, and / or a PIC chip is move up). To achieve a reliable bond, the bonding surfaces may be parallel and in full contact. The fiber-array holder unit is designed to allow small movements for v-groove array in roll and pitch angle relative to the PIC. Additionally, placing a soft spacer between PIC and vacuum chuck also allows roll and pitch movement for the PIC itself. While bringing in contact v-groove array and PIC together, the v-groove and PIC can pivot (roll and pitch), two surfaces, once in contact are fully parallel, and a maximum surface area contact is achieved. After adjusting roll and pitch angles on the hexapod the facet of the v-groove is made parallel to the surface of the photonic chip. While maintaining the chip in the plane parallel to the facet of v-groove array, the chip position is adjusted until the light can couple from optical fibers of the v-groove array into the grating couplers on a chip. After aligning the chip, the facet of the v-groove is brought in contact with the top surface of the chip.

[0070] At block 530, the solution is dispensed. Alkali-based hydroxide composition can be delivered between the bonding photonic interfaces (endfacet on a vi-groove array and the surface of PIC) via a local structured pattern on the PIC surface. A small volume of the hydroxide composition can be dispensed to microfluidic ports 157, as shown FIGs. 4 and 7. Microfluidic structure 150 facilitates self-delivery of the hydroxide composition via capillary forces directly to the bonding interface.

[0071] In an embodiment with reference to FIGs. 8, 9, and FIGs. 12, 13, the HCB solution 171 can be microdispensed directly onto the facet of v-groove array (FIGs. 9, 13).

[0072] In an embodiment with reference to FIGs. 8, 10, and FIGs. 12, 14, the HCB solution 171 can be microdispensed directly on the chip at or in the proximity of light coupling ports (grating couplers 135, ends of waveguides 130) (FIGs. 10, 14).

[0073] In an embodiment with reference to FIGs. 8, 11 , and FIGs. 12, 15, the HCB solution 171 can be microdispensed at or in the proximity of light coupling ports (grating couplers 135, ends of waveguides 130) (FIGs. 11 , 15), when v- groove is pre-aligned to the chip and there is a small air gap between the facet of v-groove array and the chip as shown in FIGS. 11 , 15. The HCB solution 171 will be pulled into the gap by a capillary force.

[0074] At block 540, the optical elements (e.g., the v-groove array and chip) are brought into contact with each other at an elevated temperature. After applying the hydroxide composition, the temperature of the PIC is ramped from 25°C to 40°C at 5°C / hr rate, and then soaked at 40°C for 48 to 168- hours. After soaking the PIC temperature ramped down to 25°C at 10°C / hr rate.

[0075] At block 550, the optical elements are removed from the hexapod 310 and testing is conducted to verify the bond.

[0076] HCB stability have been tested for several materials including quartz, silicon (Si), oxidized silicon with thermally grown oxide, LPCVD (low-pressure chemical vapor deposition) and PECVD (plasma-enhanced chemical vapor deposition) deposited oxide, and SiN with deposited oxide. The bonded chips were tested in a tube furnace up to 700°C temperature. The dies (both quarts and silicon dies) remained strongly bonded after two consecutive thermal cycles.

[0077] The photonic chip with HCB-bonded v-groove fiber array (photonic article 200) has been tested down to deep cryogenic temperatures (<4 K) during slow cooling from 300 K t o4 K over 2 h to 3 h. The HCB packaged chip shows a strong resilience to large thermal shocks as a result of rapid submerging into liquid nitrogen bath at 77 K.

[0078] Using the same hydroxide catalysis bonding (HCB) method, an optical fiber v-groove array was bonded to a photonic chip. The chip includes integrated waveguides terminated with on-surface grating coupler. A decrease of light coupling efficiency was not observed after applying bonding agent and curing such that light coupling efficiency may be limited by grating coupler efficiency instead of bonding procedure. Photonic article 200 can be made of various elements and components that are microfabricated. Elements of photonic article 200 can be various sizes. Elements of photonic article 200 can be made of a material that is physically or chemically resilient in an environment in which photonic article 200 is disposed. Exemplary materials include a metal, ceramic, thermoplastic, glass, semiconductor, and the like. The elements of photonic article 200 can be made of the same or different material and can be monolithic in a single physical body or can be separate members that are physically joined.

[0079] FIG. 18 shows a schematic of an exemplary optical setup for a photonic article 200 under test. A tunable laser (e.g., 1550nm) is fiber coupled to a polarization controller and fiber polarized beam splitter (PBS) to control the optical power to the photonic article 200 under test. The transmitted light is coupled to an isolator and a second polarization controller that is comprised of quarter and half wave plates. Light coupled out of the photonic article 200 under test is split 50:50 to a photodiode (PD) and power meter (PM). Both single-mode (SM) and polarization-maintaining (PM) fiber were used in the setup.

[0080] Photonic article 200 can be made in various ways. It should be appreciated that photonic article 200 includes a number of optical, electrical, or mechanical components, wherein such components can be interconnected and placed in communication (e.g., optical communication, electrical communication, mechanical communication, and the like) by physical, chemical, optical, or free- space interconnects. The components can be disposed on mounts that can be disposed on a bulkhead for alignment or physical compartmentalization. As a result, photonic article 200 can be disposed in a terrestrial environment or space environment. Elements of photonic article 200 can be formed from silicon, silicon nitride, and the like although other suitable materials, such ceramic, glass, or metal can be used.

[0081] It should be understood that the calculations may be performed by any suitable computer system, such as that diagrammatically shown in FIG. 20. Data is entered into system 600 via any suitable type of user interface 616, and may be stored in memory 612, which may be any suitable type of computer readable and programmable memory and is preferably a non-transitory, computer readable storage medium. Calculations are performed by processor 614, which may be any suitable type of computer processor and may be displayed to the user on display 618, which may be any suitable type of computer display. Processor 614 may be associated with, or incorporated into, any suitable type of computing device, for example, a personal computer or a programmable logic controller. The display 618, the processor 614, the memory 612 and any associated computer readable recording media are in communication with one another by any suitable type of data bus, as is well known in the art.

[0082] Examples of computer-readable recording media include non-transitory storage media, a magnetic recording apparatus, an optical disk, a magnetooptical disk, and / or a semiconductor memory (for example, RAM, ROM, etc.). Examples of magnetic recording apparatus that may be used in addition to memory 612, or in place of memory 612, include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape (MT). Examples of the optical disk include a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc- Read Only Memory), and a CD-R (Recordable)ZRW. It should be understood that non-transitory computer-readable media include all computer-readable media except for a transitory, propagating signal.

[0083] The processes described herein may be embodied in, and fully automated via, software code modules executed by a computing system that includes one or more general purpose computers or processors. The code modules may be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all the methods may alternatively be embodied in specialized computer hardware. In addition, the components referred to herein may be implemented in hardware, software, firmware, or a combination thereof.

[0084] Many other variations than those described herein will be apparent from this disclosure. For example, depending on the embodiment, certain acts, events, or functions of any of the algorithms described herein can be performed in a different sequence, can be added, merged, or left out altogether (e.g., not all described acts or events are necessary for the practice of the algorithms). Moreover, in certain embodiments, acts or events can be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors or processor cores or on other parallel architectures, rather than sequentially. In addition, different tasks or processes can be performed by different machines and / or computing systems that can function together.

[0085] Any logical blocks, modules, and algorithm elements described or used in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, and elements have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality can be implemented in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.

[0086] The various illustrative logical blocks and modules described or used in connection with the embodiments disclosed herein can be implemented or performed by a machine, such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be a controller, microcontroller, or state machine, combinations of the same, or the like. A processor can include electrical circuitry configured to process computerexecutable instructions. In another embodiment, a processor includes an FPGA or other programmable device that performs logic operations without processing computer-executable instructions. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, a processor may also include primarily analog components. For example, some or all of the signal processing algorithms described herein may be implemented in analog circuitry or mixed analog and digital circuitry. A computing environment can include any type of computer system, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computational engine within an appliance, to name a few.

[0087] The elements of a method, process, or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module stored in one or more memory devices and executed by one or more processors, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of non-transitory computer-readable storage medium, media, or physical computer storage known in the art. An example storage medium can be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The storage medium can be volatile or nonvolatile.

[0088] While one or more embodiments have been shown and described, modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation. Embodiments herein can be used independently or can be combined.

[0089] All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. The ranges are continuous and thus contain every value and subset thereof in the range. Unless otherwise stated or contextually inapplicable, all percentages, when expressing a quantity, are weight percentages. The suffix (s) as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including at least one of that term (e.g., the colorant(s) includes at least one colorants). Option, optional, or optionally means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where the event occurs and instances where it does not. As used herein, combination is inclusive of blends, mixtures, alloys, reaction products, collection of elements, and the like. As used herein, a combination thereof refers to a combination comprising at least one of the named constituents, components, compounds, or elements, optionally together with one or more of the same class of constituents, components, compounds, or elements.

[0090] All references are incorporated herein by reference.

[0091] The use of the terms “a,” “an,” and “the” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. It can further be noted that the terms first, second, primary, secondary, and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. For example, a first current could be termed a second current, and, similarly, a second current could be termed a first current, without departing from the scope of the various described embodiments. The first current and the second current are both currents, but they are not the same condition unless explicitly stated as such.

[0092] The modifier about used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., it includes the degree of error associated with measurement of the particular quantity). The conjunction or is used to link objects of a list or alternatives and is not disjunctive; rather the elements can be used separately or can be combined together under appropriate circumstances.

[0093] Although the invention has been shown and described with respect to a certain embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described elements (components, assemblies, devices, compositions, etc.), the terms (including a reference to a "means") used to describe such elements are intended to correspond, unless otherwise indicated, to any element which performs the specified function of the described element (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiment or embodiments of the invention. In addition, while a particular feature of the invention may have been described above with respect to only one or more of several illustrated embodiments, such feature may be combined with one or more other features of the other embodiments, as may be desired and advantageous for any given or particular application.

Claims

ClaimsWhat is claimed is:1 . A photonic article comprising: a photonic chip with at least one integrated photonic passive component; an optical fiber v-groove array; and a bonding agent applied to the bonding photonic interfaces, and wherein the optical fiber v-groove array is structurally bonded to the photonic chip via the bonding agent, and wherein the optical fiber v-groove array is optically coupled to the at least one integrated photonic passive component of the photonic chip.

2. The photonic article of claim 1 , further including a thin layer of silicon dioxide on a facet of the v-groove array.

3. The photonic article of claim 1 , wherein a microfluidic structure on the chip includes microfluidic trenches or pillars, microfluidic fill ports, and microfluidic connection channels.

4. The photonic article of claim 1 , wherein a microfluidic structure delivers the bonding agent to the bonding interfaces via capillary forces.

5. The photonic article of claim 1 , wherein the bonding agent is an alkali-based hydroxide composition.

6. The photonic article of claim 1 , wherein the bonding agent is a liquid sodium silicate (41 %) composition of sodium and silica particles additionally diluted in water (1 :6 vol).

7. The photonic article of claim 1 , wherein the photonic chip further comprises a grating coupler area.

8. The photonic article of claim 1 , wherein the at least one integrated photonic passive component includes a waveguide.

9. The photonic article of claim 1 , wherein the at least one integrated photonic passive component includes surface grating couplers.

10. The photonic article of claim 9, wherein spacing between the surface grating couplers on a chip are configured to match inter-channel spacing of the v-groove array.

11. A method of making a photonic article with a photonic packaging assembly, the method comprising the steps of: making a bonding solution; aligning an optical fiber v-groove array having an interface area with at least one integrated photonic passive component on a chip using the photonic packaging assembly; dispensing the bonding solution to or adjacent to at least one of the interface area of the v-groove array or the at least one integrated photonic passive component on the chip; bringing the v-groove array into physical contact with the chip at a temperature elevated above ambient; and removing the photonic article from the photonic packaging assembly.

12. The method of making a photonic article of claim 11 , wherein the bonding solution is a hydroxide solution liquid.

13. The method of making a photonic article of claim 11 , wherein the step of aligning includes securing the chip on a hexapod via a vacuum chuck14. The method of making a photonic article of claim 11 , wherein the step of aligning includes securing the optical fiber v-groove array via vacuum15. The method of making a photonic article of claim 11 , wherein the step of aligning includes the steps of: pre-aligning the v-groove array and chip, wherein during pre-alignment, a small air gap is maintained between the chip and v-groove array; testing the pre-alignment using a light from a laser source to couple via optical fiber to the chip, and then out of the chip via optical fiber to a photodetector; and iteratively adjusting alignment from pre-alignment using feedback from the testing step.

16. The method of making a photonic article of claim 11 , wherein the solution is delivered between bonding photonic interfaces via a local structured pattern on the chip surface17. The method of making a photonic article of claim 11 , wherein the step of dispensing includes dispensing to microfluidic ports of the chip18. The method of making a photonic article of claim 11 , wherein the step of dispensing includes delivering the bonding solution to bonding surfaces directly and / or via capillary forces of the chip.

19. The method of making a photonic article of claim 11 , wherein the step of bringing the v-groove array into physical contact with the chip at a temperature elevated above ambient includes ramping chip temperature from 25°C to 40°C at 5°C / hr rate, and then soaking at 40°C for 48-168 hours, and then ramping chip temperature down to 25°C at 10°C / hr rate.

20. The method of making a photonic article of claim 11 , wherein the step of removing the photonic article from the photonic packaging assembly includes testing the photonic article to verify optical coupling between the v- groove array and the chip.

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