Method for preparing heterojunction solar cell and heterojunction solar cell

Abstract

The present invention relates to the technical field of solar cell preparation. Provided are a method for preparing a heterojunction solar cell and a heterojunction solar cell. The method for preparing a heterojunction solar cell in the present invention may comprise: providing a substrate; respectively preparing on two sides of the substrate a first passivation layer, a first doped layer and a first transparent conductive layer, and a second passivation layer, a second doped layer and a second transparent conductive layer; etching the second transparent conductive layer to form an isolation region; etching the second doped layer at a position corresponding to the isolation region; and isolating the first transparent conductive layer from the second transparent conductive layer to avoid a short circuit of a cell. The width of the isolation region in the present invention is less than 0.3 mm, and thus for a solar cell prepared by means of the preparation method, a short circuit is avoided, and an etching area of the cell is reduced as much as possible, thus making full use of a substrate area, thereby improving the cell efficiency under the same substrate area.

Description

Preparation method of heterojunction solar cell and heterojunction solar cell TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cell preparation, in particular to a preparation method of heterojunction solar cell and heterojunction solar cell. BACKGROUND

[0002] In the prior art, the manufacturing process of the heterojunction solar cell is simple, only four steps: cleaning and texturing, depositing passivation layer and doped layer on the front and back surfaces, depositing transparent conductive oxide film (TCO), and preparing electrodes. When preparing the doped layer and the TCO layer, if a mask is not used for shielding, the deposited doped layer and TCO layer material will cover the entire surface of the product. In this full-coverage preparation process, part of the material will inevitably reach the side edge of the substrate or even wrap around to the opposite side. When the materials on the two surfaces are connected together at the edge of the solar cell or the silicon wafer, a conductive condition will occur between the front and back surfaces of the solar cell, which will cause short circuit of the solar cell. In the prior art, such as patent CN114990514B, in order to prevent short circuit of the solar cell, a carrier plate is used as a mask during the preparation of the transparent conductive layer (TCO) to achieve the purpose of blocking the connection of the TCO on the front and back surfaces. The heterojunction solar cell prepared by this method has a edge area with a width of about 1-2mm around the back surface. Specifically, as shown in FIGS. 1, 2 and 3, the carrier plate has a support surface 103 and an inclined surface 104. During the preparation process, the silicon wafer is placed on the support surface 103. This part of the area cannot absorb and utilize sunlight because the TCO film is not deposited there, which affects the improvement of the efficiency of the solar cell. If a mask-free carrier plate is used for film plating to increase the use area of the solar cell, at least one edge etching process needs to be added to block the electrical properties of the front and back surfaces of the solar cell. However, in the prior art, dry etching or wet etching both have certain technical problems. For example, the laser etching in dry etching has poor etching effect on microcrystalline doping, and when wet etching is used for edge etching, considering the tolerance problem of the size of the silicon wafer in the photovoltaic industry, neither the mask plate nor the screen printing plate selected for wet etching can fully utilize the area of the silicon wafer during mass production, which leads to the problem that the final efficiency of the solar cell cannot be fully realized. SUMMARY

[0003] One object of the first aspect of the present application is to provide a preparation method of heterojunction solar cell, which solves the problem that the substrate area cannot be fully utilized in the prior art.

[0004] In particular, the present application also provides a preparation method of heterojunction solar cell, comprising:

[0005] providing a substrate;

[0006] forming a first passivation layer covering the front surface of the substrate and a first doped layer covering the first passivation layer on the front surface of the substrate, and forming a second passivation layer covering the back surface of the substrate and a second doped layer covering the second passivation layer on the back surface of the substrate;

[0007] forming a first transparent conductive layer covering the first doped layer and a second transparent conductive layer covering the second doped layer on the first doped layer and the second doped layer;

[0008] forming an isolation region on the second transparent conductive layer and the second doped layer by an etching process.

[0009] Optionally, the etching process includes a first etching process and a second etching process, the first etching process is used to etch the second transparent conductive layer to form a first isolation region, and the second etching process is used to etch the second doped layer at a position corresponding to the first isolation region to form a second isolation region; wherein the first isolation region and the second isolation region form the isolation region.

[0010] Optionally, the first etching process includes coating etching paste on the second transparent conductive layer by using a roller coating method, and etching the second transparent conductive layer by using the etching paste to form the first isolation region.

[0011] The step of coating etching paste by using the roller coating method includes:

[0012] simultaneously coating the second transparent conductive layer by using two rollers arranged oppositely; or

[0013] coating one pair of edges of the second transparent conductive layer by using two rollers arranged oppositely, and then coating another pair of edges of the second transparent conductive layer after rotating the battery piece horizontally by 90°.

[0014] Optionally, before the roller coats the etching paste on the battery piece, the method further includes:

[0015] controlling the amount of etching paste on the surface of the roller by using a scraper, so as to control the width of the etching paste coated on the second transparent conductive layer.

[0016] Optionally, the axis of the roller is inclined to one side of the plane where the battery piece is located, and the etching paste needs to be coated on the side.

[0017] Optionally, the size of the two ends of the roller is greater than the size of the middle region.

[0018] Optionally, the first etching process includes printing etching paste on the second transparent conductive layer by using a screen printing method, and the printing of etching paste specifically includes:

[0019] The etching paste is printed on the surface of the second transparent conductive layer by screen printing multiple times, and the second transparent conductive layer is etched by the etching paste to form the first isolation area.

[0020] Optionally, the first isolation area is a closed square area extending along the outer periphery of the substrate.

[0021] The etching paste is printed on the surface of the second transparent conductive layer by screen printing four times, and each printing area corresponds to the area where one side of the closed area is located; or

[0022] The etching paste is printed on the surface of the second transparent conductive layer by screen printing twice, and the first printing area corresponds to the area where two adjacent sides of the closed area are located, and the second printing area corresponds to the area where the remaining two adjacent sides are located.

[0023] Optionally, before the etching paste is printed on the second transparent conductive layer by screen printing, the method further comprises: when the second transparent conductive layer is formed, using the bearing part of the carrier plate as a mask to form a non-plating film area which is not plated with the second transparent conductive layer; wherein the non-plating film area at least partially overlaps with the area to be screen printed.

[0024] Optionally, the number of non-plating film areas is four, and each non-plating film area is located at a corner area of the substrate.

[0025] Optionally, the size of each non-plating film area in the direction parallel to the side of the closed area is a, a is greater than or equal to 0.25 mm, and a is less than half of the length of the side of the substrate.

[0026] Optionally, the shape of each non-plating film area includes L-shaped, fan-shaped, triangular or quadrilateral.

[0027] Optionally, the first etching process comprises at least one scanning of the position corresponding to the second transparent conductive layer and the first isolation area by laser etching to form the first isolation area.

[0028] Optionally, the first etching process comprises spraying etching paste on the position corresponding to the second transparent conductive layer and the first isolation area by inkjet printing, and etching the second transparent conductive layer by the etching paste to form the first isolation area.

[0029] Optionally, the second etching process comprises one of wet etching, ICP etching or CCP etching, and etching the second doped layer at the position corresponding to the first isolation area by using the second transparent conductive layer as a mask to form the second isolation area.

[0030] Optionally, the etching process is a one-step etching process, and the second transparent conductive layer and the second doped layer are etched by the one-step etching process to form the isolation region.

[0031] Optionally, the one-step etching process comprises coating the etching paste on the second transparent conductive layer by using a roller coating method, and etching the second transparent conductive layer and the second doped layer by using the etching paste to form the isolation region.

[0032] The step of coating the etching paste by using the roller coating method specifically comprises:

[0033] simultaneously coating the second transparent conductive layer by using two rollers arranged oppositely; or

[0034] coating one pair of edges of the second transparent conductive layer by using two rollers arranged oppositely, and then rotating the battery piece horizontally by 90° to coat the other pair of edges of the second transparent conductive layer.

[0035] Optionally, before the roller coats the etching paste on the battery piece, the method further comprises:

[0036] controlling the amount of the etching paste on the surface of the roller by using a scraper, so as to control the width of the etching paste coated on the second transparent conductive layer.

[0037] Optionally, the axis of the roller is inclined to the side of the battery piece where the etching paste needs to be coated.

[0038] Optionally, the size of the two ends of the roller is greater than the size of the middle region.

[0039] Optionally, the isolation region comprises a square closed region formed along the outer periphery of the substrate.

[0040] The one-step etching process comprises printing the etching paste on the surface of the second transparent conductive layer by using a screen printing method multiple times, and etching the second transparent conductive layer and the second doped layer by using the etching paste to form the isolation region.

[0041] Optionally, the etching paste is printed on the surface of the second transparent conductive layer by using the screen printing method four times, and each printing area corresponds to the region where one side of the closed region is located; or

[0042] The etching paste is printed on the surface of the second transparent conductive layer by using the screen printing method twice, and the first printing area corresponds to the region where two adjacent sides of the closed region are located, and the second printing area corresponds to the region where the remaining two adjacent sides are located.

[0043] Optionally, before the etching by screen printing, the method further comprises, when forming the second transparent conductive layer, using the bearing part of the carrier as a mask to form a non-plating area, the non-plating area at least partially overlapping the area to be screen printed.

[0044] Optionally, the number of the non-plating areas is four, and each of the non-plating areas is located at a corner region of the substrate.

[0045] Optionally, the size of each of the non-plating areas in the direction parallel to the side of the closed area is a, a is greater than or equal to 0.25 mm, and a is less than half of the length of the side of the substrate.

[0046] Optionally, the shape of each of the non-plating areas comprises an L shape, a sector shape, a triangle shape, or a quadrilateral shape.

[0047] Optionally, the width b of the isolation area is less than 0.3 mm.

[0048] Optionally, the distance c of the isolation area from the edge of the substrate is less than 0.1 mm.

[0049] In particular, the application also provides a heterojunction solar cell prepared by the above method.

[0050] The preparation method of the present application forms an isolation area on the second transparent conductive layer and the second doped layer of the heterojunction solar cell by etching, thereby separating the first transparent conductive layer and the second transparent conductive layer on the front side and the back side of the substrate to avoid short circuit. When the second transparent conductive layer is etched to form the isolation area, the width b of the separation area is less than 0.3 mm, so that the solar cell not only avoids short circuit, but also reduces the etching area as much as possible, fully utilizes the substrate area, and improves the efficiency of the solar cell under the same substrate area.

[0051] The present application etches the second doped layer at a position corresponding to the isolation area. Since the second doped layer is located below the second transparent conductive layer, the second transparent conductive layer forms an isolation area after etching, thereby allowing the second transparent conductive layer to be directly used as a mask plate for etching the second doped layer without the need for an additional mask plate, reducing the mask process and improving production efficiency. In addition, since the second transparent conductive layer is used as a mask, the etching size of the second doped layer is less than or equal to the size of the isolation area, so that the etching area of the second doped layer is smaller, thereby improving the efficiency of the solar cell.

[0052] The scheme is because the substrate has a certain tolerance in the preparation process, specifically, the tolerance range is generally about 0.25 mm. The size of the non-coating area in the direction parallel to the edge of the closed area is designed to be greater than or equal to 0.25 mm, but less than half the length of the closed area, which not only satisfies the formation of the etched closed area by the air-coating area during screen printing, but also reduces the area of the non-closed area, and improves the efficiency of the battery as much as possible.

[0053] The scheme can process the surface of the second doped layer during etching of the second transparent conductive layer, which is equivalent to that the surface of the second doped layer has been pretreated before etching, so that the etching of the second doped layer is more favorable.

[0054] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of specific embodiments thereof, when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0055] Some specific embodiments of the present application will be described in detail below with reference to the accompanying drawings, which are presented by way of illustration and not of limitation. The same reference numbers in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that the drawings are not necessarily drawn to scale. In the drawings:

[0056] FIG. 1 is a schematic structural diagram of a carrier plate in the prior art;

[0057] FIG. 2 is a partially enlarged schematic diagram of a carrier plate in the prior art;

[0058] FIG. 3 is a partial cross-sectional view of a carrier plate in the prior art;

[0059] FIG. 4 is a schematic flowchart of a preparation method of a heterojunction solar cell according to one specific embodiment of the present application;

[0060] FIG. 5 is a schematic structural diagram of a heterojunction solar cell before being etched according to one specific embodiment of the present application;

[0061] FIG. 6 is a cross-sectional view of a heterojunction solar cell after the second transparent conductive layer and the second doped layer are etched according to one specific embodiment of the present application;

[0062] FIG. 7(a) is a bottom view of a heterojunction solar cell after the second transparent conductive layer and the second doped layer are etched according to one specific embodiment of the present application;

[0063] FIG. 7(b) is a partial schematic diagram of FIG. 7(a);

[0064] FIG. 8(a) is a bottom view of a heterojunction solar cell after the second transparent conductive layer and the second doped layer are etched according to another specific embodiment of the present application;

[0065] Figure 8(b) is a partial view of Figure 8(a);

[0066] Figure 9 is a cross-sectional view of a heterojunction solar cell after etching of a second transparent conductive layer according to one embodiment of the present application;

[0067] Figure 10 is a schematic view of a roller and a doctor blade used for roller coating of an etching paste according to one embodiment of the present application;

[0068] Figure 11 is a schematic view of a roller used for roller coating of an etching paste and a solar cell according to one embodiment of the present application;

[0069] Figure 12(a) is a schematic view of a solar cell with a second transparent conductive layer coated with an etching paste and a first isolation region formed by etching of the second transparent conductive layer according to one embodiment of the present application;

[0070] Figure 12(b) is a partial view of Figure 12(a);

[0071] Figure 13 is a schematic view of a carrier plate used for forming a non-plated region according to one embodiment of the present application;

[0072] Figure 14 is a partial view of a carrier plate used for forming a non-plated region according to one embodiment of the present application;

[0073] Figure 15 is a schematic view of a solar cell with a second transparent conductive layer having a non-plated region according to one embodiment of the present application;

[0074] Figure 16(a) is a schematic view of a carrier according to one embodiment of the present application;

[0075] Figure 16(b) is a schematic view of a carrier according to another embodiment of the present application;

[0076] Figure 16(c) is a schematic view of a carrier according to yet another embodiment of the present application;

[0077] Figure 16(d) is a schematic view of a carrier according to yet another embodiment of the present application;

[0078] Figure 17(a) is a schematic view of a solar cell with a second transparent conductive layer having a non-plated region after printing of an etching paste according to yet another embodiment of the present application;

[0079] Figure 17(b) is a partial view of Figure 17(a);

[0080] BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Base-100; second passivation layer-200; first passivation layer-300; first doped layer-400; second doped layer-500; first transparent conductive layer-600; second transparent conductive layer-700; isolation region-710; first isolation region-711; second isolation region-712; non-plating area-720; roller-810; middle area-811; end-812; scraper-820; etching slurry-830; cell-900; chamfer-910;

[0082] Carrier plate-1000; carrying area-1100; carrying part-1110. DETAILED DESCRIPTION

[0083] In the description of the present embodiment, it should be understood that the terms "length", "width", "height", "upper", "lower", "left", "right", "vertical", "horizontal", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0084] As a specific embodiment of the present application, as shown in FIG. 4, the present embodiment discloses a preparation method of a heterojunction solar cell, which can include:

[0085] Step S100, providing a base 100;

[0086] Step S200, forming a first passivation layer 300 covering the front surface of the base 100 and a first doped layer 400 covering the first passivation layer 300 on the front surface of the base 100, and forming a second passivation layer 200 covering the base 100 on the back surface of the base 100 and a second doped layer 500 covering the second passivation layer 200;

[0087] Step S300, forming a first transparent conductive layer 600 covering the first doped layer 400 and a second transparent conductive layer 700 covering the second doped layer 500 on the first doped layer 400 and the second doped layer 500;

[0088] Step S400, forming an isolation region 710 on the second transparent conductive layer 700 and the second doped layer 500 by etching process.

[0089] In step S200, the first passivation layer 300 can be a single-layer structure or a multi-layer structure; similarly, the second passivation layer 200 can be a single-layer structure or a multi-layer structure, which is not limited further herein.

[0090] In step S200, the first doped layer 400 can be a single-layer structure or a multi-layer structure; similarly, the second doped layer 500 can be a single-layer structure or a multi-layer structure, which will not be further limited herein.

[0091] In step S300, the first transparent conductive layer 600 can be a single-layer structure or a multi-layer structure; similarly, the second transparent conductive layer 700 can be a single-layer structure or a multi-layer structure, which will not be further limited herein. In addition, a double-sided film plating process can be used to form the first transparent conductive layer 600 covering the first doped layer 400 and the second transparent conductive layer 700 covering the second doped layer 500 on the first doped layer 400 and the second doped layer 500, which does not need to flip the substrate, simplifying the process. Of course, a single-sided film plating process can also be used to form the first transparent conductive layer 600 covering the first doped layer 400 and the second transparent conductive layer 700 covering the second doped layer 500 on the first doped layer 400 and the second doped layer 500, respectively. It should be noted that the single-sided film plating process requires the substrate 100 to be flipped between the two transparent conductive layer film plating processes. The above belongs to a conventional process, which will not be further limited herein.

[0092] Specifically, the structure after step S300 in the embodiment is shown in FIG. 5. The structure after step S400 is shown in FIG. 6 and FIG. 7.

[0093] Specifically, in the embodiment, the lower surface in FIG. 5 and FIG. 6 is the back surface, and the upper surface in FIG. 5 and FIG. 6 is the front surface.

[0094] In addition, it should be noted that before step S400, a first electrode (not shown in the figure) can be formed on the first transparent conductive layer 600, and a second electrode (not shown in the figure) can be formed on the second transparent conductive layer 700, and then step S400 is performed to form the isolation region 710 on the second transparent conductive layer 700 and the second doped layer 500 by etching process, which will not be further described.

[0095] The preparation method of the embodiment forms the isolation region 710 on the second transparent conductive layer 700 and the second doped layer 500 of the heterojunction cell by etching process, which separates the transparent conductive film on the front surface and the back surface of the cell sheet, avoiding short circuit of the cell. When etching the second transparent conductive layer 700, the width b of the separation region is less than 0.3 mm, so that the cell can avoid short circuit and reduce the etching area as much as possible, fully utilize the light emitting area of the cell, and improve the efficiency of the cell under the same area.

[0096] Specifically, as shown in (a) of FIG. 7 and (b) of FIG. 7, in the embodiment, the width b of the partition region is less than 0.3 mm, and of course, the width b is greater than 0. Preferably, the width b of the partition region can be designed to be less than 0.1 mm, so that the area of the partition region 710 can be further reduced, and the efficiency of the battery can be improved. In one embodiment, as shown in (a) of FIG. 7 and (b) of FIG. 7, the partition region 710 is further away from the side of the substrate 100, and the partition region 710 is formed in a square shape. In another embodiment, as shown in (a) of FIG. 8 and (b) of FIG. 8, the partition region 710 is away from the side of the substrate 100. The partition region 710 directly extends along the side of the edge region of the substrate 100. When the corner of the substrate 100 has a chamfer, the partition region also extends along the chamfer. In other embodiments, the distance between the partition region 710 and the side of the substrate 100 can be 0 (see FIG. 12). When the first partition region 711 is formed at the second transparent conductive layer 700, because the width of the first partition region 711 is small (less than 0.3 mm, and preferably, less than 0.1 mm), in order to make the partition effect of the battery better, the embodiment further needs to etch the second doped layer 500 at the same position to form the second partition region 712 after the first partition region 711 is formed at the second transparent conductive layer 700.

[0097] As a specific embodiment of the present application, the etching process of the embodiment includes a first etching process and a second etching process. The first etching process is used to etch the second transparent conductive layer 700 to form the first partition region 711 (as shown in FIG. 9). The second etching process is used to etch the second doped layer 500 at the position corresponding to the first partition region 711 to form the second partition region 712 (as shown in FIG. 6). The first partition region 711 and the second partition region 712 form the partition region 710.

[0098] Specifically, in the embodiment, the first partition region 711 is obtained by etching the second transparent conductive layer 700 by the first etching process. The second partition region 712 is obtained by etching the second doped layer 500 by the second etching process. The first partition region 711 and the second partition region 712 jointly form the partition region 710. In this way, the preparation method of the embodiment can select the same or different processes according to the material characteristics of the second transparent conductive layer 700 and the second doped layer 500, so that the etching can be smoothly performed.

[0099] As a specific embodiment of the present application, as shown in FIG. 10, the first etching process can include coating the etching slurry 830 on the second transparent conductive layer 700 by using the roller 810, and etching the second transparent conductive layer 700 by using the etching slurry 830 to form the first partition region 711.

[0100] In the prior art, the battery piece is usually coated by a roller coating for double-sided coating. In the present application, the battery piece is coated by a roller for one-side etching paste coating, the battery piece is etched on one side, i.e. only the back of the battery piece is etched, to further ensure the utilization rate of the light receiving surface of the battery piece. Specifically, in the present embodiment, since the roller 810 needs to be coated with a layer of etching paste 830 on the roller 810 before coating, and then the roller 810 is contacted with the battery piece 900, so that the etching paste 830 is transferred to the edge position of one side of the battery piece 900, and then the second transparent conductive layer 700 is etched by the etching paste 830 to form a first isolation zone. Specifically, in the present embodiment, since the etching paste 830 is directly coated on the edge of the battery piece 900, the distance between the formed isolation zone and the edge of the battery piece 900 is 0.

[0101] As one of the specific embodiments of the present application, the step of coating the etching paste 830 by the roller 810 coating method in the present embodiment can include:

[0102] Two sets of two rollers 810 are arranged opposite to each other and simultaneously coated on the periphery of the second transparent conductive layer 700.

[0103] Specifically, the rollers 810 are arranged on the periphery of the silicon wafer, and the four rollers 810 simultaneously coat the etching paste 830 on the periphery of the silicon wafer.

[0104] As one of the specific embodiments of the present application, the step of coating the etching paste 830 by the roller 810 coating method in the present embodiment can include:

[0105] Two sets of two rollers 810 are arranged opposite to each other, one set of opposite edges of the second transparent conductive layer 700 is coated first, and after heat treatment, the battery piece 900 is rotated horizontally by 90°, and then the other set of opposite edges of the second transparent conductive layer 700 is coated.

[0106] In the two sets of embodiments, the etching paste 830 is finally coated on the periphery of the battery piece 900, and the etching paste 830 on the periphery is connected to form a closed shape, and finally the first transparent conductive layer and the second transparent conductive layer are separated after the second transparent conductive layer is etched.

[0107] As one of the specific embodiments of the present application, the present embodiment further includes, before the roller 810 coats the etching paste 830 for the battery piece 900:

[0108] The amount of etching paste 830 on the surface of the roller 810 is controlled by the scraper 820, and then the width of the etching paste 830 coated on the second transparent conductive layer 700 is controlled.

[0109] Specifically, before the coating of the etching slurry 830, the etching slurry 830 is coated on the roller 810, and the thickness of the etching slurry 830 on the roller 810 is controlled by the doctor blade 820 arranged on one side of the roller 810 during the continuous rotation of the roller 810. Since the roller 810 and the battery piece 900 are in contact with each other, the etching slurry 830 on the roller 810 is coated on the outer periphery of the battery piece 900, and thus the thickness of the etching slurry 830 on the roller 810 affects the width of the etching slurry 830 coated on the outer periphery of the battery piece 900. Specifically, the thickness of the etching slurry 830 on the roller 810 and the width of the etching slurry 830 coated on the battery piece 900 are in a linear relationship. Generally, the greater the thickness of the etching slurry 830 on the roller 810, the wider the width of the etching slurry 830 coated on the battery piece 900. Therefore, the thickness of the etching slurry 830 on the roller 810 can be controlled by the doctor blade 820, and thus the width of the etching slurry 830 coated on the battery piece 900 can be controlled.

[0110] As a specific embodiment of the present application, the axis of the roller 810 in the embodiment is inclined to the side of the battery piece 900 on which the etching slurry 830 needs to be coated.

[0111] Specifically, if the upper side of the battery piece 900 needs to be coated with the etching slurry 830, the axis of the roller 810 is located above the plane on which the battery piece 900 is located, and if the lower side of the battery piece 900 needs to be coated with the etching slurry 830, the axis of the roller 810 is located below the plane on which the battery piece 900 is located. That is, the plane on which the axis of the roller 810 is located is at a certain distance from the plane on which the battery piece 900 is located, and the front and back surfaces of the battery piece 900 are selected to be coated by controlling the plane on which the axis of the roller 810 is located. Of course, the position at which the battery piece 900 contacts the roller 810 also affects the thickness of the slurry coated on the battery piece 900.

[0112] More specifically, in the embodiment, the angle between the line connecting the contact point of the battery piece 900 and the axis of the roller 810 and the horizontal plane is controlled to control the amount of etching slurry coated on the side and the edge of the battery piece 900 by the roller 810, for example, the angle is between 20-70 degrees. Preferably, the angle between the line connecting the contact point of the battery piece 900 and the axis of the roller 810 and the horizontal plane is preferably 45 degrees, so as to coat the etching slurry on the back surface and the edge of the battery piece 900, and etch the transparent conductive layer on the coated area to form electrical isolation, further improve the electrical isolation effect of the first transparent conductive layer 600 and the second transparent conductive layer 700 on the front and back surfaces of the battery piece 900, and improve the battery light conversion efficiency.

[0113] Specifically, in the embodiment, the axis of the roller 810 is offset to one side of the battery piece 900, so that the etching paste 830 on the roller 810 is only coated on the side of the battery piece 900 that needs to be coated (preferably, the back of the battery piece is coated with the etching paste), ensuring that the other side (the front of the battery piece) is not coated with the etching paste 830, further ensuring the light-receiving area of the front of the solar cell and improving the photoelectric conversion efficiency of the battery piece.

[0114] As a specific embodiment of the present application, as shown in FIG. 11, the battery piece 900 of the embodiment is provided with a chamfer 910, and the two ends of the roller 810 are provided in a shape matching the shape of the chamfer 910.

[0115] Specifically, in the embodiment, the chamfer 910 is provided around the battery piece 900 mainly to eliminate the sharp edges and corners of the silicon wafer, reduce stress concentration and dislocation, and thus reduce the mechanical damage and cracking risk of the silicon wafer. However, due to the presence of the chamfer 910, the roller 810 may not be able to coat the etching paste 830 at the chamfer 910 when coating the etching paste 830. Therefore, in the embodiment, the two ends of the roller 810 are provided in a shape matching the shape of the chamfer 910, so that the etching paste 830 can also be coated at the chamfer 910, and thus the entire battery piece 900 can be coated with the etching paste 830, and a closed isolation region is subsequently formed.

[0116] Specifically, the size of the two ends of the roller 810 is greater than the size of the middle region 811, and gradually increases from the middle region 811 to the end 812.

[0117] Specifically, since the battery piece 900 of the embodiment is provided with the chamfer 910 around the entire battery piece 900, the chamfer 910 can be a bevel or an arc surface, regardless of the form, the size of the chamfer 910 is smaller than the size of other parts. Therefore, in the embodiment, the size of the two ends of the roller 810 is greater than the size of the middle region 811, and gradually increases from the middle region 811 to the end 812, so that the etching paste 830 can also be coated at the chamfer 910 of the battery piece 900. Finally, the battery piece 900 coated with the etching paste is dried and fully reacted to remove the TCO in the area covered by the etching paste 830, exposing the second doped layer 500, and the schematic diagram of the bottom view of the battery piece after etching of the second transparent conductive layer 700 is shown in (a) of FIG. 12 and (b) of FIG. 12.

[0118] In addition, the structure of the roller can be profiled according to the shape of the silicon wafer. For a silicon wafer without chamfer, the corresponding roller structure can be linear. For a silicon wafer with chamfer, the size of the roller in the chamfer region is greater than the size of the roller in other regions. Therefore, the structures of the symmetrically arranged group of rollers can be the same or different.

[0119] As a specific embodiment of the present application, the first etching process comprises printing the etching paste on the second transparent conductive layer 700 by means of screen printing, and the printed etching paste specifically comprises:

[0120] The etching paste is printed on the surface of the second transparent conductive layer 700 by means of screen printing for multiple times, and the second transparent conductive layer 700 is etched by the etching paste to form the first isolation region 711.

[0121] In the embodiment, the isolation region 710 is formed on the second transparent conductive layer 700 by means of screen printing, without the need of masking the edges of the battery piece, and the isolation region 710 with a small size (width b less than 0.3 mm) can be formed, so as to maximize the efficiency of the battery.

[0122] Specifically, the specific steps of etching by means of screen printing in the embodiment can be as follows: the battery piece is placed on a printing table, a vacuum chuck is used to fix the silicon piece, a digital camera is used to take a photo to determine the actual edge position of the battery piece, and the signal is converted into a digital signal, and then the position and angle of the screen plate are adjusted so that the longest distance between the printed adhesive and the edge of the battery piece is less than 0.1 mm. Finally, the distance c between the edge of the isolation region 710 and the edge of the entire battery is less than 0.1 mm.

[0123] Specifically, since the isolation region 710 of the embodiment can be located on the front surface of the battery or on the back surface of the battery piece, the first transparent conductive layer 600 located on the front surface of the battery and the second transparent conductive layer 700 located on the back surface of the battery are electrically disconnected, thereby avoiding short circuit of the battery. Therefore, the isolation region 710 has various forms. In the embodiment, the isolation region 710 is preferably arranged at the second transparent conductive layer 700 and the second doped layer 500, and the distance c between the edge of the isolation region 710 and the edge of the battery is less than 0.1 mm, so as to maximize the efficiency of the battery.

[0124] More specifically, the first isolation region 711 of the embodiment is a square closed region extending along the outer periphery of the substrate 100.

[0125] As one of the embodiments, the step of printing the etching paste on the surface of the second transparent conductive layer 700 by means of screen printing for multiple times can be as follows: the etching paste is printed on the surface of the second transparent conductive layer 700 by means of screen printing for four times, and each time of printing corresponds to the region where one side of the closed region is located.

[0126] When the first isolation region 711 is formed by means of four times of printing, one side of the closed region is printed each time. In the embodiment, the four times of printing can make the printing more accurate, but the time spent on printing is longer in this way.

[0127] As another specific embodiment, the step of printing the second transparent conductive layer 700 multiple times by using the screen printing method can be: printing the etching paste on the surface of the second transparent conductive layer 700 twice by using the screen printing method, the first printing area corresponding to the area where two adjacent sides of the closed area are located, and the second printing area corresponding to the area where the remaining two adjacent sides are located.

[0128] In this embodiment, the number of times of printing the etching paste on the back of the second transparent conductive layer 700 by using the screen printing method is twice, and the two adjacent sides of the closed area are printed first, and then the remaining two adjacent sides are printed. In this way, the printing time can be reduced while ensuring the printing accuracy.

[0129] In this embodiment, since the screen printing needs to be accurate in printing the area, the silicon wafer needs to be calibrated, and at most one adjacent side of the silicon wafer can be calibrated at a time during the calibration process. Therefore, at most one adjacent side can be printed at a time in this embodiment. Therefore, when the second transparent conductive layer 700 is etched by using the screen printing method, at least two times of printing are required to complete the entire process.

[0130] In the above embodiment, the closed area of the first isolation area 711 is formed by etching the second transparent conductive layer 700.

[0131] In the above embodiment, in an ideal case, the end portions of the etching paste printed on the edges of the battery piece overlap with each other during the process of screen printing the etching paste, thereby forming a closed area (as shown in FIG. 7), and the TCO layer and / or the doped layer at the edge portion are cut off by using the etching paste. However, due to the tolerance problem of the size of the silicon wafer in the photovoltaic industry, although the camera is used to take a picture before screen printing to make the printing position more accurate, there can still be a printing deviation, thereby making the etching paste printed on the edge of the battery piece unable to form a closed area, resulting in the case that the back TCO layer is not completely cut off.

[0132] Based on the above situation, preferably, as a specific embodiment of the present application, the embodiment further comprises: when the second transparent conductive layer 700 is formed, using the bearing part of the carrier plate 1000 as a mask to form a non-plating film area 720 where the second transparent conductive layer 700 is not plated, before the etching paste is printed on the second transparent conductive layer 700 by using the screen printing method; wherein the non-plating film area 720 at least partially overlaps with the area to be printed with the etching paste.

[0133] Specifically, the step of forming the non-plating area 720 can be that after the second doped layer 500 is prepared, the back surface of the product is regionally masked by the carrier plate 1000, and then the first transparent conductive layer 600 and the second transparent conductive layer 700 are prepared, and then the non-plating area 720 is formed at the second transparent conductive layer 700. In this embodiment, the shape of the contact surface of the mask carrier plate 1000 matches the shape of the non-plating area 720. Specifically, as shown in FIGS. 13 and 14, the carrier plate 1000 of this embodiment can include a plurality of bearing areas 1100 for placing the substrate, and in this embodiment, one carrier plate 1000 includes 24 bearing areas 1100. Four corners of each bearing area 1100 are formed with a bearing part 1110, and the four corners of the substrate 100 are placed at the bearing part 1110, and then the product is deposited with the first transparent conductive layer 600 and the second transparent conductive layer 700, and finally the first transparent conductive layer 600 is formed on the front surface and the product with the non-plating area 720 is formed on the back surface (as shown in FIG. 15). Generally, the four corners of the silicon wafer are provided with a chamfer 910, and the size of the bearing part 1110 in this embodiment is larger than the chamfer, so that the four corners of the silicon wafer can be placed at the bearing part 1110, and the size of the non-plating area 720 formed is also larger than the chamfer, which can be basically ignored. The following will be described in detail taking the silicon wafer without chamfer around as an example.

[0134] Specifically, the size of the non-plating area 720 in the direction parallel to the edge of the closed area in this embodiment is a, wherein a is greater than or equal to 0.25 mm, and a is less than half of the length of the edge of the substrate 100.

[0135] Specifically, in this embodiment, due to the tolerance problem of the size of the silicon wafer in the photovoltaic industry, specifically, the tolerance range is generally about 0.25 mm. The size of the non-plating area 720 in the direction parallel to the edge of the closed area is designed to be greater than or equal to 0.25 mm, but less than half of the length of the edge of the closed area, which not only meets the requirement of forming the etched closed area by screen printing through the plating area, but also reduces the area of the non-closed area, and improves the efficiency of the battery as much as possible.

[0136] Preferably, the size a of the non-plating area 720 in the direction parallel to the length of the edge of the closed area in this embodiment is designed to be 0.25 mm. In this way, the area of the non-closed area can be reduced as much as possible, so that the efficiency of the battery is higher under the premise of meeting the etching requirement.

[0137] As a specific embodiment of the present application, the shape of the bearing part 1110 corresponding to each corner of the battery piece can include a triangle (as shown in (a) of FIG. 16), an L shape (as shown in (b) of FIG. 16), a quadrilateral (as shown in (c) of FIG. 16) or a sector (as shown in (d) of FIG. 16).

[0138] Specifically, since the substrate 100 is generally a whole or half piece, the number of non-plating areas 720 is generally four, and the shape of each non-plating area 720 can be the same or different. Specifically, the shape of each non-plating area 720 can be selected from an L shape, a fan shape, a triangular shape, or a quadrilateral shape.

[0139] When the four non-plating areas 720 are all quadrilaterals, it is preferred that the shape of the non-plating area 720 can be a square, as shown in (c) of FIG. 16, and the side length of each non-plating area 720 can be 0.25 mm. Of course, when the non-plating area 720 is an L shape, as shown in (b) of FIG. 16, the size in the direction parallel to the side length of the closed area can be 0.25 mm. In addition, the width of the L can be greater than or equal to 0.1 mm and less than 0.25 mm. In this way, the non-plating area 720 in the L shape has a smaller area than the square non-plating area 720, so that the area of the final isolation area 710 is correspondingly smaller, and thus the efficiency of the final battery is also higher.

[0140] Alternatively, the shape of the non-plating area 720 of the present embodiment can also be selected from a fan shape or a triangular shape, etc., as shown in (a) of FIG. 16 and (d) of FIG. 16. Of course, other arbitrary shapes that can meet the requirements can also be selected. However, regardless of the shape of the non-plating area 720, the size a in the direction parallel to the side of the isolation area 710 needs to be greater than or equal to 0.25 mm.

[0141] More specifically, after forming the non-plating area on the second transparent conductive layer 700, the etching paste is printed on the second transparent conductive layer 700 by screen printing (as shown in FIG. 17). Due to the presence of the non-plating area 720, the etching paste is printed according to the minimum value. Considering the maximum tolerance of the silicon wafer, the etching paste can always pass through the non-plating area 720, and thus the first isolation area 711 formed on the second transparent conductive layer 700 can electrically disconnect the first transparent conductive layer 600 and the second transparent conductive layer 700. The drawings after printing the etching paste on the second transparent conductive layer 700 where the non-plating area 720 is formed are shown in (a) of FIG. 17 and (b) of FIG. 17.

[0142] When the etching paste is printed on the second transparent conductive layer 700 by screen printing in the present embodiment, the width of the printing can be 10-300 μm, and the width is preferably less than 0.1 mm. The length of the printing can be the side length of the substrate 100 minus 0.25 mm. In this way, it can be ensured that after the etching paste etches the second transparent conductive layer 700, the area etched by the etching paste is in communication with the non-plating area 720, so that the isolation area 710 in a closed shape is formed.

[0143] In the above embodiment, the closed area of the first isolation region 711 is composed of the area formed by etching the second transparent conductive layer 700 and the non-coating area 720.

[0144] Compared with the mask carrier plate in the prior art, the above carrier plate is used to perform double-sided simultaneous deposition of the transparent conductive layer on the battery piece, and the isolation region is formed by etching process, so that the positive and back surface electrical isolation effect is achieved, which reduces the area of the mask shielding, that is, the light conversion area of the battery which is fully used. In addition, compared with the full-area battery piece formed by depositing the transparent conductive layer on the single surface in the prior art, the isolation region is formed by the single surface etching process in the present application, so that the positive and back surface electrical isolation effect is achieved, and the number of piece turning is reduced, and the process cycle is shortened.

[0145] As another specific embodiment of the present application, the step of etching the second transparent conductive layer 700 to form the first isolation region 711 in the present embodiment can further include:

[0146] The laser etching method is used to perform at least one scanning on the position of the second transparent conductive layer 700 corresponding to the isolation region 710 to form the first isolation region 711 (as shown in FIG. 8).

[0147] When the laser etching method is generally used, the solar cell silicon base film layer will be damaged due to excessive laser energy, and the solar cell efficiency will be reduced. In the present embodiment, the multiple scanning etching method is used when the laser etching is used, so that the purpose of etching is achieved while the damage to the silicon base film layer is avoided.

[0148] As another specific embodiment of the present application, the step of etching the second transparent conductive layer 700 to form the first isolation region 711 in the present embodiment can further include:

[0149] The inkjet printing method is used to spray etching paste on the position of the second transparent conductive layer 700 corresponding to the isolation region 710, and the etching paste is used to etch the second transparent conductive layer 700 to form the first isolation region 711.

[0150] In the above three etching methods of the second transparent conductive layer 700, the second transparent conductive layer 700 in the area to be etched is completely etched, and at the same time, the surface of the second doped layer 500 is treated, for example, the etching paste is heat treated or the second doped layer 500 is pretreated in the laser etching process, which is equivalent to that the surface of the second doped layer 500 has been pretreated before etching, so that the etching of the second doped layer 500 is more favorable in the second etching process.

[0151] As another specific embodiment of the present application, the step S400 of etching the second doped layer 500 at the position corresponding to the isolation region 710 in the present embodiment can include:

[0152] The second doped layer 500 is etched at a position corresponding to the isolation region 710 by one of an acid etching method, an alkali etching method, an ICP etching method, or a CCP etching method.

[0153] In the embodiment, the second doped layer 500 is etched at a position corresponding to the first isolation region 711. Since the second doped layer 500 is located below the second transparent conductive layer 700, the second transparent conductive layer 700 forms the first isolation region 711 after etching, so that the second transparent conductive layer 700 can be directly used as a mask plate for etching the second doped layer 500 without an additional mask plate, reducing the mask process and improving the production efficiency. In addition, since the second transparent conductive layer 700 is used as a mask plate, the size of the etching of the second doped layer 500 is less than or equal to the size of the first isolation region 711, so that the etching area of the second doped layer 500 is smaller, improving the battery efficiency.

[0154] As another specific embodiment of the present application, the etching process in the embodiment is a one-step etching process. The second transparent conductive layer 700 and the second doped layer 500 are etched by the one-step etching process to form the isolation region 710.

[0155] Specifically, in the embodiment, the one-step etching process is directly used to etch the second transparent conductive layer 700 and the second doped layer 500 to obtain the isolation region 710, so that the battery is separated on both sides to prevent short circuit of the battery.

[0156] In the embodiment, the one-step etching process is a screen printing method directly used to etch the second transparent conductive layer 700 and the second doped layer 500 to form the isolation region 710. Compared with the two-step etching process, the one-step etching process for forming the isolation region 710 reduces the process steps, reduces the pollution and damage of the product during the transfer process, and improves the quality.

[0157] Specifically, in the embodiment, the one-step etching process includes a roller 810 coating method for coating the etching slurry 830 on the second transparent conductive layer 700, and the etching slurry 830 is used to etch the second transparent conductive layer 700 and the second doped layer 500 to form the isolation region 710.

[0158] The step of using the roller 810 to coat in the one-step etching process is the same as the step of using the roller 810 to coat in the first etching process, except that the etching slurry 830 used in the one-step etching process can etch both the second transparent conductive layer 700 and the second doped layer 500. The etching slurry 830 used in the first etching process can only etch the second transparent conductive layer 700, and cannot etch the second doped layer 500. The step of using the roller 810 to coat is described above, and will not be repeated here.

[0159] As another specific embodiment of the present application, the one-step etching process of the present embodiment can also include using a screen printing method to print the etching slurry on the surface of the second transparent conductive layer 700 multiple times, and using the etching slurry to etch the second transparent conductive layer 700 and the second doped layer 500 to form the isolation region 710. The step of using the screen printing method in the one-step etching process is different from the step of using the screen printing method to etch the second transparent conductive layer 700 in the first etching process. In the one-step etching process, the screen-printed etching slurry can etch both the second transparent conductive layer 700 and the second doped layer 500. In the first etching process, the amount and parameters of the screen-printed etching slurry can be set so that the etching slurry can only etch the second transparent conductive layer 700, and cannot etch the second doped layer 500.

[0160] Specifically, the present application also provides a heterojunction solar cell, which can be prepared by the above preparation method. The area utilization of the silicon wafer in the solar cell is increased, and the photoelectric conversion efficiency is improved.

[0161] Embodiment 1

[0162] The preparation steps of the solar cell without etching include:

[0163] In step S210, an n-type single crystal silicon wafer is provided, the back surface of the n-type single crystal silicon wafer is upward, and the n-type single crystal silicon wafer is placed on a PECVD carrier plate. Then, the PECVD carrier plate with the silicon wafer is brought into a PECVD cavity. A second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200) is deposited on the back surface of the n-type single crystal silicon wafer by a chemical vapor deposition method. Due to the phenomenon of around-plating during chemical vapor deposition, the side edges of the silicon wafer are also deposited with a second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200).

[0164] Step S220, the sample obtained in step S210 is turned over so that the front side of the sample faces upward, and is placed in a PECVD carrier plate, and then the sample is taken into a PECVD cavity together with the PECVD carrier plate, so as to deposit a first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and an n-type amorphous or microcrystalline layer (first doped layer 400) on the front side of the n-type monocrystalline silicon wafer. Similarly, in this process, the side edges of the silicon wafer will also deposit the first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and the n-type amorphous or microcrystalline layer (first doped layer 400).

[0165] Step S230, the sample obtained in step S220 is turned over so that the back side of the sample faces upward, and is placed in a PECVD carrier plate, and then the sample is taken into a PECVD cavity together with the PECVD carrier plate, so as to deposit a p-type amorphous or microcrystalline layer (second doped layer 500) on the first passivation layer 300 on the back side of the n-type monocrystalline silicon wafer; similarly, in this process, the side edges of the first passivation layer 300 will also deposit the p-type amorphous or microcrystalline layer.

[0166] In the film plating process, due to the fact that the diffusion coefficient of boron is higher than that of phosphorus, considering the pollution problem caused by the film plating process doping of the n-type amorphous or microcrystalline layer and the p-type amorphous or microcrystalline layer, and the number of film plating flip pieces, the process of the p-type amorphous or microcrystalline layer is arranged at the last in the present application, thereby improving the light conversion efficiency of the battery piece.

[0167] In the deposition process of the first intrinsic amorphous or microcrystalline silicon passivation layer (first passivation layer 300) and the second intrinsic amorphous or microcrystalline silicon passivation layer (second passivation layer 200), the power supply power is 550 W, the gas flow ratio of hydrogen to silane (hydrogen dilution ratio) is 12:1, the pressure is 70 Pa, and the substrate temperature during deposition is 220℃.

[0168] In the deposition process of the n-type amorphous or microcrystalline layer (first doped layer 400), the power supply power is 400 W, the gas flow ratio of hydrogen to silane (hydrogen dilution ratio) is 4:1, the gas flow ratio of phosphine to silane (phosphorus to silicon ratio) is 1:100, the pressure is 40 Pa, and the substrate temperature during deposition is 210℃.

[0169] In the deposition process of the p-type amorphous or microcrystalline silicon layer (second doped layer 500), the power supply power is 500 W, the gas flow ratio of hydrogen to silane (hydrogen dilution ratio) is 5:1, the gas flow ratio of TMB to silane is 3:97, the pressure is 30 Pa, and the substrate temperature during deposition is 180℃.

[0170] Step S240, the sample obtained in step S230 is placed face up, and the sample is taken into a PVD magnetron sputtering device together with a carrier plate, and TCO (transparent conductive layer) is deposited. A first transparent conductive layer 600 is deposited on the n-type amorphous or microcrystalline layer (first doped layer 400), and a second transparent conductive layer 700 is deposited on the p-type amorphous or microcrystalline silicon layer (second doped layer 500). Similarly, the side edges of the sample are also coated with the first transparent conductive layer 600 and the second transparent conductive layer 700.

[0171] The conditions for depositing the TCO are: room temperature, argon and oxygen are introduced, the gas flow ratio of argon to oxygen is set to 50:1, the cavity pressure is kept at 0.7 Pa, and the transparent conductive material is ITO material or other non-indium-based TCO material, such as tin oxide-based TCO.

[0172] Specifically, the substrate 100 of the solar cell prepared by the above preparation method can be an n-type monocrystalline silicon wafer, and the thickness of the silicon wafer can be 110-180 μm. The first passivation layer 300 and the second passivation layer 200 can be intrinsic amorphous or microcrystalline silicon passivation layers. The thickness of the first passivation layer 300 and the second passivation layer 200 can be 7 nm. The first doped layer 400 can be an n-type amorphous or microcrystalline layer, and the thickness of the first doped layer 400 can be 30 nm. The second doped layer 500 can be a p-type amorphous or microcrystalline layer, and the thickness can be 35 nm. The thickness of the first transparent conductive layer 600 and the second transparent conductive layer 700 can be 80 nm.

[0173] In this process, since the side edges are deposited with the corresponding material when each film layer is deposited, there will be a conductive condition between the front and back surfaces of the silicon wafer.

[0174] Then, the second transparent conductive layer 700 and the second doped layer 500 are etched by an etching process to form an isolation area 710 on the back surface of the cell wafer, and the first transparent conductive layer 600 and the second transparent conductive layer 700 are electrically isolated.

[0175] Example 2

[0176] The steps S210 to S240 in this embodiment are consistent with those of Example 1, and after step S240, the following steps are further included:

[0177] The cell wafer 900 prepared in step S240 is positioned and then transported to the roller 810 coating station. The roller 810 is controlled to move to contact the outer periphery of the cell wafer 900, and then the etching slurry 830 is coated on the outer periphery of the cell wafer 900.

[0178] Specifically, two sets of two rollers 810 are arranged opposite to each other and simultaneously coated on the periphery of the second transparent conductive layer 700, and the specific steps include:

[0179] Four rollers 810 are arranged at four sides of the roller coating station respectively, and each roller 810 is matched with a doctor blade 820, which is used to control the thickness of the etching paste 830 at the corresponding roller 810. The positioned battery piece 900 is transported to the roller coating station, and the four rollers 810 are controlled to move to the four sides of the battery piece 900 and closely contact the battery piece 900, so as to coat the etching paste 830 at the edge position of the battery piece 900. After coating, drying and sufficient reaction are performed, the TCO in the covered area of the etching paste 830 is removed, and the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is exposed.

[0180] Alternatively, specifically, a pair of oppositely arranged rollers 810 are used to coat the second transparent conductive layer 700, and the specific steps include:

[0181] The thickness of the etching paste 830 at the corresponding roller 810 is controlled by the doctor blade 820, the positioned battery piece 900 is transported to the roller coating station, and the two rollers 810 are controlled to move to the pair of oppositely arranged side edges of the battery piece 900 to coat a group of opposite edges of the second transparent conductive layer 700. After heat treatment, the battery piece 900 is rotated horizontally by 90°, and the other group of opposite edges of the second transparent conductive layer 700 is coated. After coating, drying and sufficient reaction are performed, the TCO in the covered area of the etching paste 830 is removed, and the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is exposed.

[0182] In the embodiment, the carrier plate related to the present application can also be used to simultaneously deposit transparent conductive layers on both sides. The side of the battery piece to be coated with the etching paste is on the same side as the supporting surface of the carrier plate, that is, only the back surface of the battery piece is etched to form an isolation area, so as to ensure the use area of the front light-receiving surface of the battery piece and improve the photoelectric conversion efficiency.

[0183] Embodiment 3

[0184] Due to the tolerance problem of the size of the silicon wafer in the photovoltaic industry, only the size of the screen printing plate in screen printing can be set according to the minimum size, which will cause that the etching paste cannot form a closed etching area after being printed on the silicon wafer with a large size, and thus the front and back surfaces of the battery piece cannot be electrically isolated.

[0185] Before the second transparent conductive layer 700 is etched by using the screen printing method in the embodiment, the non-plating film area 720 needs to be formed first. Therefore, in the steps of preparing the solar cell in the embodiment, the steps S210, S220 and S230 are consistent with those in Embodiment 1, and after the step S230, the steps further include:

[0186] The sample prepared in step S230 is placed on the carrier plate 1000 with the front face upward, and the four corners of the sample are supported by the bearing part 1110 of the carrier plate 1000, the mask width (i.e., the dimension parallel to the edge of the sample) is 0.25 mm, and the sample is taken into the PVD magnetron sputtering device together with the carrier plate 1000 to deposit the TCO. The first transparent conductive layer 600 is deposited on the n-type amorphous or microcrystalline layer (the first doped layer 400) and the side edge of the silicon wafer, and the second transparent conductive layer 700 is deposited on the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) and the side edge of the silicon wafer. The conditions for depositing the TCO are: room temperature, argon and oxygen are introduced, the gas flow ratio of argon to oxygen is set to 50:1, the cavity pressure is kept at 0.7 Pa, and the transparent conductive material is ITO material or other non-indium-based TCO material, such as tin oxide-based TCO.

[0187] The steps of etching the second transparent conductive layer 700 by four-step screen printing include:

[0188] The back of the sample after the non-sputtering area mask is formed on the sample is placed on the sample conveying belt of the screen printing equipment, the sample is placed on the first sample table for screen printing, the camera takes a picture, the screen printing screen is adjusted, and the etching paste for etching TCO is printed on the second transparent conductive layer 700 on the back of the sample. For example, the etching paste printed pattern is a rectangle, the length is the standard length of the A edge of the silicon wafer minus 0.25 mm, and the width is 10 microns to 300 microns. Then repeat the above steps to complete the printing in turn on the BCD edge. After printing, drying and sufficient reaction are performed to remove the TCO in the area covered by the paste, and the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) is exposed.

[0189] The steps of etching the second transparent conductive layer 700 by two-step screen printing include:

[0190] The back of the sample after the non-sputtering area mask is formed on the sample is placed on the sample conveying belt of the screen printing equipment, the sample is placed on the first sample table for screen printing, the camera takes a picture, the screen printing screen is adjusted, and the etching paste for etching TCO is printed on the second transparent conductive layer 700 on the back of the sample. For example, the etching paste printed pattern is a rectangle, the length is the standard length of the A edge of the silicon wafer minus 0.25 mm, and the width is 10 microns to 300 microns. Then repeat the above steps to complete the printing in turn on the BCD edge. After printing, drying and sufficient reaction are performed to remove the TCO in the area covered by the paste, and the p-type amorphous or microcrystalline silicon layer (the second doped layer 500) is exposed.

[0191] Based on the above scheme, due to the existence of the non-coating area 720, no matter how many times the printing etching paste is printed, the size of the isolation area 710 can be supplemented by the non-coating area 720, so as to ensure that the first transparent conductive layer 600 on the front surface and the second transparent conductive layer 700 on the back surface are completely electrically isolated after etching the etching paste.

[0192] Embodiment 4

[0193] The steps of preparing the solar cell are consistent with those of Embodiment 1, but in this embodiment, the etching of the second transparent conductive layer 700 is performed by using a laser. In this embodiment, the isolation area can be formed by etching the second transparent conductive layer 700 first, and then electrodes are formed on the first transparent conductive layer 600 and the second transparent conductive layer 700. Alternatively, the electrodes can be formed on the first transparent conductive layer 600 and the second transparent conductive layer 700, and then the isolation area is formed by etching the second transparent conductive layer 700. The specific process can be adjusted according to requirements, and will not be described further herein.

[0194] Specifically, the step of etching the second transparent conductive layer 700 by using a laser in this embodiment includes:

[0195] Pre-cleaning: the sample prepared in Embodiment 1 is cleaned by passing through a brush on a CV conveyor;

[0196] Visual positioning: the sample is coarsely positioned by clamping on the CV conveyor, and then the product is transferred to a marking area by a swing arm or a linear motor, and is finely positioned by multiple cameras;

[0197] Laser etching: ion air knives are used to blow air, and dust generated by laser etching is removed by dust extraction;

[0198] Post-cleaning: after etching is completed, the sample is transferred to the CV by the swing arm or the linear motor, and is cleaned by an ultrasonic dust removal device during the CV conveying process;

[0199] Defect detection: the cleaned sample is subjected to IV test efficiency and IR leakage detection.

[0200] In this embodiment, the wavelength of the laser can be 193 nm to 355 nm. The power can be 0.5 W to 30 W. The size and shape of the light plate can be 20 μm to 100 μm in circular or square shape. The frequency can be 500 KHZ to 20 MHZ. The scanning speed can be 2000 ㎜ / s to 60000 ㎜ / s. The pulse width can be femtosecond or picosecond level. In the laser etching of this embodiment, DOE shaping is involved, and the spot size and shape can be customized, and the spot uniformity is ≥95%. The laser scanning accuracy is ±15 μm, and the edge etching line width is ≤100 μm.

[0201] Embodiment 5

[0202] The first several steps in the process of preparing the solar cell are consistent with those of Example 1. In the etching of the second transparent conductive layer 700, an inkjet printing method is used. The inkjet printing etching paste is printed on the second transparent conductive layer 700, and then dried and fully reacted to remove the TCO in the area covered by the etching paste, exposing the p-type amorphous or microcrystalline silicon layer (second doped layer 500).

[0203] Example 6

[0204] After the second transparent conductive layer 700 is etched using the methods in Examples 2, 3, 4, and 5, acid etching or alkali etching is used to etch the second doped layer 500. The specific steps can include:

[0205] The sample in which the second transparent conductive layer 700 is etched and the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is exposed in Examples 2, 3, 4, and 5 is placed in an alkaline etching solution. The alkaline etching solution contains potassium hydroxide or sodium hydroxide, and the mass fraction of the solution is 1% to 20%. The solution temperature is room temperature to 80°C, the reaction time is 1s to 5min, and the etching speed is controlled to be 1 to 30nm / s.

[0206] In another embodiment, the sample in which the edge TCO is removed and the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is exposed is placed in an acid etching solution. The acid etching solution contains hydrofluoric acid and a deboron additive, and the solution temperature is room temperature to 60°C. The reaction time is 1s to 5min, and the etching speed is controlled to be 1 to 30nm / s.

[0207] In the above-mentioned acid etching or alkali etching steps, the process parameters need to be accurately controlled to ensure that the exposed second doped layer 500 is etched cleanly, while the second doped layer 500 in other areas is preserved and the second passivation layer 200 is not damaged.

[0208] In this embodiment, after the second transparent conductive layer 700 is etched in Examples 2, 3, 4, or 5, the second first isolation region 711 is etched. During the process of using the steps of Examples 2, 3, or 4, the surface of the second doped layer 500 is pretreated, and the etching efficiency of the second doped layer 500 can be improved in the second etching process.

[0209] Example 7

[0210] After the second transparent conductive layer 700 is etched using the methods in Examples 2, 3, 4, or 5, and the second transparent conductive layer 700 is used as a mask, ICP or CCP technology is used to etch the p-type amorphous or microcrystalline silicon layer (second doped layer 500). The specific steps include:

[0211] The sample of the second transparent conductive layer 700 obtained by the steps of Example 2, Example 3, Example 4 or Example 5 after etching is placed in a carrier plate and transferred into a chamber with one or more reaction gases of SF6, NF3, CF4, and argon gas is introduced to maintain the chamber pressure, the chamber pressure is maintained at 0.01-1T, the power is 100W-2000W, and the etching thickness of the p-type amorphous or microcrystalline silicon layer (second doped layer 500) is precisely controlled by different times. After the etching process is completed, the sample is transferred out for scribing.

[0212] The step of removing the second doped layer 500 by the above ICP or CCP process needs to precisely control the process parameters to ensure that the exposed p-type amorphous or microcrystalline silicon layer (second doped layer 500) is etched clean, but at the same time the second doped layer 500 in other areas is retained, and there is no damage to the second passivation layer 200.

[0213] In this embodiment, since the second transparent conductive layer 700 is etched after the second first isolation region 711 in Example 2, 3, 4 or 5, the surface of the second doped layer 500 is pretreated during the process of the steps of Example 2, 3, 4 or 5, and the etching efficiency of the second doped layer 500 can be improved in the second etching process.

[0214] Example 8

[0215] The steps in this embodiment are consistent with those in Example 2, and the difference is that in this embodiment, the etching paste etches both the second transparent conductive layer 700 and the second doped layer 500 to form the isolation region 710 after the etching paste is coated on the second transparent conductive layer 700 by the roll coating process in a one-step etching process. There is no need for subsequent etching steps of the second doped layer 500. The one-step etching of the second transparent conductive layer 700 and the second doped layer 500 to obtain the isolation region 710 can reduce the etching process steps, reduce the damage and pollution to the product during the transfer of the product, and improve the quality.

[0216] Example 9

[0217] The steps in this embodiment are consistent with those in Example 3, and the difference is that in this embodiment, the etching paste etches both the second transparent conductive layer 700 and the second doped layer 500 to form the isolation region 710 after the etching paste is screen printed on the second transparent conductive layer 700 by the screen printing method in a one-step etching process. There is no need for subsequent etching steps of the second doped layer 500. The one-step etching of the second transparent conductive layer 700 and the second doped layer 500 to obtain the isolation region 710 can reduce the etching process steps, reduce the damage and pollution to the product during the transfer of the product, and improve the quality.

[0218] At this point, those skilled in the art will appreciate that although specific exemplary embodiments of the application have been described herein, the present application also encompasses many other variations or modifications in accordance with the principles of the application as set forth above. Accordingly, the scope of the present application should be understood to include all such variations and modifications.

Claims

1. A method for producing a heterojunction solar cell, characterized by, The method comprises the following steps: providing a substrate; forming a first passivation layer covering the front surface of the substrate and a first doped layer covering the first passivation layer on the front surface of the substrate, and forming a second passivation layer covering the back surface of the substrate and a second doped layer covering the second passivation layer on the back surface of the substrate; forming a first transparent conductive layer covering the first doped layer and a second transparent conductive layer covering the second doped layer on the first doped layer and the second doped layer; forming an isolation region on the second transparent conductive layer and the second doped layer by an etching process.

2. The method according to claim 1, wherein the etching process comprises a first etching process and a second etching process, the first etching process is used to etch the second transparent conductive layer to form a first isolation region, and the second etching process is used to etch the second doped layer at a position corresponding to the first isolation region to form a second isolation region, wherein the first isolation region and the second isolation region form the isolation region. the first etching process comprises coating etching paste on the second transparent conductive layer by using a roller coating method, and etching the second transparent conductive layer by using the etching paste to form the first isolation region.

3. The method of producing a heterojunction solar cell according to claim 2, wherein the step of coating etching paste by using the roller coating method comprises: simultaneously coating the second transparent conductive layer around by using two rollers arranged oppositely; or coating one pair of edges of the second transparent conductive layer by using two rollers arranged oppositely, and then coating the other pair of edges of the second transparent conductive layer after rotating the cell by 90°.

4. The method according to claim 3, wherein before the roller is used to coat etching paste on the cell, the method further comprises: controlling the amount of etching paste on the surface of the roller by using a scraper, so as to control the width of the etching paste coated on the second transparent conductive layer.

5. The method according to claim 3, wherein the axis of the roller is inclined to the side of the cell plane where the etching paste is needed to be coated.

6. The method according to claim 3, wherein the size of the two ends of the roller is greater than the size of the middle region.

7. The method according to claim 2, wherein the first etching process comprises printing etching paste on the second transparent conductive layer by using a screen printing method, and the printing of etching paste specifically comprises: printing etching paste on the surface of the second transparent conductive layer by using the screen printing method for multiple times, and etching the second transparent conductive layer by using the etching paste to form the first isolation region.

8. The method according to claim 7, wherein the first isolation region is a closed square region extending along the outer periphery of the substrate. ​ ​ ​ ​ ​ ​ ​ The etching paste is printed on the surface of the second transparent conductive layer by screen printing four times, and each printing area corresponds to the area where one side of the closed area is located. Or The etching paste is printed on the surface of the second transparent conductive layer by screen printing twice, and the first printing area corresponds to the area where two adjacent sides of the closed area are located, and the second printing area corresponds to the area where the remaining two adjacent sides are located.

9. The preparation method of the heterojunction solar cell according to claim 8, wherein, before the etching paste is printed on the second transparent conductive layer by screen printing, the method further comprises: when the second transparent conductive layer is formed, using the bearing part of the carrier plate as a mask to form a non-coating film area which is not coated with the second transparent conductive layer; and wherein the non-coating film area at least partially overlaps with the area to be screen printed.

10. The preparation method of the heterojunction solar cell according to claim 9, wherein, the number of the non-coating film areas is four, and each of the non-coating film areas is located at a corner area of the substrate. Optionally, the size of each non-coating film area in the direction parallel to the side of the closed area is a, and a is greater than or equal to 0.25 mm and less than half of the length of the side of the substrate. Optionally, the shape of each bearing part includes L-shaped, sector-shaped, triangular or quadrilateral.

11. The preparation method of the heterojunction solar cell according to claim 2, wherein, the first etching process comprises: using laser etching to scan the position corresponding to the first isolation area of the second transparent conductive layer at least once to form the first isolation area.

12. The preparation method of the heterojunction solar cell according to claim 2, wherein, the first etching process comprises: using inkjet printing to spray etching paste on the position corresponding to the first isolation area of the second transparent conductive layer, and using the etching paste to etch the second transparent conductive layer to form the first isolation area.

13. The preparation method of the heterojunction solar cell according to claim 2, wherein, the second etching process comprises: using one of wet etching, ICP etching or CCP etching to etch the second doped layer at the position corresponding to the first isolation area using the second transparent conductive layer as a mask to form the second isolation area.

14. The preparation method of the heterojunction solar cell according to claim 1, wherein, the etching process is one-step etching process, the second transparent conductive layer and the second doped layer are etched by one-step etching process to form the isolation area. The one-step etching process comprises: using roller coating to coat etching paste on the second transparent conductive layer, and using the etching paste to etch the second transparent conductive layer and the second doped layer to form the isolation area. The step of coating etching paste by using roller coating comprises: Two groups of two rollers arranged oppositely are used to coat simultaneously around the second transparent conductive layer. Or ​ ​ 15. The method of producing a heterojunction solar cell according to claim 14, wherein ​ ​ ​ ​ A set of opposite two rollers are used to coat a set of opposite edges of the second transparent conductive layer, and then the cell is rotated horizontally by 90° to coat another set of opposite edges of the second transparent conductive layer. 16.The method of claim 15, wherein, Before the roller is used to coat the etching paste on the cell, the method further comprises: The amount of etching paste on the surface of the roller is controlled by a scraper, so as to control the width of the etching paste coated on the second transparent conductive layer. 17.The method of claim 16, wherein, The axis of the roller is inclined to the side of the cell where the etching paste needs to be coated. 18.The method of claim 16, wherein, The size of the two ends of the roller is larger than the size of the middle region. 19.The method of claim 14, wherein, The isolation region comprises a square closed region formed along the outer periphery of the substrate; The one-step etching process comprises printing the etching paste on the surface of the second transparent conductive layer multiple times by screen printing, and etching the second transparent conductive layer and the second doped layer by the etching paste to form the isolation region. 20.The method of claim 19, wherein, The etching paste is printed on the surface of the second transparent conductive layer four times by screen printing, and each printing area corresponds to a region where one side of the closed region is located; Or The etching paste is printed on the surface of the second transparent conductive layer twice by screen printing, and the first printing area corresponds to two adjacent sides of the closed region, and the second printing area corresponds to the remaining two adjacent sides. 21.The method of claim 20, wherein, Before the etching by screen printing, the method further comprises, when the second transparent conductive layer is formed, using the bearing part of the carrier plate as a mask to form a non-coating region, and the non-coating region at least partially overlaps with the area to be screen printed. 22.The method of claim 21, wherein, The number of the non-coating regions is four, and each non-coating region is located at a corner region of the substrate; Optionally, the size of each non-coating region in the direction parallel to the side of the closed region is a, and a is greater than or equal to 0.25 mm and less than half of the length of the side of the substrate; Optionally, the shape of each bearing part comprises an L shape, a sector shape, a triangle shape or a quadrilateral shape.

23. The method of producing a heterojunction solar cell according to claim 1, wherein The width b of the isolation region is less than 0.3 mm. 24.The method of claim 1, wherein, The distance c of the isolation region from the edge of the substrate is less than 0.1 mm.

25. A heterojunction solar cell, characterized by The heterojunction solar cell is prepared by the method of any one of claims 1-24.

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