Multi-modal sensing-memory-computing integrated brain-inspired chip and preparation method therefor

Abstract

Disclosed in the present invention are a multi-modal sensing-memory-computing integrated brain-inspired chip and a preparation method therefor. The chip comprises: a gate dielectric layer and a channel layer sequentially arranged on the surface of a substrate, and a source-drain electrode arranged on two ends of the channel layer. The channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source-drain electrode is respectively arranged on the ferroelectric semiconductor layer and the organic semiconductor layer. The ferroelectric semiconductor layer serves as a response layer for an optical signal and an electrical signal, and the organic semiconductor layer serves as a response layer for gas. The present invention uses a heterojunction of ferroelectric semiconductors and organic semiconductors to construct a sensing-memory-computing integrated brain-inspired chip to obtain a neuromorphic electronic device having optical, electrical and gas storage effects, and is suitable for multi-modal information sensing, storage and processing.

Description

A multi-modal sensing, storing and computing integrated brain-like chip and a preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a multi-modal sensing, storing and computing integrated brain-like chip and a preparation method thereof. BACKGROUND

[0002] In the conventional information processing system, the information sensing unit, the information processing unit and the information storage unit are in a structural separation state. The information detected by the information sensing unit needs to be converted by an analog-to-digital converter or the like before being transmitted to the information processing unit for further calculation, which limits the processing efficiency of the signal. Especially when a large amount of data is encountered, it will cause the accumulation of redundant information and signal delay, which is not conducive to the realization of high-speed signal processing feedback. Therefore, it is crucial to develop a sensing, storing and computing integrated electronic device with the functions of information sensing, information storage and information processing for efficient information processing.

[0003] In addition, the conventional information sensing device can only sense a single signal source, such as a photoelectric detection device or a gas sensing device, which cannot meet the processing requirements of the current sensing system for multi-modal information. As an important information source, electrical signals, optical signals and gas signals carry important environmental information. How to realize the sensing of multi-modal signals in the same intelligent electronic device has become a core problem in the development of new intelligent electronics.

[0004] SUMMARY

[0005] The present application aims to overcome the above-mentioned defects in the prior art and provide a multi-modal sensing, storing and computing integrated brain-like chip and a preparation method thereof.

[0006] To achieve the above-mentioned purpose, the technical solution of the present application is as follows:

[0007] The present application provides a multi-modal sensing, storing and computing integrated brain-like chip, comprising:

[0008] A gate dielectric layer and a channel layer are sequentially arranged on the surface of a substrate, and source-drain electrodes are arranged on both ends of the channel layer;

[0009] The channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are arranged on the ferroelectric semiconductor layer and the organic semiconductor layer, respectively;

[0010] The ferroelectric semiconductor layer serves as a response layer for optical signals and electrical signals, and the organic semiconductor layer serves as a response layer for gas.

[0011] Further, the gate dielectric layer comprises a ferroelectric gate dielectric layer, and an interface modification layer is further arranged between the surface of the substrate and the ferroelectric gate dielectric layer.

[0012] Further, the ferroelectric gate dielectric layer comprises a lanthanum hafnium oxide layer, and the interface modification layer comprises a semiconductor quantum dot layer.

[0013] Further, the semiconductor quantum dot layer material comprises graphene quantum dots, molybdenum sulfide quantum dots or black phosphorus quantum dots, the ratio of hafnium elements to lanthanum elements in the lanthanum hafnium oxide layer is 10:1-30:1, the ferroelectric semiconductor layer comprises a two-dimensional indium selenide layer, the organic semiconductor layer material comprises copper phthalocyanine, pentacene, PTCDI-Ph, NDI2OD-DTYM2 or PBTTT-C12, and the source-drain electrode material comprises indium tin oxide, graphene, silver nanowires or PEDOT:PSS.

[0014] Further, the substrate comprises a silicon wafer with an oxide layer on the surface, the gate dielectric layer is arranged on the surface of the oxide layer, and the gate electrode is arranged on the silicon wafer to form a ferroelectric field effect transistor, thereby realizing multi-modal sensing and computing integrated processing of optical signals, electrical signals and gas signals.

[0015] The application further provides a preparation method of the multi-modal sensing and computing integrated brain-like chip, comprising:

[0016] providing a substrate;

[0017] forming a gate dielectric layer and a channel layer on the surface of the substrate in sequence, and forming source-drain electrodes on both ends of the channel layer;

[0018] wherein the channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are respectively formed on the ferroelectric semiconductor layer and the organic semiconductor layer, so that the ferroelectric semiconductor layer serves as a response layer of optical signals and electrical signals, and the organic semiconductor layer serves as a response layer of gas.

[0019] Further, before forming the gate dielectric layer, the method further comprises:

[0020] forming an interface modification layer on the surface of the substrate;

[0021] when forming the gate dielectric layer, the method further comprises:

[0022] forming a ferroelectric gate dielectric layer on the surface of the interface modification layer.

[0023] Further, the method for forming the interface modification layer specifically comprises:

[0024] adopting a silicon wafer with an oxide layer as the substrate, and forming a gate electrode with the silicon wafer;

[0025] Spin coating semiconductor quantum dots on the surface of the oxide layer, and performing first annealing to form a semiconductor quantum dot layer as an interface modification layer; wherein the spin coating rotation speed is 2000-4500 rpm, the spin coating time is 30 seconds-2 minutes, the first annealing is performed by vacuum annealing, the first annealing temperature is 180-250℃, the first annealing time is 15-30 minutes, and the semiconductor quantum dots include graphene quantum dots, molybdenum sulfide quantum dots or black phosphorus quantum dots;

[0026] The method for forming the ferroelectric gate dielectric layer specifically comprises:

[0027] The lanthanum hafnium oxide film is grown on the surface of the interface modification layer by atomic layer deposition technology, and second annealing is performed to realize the transition of the lanthanum hafnium oxide film from a non-ferroelectric phase to a ferroelectric phase, thereby forming a lanthanum hafnium oxide layer with a thickness of 3-6 nm as the ferroelectric gate dielectric layer; wherein the ratio of hafnium elements to lanthanum elements is set to 10:1-30:1, the growth temperature of atomic layer deposition is 200-300℃, the second annealing is performed by rapid thermal annealing, the second annealing temperature is 400-600℃, and the second annealing time is 15-40s.

[0028] Further, the method for forming the channel layer specifically comprises:

[0029] The two-dimensional indium selenide layer is transferred on the surface of the ferroelectric gate dielectric layer by a mechanical exfoliation method to form a ferroelectric semiconductor layer with a thickness of 30-100 nm; wherein the width of the two-dimensional indium selenide layer is 2-10 μm, and the length is 5-20 μm.

[0030] Phthalocyanine copper, pentacene, PTCDI-Ph, NDI2OD-DTYM2 or PBTTT-C12 is evaporated on one end of the two-dimensional indium selenide layer by electron beam lithography as a mask and an organic evaporation method to form an organic semiconductor layer with a thickness of 30-100 nm connected on one end of the ferroelectric semiconductor layer by one end, thereby forming a channel layer on the surface of the ferroelectric gate dielectric layer.

[0031] Further, the method for forming the source-drain electrode specifically comprises:

[0032] The patterns of indium tin oxide, graphene, silver nanowires or PEDOT:PSS material are formed on the two ends of the ferroelectric semiconductor layer and the organic semiconductor layer, respectively, as the source-drain electrode, and the source-drain electrode is also formed on the surface of the corresponding side of the ferroelectric gate dielectric layer; wherein the thickness of the source-drain electrode is 50-100 nm.

[0033] It can be seen from the technical scheme that the application realizes the signal storage function by using the storage characteristics of the formed ferroelectric FET, and can construct a brain-like transistor to realize neuromorphic computing; meanwhile, the sensitive response of the ferroelectric semiconductor layer to optical signals and electrical signals can realize the detection and sensing of optical signals and electrical signals, and the sensitive response of the organic semiconductor layer to gas can realize the detection and sensing of gas signals, so that a multi-modal sensing effect can be constructed at the channel layer level, and finally a multi-modal sensing and computing integrated ferroelectric chip is constructed. The application has the following advantages:

[0034] (1) The neuromorphic ferroelectric FET is constructed by using the ferroelectric semiconductor, which breaks the traditional computer hardware bottleneck and avoids the conversion and transmission of signals between different modules, so that the sensing, storage and computing integrated can be realized in the same unit, and the information processing efficiency of the device is improved.

[0035] (2) The neuromorphic device with multi-modal signal sensing is developed by using the unique current response characteristics of the ferroelectric semiconductor and the organic semiconductor material to optical and electrical signals and gas signals, which provides a new hardware for realizing multi-modal information processing. BRIEF DESCRIPTION OF DRAWINGS

[0036] Fig. 1 is a structural schematic diagram of a multi-modal sensing and computing integrated brain-like chip according to an embodiment of the application.

[0037] Figs. 2-6 are process flow schematic diagrams of a preparation method of a multi-modal sensing and computing integrated brain-like chip according to an embodiment of the application.

[0038] Fig. 7 is a working principle schematic diagram of a multi-modal sensing and computing integrated brain-like chip according to an embodiment of the application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the embodiments of the application more clear, the technical scheme of the embodiments of the application will be described clearly and completely below. Obviously, the described embodiments are some embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the usual meanings understood by those skilled in the art in the field of the application. The words such as "include" and similar words used herein mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, and do not exclude other elements or objects.

[0040] Traditional sensor devices can only detect a single signal and cannot realize signal processing and storage in the same device. Inspired by the human brain, brain-like chips have a unique storage and calculation integrated working mode and exhibit obvious advantages in efficient information processing. By integrating memory functions and computing functions, brain-like chips can simultaneously complete information processing and information storage, providing a new path for neuromorphic computing for artificial intelligence application scenarios. Integrating information perception with brain-like chips and using brain-like chips to realize information perception functions will greatly promote the development of integrated sensing, storage and calculation.

[0041] The present application relates to a kind of to build sensing, storage and calculation integrated brain-like chip using the heterostructure of ferroelectric semiconductor and organic semiconductor, to obtain the neuromorphic electronic device with light, electricity, gas storage effect, suitable for multi-modal information perception, storage and processing.

[0042] The present application aims at the problems that traditional sensor devices can only detect a single signal and cannot realize signal processing and storage, and adopts the heterostructure of two-dimensional ferroelectric semiconductor and organic semiconductor to build a new sensing, storage and calculation integrated brain-like chip. Using the visible light signal detection capability and electrical signal detection capability of two-dimensional ferroelectric semiconductor, combined with the gas detection capability of organic semiconductor, multi-modal signal detection is realized in the same device. On the other hand, the sensing, storage and calculation integrated brain-like chip can utilize the sensing capability of the channel material, combined with the storage and calculation capability of the ferroelectric field effect transistor (ferroelectric FET), and realize information sensing, calculation and memory in the same device, which greatly promotes the development of sensing, storage and calculation integrated chip.

[0043] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0044] Referring to FIG. 1, a multi-modal sensing, storage and calculation integrated brain-like chip according to the present application includes a gate dielectric layer 13 and a channel layer 15 arranged on the surface of a substrate 10 in sequence, and source-drain electrodes 14 arranged on both ends of the channel layer 15 (i.e., one end of the two ends is provided with a source electrode, and the other end of the two ends is provided with a drain electrode).

[0045] Among them, the channel layer 15 includes a ferroelectric semiconductor layer 152 and an organic semiconductor layer 151 arranged on the surface of the gate dielectric layer 13 at the same time. And the ferroelectric semiconductor layer 152 and the organic semiconductor layer 151 are connected at one end of each, forming a heterojunction. The source-drain electrodes 14 are arranged on the ferroelectric semiconductor layer 152 and the organic semiconductor layer 151, respectively. For example, the drain electrode 142 (connected to V D ) is arranged on the ferroelectric semiconductor layer 152, and the source electrode 141 (grounded) is arranged on the organic semiconductor layer 151.

[0046] The ferroelectric semiconductor layer 152 is used as a response layer of optical signals and electrical signals, and the organic semiconductor layer 151 is used as a response layer of gases. Thus, by constructing a ferroelectric field effect transistor, the storage function of signals can be realized by using the storage characteristics of the ferroelectric FET, and the neural morphic computing can be realized by constructing a brain-like transistor. Moreover, by using the sensitive response of the ferroelectric semiconductor to optical signals and electrical signals, the detection and sensing of optical signals and electrical signals can be realized. At the same time, by using the sensitive response of the organic semiconductor to gases, the detection and sensing of gas signals can be realized, and the multi-modal sensing effect can be constructed at the channel level. Finally, a multi-modal sensing and computing integrated ferroelectric chip is constructed.

[0047] Referring to FIG. 1. In some embodiments, the gate dielectric layer 13 includes a ferroelectric gate dielectric layer 131.

[0048] In some embodiments, an interface modification layer 16 is further arranged between the surface of the substrate 10 and the ferroelectric gate dielectric layer 131.

[0049] In some embodiments, the ferroelectric gate dielectric layer 131 includes a lanthanum hafnium oxide layer 132. Alternatively, the material of the ferroelectric gate dielectric layer 131 includes lanthanum hafnium oxide (HfLaO x ).

[0050] In some embodiments, the lanthanum hafnium oxide layer 132 is an ultrathin lanthanum hafnium oxide film layer.

[0051] Further, the thickness of the lanthanum hafnium oxide layer 132 (ferroelectric gate dielectric layer 131) is 3-6 nm. Preferably, the thickness of the lanthanum hafnium oxide layer 132 is preferably 5 nm.

[0052] In some embodiments, the ratio of hafnium (Hf) elements to lanthanum (La) elements in the lanthanum hafnium oxide layer 132 is 10:1-30:1. Preferably, the ratio of hafnium (Hf) elements to lanthanum (La) elements in the lanthanum hafnium oxide layer 132 is preferably 12:1.

[0053] In some embodiments, the interface modification layer 16 includes a semiconductor quantum dot layer 161.

[0054] Further, the material of the semiconductor quantum dot layer 161 includes graphene quantum dots, molybdenum sulfide quantum dots, or black phosphorus quantum dots. Alternatively, the semiconductor quantum dot layer 161 includes a graphene quantum dot layer 162, a molybdenum sulfide quantum dot layer, or a black phosphorus quantum dot layer.

[0055] In some embodiments, the ferroelectric semiconductor layer 152 includes an indium selenide layer (InSe layer) 1521. The indium selenide ferroelectric semiconductor has a dual response function to electrical signals and optical signals as a channel material.

[0056] Further, the indium selenide layer 1521 is a two-dimensional indium selenide layer.

[0057] In some embodiments, the thickness of the indium selenide layer 1521 (ferroelectric semiconductor layer 152) is 30-100 nm. Preferably, the thickness of the indium selenide layer 1521 is preferably 50 nm.

[0058] In some embodiments, the indium selenide layer 1521 is disposed on the surface of the gate dielectric layer 13, and the area of the indium selenide layer 1521 is smaller than the area of the gate dielectric layer 13.

[0059] Further, the width of the indium selenide layer 1521 is 2-10 μm, and the length is 5-20 μm. Preferably, the width of the indium selenide layer 1521 is preferably 2 μm, and the length is preferably 10 μm.

[0060] In some embodiments, the organic semiconductor layer 151 is a functional organic layer, and has a sensitive response to gas. The material of the organic semiconductor layer 151 includes copper phthalocyanine (CuPc), pentacene, PTCDI-Ph, NDI2OD-DTYM2, or PBTTT-C12. Alternatively, the organic semiconductor layer 151 includes a copper phthalocyanine layer (CuPc layer) 1511, a pentacene layer, a PTCDI-Ph layer, a NDI2OD-DTYM2 layer, or a PBTTT-C12 layer.

[0061] In some embodiments, the thickness of the organic semiconductor layer 151 is 30-100 nm. Preferably, the thickness of the organic semiconductor layer 151 is preferably 50 nm.

[0062] In some embodiments, the width of the organic semiconductor layer 151 is not less than the width of the ferroelectric semiconductor layer 152. Further, the organic semiconductor layer 151 is laminated on the surface of the opposite end of the ferroelectric semiconductor layer 152 by one end, and is connected to the ferroelectric semiconductor layer 152. The organic semiconductor layer 151 (functional organic layer) and the ferroelectric semiconductor layer 152 are laminated to form the channel layer 15.

[0063] In some embodiments, the source-drain electrode 14 is disposed on the surface of the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152 outside the overlapping part of the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152, and the source-drain electrode 14 further extends to the surface of the ferroelectric gate dielectric layer 131 on the corresponding side.

[0064] In some embodiments, the material of the source-drain electrode 14 includes indium tin oxide (ITO), graphene, silver nanowire, or PEDOT:PSS.

[0065] In some embodiments, the source-drain electrode 14 includes a transparent electrode.

[0066] In some embodiments, the thickness of the source-drain electrode 14 is 50-100 nm. Preferably, the thickness of the source-drain electrode 14 is preferably 70 nm.

[0067] In some embodiments, the source-drain electrode 14 (source electrode 141 and drain electrode 142) comprises a contact end, a connecting arm and an electrode seat connected in sequence. The source-drain electrode 14 is connected to the surface of the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152 through the contact end, and the source-drain electrode 14 is connected to the surface of the ferroelectric gate dielectric layer 131 through the electrode seat. The electrode seat of the source-drain electrode 14 serves as a lead-out end.

[0068] In some embodiments, the contact end of the source-drain electrode 14 arranged on the surface of the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152 completely covers the surface in the width direction of the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152. The electrode seat of the source-drain electrode 14 is arranged on the surface of the ferroelectric gate dielectric layer 131 away from the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152.

[0069] Referring to FIG. 1. In some embodiments, the substrate 10 comprises a silicon oxide wafer substrate 10, i.e., a substrate 10 formed by a silicon wafer 11 with an oxide layer 12 (silicon dioxide layer) on the surface, but is not limited thereto. The interface modification layer 16 is arranged on the surface of the silicon dioxide oxide layer 12 of the substrate 10, so that the ferroelectric gate dielectric layer 131 is arranged on the surface of the oxide layer 12 through the interface modification layer 16. The silicon wafer 11 is provided with a gate electrode (connected to V gate ), or, by using the silicon wafer 11 (for example, a highly doped silicon wafer 11) as a gate electrode (back gate electrode) to form a ferroelectric field effect transistor, so as to realize multi-modal sensing, storage and computing integrated processing of optical signals, electrical signals and gas signals.

[0070] In some embodiments, the highly doped silicon wafer 11 is used as a back gate electrode (connected to V gate ), the ITO transparent drain electrode 142 (connected to V D ) is arranged on the InSe ferroelectric semiconductor layer 152, and the ITO transparent source electrode 141 is arranged on the CuPc organic semiconductor layer 151 and is grounded.

[0071] The present application uses a ferroelectric semiconductor to construct a neuromorphic ferroelectric FET, breaks the traditional computer hardware bottleneck, avoids the conversion and transmission of signals between different modules, realizes the integration of sensing, storage and computing in the same unit, and improves the information processing efficiency of the device. At the same time, by using the unique current response characteristics of the ferroelectric semiconductor and the organic semiconductor material to optical and electrical signals, gas signals, a neuromorphic device with multi-modal signal sensing is developed, which provides a new hardware for realizing multi-modal information processing. The neuromorphic electronic device with optical, electrical and gas storage effect obtained by the present application is suitable for multi-modal information sensing, storage and processing.

[0072] The preparation method of the multi-modal sensing and computing integrated brain-like chip according to the present application is further described in detail below with reference to the specific embodiments and in conjunction with the accompanying drawings.

[0073] The preparation method of the multi-modal sensing and computing integrated brain-like chip according to the present application comprises:

[0074] providing a substrate;

[0075] forming a gate dielectric layer and a channel layer on the surface of the substrate in sequence, and forming source-drain electrodes on both ends of the channel layer;

[0076] wherein the channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are formed on the ferroelectric semiconductor layer and the organic semiconductor layer, respectively, so that the ferroelectric semiconductor layer serves as a response layer for optical signals and electrical signals, and the organic semiconductor layer serves as a response layer for gases.

[0077] Reference is made to FIGS. 2-6. In some embodiments, the preparation method of the multi-modal sensing and computing integrated brain-like chip according to the present application comprises the following steps:

[0078] Step S1: preparing an interface modification layer 16 on the surface of a substrate 10.

[0079] As shown in FIG. 2, a silicon oxide wafer is used as the substrate 10, i.e., a silicon wafer 11 with a SiO2 oxide layer 12 on the surface is used as the substrate 10. The silicon wafer 11 can be used to form a gate electrode (back gate electrode) to form a ferroelectric field effect transistor.

[0080] By spin-coating semiconductor quantum dots on the surface of the oxide layer 12 of the silicon wafer 11 and performing first annealing, a semiconductor quantum dot layer 161 is formed as the interface modification layer 16.

[0081] In some embodiments, when spin-coating semiconductor quantum dots on the surface of the oxide layer 12, the spin-coating rotation speed is 2000-4500 rpm, and the spin-coating time is 30 seconds-2 minutes.

[0082] In some embodiments, the substrate 10 with semiconductor quantum dots spin-coated thereon is placed in a vacuum annealing furnace and vacuum annealing is performed to perform the first annealing. In this case, the annealing temperature during the first annealing is 180-250°C, and the annealing time is 15-30 minutes.

[0083] In some embodiments, the semiconductor quantum dots include graphene quantum dots, molybdenum sulfide quantum dots, or black phosphorus quantum dots to form the interface modification layer 16 of the graphene quantum dot layer 162, the molybdenum sulfide quantum dot layer, or the black phosphorus quantum dot layer.

[0084] In this embodiment, graphene quantum dots are spin-coated on the surface of the oxide layer 12 of the substrate 10 to form the interface modification layer 16, the spin-coating speed is 4000 rpm, and the spin-coating time is 1 minute. Subsequently, the substrate 10 with the graphene quantum dots spin-coated is placed in a vacuum annealing furnace and annealed at a set temperature of 200°C and in a nitrogen atmosphere for 20 minutes to form a graphene quantum dot layer 162 and as the interface modification layer 16.

[0085] Step S2: preparing a ferroelectric gate dielectric layer 131 on the surface of the interface modification layer 16.

[0086] As shown in FIG. 3, an ultra-thin hafnium lanthanum oxide (HfLaO x ) film is grown on the surface of the graphene quantum dot layer 162 as the interface modification layer 16 by atomic layer deposition, and a second annealing is performed to realize the phase transition of the non-ferroelectric phase hafnium lanthanum oxide to the ferroelectric phase, so as to form a ferroelectric phase hafnium lanthanum oxide layer 132 as the ferroelectric gate dielectric layer 131 (gate dielectric layer 13).

[0087] In some embodiments, the growth temperature of the atomic layer deposition is 200-300°C.

[0088] In some embodiments, the thickness of the formed hafnium lanthanum oxide layer 132 is 3-6 nm.

[0089] In some embodiments, the ratio of hafnium element to lanthanum element in the hafnium lanthanum oxide layer 132 is set to 10:1-30:1.

[0090] In some embodiments, the second annealing is performed by rapid thermal annealing in a nitrogen atmosphere. The second annealing temperature is 400-600°C, and the second annealing time is 15-40 s.

[0091] In this embodiment, an ultra-thin hafnium lanthanum oxide film with a thickness of about 5 nm is grown on the surface of the graphene quantum dot layer 162 by atomic layer deposition, the growth temperature is set to 260°C, and the ratio of hafnium element to lanthanum element is set to 12:1. Subsequently, rapid thermal annealing is used, and the annealing is performed at a set temperature of 500°C and in a nitrogen atmosphere for about 30 s to realize the phase transition of the non-ferroelectric phase HfLaO x to the ferroelectric phase, so as to prepare a ferroelectric phase ultra-thin hafnium lanthanum oxide layer 132 on the surface of the graphene quantum dot layer 162 as the ferroelectric gate dielectric layer 131.

[0092] Step S3: preparing a ferroelectric semiconductor layer 152 on the surface of the ferroelectric gate dielectric layer 131.

[0093] As shown in FIG. 4, a two-dimensional indium selenide (InSe) layer 1521 is transferred on the surface of the ultra-thin lanthanum hafnium oxide ferroelectric gate dielectric layer 131 as a ferroelectric semiconductor layer 152 by a mechanical exfoliation method. The two-dimensional indium selenide layer 1521 serves as a channel material and has a dual response function to electrical signals and optical signals.

[0094] In some embodiments, the thickness of the ferroelectric semiconductor layer 152 formed after transfer is 30-100 nm. In this case, the width of the transferred two-dimensional indium selenide layer 1521 is 2-10 μm, and the length is 5-20 μm.

[0095] In this embodiment, a two-dimensional indium selenide layer 1521 with a thickness of about 50 nm, a width of about 2 μm, and a length of about 10 μm is transferred on the surface of the ultra-thin lanthanum hafnium oxide ferroelectric gate dielectric layer 131 as a channel material by a mechanical exfoliation method.

[0096] Step S4: An organic semiconductor layer 151 is prepared on the surface of the ferroelectric gate dielectric layer 131 to form a channel layer 15.

[0097] As shown in FIG. 5, a copper phthalocyanine (CuPc) layer 1511 is formed on one end of the two-dimensional indium selenide layer 1521 as an organic functional layer (organic semiconductor layer 151) having a sensitive response to gas by electron beam lithography as a mask and an organic evaporation method.

[0098] In this case, the width of the copper phthalocyanine layer 1511 is not less than the width of the indium selenide layer 1521, and the copper phthalocyanine layer 1511 is partially laminated on the surface of the opposite end of the indium selenide layer 1521 by one end, so that the copper phthalocyanine layer 1511 is connected to the indium selenide layer 1521. The other part of the copper phthalocyanine layer 1511 is deposited on the surface of the ultra-thin lanthanum hafnium oxide ferroelectric gate dielectric layer 131. In this way, the copper phthalocyanine layer 1511 and the two-dimensional indium selenide layer 1521 are laminated to form a heterojunction and jointly construct a two-dimensional composite channel layer 15. By using the visible light signal detection capability and electrical signal detection capability of the two-dimensional indium selenide ferroelectric semiconductor and combining the gas detection capability of the copper phthalocyanine organic semiconductor, multi-modal signal detection is realized on the same device. On the other hand, the constructed sensing and storage integrated brain chip can use the sensing capability of the channel material and combine the storage and calculation capability of the ferroelectric FET to realize information sensing, calculation and memory by using the same device, which greatly promotes the development of the sensing, storage and calculation integrated chip.

[0099] In some embodiments, the thickness of the copper phthalocyanine layer 1511 (organic semiconductor layer 151) is 30-100 nm.

[0100] In some embodiments, the thickness of the copper phthalocyanine layer 1511 is consistent with the thickness of the indium selenide layer 1521.

[0101] In this embodiment, the thickness of the copper phthalocyanine layer 1511 formed by evaporation is about 50 nm.

[0102] In some other embodiments, the organic semiconductor layer 151 can also be prepared by using pentacene, PTCDI-Ph, NDI2OD-DTYM2 or PBTTT-C12.

[0103] Step S5: preparing the source-drain electrode 14.

[0104] As shown in FIG. 6, a transparent indium tin oxide (ITO) electrode material is evaporated on the two ends of the indium selenide layer 1521 and the copper phthalocyanine layer 1511 (i.e. on the surfaces of the indium selenide layer 1521 and the copper phthalocyanine layer 1511 outside the overlapping area of the two layers) by using a magnetron sputtering method, so as to form a pattern of the indium tin oxide material as the source-drain electrode 14. The formed source-drain electrode 14 includes a drain electrode 142 arranged on the surface of the indium selenide layer 1521 and a source electrode 141 arranged on the surface of the copper phthalocyanine layer 1511. During the evaporation, the pattern of the indium tin oxide material is also formed on the surface of the ultra-thin lanthanum hafnium iron oxide ferroelectric gate dielectric layer 131, i.e. the electrode seats of the source-drain electrode 14 are arranged on the surface of the ultra-thin lanthanum hafnium iron oxide ferroelectric gate dielectric layer 131 away from the organic semiconductor layer 151 and the ferroelectric semiconductor layer 152. Thus, a ferroelectric field effect transistor is formed, and a neuromorphic electronic device with photoelectric and gas storage effects is obtained, and a brain-like chip integrating sensing, storage and calculation is constructed, which is suitable for multi-modal information sensing, storage and processing.

[0105] In some embodiments, the thickness of the source-drain electrode 14 is 50-100 nm. In this embodiment, the thickness of the source-drain electrode 14 is about 70 nm.

[0106] In some other embodiments, the source-drain electrode 14 can also be prepared by using transparent electrode materials such as graphene, silver nanowires or PEDOT:PSS.

[0107] Thus, the above-mentioned preparation method of the multi-modal sensing, storage and calculation integrated brain-like chip can be used to prepare, for example, the multi-modal sensing, storage and calculation integrated brain-like chip shown in FIG. 1. In other words, the multi-modal sensing, storage and calculation integrated brain-like chip shown in FIG. 1 can be prepared by the above-mentioned preparation method of the multi-modal sensing, storage and calculation integrated brain-like chip shown in, for example, FIGS. 2-6.

[0108] Referring to FIG. 7, a back gate electrode (connected to V gate ) is arranged on the silicon wafer 11 of the substrate 10 of the device shown in FIG. 1, and an ITO transparent drain electrode (connected to V D), and the ITO transparent source electrode is arranged on the copper phthalocyanine layer 1511 on the other side of the channel, and is grounded, to form a brain-like chip integrated with sensing and storage, which is built by using the heterojunction of the ferroelectric semiconductor and the organic semiconductor, and obtain a neuro-morphic electronic device with light, electrical and gas storage effects, which is suitable for multi-modal information sensing, storage and processing. The response of the indium selenide ferroelectric semiconductor channel to the optical signal of light stimulation and the electrical signal of electrical stimulation, and the response of the CuPc organic semiconductor channel to, for example, SO2 gas, realize the detection function of the overall device to multi-modal signals such as light, electricity and gas. At the same time, the storage effect and brain-like computing behavior of the ferroelectric field effect transistor realize the integrated processing of multi-modal signals such as light signals, electrical signals and gas signals.

[0109] In summary, by designing the heterojunction channel layer 15 of the ferroelectric semiconductor layer 152 and the organic semiconductor layer 151, the storage function of the signal is realized by using the storage characteristics of the formed ferroelectric FET, and the neuro-morphic transistor can be constructed to realize neuro-morphic computing. At the same time, the sensitive response of the ferroelectric semiconductor layer 152 to the optical signal and the electrical signal can realize the detection and sensing of the optical signal and the electrical signal, and the sensitive response of the organic semiconductor layer 151 to the gas can realize the detection and sensing of the gas signal, so that the multi-modal sensing effect can be constructed at the channel level, and finally the multi-modal sensing and computing integrated ferroelectric chip is constructed. Therefore, the present application can realize the integrated sensing, storage and computing in the same unit, improve the information processing efficiency of the device, and develop a neuro-morphic device with multi-modal signal sensing, which can provide a new hardware for realizing multi-modal information processing.

[0110] Although the embodiments of the present application have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes all belong to the scope and spirit of the present application described in the claims. Moreover, the present application described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A multi-modal neuromorphic integrated brain chip, characterized in that, The application relates to a ferroelectric field effect transistor, which comprises the following parts: a gate dielectric layer and a channel layer arranged on the surface of a substrate in sequence, and source-drain electrodes arranged on both ends of the channel layer; the channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are arranged on the ferroelectric semiconductor layer and the organic semiconductor layer respectively; the ferroelectric semiconductor layer serves as a response layer of optical signals and electrical signals, and the organic semiconductor layer serves as a response layer of gases.

2. The multi-modal neuromorphic all-brain chip of claim 1, wherein, the gate dielectric layer comprises a ferroelectric gate dielectric layer, and an interface modification layer is further arranged between the surface of the substrate and the ferroelectric gate dielectric layer.

3. The multi-modal neuromorphic all-brain chip of claim 2, wherein, the ferroelectric gate dielectric layer comprises a lanthanum hafnium oxide layer, and the interface modification layer comprises a semiconductor quantum dot layer.

4. The multi-modal neuromorphic all-brain chip of claim 3, wherein, the material of the semiconductor quantum dot layer comprises graphene quantum dots, molybdenum sulfide quantum dots or black phosphorus quantum dots, the ratio of hafnium elements to lanthanum elements in the lanthanum hafnium oxide layer is 10:1-30:1, the ferroelectric semiconductor layer comprises a two-dimensional indium selenide layer, the material of the organic semiconductor layer comprises copper phthalocyanine, pentacene, PTCDI-Ph, NDI2OD-DTYM2 or PBTTT-C12, and the material of the source-drain electrodes comprises indium tin oxide, graphene, silver nanowires or PEDOT:PSS.

5. The multi-modal neuromorphic all-brain chip of claim 1, wherein, the substrate comprises a silicon wafer with an oxide layer on the surface, the gate dielectric layer is arranged on the surface of the oxide layer, and a gate electrode is arranged on the silicon wafer to form a ferroelectric field effect transistor, so that multi-modal sensing and integrated processing of optical signals, electrical signals and gas signals can be realized.

6. A preparation method of a multi-modal neuromorphic integrated brain chip, characterized in that, The application relates to a ferroelectric field effect transistor, which comprises the following parts: a substrate is provided; a gate dielectric layer and a channel layer are formed on the surface of the substrate in sequence, and source-drain electrodes are formed on both ends of the channel layer; the channel layer comprises a ferroelectric semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are arranged on the ferroelectric semiconductor layer and the organic semiconductor layer respectively, so that the ferroelectric semiconductor layer serves as a response layer of optical signals and electrical signals, and the organic semiconductor layer serves as a response layer of gases.

7. The preparation method of the multi-modal neuromorphic integrated brain chip according to claim 6, characterized in that, before the gate dielectric layer is formed, the following steps are further included: an interface modification layer is formed on the surface of the substrate; when the gate dielectric layer is formed, the following steps are further included: a ferroelectric gate dielectric layer is formed on the surface of the interface modification layer.

8. The preparation method of the multi-modal neuromorphic integrated brain chip according to claim 7, characterized in that, The method for forming the interface modification layer comprises the following steps: a silicon wafer with an oxide layer is used as the substrate, and a gate electrode is formed on the silicon wafer; semiconductor quantum dots are spin-coated on the surface of the oxide layer, and first annealing is performed to form a semiconductor quantum dot layer as the interface modification layer; wherein the spin-coating rotation speed is 2000-4500 revolutions per minute, the spin-coating time is 30 seconds-2 minutes, the first annealing is performed by vacuum annealing, the first annealing temperature is 180-250 DEG C, the first annealing time is 15-30 minutes, and the semiconductor quantum dots comprise graphene quantum dots, molybdenum sulfide quantum dots or black phosphorus quantum dots; the method for forming the ferroelectric gate dielectric layer comprises the following steps: The lanthanum hafnium oxide film is grown on the surface of the interface modification layer by using atomic layer deposition technology, and a second annealing is performed to realize the transition of the lanthanum hafnium oxide film from a non-ferroelectric phase to a ferroelectric phase, and form a lanthanum hafnium oxide layer with a thickness of 3-6 nm as a ferroelectric gate dielectric layer; wherein the ratio of hafnium element to lanthanum element is set to 10:1-30:1, the growth temperature of atomic layer deposition is 200-300 DEG C, the second annealing is performed by using rapid thermal annealing, the second annealing temperature is 400-600 DEG C, and the second annealing time is 15-40 s.

9. The preparation method of the multi-modal neuromorphic integrated brain chip according to claim 8, characterized in that, The method for forming the channel layer specifically comprises: The two-dimensional indium selenide layer is transferred on the surface of the ferroelectric gate dielectric layer by using a mechanical exfoliation method to form a ferroelectric semiconductor layer with a thickness of 30-100 nm; wherein the width of the two-dimensional indium selenide layer is 2-10 microns, and the length is 5-20 microns; The electron beam lithography is used as a mask, and the organic evaporation method is used to evaporate copper phthalocyanine, pentacene, PTCDI-Ph, NDI2OD-DTYM2 or PBTTT-C12 on one end of the two-dimensional indium selenide layer to form an organic semiconductor layer with a thickness of 30-100 nm connected on one end of the ferroelectric semiconductor layer through the one end, so as to form the channel layer on the surface of the ferroelectric gate dielectric layer. The method for forming the source-drain electrode specifically comprises:

10. The preparation method of the multi-modal neuromorphic all-brain chip according to claim 9, characterized in that, The patterns of indium tin oxide, graphene, silver nanowire or PEDOT:PSS material are respectively formed on the two ends of the ferroelectric semiconductor layer and the organic semiconductor layer away from each other as the source-drain electrode, and the source-drain electrode is also formed on the surface of the corresponding side of the ferroelectric gate dielectric layer; wherein the thickness of the source-drain electrode is 50-100 nm. ​

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