Optoelectronic computing-in-memory integrated device based on semiconductor heterojunction, and fabrication method therefor

Abstract

Disclosed in the present invention are an optoelectronic computing-in-memory integrated device based on a semiconductor heterojunction, and a fabrication method therefor. The device comprises: a charge blocking layer, a charge trapping layer, a charge tunneling layer and a channel layer, which are sequentially arranged on a surface of a substrate; and source and drain electrodes arranged on two ends of the channel layer, wherein the channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer, which are connected at one end to form a heterojunction, and the source and drain electrodes are respectively arranged on the two-dimensional semiconductor layer and the organic semiconductor layer; and the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier tuning and optoelectronic-signal response and achieve band alignment tuning, and cooperates with the charge trapping layer to complete in-situ computing and storage of information. The present invention constructs a channel material by using a heterojunction formed made up of a two-dimensional material and an organic material, thereby fabricating a neuromorphic electronic device having an optoelectronic storage effect, and the present invention is suitable for optoelectronic neuromorphic computing and applications.

Description

A semiconductor heterojunction-based optoelectronic in-memory computing device and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an optoelectronic in-memory computing device based on a semiconductor heterojunction and its fabrication method. Background Technology

[0002] As a core information recording unit in the information age, memory plays a crucial role in integrated circuits. Traditional semiconductor silicon-based memories, composed of silicon-based materials, are gradually approaching their physical limits during the miniaturization process, leading to increasingly apparent problems such as leakage current, making it difficult to meet the ever-increasing demand for high-density storage. Furthermore, traditional semiconductor silicon-based memories can only store "0" and "1" signals through electrical signals, failing to meet the computing requirements of in-memory computing and thus hindering multi-dimensional signal control.

[0003] Therefore, it is necessary to provide a novel optoelectronic in-memory computing device to solve the above-mentioned problems existing in the prior art.

[0004] Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide an optoelectronic in-memory computing device based on a semiconductor heterojunction and its fabrication method.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] This invention provides an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:

[0008] A charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially disposed on the surface of a substrate, and source and drain electrodes are disposed at both ends of the channel layer.

[0009] The channel layer includes a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer;

[0010] The heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, as well as band matching regulation, and works in conjunction with the charge trapping layer to complete in-situ calculation and storage of information.

[0011] Furthermore, the charge blocking layer material comprises a ternary metal high-k oxide formed by a first metal element, a second metal element, and an oxygen element; the charge trapping layer material comprises a binary metal oxide formed by a second metal element and an oxygen element; and the charge tunneling layer material comprises a binary metal high-k oxide formed by a first metal element and an oxygen element.

[0012] Further, the first metal element includes Hf, the second metal element includes Al, La, Ti, or Zr, and the charge blocking layer includes HfAlO. x Layer, HfLaO x Layer, HfTiO x Layer or HfZrO x The charge trapping layer includes an Al2O3 layer, a La2O3 layer, a TiO2 layer, or a ZrO2 layer; the charge tunneling layer includes an HfO2 layer; and / or, the thickness of the charge blocking layer is 20–50 nm, the thickness of the charge trapping layer is 10–20 nm, and the thickness of the charge tunneling layer is 3–12 nm.

[0013] Furthermore, the two-dimensional semiconductor layer is n-type, the organic semiconductor layer is p-type, the organic semiconductor layer and the two-dimensional semiconductor layer form a pn junction, the material of the two-dimensional semiconductor layer includes MoS2, MoSe2 or WS2, the material of the organic semiconductor layer includes C8-BTBT, DNTT, pentacene or P3HT, and / or, the thickness of the two-dimensional semiconductor layer is 1-10 nm, and the thickness of the organic semiconductor layer is 20-50 nm.

[0014] Furthermore, the substrate includes a highly doped silicon wafer, which also serves as a back gate electrode; and / or, the source / drain electrodes include stacked metal electrodes, the stacked metal electrodes including a third metal layer and a fourth metal layer stacked together, the third metal layer being made of Cr or Ti, the fourth metal layer being made of Au, Pt, or Pd, the thickness of the third metal layer being 5–15 nm, and the thickness of the fourth metal layer being 30–100 nm.

[0015] This invention also provides a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:

[0016] Provide substrate;

[0017] A charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially formed on the surface of the substrate, and source and drain electrodes are formed at both ends of the channel layer.

[0018] The channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer.

[0019] The heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, as well as band matching regulation, and works in conjunction with the charge trapping layer to complete in-situ calculation and storage of information.

[0020] Furthermore, the method for forming the charge blocking layer, the charge trapping layer, and the charge tunneling layer specifically includes:

[0021] A highly doped silicon wafer is used as the substrate and back gate electrode;

[0022] A thin film layer of ternary metal high-k oxide formed of a first metal element, a second metal element and an oxygen element is formed on the surface of the highly doped silicon wafer as a charge blocking layer.

[0023] A thin film layer of binary metal oxide formed of a second metal element and an oxygen element is formed on the surface of the charge blocking layer as a charge trapping layer;

[0024] A thin film layer of binary metal high-k oxide formed of a first metal element and an oxygen element is formed on the surface of the charge trapping layer as a charge tunneling layer.

[0025] Further, the first metallic element includes Hf, and the second metallic element includes Al, La, Ti, or Zr; wherein:

[0026] Using atomic layer deposition (ALD) technology, HfAlO with a thickness of 20–50 nm is grown on the surface of the highly doped silicon wafer. x Layer, HfLaO x Layer, HfTiO x Layer or HfZrO x A layer is formed to create the charge-blocking layer;

[0027] At room temperature, a physical vapor deposition technique is used to grow an Al2O3 layer, La2O3 layer, TiO2 layer or ZrO2 layer with a thickness of 10-20 nm on the surface of the charge barrier layer to form the charge trapping layer.

[0028] The substrate is heated using a tray-heated physical vapor deposition technique at a temperature of 80–150°C to grow an HfO2 layer with a thickness of 3–12 nm on the surface of the charge trapping layer, thereby forming the charge tunneling layer.

[0029] Furthermore, the method for forming the channel layer specifically includes:

[0030] Oxygen plasma treatment technology is used to treat the surface of the charge tunneling layer with oxygen plasma. The treatment power is 100-200W and the treatment time is 20-120s.

[0031] A MoS2 layer, MoSe2 layer, or WS2 layer with a thickness of 1–10 nm is transferred to the surface of the charge tunneling layer using a mechanical peeling method to form an n-type two-dimensional semiconductor layer.

[0032] Electron beam lithography is used as a mask, and an organic evaporation method is used to grow a C8-BTBT layer, a DNTT layer, a pentacene layer, or a P3HT layer on one end of an n-type two-dimensional semiconductor layer. This forms a p-type organic semiconductor layer with a thickness of 20-50 nm that is connected to one end of the n-type two-dimensional semiconductor layer. As a result, a channel layer based on a pn junction of organic semiconductor and two-dimensional semiconductor is formed on the surface of the charge tunneling layer.

[0033] Furthermore, the method for forming the source and drain electrodes specifically includes:

[0034] Electron beam evaporation technology is used to form stacked metal electrodes on opposite ends of a two-dimensional semiconductor layer and an organic semiconductor layer. The stacked metal electrodes include a lower third metal layer and an upper fourth metal layer stacked together to form source and drain electrodes. The material of the third metal layer includes Cr or Ti, and the material of the fourth metal layer includes Au, Pt or Pd. The thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm.

[0035] As can be seen from the above technical solution, this invention constructs a nanoscale charge-trapping memory device by designing a novel scheme for a neuromorphic optoelectronic memory device based on a pn junction of n-type two-dimensional semiconductors and p-type organic semiconductors. Leveraging the excellent carrier manipulation capabilities of two-dimensional semiconductor and organic semiconductor materials, it achieves efficient charge storage under optical field control, realizing a memory-computing integrated optoelectronic memory device with neuromorphic computing capabilities. This invention has the following advantages:

[0036] (1) Two-dimensional semiconductor materials have atomic-level thickness, which can greatly improve the size miniaturization capability of devices and have the application function of new electronic devices for the post-Moore era.

[0037] (2) The innovative use of two-dimensional semiconductor materials and organic semiconductor materials to construct semiconductor heterojunctions greatly improves the electron-hole separation efficiency of the device under photoelectric excitation and enhances the photoelectric storage capacity of the device.

[0038] (3) Utilizing optoelectronic storage devices to realize neuromorphic computing greatly improves the storage and computing efficiency of the devices, breaks through the traditional bottleneck of separation between storage and computing, and completes in-situ computing and storage of information, which is of great significance for building a new in-situ computing architecture. Attached Figure Description

[0039] Figure 1 is a schematic diagram of the structure of a preferred embodiment of the present invention, which is an optoelectronic in-memory computing device based on a semiconductor heterojunction.

[0040] Figures 2-7 are schematic diagrams of the process flow of a preferred embodiment of the present invention for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction.

[0041] Figure 8 is a schematic diagram illustrating the working principle of an optoelectronic in-memory computing device based on a semiconductor heterojunction according to a preferred embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0043] This invention relates to a heterostructure channel material (forming a channel layer) using a two-dimensional material (forming a two-dimensional semiconductor layer) and an organic material (forming an organic semiconductor layer) to form a neuromorphic electronic device with photoelectric storage effect, suitable for photoelectric neuromorphic computing and applications.

[0044] Traditional silicon-based semiconductor memories are made of silicon-based materials. As their size shrinks, they gradually approach their physical limits, and problems such as leakage current become increasingly apparent, making it difficult to meet the ever-increasing demand for high-density storage. In addition, traditional silicon-based semiconductor memories can only achieve storage through electrical signals, making it difficult to achieve multi-dimensional signal control.

[0045] Two-dimensional (2D) materials, as novel semiconductor materials with atomically thin profiles, exhibit significant size reduction advantages in the post-Moore's Law era, demonstrating potential applications in novel memory devices. As a novel semiconductor channel material, 2D materials can serve as channels for floating-gate memories, simultaneously enabling carrier modulation and photoelectric signal response. Furthermore, by constructing heterostructures between 2D materials and organic semiconductors, bandgap matching modulation can be achieved, further enhancing the storage performance of devices under photoelectric stimulation and providing new insights for novel memory devices.

[0046] Traditional memory can only store "0" and "1" signals, which cannot meet the computing needs of in-memory computing. Inspired by the human brain, storage devices with brain-like computing capabilities can be developed, performing both storage and computation functions on the same device, greatly improving computing efficiency. At the same time, by leveraging the neuromorphic characteristics of the device, intelligent computing tasks such as neuromorphic computing can be performed simultaneously with storage, breaking through the bottlenecks of the traditional von Neumann architecture.

[0047] Traditional semiconductor pn structures require different doping processes to achieve. Leveraging the superior carrier control capabilities of two-dimensional and organic materials, we constructed a heterojunction channel with excellent photoelectric response using n-type two-dimensional semiconductor materials and p-type organic semiconductor materials. This enabled the construction of high-performance optoelectronic memory devices at the nanoscale, extending the signal control mode of memory devices from purely electrical control to optical control, providing a new approach for novel optoelectronic memory devices aimed at miniaturization.

[0048] Furthermore, by designing the stored charge trapping layer, neuromorphic computing characteristics can be realized using the designed storage device, and signal processing and computation can be completed in the storage device. This is of great significance for building a new type of storage and computing integrated storage device, and provides a core device unit for breaking the von Neumann computing paradigm.

[0049] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0050] Referring to Figure 1, an optoelectronic in-memory computing device based on a semiconductor heterojunction according to the present invention includes a charge blocking layer 11, a charge trapping layer 12, a charge tunneling layer 13 and a channel layer 15 sequentially disposed on the surface of a substrate 10, and source / drain electrodes 14 disposed at both ends of the channel layer 15.

[0051] The channel layer 15 includes a two-dimensional semiconductor layer 152 and an organic semiconductor layer 151 simultaneously disposed on the surface of the charge tunneling layer 13. The two-dimensional semiconductor layer 152 and the organic semiconductor layer 151 are connected at one end to form a heterojunction. Source and drain electrodes 14 are respectively disposed on the two-dimensional semiconductor layer 152 and the organic semiconductor layer 151.

[0052] Thus, the heterojunction formed by the two-dimensional semiconductor layer 152 and the organic semiconductor layer 151 serves as the channel layer 15, simultaneously realizing carrier regulation and photoelectric signal response, as well as band matching regulation, and cooperating with the charge trapping layer 12 to complete in-situ calculation and storage of information.

[0053] Referring to Figure 1. In some embodiments, the charge blocking layer 11 material comprises a ternary metal high-k oxide formed of a first metal element, a second metal element, and an oxygen element, i.e., the charge blocking layer 11 comprises a ternary metal high-k oxide layer.

[0054] The charge trapping layer 12 material includes a binary metal oxide formed from a second metal element and an oxygen element, that is, the charge trapping layer 12 includes a binary metal oxide layer.

[0055] The charge tunneling layer 13 material includes a binary metal high-k oxide formed from a first metal element and an oxygen element, that is, the charge tunneling layer 13 includes a binary metal high-k oxide layer.

[0056] In some embodiments, the first metal element includes Hf, and the second metal element includes Al, La, Ti, or Zr.

[0057] In some embodiments, the charge blocking layer 11 includes HfAlO x Layer 111, HfLaO x Layer, HfTiO x Layer or HfZrO x The charge-blocking layer 11 is made of HfAlO. x HfLaO x HfTiO x or HfZrO x .

[0058] The charge trapping layer 12 includes an Al2O3 layer 121, a La2O3 layer, a TiO2 layer, or a ZrO2 layer. That is, the material of the charge trapping layer 12 includes Al2O3, La2O3, TiO2, or ZrO2.

[0059] The charge tunneling layer 13 includes an HfO2 layer 131. That is, the material of the charge tunneling layer 13 includes HfO2.

[0060] In some embodiments, the thickness of the charge blocking layer 11 is 20–50 nm. Preferably, the thickness of the charge blocking layer 11 is approximately 30 nm.

[0061] The thickness of the charge trapping layer 12 is 10–20 nm. Preferably, the thickness of the charge trapping layer 12 is about 15 nm.

[0062] The thickness of the charge tunneling layer 13 is 3–12 nm. Preferably, the thickness of the charge tunneling layer 13 is about 7 nm.

[0063] Referring to Figure 1. In some embodiments, the two-dimensional semiconductor layer 152 is n-type, the organic semiconductor layer 151 is p-type, and the organic semiconductor layer 151 and the two-dimensional semiconductor layer 152 form a pn junction.

[0064] In some embodiments, the material of the two-dimensional semiconductor layer 152 includes MoS2, MoSe2 or WS2, that is, the n-type two-dimensional semiconductor layer 152 includes an n-type MoS2 layer 1521, an n-type MoSe2 layer or an n-type WS2 layer.

[0065] The organic semiconductor layer 151 material includes C8-BTBT, DNTT, pentacene, or P3HT, that is, the p-type organic semiconductor layer 151 material includes p-type C8-BTBT layer 1511, p-type DNTT layer, p-type pentacene layer, or p-type P3HT layer.

[0066] In some embodiments, the thickness of the two-dimensional semiconductor layer 152 is 1 to 10 nm. Preferably, the thickness of the two-dimensional semiconductor layer 152 is about 3 nm.

[0067] The thickness of the organic semiconductor layer 151 is 20–50 nm. Preferably, the thickness of the organic semiconductor layer 151 is about 30 nm.

[0068] Referring to Figure 1. In some embodiments, the substrate 10 includes a highly doped silicon wafer 101. Furthermore, the highly doped silicon wafer 101 also serves as a back gate electrode (connected to V). gate ).

[0069] In some embodiments, the source / drain electrodes 14 include a source electrode disposed at one end of the channel layer 15 and a drain electrode disposed at the other end of the channel layer 15. For example, the source electrode 141 (connected to V) S The drain electrode 142 is disposed on the outer end (right end shown in the figure) of the organic semiconductor layer 151 and grounded; D It is disposed on the outer end (left end shown in the figure) of the two-dimensional semiconductor layer 152, thereby forming an optoelectronic storage device.

[0070] In some embodiments, the source and drain electrodes 14 (source electrode 141 and drain electrode 142) include a multilayer metal electrode, which includes a third metal layer and a fourth metal layer stacked on top of each other. The third metal layer is in contact with the surface of the channel layer 15, and the fourth metal layer is stacked on the surface of the third metal layer.

[0071] In some embodiments, the third metal layer material includes Cr or Ti, and the fourth metal layer material includes Au, Pt, or Pd.

[0072] In some embodiments, the thickness of the third metal layer is 5–15 nm. Preferably, the thickness of the third metal layer is approximately 10 nm.

[0073] The thickness of the fourth metal layer is 30–100 nm. Preferably, the thickness of the fourth metal layer is about 50 nm.

[0074] The aforementioned two-dimensional semiconductor materials, with atomic-level thickness, can significantly improve the miniaturization capability of devices, enabling applications in novel electronic devices for the post-Moore's Law era. Constructing semiconductor heterojunctions using two-dimensional and organic semiconductor materials can greatly improve the electron-hole separation efficiency under photoelectric excitation, enhancing the device's photoelectric storage capacity. Utilizing photoelectric storage devices for neuromorphic computing can significantly improve the device's in-memory computing efficiency, breaking through the traditional bottleneck of separating storage and computation, and achieving in-situ computation and storage of information, which is of great significance for constructing novel in-memory computing architectures.

[0075] The following detailed description, in conjunction with specific embodiments and accompanying drawings, provides a further detailed explanation of a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction according to the present invention.

[0076] The present invention discloses a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:

[0077] Provide substrate;

[0078] A charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially formed on the surface of the substrate, and source and drain electrodes are formed at both ends of the channel layer.

[0079] The channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer.

[0080] The heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer can simultaneously achieve carrier control and photoelectric signal response, as well as band matching control, and cooperate with the charge trapping layer to complete in-situ calculation and storage of information.

[0081] Referring to Figures 2-7, in some embodiments, a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction according to the present invention includes the following steps:

[0082] Step S1: Form a charge blocking layer 11 on the surface of substrate 10.

[0083] As shown in Figure 2, a highly doped silicon wafer 101 is used as the substrate 10 and the back gate electrode.

[0084] A ternary high-k oxide ternary metal layer, composed of a first metal element, a second metal element, and an oxygen element, is formed on the surface of a highly doped silicon wafer 101 as a charge blocking layer 11. Further, the first metal element includes Hf, and the second metal element includes Al, La, Ti, or Zr.

[0085] In some embodiments, atomic layer deposition is used to grow HfAlO with a thickness of 20–50 nm on the surface of a highly doped silicon wafer 101. x Layer 111, HfLaO x Layer, HfTiO x Layer or HfZrO x The layer serves as a charge-blocking layer 11.

[0086] In this embodiment, atomic layer deposition (ALD) is used to grow a ternary high-k oxide HfAlO with a thickness of approximately 30 nm on the surface of a highly doped silicon wafer 101. x Layer 111 forms a charge blocking layer 11.

[0087] Step S2: Form a charge trapping layer 12 on the surface of the charge blocking layer 11.

[0088] As shown in Figure 3, a thin film layer of binary metal oxide formed by a second metal element (Al, La, Ti or Zr) and an oxygen element is then formed on the surface of the charge blocking layer 11 as the charge trapping layer 12.

[0089] In some embodiments, at room temperature, a 10-20 nm thick Al₂O₃ layer 121, La₂O₃ layer, TiO₂ layer, or ZrO₂ layer is grown on the surface of the charge barrier layer 11 using physical vapor deposition (PVD) as the charge trapping layer 12. The elements in the charge trapping layer 12 material must be consistent with the remaining elements in the ternary high-k oxide of the charge barrier layer 11 after removing the first metal element to achieve high-quality interface growth. For example, when the charge barrier layer 11 material is HfAlO₂... x When the charge trapping layer 12 is made of Al2O3, the charge blocking layer 11 is made of HfLaO. x When the charge trapping layer 12 is made of La2O3, the charge blocking layer 11 is made of HfTiO. x When the charge trapping layer 12 is TiO2, the charge blocking layer 11 is HfZrO. x At that time, the charge trapping layer 12 material is ZrO2.

[0090] In this embodiment, physical vapor deposition (PVD) is used at room temperature to deposit HfAlO xA binary metal oxide Al2O3 layer 121 with a thickness of about 15 nm is grown on the surface of the charge blocking layer 11 to form a charge trapping layer 12.

[0091] Step S3: Form a charge tunneling layer 13 on the surface of the charge trapping layer 12.

[0092] As shown in Figure 4, a thin film layer of binary metal high-k oxide formed of a first metal element and an oxygen element is then formed on the surface of the charge trapping layer 12 as the charge tunneling layer 13.

[0093] In some embodiments, a tray-heated physical vapor deposition technique is used to heat the substrate 10 to a temperature of 80–150°C, and an HfO2 layer 131 with a thickness of 3–12 nm is grown on the surface of the charge trapping layer 12 to form a charge tunneling layer 13.

[0094] In this embodiment, the substrate 10 is heated using a tray-heated physical vapor deposition technique. The heating temperature is set to 100°C, and a binary metal high-k oxide HfO2 layer 131 with a thickness of about 7 nm is grown on the surface of the Al2O3 charge trapping layer 12 to form a charge tunneling layer 13.

[0095] Step S4: Form an n-type two-dimensional semiconductor layer 152 on the surface of the charge tunneling layer 13.

[0096] Before forming an n-type two-dimensional semiconductor layer 152 on the surface of the charge tunneling layer 13, the surface of the charge tunneling layer 13 can be treated to improve the interface quality of the charge tunneling layer 13.

[0097] As shown in Figure 5, in some embodiments, oxygen plasma treatment technology is used to treat the surface of the charge tunneling layer 13 with oxygen plasma. The treatment power during oxygen plasma treatment is 100–200 W, and the treatment duration is 20–120 s.

[0098] Subsequently, a mechanical peeling method is used to transfer a MoS2 layer 1521, MoSe2 layer or WS2 layer with a thickness of 1 to 10 nm as an n-type semiconductor material in the channel onto the surface of the charge tunneling layer 13 to form an n-type two-dimensional semiconductor layer 152.

[0099] In this embodiment, the HfO2 charge tunneling layer 13 is treated for about 40 seconds using oxygen plasma formed by oxygen at a power of 150W. Then, a MoS2 layer 1521 with a thickness of about 3nm is transferred onto the surface of the HfO2 charge tunneling layer 13 by mechanical peeling to form an n-type two-dimensional semiconductor layer 152.

[0100] Step S5: A p-type organic semiconductor layer 151 is formed on one end of the n-type two-dimensional semiconductor layer 152 to form a channel layer 15.

[0101] As shown in Figure 6, in some embodiments, electron beam lithography is used as a mask to define the working area of ​​the pn junction. A photoresist protection method is employed, and an organic vapor deposition method is used to grow a C8-BTBT layer 1511, a DNTT layer, a pentacene layer, or a P3HT layer on one end of the n-type two-dimensional semiconductor layer 152. This forms a p-type organic semiconductor layer 151 with a thickness of 20–50 nm, connected at one end to the n-type two-dimensional semiconductor layer 152. The p-type organic semiconductor layer 151 is also simultaneously formed on the surface of the charge tunneling layer 13. Thus, a channel layer 15 based on the pn junction of the organic semiconductor and the two-dimensional semiconductor (p-type organic semiconductor layer 151 and n-type two-dimensional semiconductor layer 152) is formed on the surface of the charge tunneling layer 13.

[0102] In some embodiments, the p-type organic semiconductor layer 151 is disposed along the length extension direction of the n-type two-dimensional semiconductor layer 152 and is connected to one end of the n-type two-dimensional semiconductor layer 152.

[0103] In this embodiment, electron beam lithography is used to define the working area of ​​the pn junction. Photoresist is used for protection. P-type organic semiconductor material C8-BTBT is grown on the surface of HfO2 charge tunneling layer 13 and one end of n-type MoS2 two-dimensional semiconductor layer 152 using organic evaporation equipment. The thickness is controlled at about 30nm to form C8-BTBT layer 1511, which serves as p-type organic semiconductor layer 151, thus constructing a pn junction channel based on n-type two-dimensional material and p-type organic material.

[0104] Step S6: Prepare source and drain electrodes 14.

[0105] As shown in Figure 7, in some embodiments, electron beam evaporation technology is used to form stacked metal electrodes on the left and right ends of the n-type two-dimensional semiconductor layer 152 and the p-type organic semiconductor layer 151, which are opposite to each other. The stacked metal electrodes include a lower third metal layer and an upper fourth metal layer, forming source and drain electrodes 14. The material of the third metal layer includes Cr or Ti, and the material of the fourth metal layer includes Au, Pt, or Pd. The thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm.

[0106] In this embodiment, electron beam evaporation is used to grow Cr / Au stacked metal electrodes on the surfaces of the n-type MoS2 two-dimensional semiconductor layer 152 and the p-type C8-BTBT organic semiconductor layer 151, which are opposite to each other. A source electrode 141 is formed on the surface of the p-type C8-BTBT organic semiconductor layer 151, and a drain electrode 142 is formed on the surface of the n-type MoS2 two-dimensional semiconductor layer 152. The source electrode 141 and the drain electrode 142 together form the source-drain electrode 14. The thickness of the Cr third metal layer is about 10 nm, and the thickness of the Au fourth metal layer is about 50 nm.

[0107] Therefore, the method for fabricating a semiconductor heterojunction-based opto-in-memory computing device according to the present invention described above can be used to fabricate, for example, the semiconductor heterojunction-based opto-in-memory computing device shown in FIG1. ​​In other words, the semiconductor heterojunction-based opto-in-memory computing device shown in FIG1 can be fabricated using the method for fabricating a semiconductor heterojunction-based opto-in-memory computing device according to the present invention described above, for example, in FIG2-7.

[0108] Referring to Figure 8. When V is connected to the highly doped silicon wafer 101 (back gate electrode) of the device in Figure 1 above. gate The voltage (gate voltage) is connected to the drain electrode 142 at one end of the MoS2 two-dimensional semiconductor layer 152. D Voltage (drain voltage), and ground the source electrode 141 at one end of the C8-BTBT organic semiconductor layer 151 (source voltage V). S To form a storage-in-memory optoelectronic storage device with neuromorphic computing capabilities, light pulses are applied to a pn junction (a channel layer 15 composed of a MoS2 two-dimensional semiconductor layer 152 and a C8-BTBT organic semiconductor layer 151) constructed from two-dimensional and organic materials. This achieves efficient electron-hole pair separation, which then enters the Al2O3 charge trapping layer 12 under voltage excitation, resulting in high-performance optoelectronic storage. Brain-like computing is achieved by utilizing the changing resistance value of the optoelectronic storage device, thus completing the storage-in-memory application under optoelectronic excitation.

[0109] In summary, this invention constructs a nanoscale charge-trapping memory device by designing a novel scheme for a neuromorphic optoelectronic memory device based on a pn junction of an n-type two-dimensional semiconductor and a p-type organic semiconductor. By leveraging the excellent carrier modulation capabilities of two-dimensional semiconductor materials and organic semiconductor materials, it achieves efficient charge storage under optical field modulation, thereby realizing a memory-computing integrated optoelectronic memory device with neuromorphic computing capabilities.

[0110] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A semiconductor heterojunction-based optoelectronic in-memory device, comprising: Comprise: A charge blocking layer, a charge trapping layer, a charge tunneling layer and a channel layer are sequentially arranged on the surface of a substrate, and source-drain electrodes are arranged on both ends of the channel layer; The channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are arranged on the two-dimensional semiconductor layer and the organic semiconductor layer respectively; Wherein, the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, realizes energy band matching regulation, and cooperates with the charge trapping layer to complete in-situ calculation and storage of information.

2. The semiconductor heterojunction based optoelectronic in-memory device of claim 1, wherein, The charge blocking layer material comprises a ternary metal high-k oxide formed by a first metal element, a second metal element and an oxygen element, the charge trapping layer material comprises a binary metal oxide formed by a second metal element and an oxygen element, and the charge tunneling layer material comprises a binary metal high-k oxide formed by a first metal element and an oxygen element.

3. The semiconductor heterojunction based optoelectronic in-memory device of claim 2, wherein, the first metal element comprises Hf, the second metal element comprises Al, La, Ti or Zr, and the charge blocking layer comprises HfAlO x layer, HfLaO x layer, HfTiO x layer or HfZrO x layer, the charge trapping layer comprises an Al2O3 layer, a La2O3 layer, a TiO2 layer or a ZrO2 layer, the charge tunneling layer comprises a HfO2 layer, and / or the thickness of the charge blocking layer is 20-50 nm, the thickness of the charge trapping layer is 10-20 nm, and the thickness of the charge tunneling layer is 3-12 nm.

4. The semiconductor heterojunction based optoelectronic memory and computing integrated device of claim 1, wherein, The two-dimensional semiconductor layer is n-type, the organic semiconductor layer is p-type, the organic semiconductor layer and the two-dimensional semiconductor layer form a pn junction, the two-dimensional semiconductor layer material comprises MoS2, MoSe2 or WS2, the organic semiconductor layer material comprises C8-BTBT, DNTT, pentacene or P3HT, and / or the thickness of the two-dimensional semiconductor layer is 1-10 nm, and the thickness of the organic semiconductor layer is 20-50 nm.

5. The semiconductor heterojunction based optoelectronic memory and computing integrated device of claim 1, wherein The substrate comprises a highly doped silicon wafer which also serves as a back gate electrode; and / or the source-drain electrodes comprise a laminated metal electrode, the laminated metal electrode comprises a third metal layer and a fourth metal layer arranged in layers, the third metal layer material comprises Cr or Ti, the fourth metal layer material comprises Au, Pt or Pd, the thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm. 6.A method for preparing a semiconductor heterojunction-based optoelectronic in-memory device, characterized in that, Comprise: A substrate is provided; A charge blocking layer, a charge trapping layer, a charge tunneling layer and a channel layer are sequentially formed on the surface of the substrate, and source-drain electrodes are formed on both ends of the channel layer; Wherein, the channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end and forming a heterojunction, and the source-drain electrodes are arranged on the two-dimensional semiconductor layer and the organic semiconductor layer respectively; Wherein, the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, realizes energy band matching regulation, and cooperates with the charge trapping layer to complete in-situ calculation and storage of information.

7. The method of claim 6, wherein the semiconductor heterojunction-based optoelectronic in-memory computing device is prepared by the steps of: providing a substrate; forming a first semiconductor layer on the substrate; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; and forming a fourth semiconductor layer on the third semiconductor layer. The method for forming the charge blocking layer, the charge trapping layer and the charge tunneling layer comprises specifically: A highly doped silicon wafer is used as a substrate and a back gate electrode; A thin film layer of a ternary metal high-k oxide formed by a first metal element, a second metal element and an oxygen element is formed on the surface of the highly doped silicon wafer as a charge blocking layer; A thin film layer of a binary metal oxide formed by a second metal element and an oxygen element is formed on the surface of the charge blocking layer as a charge trapping layer; A thin film layer of binary metal high-k oxide formed by a first metal element and an oxygen element is formed on the surface of the charge trapping layer as a charge tunneling layer.

8. The method of claim 7, wherein the semiconductor heterojunction-based optoelectronic in-memory computing device is prepared by the steps of: providing a substrate; forming a first semiconductor layer on the substrate; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; and forming a fourth semiconductor layer on the third semiconductor layer. The first metal element comprises Hf, and the second metal element comprises Al, La, Ti or Zr; wherein: A thickness of 20-50nm of HfAlO x layer, HfLaO x layer, HfTiO x layer or HfZrO x layer, forming the charge blocking layer; At room temperature, a 10-20 nm thick Al2O3 layer, La2O3 layer, TiO2 layer or ZrO2 layer is grown on the surface of the charge blocking layer by physical vapor deposition, forming the charge trapping layer; The substrate is heated by a tray heating type physical vapor deposition technology, and a 3-12 nm thick HfO2 layer is grown on the surface of the charge trapping layer by heating at a temperature of 80-150 DEG C, forming the charge tunneling layer.

9. The method of claim 8, wherein the semiconductor heterojunction-based optoelectronic in-memory computing device is prepared by the steps of: providing a substrate; forming a first semiconductor layer on the substrate; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; and forming a fourth semiconductor layer on the third semiconductor layer. The method for forming the channel layer specifically comprises: The surface of the charge tunneling layer is treated by oxygen plasma using an oxygen plasma treatment technology, and the treatment power is 100-200 W and the treatment time is 20-120 s; A 1-10 nm thick MoS2 layer, MoSe2 layer or WS2 layer is transferred on the surface of the charge tunneling layer by a mechanical exfoliation method, forming an n-type two-dimensional semiconductor layer; C8-BTBT, DNTT, pentacene or P3HT is grown on one end of the n-type two-dimensional semiconductor layer by electron beam lithography as a mask and an organic evaporation method, forming a 20-50 nm thick p-type organic semiconductor layer connected to one end of the n-type two-dimensional semiconductor layer through the one end, thereby forming a channel layer based on an organic semiconductor and two-dimensional semiconductor pn junction on the surface of the charge tunneling layer.

10. The method of claim 6, wherein the semiconductor heterojunction-based optoelectronic in-memory computing device is prepared by the steps of: The method for forming the source-drain electrode specifically comprises: ​ A stacked metal electrode is formed on the two ends of the two-dimensional semiconductor layer and the organic semiconductor layer away from each other by electron beam evaporation, so that the stacked metal electrode comprises a lower third metal layer and an upper fourth metal layer arranged in layers, forming a source-drain electrode; wherein the third metal layer material comprises Cr or Ti, the fourth metal layer material comprises Au, Pt or Pd, the thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm.

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