Display panel and display apparatus

Abstract

Disclosed in the present application are a display panel and a display apparatus. The display panel comprises a first display area, a second display area and a plurality of signal lines, wherein a plurality of first pixel circuits and a plurality of light-transmitting portions located between the plurality of first pixel circuits are disposed in the first display area, a plurality of second pixel circuits are disposed in the second display area, each signal line is connected to a row of second pixel circuits, and at least two signal lines transmitting the same control signal are connected to a plurality of identical first pixel circuits.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly relates to a display panel and a display device. BACKGROUND

[0002] In a camera under panel (CUP) technology of an organic light-emitting diode (OLED) display panel, the distribution density of pixel driving circuits in a camera under panel area is usually less than the distribution density of pixel driving circuits in a display area, so that some signal lines for transmitting control signals in the display area on both sides of the camera under panel area are directly connected horizontally, which do not avoid the camera under panel area, and the horizontally connected signal lines occupy the area of part of the light transmission area in the camera under panel area, so that the area of the light transmission area in the camera under panel area is reduced, and the infrared transmittance of the camera under panel area cannot meet the standard. SUMMARY

[0003] The present application provides a display panel and a display device to improve the problem that the light transmission area of the camera under panel area of the existing display panel is small.

[0004] To solve the above-mentioned solution, the technical solution provided by the present application is as follows:

[0005] The present application provides a display panel, which comprises:

[0006] a first display area, which is internally provided with a plurality of first pixel circuits and a plurality of light transmission parts, and the plurality of light transmission parts are located between the plurality of first pixel circuits;

[0007] a second display area, which is located at the periphery of the first display area and is internally provided with a plurality of second pixel circuits; and

[0008] a plurality of signal lines, each of the signal lines is connected with a row of the second pixel circuits, and at least two signal lines for transmitting the same control signal are connected with a plurality of the same first pixel circuits.

[0009] The present application further provides a display device, which comprises the above-mentioned display panel. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a first structure diagram of the display panel of the present application;

[0011] FIG. 2 is a first structure diagram of the region AA in FIG. 1;

[0012] FIG. 3 is a second structure diagram of the region AA in FIG. 1;

[0013] Fig. 4 is an equivalent circuit diagram of the second pixel circuit and the first pixel circuit in the display panel of the present application;

[0014] Fig. 5 is a circuit diagram of the first circuit in the display panel of the present application;

[0015] Fig. 6 is a circuit diagram of the second circuit in the display panel of the present application;

[0016] Fig. 7 is a circuit diagram of the third circuit in the display panel of the present application;

[0017] Fig. 8 is a schematic diagram of the film layers of the display panel of the present application;

[0018] Fig. 9 is a film layer stack diagram of the second pixel circuit in the display panel of the present application;

[0019] Fig. 10 is a film layer stack diagram of the first pixel circuit in the display panel of the present application;

[0020] Fig. 11 is a first film layer stack diagram of the first main part and the functional subpart of the region CC in Fig. 1;

[0021] Fig. 12 is a second film layer stack diagram of the first main part and the functional subpart of the region DD in Fig. 11;

[0022] Fig. 13 is a third film layer stack diagram of the first main part and the functional subpart of the region DD in Fig. 11;

[0023] Fig. 14 is a connection diagram of the first main reset line and the first auxiliary reset line of the region BB in Fig. 1;

[0024] Fig. 15 is a connection diagram of the second main reset line and the second auxiliary reset line of the region BB in Fig. 1;

[0025] Fig. 16 is a connection diagram of the third main reset line and the third auxiliary reset line of the region BB in Fig. 1. Embodiments of the present application

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0027] In the description of the present application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0028] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, at least one of which can be one, two or more, unless otherwise explicitly specified.

[0029] Referring to FIG. 1, the present application provides a display panel 100, which includes a first display area 300, a second display area 400 located at the periphery of the first display area 300, and a non-display area 200 located at one side of the second display area 400.

[0030] In some embodiments of the present application, a plurality of signal lines connected to the pixel circuit are provided in the second display area 400 and the first display area 300. Since the first display area 300 is provided with a light-transmitting portion 300b, part of the signal lines will cross the light-transmitting portion 300b in the first display area 300, occupying the area of the light-transmitting portion 300b, so that the effective light-transmitting area in the light-transmitting portion 300b is reduced, for example, the structure of FIG. 2.

[0031] Referring to FIG. 3, a plurality of first pixel circuits 310 and a plurality of light-transmitting portions 300b located between the plurality of first pixel circuits 310 are provided in the first display area 300, and a plurality of second pixel circuits 410 are provided in the second display area 400. Each of the signal lines is connected to a row of the second pixel circuits 410, and at least two signal lines transmitting the same control signal are connected to a plurality of the same first pixel circuits 310.

[0032] The present application avoids the signal lines directly crossing the first display area 300 by electrically connecting at least two signal lines transmitting the same control signal to a plurality of the same first pixel circuits 310, thereby reducing the area of the light-transmitting region occupied by the signal lines in the first display area 300, and further increasing the area of the light-transmitting region in the first display area 300.

[0033] It should be noted that, referring to FIG. 3, the first display area 300 can be provided with a plurality of functional sub-sections 300a and a plurality of light-transmitting sections 300b between the plurality of functional sub-sections 300a, each functional sub-section 300a including a plurality of first pixel circuits 310 and a group of auxiliary signal lines 320, the group of auxiliary signal lines 320 being connected to the corresponding plurality of first pixel circuits 310, and each group of auxiliary signal lines 320 including at least one auxiliary signal line.

[0034] It should be noted that, referring to FIG. 3, the second display area 400 can be provided with a plurality of first main sections 400a, each first main section 400a including at least two rows of second pixel circuits 410 arranged along the first direction X and a group of main signal lines 420, each group of main signal lines 420 being connected to a corresponding row of second pixel circuits 410, and each group of main signal lines 420 including at least one main signal line, and a functional sub-section 300a corresponding to a first main section 400a.

[0035] For example, in the functional sub-section 300a and the first main section 400a corresponding to the functional sub-section 300a, at least two main signal lines in the first main section 400a transmitting the same control signal are electrically connected to the parallel node with the auxiliary signal line in the functional sub-section 300a transmitting the same control signal, avoiding the main signal lines in the first main section 400a transmitting the same control signal crossing the functional sub-section 300a, which is equivalent to increasing the area of the light-transmitting section in the functional sub-section 300a.

[0036] It should be noted that, since there are a plurality of main signal lines transmitting different control signals across the signal lines in the first display area 300, the technical solution of the present application can electrically connect the main signal line corresponding to at least one control signal to the corresponding auxiliary signal line to avoid the light-transmitting section 300b in the first display area 300.

[0037] It should be noted that the display panel 100 can include a plurality of first display areas 300, and the shape of each first display area 300 in the top view is not limited to a circle, a rectangle, or a rounded rectangle; for example, in the structure of FIG. 1, the display panel 100 can include one first display area 300.

[0038] It should be noted that, in the structure of FIG. 3, the first display area 300 is provided with a plurality of first main sections 400a on both sides in the first direction X.

[0039] It should be noted that a first main part 400a corresponds to a functional subpart 300a, and the first main part 400a has at least two rows of second pixel circuits 410, and the functional subpart 300a has only one row of first pixel circuits 310, so that the present application reduces the number of rows of first pixel circuits 310 in the first display area 300 to improve the light transmittance of the first display area 300. For example, in the structure of FIG. 3, a first main part 400a has two rows of second pixel circuits 410, and a functional subpart 300a has one row of first pixel circuits 310, that is, one row of first pixel circuits 310 corresponds to two rows of second pixel circuits 410.

[0040] It should be noted that the number of light emitting devices connected to the first pixel circuit 310 in the first display area 300 is reduced due to the reduction in the number of rows of first pixel circuits 310, which in turn results in the resolution of the first display area 300 being less than the resolution of the second display area 400, so that the present application can increase the number of light emitting devices connected to the first pixel circuit 310 to improve the difference in resolution between the first display area 300 and the second display area 400.

[0041] For example, the first display area 300 can include a plurality of first light emitting devices 330, the second display area 400 further includes a plurality of second light emitting devices 430, and a second pixel circuit 410 is electrically connected to a second light emitting device 430, and a first pixel circuit 310 is electrically connected to two first light emitting devices 330; one first pixel circuit 310 in the first display area 300 is electrically connected to two first light emitting devices 330, which improves the resolution of the first display area 300.

[0042] It should be noted that since a first pixel circuit 310 is electrically connected to two first light emitting devices 330, in order to avoid the light emitting devices occupying a larger area of the light transmissive part 300b, the area of the first light emitting device 330 of the present application is smaller than the area of the second light emitting device 430.

[0043] It should be noted that in order to avoid the arrangement of the first pixel circuit 310 in the first display area 300 occupying a larger area of the light transmissive part 300b, the plurality of first pixel circuits 310 of the present application are arranged in the form of a pixel island 340, and are spaced apart between adjacent two pixel islands 340, and the structure of each first pixel circuit 310 is the same; for example, in the structure of FIGS. 11-13, one pixel island 340 can include three first pixel circuits 310 gathered together, and the light emitting colors of the six first light emitting devices 330 connected to each pixel island 340 can be two red light emitting devices, two green light emitting devices, and two blue light emitting devices.

[0044] It should be noted that the plurality of pixel islands 340 of the present application can have two arrangement modes. The first arrangement mode can be that the plurality of pixel islands 340 are arranged in an array along the first direction X and the second direction Y, that is, the plurality of pixel islands 340 are arranged in rows and columns along the first direction X and the second direction Y, that is, each auxiliary control line can be connected to a row of first pixel circuits 310. Alternatively, the plurality of pixel islands 340 of the present application can be arranged along the first direction X to form a plurality of pixel island rows, and the pixel islands 340 in adjacent two rows are arranged in a staggered manner, that is, each auxiliary control line can be connected to two rows of first pixel circuits 310 arranged in a staggered manner.

[0045] It should be noted that, in order to increase the area of the light transmission part 300b, the area of any first pixel circuit 310 is smaller than the area of any second pixel circuit 410, that is, the area occupied by the first pixel circuit 310 in the first display area 300 is further reduced.

[0046] Please refer to FIGS. 11-13, the second display area 400 is provided with a plurality of second pixel circuits 410, and in the first main part 400a, adjacent two second pixel circuits 410 arranged along the first direction X are symmetrically arranged with the center line of the adjacent two second pixel circuits 410 as the axis, that is, the present application is not limited to compact, so that the adjacent two second pixel circuits 410 are symmetrically arranged, and the structures of the second pixel circuits 410 in the same column are the same.

[0047] Please refer to FIGS. 11-13, since a row of first pixel circuits 310 corresponds to two rows of second pixel circuits 410, the present application can arrange the row of first pixel circuits 310 between the two rows of second pixel circuits 410 corresponding to the intersection line of the adjacent two rows of second pixel circuits 410, and the center line parallel to the first direction X in the corresponding first pixel circuit 310 can coincide, or the difference between the extension line and the center is within a predetermined range.

[0048] It should be noted that although the number of first pixel circuits 310 in the first display area 300 of the present application is reduced, since the area occupied by the first pixel circuit 310 is reduced, the sum of the second pixel circuit 410 and the first pixel circuit 310 in a row of pixel circuits of the present application is not reduced; for example, in the second display area 400 without the first pixel circuit 310, the number of a row of second pixel circuits 410 is a0, in the sub-pixel row provided with the first pixel circuit 310, the number of second pixel circuits 410 in the sub-pixel row is a1, and the number of first pixel circuits 310 is a2, then the sum of a1 and a2 is equal to a0.

[0049] Similarly, since one first pixel circuit 310 can be connected with two first light emitting devices 330, the area of the light emitting region in the first display area 300 is reduced, but the number of light emitting units per unit area in the first display area 300 is equal to the number of light emitting units per unit area in the second display area 400.

[0050] It should be noted that the first display area 300 can correspond to a sensor, and the sensor receives light introduced from the light-transmitting part 300b in the first display area 300 to generate a corresponding voltage or current signal, etc. For example, the sensor includes a fingerprint identification sensor, a camera, a structured light sensor, a time-of-flight sensor, a distance sensor, a light sensor, etc. The sensor can collect signals through the light-transmitting part 300b, so that the display panel 100 realizes an under-screen fingerprint identification, an under-screen camera, an under-screen face recognition, an under-screen distance sensing, etc. under-screen sensing scheme.

[0051] It should be noted that the first light emitting device 330 and the second light emitting device 430 can be organic light emitting diodes, Mini LEDs, Micro LEDs, conventional size LEDs or other light emitting sources.

[0052] It should be noted that the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X can be the transverse direction of the non-display area 200 to the display part, and the second direction Y can be the longitudinal direction. The angle between the first direction X and the second direction Y can be 90°.

[0053] The technical solutions of the present application will be described in conjunction with specific embodiments.

[0054] Please refer to FIG. 1 and FIG. 3, the lower side of the second display area 400 is provided with a binding terminal 500, which can be connected with an external circuit. The binding terminal 500 transmits the signal input by the external circuit to the data trace, so as to drive the display panel 100 to display a picture. For example, the binding terminal 500 can be connected with a chip or a chip on film, etc. for providing power supply and driving signal for the display panel 100, etc.

[0055] In the embodiment, the second pixel circuit 410 and the first pixel circuit 310 can be 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. pixel circuit. In the following embodiment, an 8T2C pixel circuit is taken as an example for description.

[0056] Referring to FIG. 4, the second pixel circuit 410 and the first pixel circuit 310 can each include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light emitting transistor T5, a second light emitting transistor T6, a boost capacitor Cboost, and a storage capacitor Cst including a first plate Cst1 and a second plate Cst2, the boost capacitor Cboost including a third plate and a fourth plate.

[0057] Referring to FIG. 4, a first electrode of the switching transistor T2 is connected to a data signal line Data, a second electrode of the switching transistor T2 is connected to a first node A1, and a gate of the switching transistor T2 receives a switching control signal Pscan1; a first electrode of the driving transistor T1 is connected to the first node A1, a second electrode of the driving transistor T1 is connected to a second node B1, and a gate of the driving transistor T1 is connected to a third node Q1; a first electrode of the compensation transistor T3 is connected to the third node Q1, a second electrode of the compensation transistor T3 is connected to the second node B1, and a gate of the compensation transistor T3 receives a compensation control signal Nscan1; a first electrode of the first reset transistor T4 receives a first reset signal Vi1, a second electrode of the first reset transistor T4 is connected to the third node Q1, and a gate of the first reset transistor T4 receives a first reset control signal Nscan2; a first electrode of the second reset transistor T7 receives a second reset signal Vi2, a second electrode of the second reset transistor T7 is connected to a fourth node, i.e., an anode of a light emitting device, and a gate of the second reset transistor T7 receives a second reset control signal Pscan2; a first electrode of the third reset transistor T8 receives a third reset signal Vi3, a second electrode of the third reset transistor T8 is connected to the first node A1, and a gate of the third reset transistor T8 receives a third reset control signal; a first electrode of the first light emitting transistor T5 is connected to a high potential line VDD, a second electrode of the first light emitting transistor T5 is connected to the first node A1, and a gate of the first light emitting transistor T5 receives a light emitting control signal EM; a first electrode of the second light emitting transistor T6 is connected to the second node B1, a second electrode of the second light emitting transistor T6 is connected to the fourth node D1, and a gate of the second light emitting transistor T6 receives the light emitting control signal EM; a third plate of the boost capacitor Cboost is connected to the third node Q1, and a fourth plate of the boost capacitor Cboost is connected to the gate of the switching transistor T2; a first plate of the storage capacitor Cst is connected to the third node Q1, and a second plate of the storage capacitor Cst is connected to the high potential line VDD; and a cathode of the light emitting device is connected to a low potential line VSS.

[0058] In the embodiment, the high potential line VDD is used to provide a constant voltage high level to the second pixel circuit 410 or the first pixel circuit 310, and the low potential line VSS is used to provide a constant voltage low level to the second pixel circuit 410 or the first pixel circuit 310.

[0059] In the embodiment, the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light emitting transistor T5, and the second light emitting transistor T6 can be one of a P-type transistor or an N-type transistor, and the compensation transistor T3 and the first reset transistor T4 can be the other one of a P-type transistor or an N-type transistor. The present application is described by taking the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light emitting transistor T5, and the second light emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0060] In the embodiment, the capacitance value of the boost capacitor Cboost is smaller than the capacitance value of the storage capacitor Cst. In the embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the third node Q1, and thus the storage capacitor Cst has a relatively large capacitance, for example, the capacitance value of the storage capacitor Cst can range from 45 fF to 55 fF, and the capacitance value of the boost capacitor Cboost can range from 5 fF to 15 fF.

[0061] In the embodiment, the first electrode can be one of a source electrode or a drain electrode, and the second electrode can be the other one of the source electrode or the drain electrode.

[0062] Referring to FIGS. 1 and 3, the non-display area 200 includes two non-display sub-areas 210 located on both sides of the second display area 400, and the two non-display sub-areas 210 are each provided with a gate drive circuit, and an output end of the gate drive circuit is connected with at least one of the signal lines.

[0063] In the embodiment, the gate drive circuit can include gate circuits outputting different control signals, and the types of the gate circuits in the non-display area 200 are related to the second pixel circuit 410 or the first pixel circuit 310, for example, the second pixel circuit 410 or the first pixel circuit 310 needs compensation control signals Nscan1, first reset control signals Nscan2, second reset control signals Pscan2, light emitting control signals EM, and switch control signals Pscan1, and thus five types of gate circuits outputting the above control signals need to be provided in the non-display area 200 of the present application.

[0064] In the structure of FIG. 3 and FIG. 9, the second display area 400 can be provided with a main compensation control line 421 constituting a main signal line group 420, a first main reset control line 422, a second main reset control line 423, a main light-emitting control line 424, a main switch control line 425, a first main reset line 426, a second main reset line 427, and a third main reset line 428.

[0065] In the structure of FIG. 3 and FIG. 10, the first display area 300 can be provided with an auxiliary compensation control line 321 constituting an auxiliary signal line group 320, a first auxiliary reset control line 322, a second auxiliary reset control line 323, an auxiliary light-emitting control line 324, an auxiliary switch control line 325, a first auxiliary reset line 326, a second auxiliary reset line 327, and a third auxiliary reset line 328.

[0066] In the present embodiment, the auxiliary compensation control line 321 and the main compensation control line 421 are used to transmit a compensation control signal Nscan1, the first auxiliary reset control line 322 and the first main reset control line 422 are used to transmit a first reset control signal Nscan2, the second auxiliary reset control line 323 and the second main reset control line 423 are used to transmit a second reset control signal Pscan2, the auxiliary light-emitting control line 324 and the main light-emitting control line 424 are used to transmit a light-emitting control signal EM, the auxiliary switch control line 325 and the main switch control line 425 are used to transmit a switch control signal Pscan1, the first main reset line 426 and the first auxiliary reset line 326 are used to transmit a first reset signal Vi1, the second main reset line 427 and the second auxiliary reset line 327 are used to transmit a second reset signal Vi2, and the third main reset line 428 and the third auxiliary reset line 328 are used to transmit a third reset signal Vi3.

[0067] In the structure of FIG. 3, the non-display area 200 can include a plurality of first gate circuits 210 arranged in the second direction Y and cascaded, a plurality of second gate circuits 220 arranged in the second direction Y and cascaded, a plurality of third gate circuits 230 arranged in the second direction Y and cascaded, a plurality of fourth gate circuits 240 arranged in the second direction Y and cascaded, and a plurality of fifth gate circuits 240 arranged in the second direction Y and cascaded.

[0068] Referring to FIG. 3, the first gate circuit 210 is arranged on both sides of the second display area 400, and is used to transmit the compensation control signal Nscan1. One first gate circuit 210 is connected to two main compensation control lines 421. Meanwhile, the first gate circuit 210 of the present application is used to output the compensation control signal Nscan1 to two rows of second pixel circuits 410, i.e., two rows of second pixel circuits 410 need one first gate circuit 210.

[0069] Referring to FIG. 3, the second gate circuit 220 is arranged at two sides of the second display area 400, and the second gate circuit 220 and the first gate circuit 210 are arranged along the second direction Y. The second gate circuit 220 is configured to transmit the first reset control signal Nscan2. One second gate circuit 220 is connected with two adjacent first main reset control lines 422. Meanwhile, one level of the second gate circuit 220 is configured to output the first reset control signal Nscan2 to two rows of the second pixel circuit 410, i.e., two rows of the second pixel circuit 410 need one level of the second gate circuit 220.

[0070] Referring to FIG. 3, the fifth gate circuit 240 is arranged at two sides of the second display area 400 and between the second display area 400 and the first gate circuit 210 and the second gate circuit 220. The fifth gate circuit 240 is configured to transmit the switch control signal Pscan1. One fifth gate circuit 240 is connected with two adjacent main switch control lines 425. Meanwhile, one level of the fifth gate circuit 240 is configured to output the switch control signal Pscan1 to one row of the second pixel circuit 410, i.e., one row of the second pixel circuit 410 needs one level of the fifth gate circuit 240.

[0071] It should be noted that in the structure of FIG. 3, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 240 are arranged in each non-display sub-area 210, i.e., the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 240 are double-side simultaneously driven.

[0072] Referring to FIG. 3, the third gate circuit 230 is arranged at the first side of the second display area 400, and the third gate circuit 230 is located at the side of the first gate circuit 210 away from the second display area 400. The third gate circuit 230 is configured to transmit the second reset control signal Pscan2. One third gate circuit 230 is connected with two adjacent second main reset control lines 423. Meanwhile, one level of the fourth gate circuit 240 is configured to output the compensation control signal Nscan1 to two rows of the second pixel circuit 410, i.e., two rows of the second pixel circuit 410 need one level of the third gate circuit 230.

[0073] Referring to FIG. 3, the fourth gate circuit 240 is arranged at the second side of the second display area 400, and the fourth gate circuit 240 is located at the side of the first gate circuit 210 away from the second display area 400. The fourth gate circuit 240 is configured to transmit the light-emitting control signal EM. One fourth gate circuit 240 is connected with two adjacent main light-emitting control lines 424. Meanwhile, one level of the fourth gate circuit 240 is configured to output the compensation control signal Nscan1 to two rows of the second pixel circuit 410, i.e., two rows of the second pixel circuit 410 need one level of the fourth gate circuit 240.

[0074] It should be noted that only the third gate circuit 230 is arranged in the non-display sub-part 210, and only the fourth gate circuit 240 is arranged in the other non-display sub-part 210, that is, the third gate circuit 230 and the fourth gate circuit 240 are single-side driving.

[0075] It should be noted that the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are constant voltage, and thus do not need to be controlled by the corresponding gate circuit, and can be directly connected to the corresponding constant voltage source.

[0076] In the embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240 and the fifth gate circuit 240 can be mTnC gate circuits. In the following embodiment, the first gate circuit 210 and the second gate circuit 220 are taken as the first type of 16T5C circuit, the third gate circuit 230 and the fourth gate circuit 240 are taken as the second type of 13T3C circuit, and the fifth gate circuit 240 is taken as the third type of 8T3C circuit.

[0077] Referring to FIG. 5, the first type of circuit 21 can include a stage transmission circuit 211, an output circuit 212, a stage transmission frequency division circuit 213 and an output frequency division circuit 214.

[0078] Referring to FIG. 5, the stage transmission circuit 211 includes a stage transmission receiving circuit 2111 and a stage transmission output circuit 2112. The stage transmission receiving circuit 2111 is configured to receive a stage transmission signal generated by an upper-stage first type of circuit 21. The stage transmission output circuit 2112 is electrically connected to the stage transmission receiving circuit 2111 through a control node P1 and a control node Q1, and is configured to output a stage transmission signal of the present stage to a lower-stage first type of circuit 21 according to a signal of the control node P1 and a signal of the control node Q1.

[0079] Referring to FIG. 5, the output circuit 212 is electrically connected to the control node P1 and the control node Q1 in the stage transmission circuit 211. The output circuit 212 is configured to output a gate control signal according to a frequency division control signal FD and the signals of the control node P1 and the control node Q1. The output circuit 212 is electrically connected to a clock signal line. Adjacent two stages of first type of circuits 21 are connected to different clock signal lines.

[0080] Referring to FIG. 5, one end of the output frequency division circuit 214 is connected to the control node S1 in the output circuit 212, and the other end of the output frequency division circuit 214 is connected to one of the control node P1 and the control node Q1 in the stage transmission circuit 211. The output frequency division circuit 214 is configured to control the signal transmission between one of the control node P1 and the control node Q1 and the output circuit 212 according to the signal of one of the control node P1 and the control node Q1 and the frequency division control signal FD.

[0081] Referring to Fig. 5, the stage transfer frequency division circuit 213 is electrically connected to the stage transfer receiving circuit 2111 through the control node R1, and is electrically connected to the stage transfer output circuit 2112 through the control node P1 or the control node Q1, and is used for controlling the signal of one of the control node P1 and the control node Q1 according to the frequency division control signal FD, so as to control the stage transfer output circuit 2112 to output the stage transfer signal of the current stage.

[0082] Referring to Fig. 5, the output frequency division circuit 214 comprises an eighteenth transistor T18A and a twentieth transistor T20A. The gate of the eighteenth transistor T18A is connected to the first frequency division signal line FDL1, the source of the eighteenth transistor T18A is electrically connected to the control node P1 or the control node Q1, and the drain of the eighteenth transistor T18A is electrically connected to the control node S1. The gate of the twentieth transistor T20A is electrically connected to the control node Z1 of the stage transfer circuit 211, the source of the twentieth transistor T20A is electrically connected to the first frequency division signal line FDL1, and the drain of the twentieth transistor T20A is electrically connected to the gate of the eighteenth transistor T18A.

[0083] Referring to Fig. 5, the stage transfer frequency division circuit 213 comprises a seventeenth transistor T17A. The gate of the seventeenth transistor T17A is electrically connected to the second frequency division signal line FDL2, the source of the seventeenth transistor T17A is electrically connected to the stage transfer receiving circuit 2111 through the control node R1, and the drain of the seventeenth transistor T17A is electrically connected to the control node P1 or the control node Q1.

[0084] Referring to Fig. 5, the stage transfer output circuit 2112 comprises a tenth transistor T10A and a ninth transistor T9A. The gate of the tenth transistor T10A is electrically connected to the control node P1, the source of the tenth transistor T10A is electrically connected to the high voltage source VGH, and the drain of the tenth transistor T10A is electrically connected to the stage transfer output end OUT in the first circuit 21 for outputting the stage transfer signal. The gate of the ninth transistor T9A is electrically connected to the control node Q1, the source of the ninth transistor T9A is electrically connected to the low voltage source VGL, and the drain of the ninth transistor T9A is electrically connected to the stage transfer output end OUT.

[0085] Referring to Fig. 5, the output circuit 212 comprises a twenty-second transistor T22A and a twenty-first transistor T21A. The gate of the twenty-second transistor T22A is electrically connected to the control node S1, the source of the twenty-second transistor T22A is electrically connected to the high voltage line VGH, and the drain of the twenty-second transistor T22A is connected to the first output end OUT1. The gate of the twenty-first transistor T21A is electrically connected to the control node P1 or the control node Q1, the source of the twenty-first transistor T21A is electrically connected to the low voltage source VGL, and the drain of the twenty-first transistor T21A is connected to the first output end OUT1.

[0086] Referring to Fig. 5, the stage transfer receiving circuit 2111 comprises a third transistor T3A, the gate of the third transistor T3A is loaded with the first type clock signal XCK, the source of the third transistor T3A is connected to the first input end IN1, and the drain of the third transistor T3A is connected to the control node D1.

[0087] Referring to Fig. 5, the stage transfer receiving circuit 2111 comprises a fourth transistor T4A, a fifth transistor T5A, a sixth transistor T6A and a seventh transistor T7A connected in series, the gate of the fifth transistor T5A is electrically connected to the drain of the third transistor T3A, the source of the fifth transistor T5A is loaded with the first type clock signal XCK, the gate of the fourth transistor T4A is loaded with the first type clock signal XCK, the source of the fourth transistor T4A is loaded with the low voltage source VGL, the drain of the fourth transistor T4A is electrically connected to the gate of the sixth transistor T6A and the drain of the fifth transistor T5A, the drain of the sixth transistor T6A is electrically connected to the source of the seventh transistor T7A, the source of the sixth transistor T6A and the gate of the seventh transistor T7A are both loaded with the second type clock signal CK, and the drain of the seventh transistor T7A is electrically connected to the control node R1.

[0088] Referring to Fig. 5, the stage transfer receiving circuit 2111 comprises a thirteenth transistor T13A, a first capacitor C1A, a first transistor T1A and a second transistor T2A connected in series, the gate of the thirteenth transistor T13A (electrically connected to the control line CL) is loaded with the control signal, the source of the thirteenth transistor T13A is loaded with the high voltage source VGH, the drain of the thirteenth transistor T13A is electrically connected to the control node Q1, the gate of the first transistor T1A is electrically connected to the drain of the fourth transistor T4A, the source of the first transistor T1A is loaded with the high voltage source VGH, the drain of the first transistor T1A is electrically connected to the source of the second transistor T2A, the drain of the second transistor T2A is loaded with the second type clock signal CK, the gate of the second transistor T2A is also loaded with the stage transfer signal generated by the upper first type circuit 21, and the first capacitor C1A is electrically connected between the gate and the drain of the second transistor T2A.

[0089] Referring to Fig. 5, the stage transmission receiving circuit 2111 comprises the eleventh transistor T11A, the second capacitor C2A and the twelfth transistor T12A, the stage transmission output circuit 2112 can further comprise the third capacitor C3A electrically connected between the gate and the source of the tenth transistor T10A, the gate of the eleventh transistor T11A and the gate of the twelfth transistor T12A can be loaded with the low voltage source VGL to maintain open, the source and the drain of the eleventh transistor T11A are electrically connected to the drain of the fourth transistor T4A and the gate of the sixth transistor T6A respectively, the second capacitor C2A is electrically connected between the gate and the drain of the sixth transistor T6A, the source and the drain of the twelfth transistor T12A are electrically connected to the drain of the third transistor T3A and the control node Q1 respectively.

[0090] Referring to Fig. 5, the stage transmission receiving circuit 2111 comprises the eighth transistor T8A, the gate of the eighth transistor is connected to the control node Z1, the drain of the nineteenth transistor T19A is connected to the high voltage source VGH, and the source of the nineteenth transistor T19A is connected to the control node S1.

[0091] Referring to Fig. 5, the first circuit further comprises the nineteenth transistor T19A, the gate of the nineteenth transistor T19A is connected to the control node Z1, the drain of the eighth transistor T8A is connected to the high voltage source VGH, and the source of the eighth transistor T8A is connected to the control node P1.

[0092] Referring to Fig. 5, the stage transmission receiving circuit 2111 comprises the fourteenth transistor T14A and the sixteenth transistor T16A. The source of the fourteenth transistor T14A is connected to the first input terminal IN1, the gate of the fourteenth transistor T14A is loaded with the first type of clock signal XCK, and the drain of the fourteenth transistor T14A is electrically connected to the gate of the second transistor T2A; the gate and the source of the sixteenth transistor T16A are both electrically connected to the gate of the second transistor T2A, and the drain of the sixteenth transistor T16A is electrically connected to the control node Q1.

[0093] Referring to Fig. 5, the stage transmission receiving circuit 2111 comprises the fifteenth transistor T15A, the gate of the fifteenth transistor T15A can be loaded with the low voltage source VGL, and the source and the drain of the fifteenth transistor T15A can be electrically connected to the drain of the fourteenth transistor T14A and the gate of the second transistor T2A respectively.

[0094] Referring to Fig. 5, the first circuit 21 further comprises the first coupling capacitor C4A and the second coupling capacitor C5A, one end of the first coupling capacitor C4A is connected to the high voltage line Vgh, the other end of the first coupling capacitor C4A is connected to the gate of the twenty-second transistor T22A, one end of the second coupling capacitor C5A is connected to the high voltage line Vgh, and the other end of the second coupling capacitor C5A is connected to the gate of the eighteenth transistor T18A.

[0095] It should be noted that the first output end OUT1 in FIG. 5 is used to output the compensation control signal Nscan1 or the first reset control signal Nscan2.

[0096] Referring to FIG. 6, the second circuit 22 can also include a receiving circuit 221 and a derivation circuit 222, the receiving circuit 221 is used to receive a stage transmission signal generated by a higher-level second circuit 22, and the derivation circuit 222 is electrically connected to the receiving circuit 221 through the control node P2 and the control node Q2, and is used to output a control signal of the current stage, such as a light-emitting control signal or a second reset control signal, according to the signals of the control node P2 and the control node Q2.

[0097] Referring to FIG. 6, the derivation circuit 222 includes a tenth transistor T10B and a ninth transistor T9B, the gate of the tenth transistor T10B is electrically connected to the control node P2, the source of the tenth transistor T10B is electrically connected to the high-level source VGH, and the drain of the tenth transistor T10B is electrically connected to the second output end OUT2 in the second circuit 22; the gate of the ninth transistor T9B is electrically connected to the control node Q2, the source of the ninth transistor T9B is electrically connected to the low-level source VGL, and the drain of the ninth transistor T9B is electrically connected to the second output end OUT2.

[0098] Referring to FIG. 6, the receiving circuit 221 includes a third transistor T3B, the gate of the third transistor T3B is loaded with the first type of clock signal XCK, the source of the third transistor T3B is connected to the second input end IN2, and the drain of the third transistor T3B is connected to the control node D2.

[0099] Referring to FIG. 6, the receiving circuit 221 includes a fourth transistor T4B, a fifth transistor T5B, a sixth transistor T6B, and a seventh transistor T7B, the gate of the fifth transistor T5B is electrically connected to the drain of the third transistor T3B, the source of the fifth transistor T5B is loaded with the first type of clock signal XCK, the gate of the fourth transistor T4B is loaded with the first type of clock signal XCK, the source of the fourth transistor T4B is loaded with the low-level source VGL, the drain of the fourth transistor T4B is electrically connected to the gate of the sixth transistor T6B and the drain of the fifth transistor T5B, the drain of the sixth transistor T6B is electrically connected to the source of the seventh transistor T7B, the source of the sixth transistor T6B and the gate of the seventh transistor T7B are both loaded with the second type of clock signal CK, and the drain of the seventh transistor T7B is electrically connected to the control node P2.

[0100] Referring to Fig. 6, the receiving circuit 221 comprises a thirteenth transistor T13B, a first capacitor C1B, a first transistor T1B and a second transistor T2B, the gate of the thirteenth transistor T13B is loaded with a control signal, the source of the thirteenth transistor T13B is loaded with a high-level source VGH, the drain of the thirteenth transistor T13B is electrically connected to a control node D2, the gate of the first transistor T1B is electrically connected to the drain of the fourth transistor T4B, the source of the first transistor T1B is loaded with the high-level source VGH, the drain of the first transistor T1B is electrically connected to the source of the second transistor T2B, the drain of the second transistor T2B is loaded with a second clock signal CK, the gate of the second transistor T2B is also loaded with a stage transmission signal generated by the upper second circuit 22, and the first capacitor C1B is electrically connected between the gate and the drain of the second transistor T2B.

[0101] Referring to Fig. 6, the receiving circuit 221 comprises an eleventh transistor T11B, a second capacitor C2B and a twelfth transistor T12B, and the deriving circuit 222 can further comprise a third capacitor C3B electrically connected between the gate and the source of the tenth transistor T10B, the gates of the eleventh transistor T11B and the twelfth transistor T12B are both loaded with a low-level source VGL to maintain opening, the source and the drain of the eleventh transistor T11B are electrically connected to the drain of the fourth transistor T4B and the gate of the sixth transistor T6B respectively, the second capacitor C2B is electrically connected between the gate and the drain of the sixth transistor T6B, and the source and the drain of the twelfth transistor T12B are electrically connected to the control node D2 and the control node Q2 respectively.

[0102] Referring to Fig. 6, the receiving circuit 221 comprises an eighth transistor T8B, the gate of the eighth transistor is connected to the control node D2, the drain of the eighth transistor T8B is connected to the high-level source VGH, and the source of the eighth transistor T8B is connected to the control node P2.

[0103] The second output end OUT2 in Fig. 6 is used to output a second reset control signal Pscan2 or a light-emitting control signal EM.

[0104] Referring to Fig. 7, the three circuits 23 can comprise a first transistor T1C, a second transistor T2C, a third transistor T3C, a fourth transistor T4C, a fifth transistor T5C, a sixth transistor T6C, a seventh transistor T7C, an eighth transistor T8C, a first capacitor C1C and a second capacitor C2C.

[0105] Referring to FIG. 7, the gate of the seventh transistor T7C is electrically connected to the control node P3, the source of the seventh transistor T7C is electrically connected to the high voltage source VGH, and the drain of the seventh transistor T7C is electrically connected to the third output terminal OUT3 in the third circuit 23; the gate of the sixth transistor T6C is electrically connected to the control node Q3, the source of the sixth transistor T6C is electrically connected to the second clock signal CK, and the drain of the sixth transistor T6C is electrically connected to the third output terminal OUT3; meanwhile, the first capacitor C1C has two ends electrically connected to the control node Q3 and the third output terminal OUT3, and the second capacitor C2C has two ends electrically connected to the control node Q3 and the third output terminal OUT3.

[0106] Referring to FIG. 7, the gate of the third transistor T3C is loaded with the first clock signal XCK, the source of the third transistor T3C is electrically connected to the third input terminal IN3, and the drain of the third transistor T3C is electrically connected to the control node D3.

[0107] Referring to FIG. 7, the gate of the fifth transistor T5C is electrically connected to the control node D3, the source of the fifth transistor T5C is loaded with the first clock signal XCK, the gate of the fourth transistor T4C is loaded with the first clock signal XCK, the source of the fourth transistor T4C is loaded with the low voltage source VGL, and the drain of the fourth transistor T4C is electrically connected to the control node P3 and the drain of the fifth transistor T5C.

[0108] Referring to FIG. 7, the gate of the first transistor T1C is electrically connected to the control node P3, the source of the first transistor T1C is loaded with the high voltage source VGH, and the drain of the first transistor T1C is electrically connected to the source of the second transistor T2C, the drain of the second transistor T2C is electrically connected to the control node D3, and the gate of the second transistor T2C is loaded with the second clock signal CK.

[0109] Referring to FIG. 7, the gate of the eighth transistor T8C is electrically connected to the low voltage source VGL, and the source and the drain of the eighth transistor T8C are electrically connected to the control node D3 and the control node Q3, respectively.

[0110] The third output terminal OUT3 in FIG. 7 is used for outputting the switch control signal Pscan1.

[0111] Next, the film layer structures of the second pixel circuit 410, the first pixel circuit 310 and the five gate circuits in the pixel structure of FIG. 4 are described.

[0112] Referring to FIG. 8, the first display area 300, the second display area 400, and the non-display area 200 of the display panel 100 can each include a substrate 110 and an array driving layer 120 disposed on the substrate 110; in the second display area 400 and the first display area 300, the display panel 100 can further include a pixel definition layer (not shown) disposed on the array driving layer 120, a light emitting device layer (not shown) disposed in the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. Hereinafter, a film layer structure of the array driving layer 120 will be described.

[0113] In the present embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom emission light emitting display device or a dual emission light emitting display device, a transparent substrate is used. When the display panel 100 is a top emission light emitting display device, a semi-transparent or non-transparent substrate as well as a transparent substrate can be used.

[0114] In the present embodiment, the substrate 110 is used to support various film layers disposed on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0115] In the present embodiment, the substrate 110 can include a first flexible base 111, a first barrier layer 112, a second flexible base 113, and a second barrier layer 114 stacked, the first flexible base 111 and the second flexible base 113 can be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0116] In the present embodiment, the first flexible base 111 is formed by coating a polymeric material on a support base and then curing the polymeric material, the second flexible base 113 is formed by coating the same material as the material of the first flexible base 111 and curing the material, and the second flexible base 113 is formed by the same method as the method of forming the first flexible base 111. Each of the first flexible base 111 and the second flexible base 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the substrate 110 is formed of the first flexible base 111 and the second flexible base 113, small holes, cracks, etc. formed during the manufacturing of the first flexible base 111 are covered by the second flexible base 113, so that the above-described defects can be removed.

[0117] Referring to FIG. 8, the array driving layer 120 can include a plurality of thin film transistors, which can be etch stop type, back channel etch type, or divided into bottom gate thin film transistors, top gate thin film transistors, etc. according to the position of the gate and the active layer, or divided into N-type thin film transistors, P-type thin film transistors according to the performance of the thin film transistor; wherein the thin film transistor in FIG. 8 does not represent the structure diagram of any transistor in FIG. 4, but is only a schematic diagram of each film layer of the display panel 100 of the present application.

[0118] Referring to FIG. 8, the array driving layer 120 can include a light shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third gate insulating layer 128, a fourth gate insulating layer 130 disposed on the second active layer 129, a third gate layer 131 disposed on the fourth gate insulating layer 130, a first interlayer insulating layer 132 disposed on the third gate layer 131, a first source-drain layer 133 disposed on the first interlayer insulating layer 132, a second interlayer insulating layer 134 disposed on the first source-drain layer 133, a second source-drain layer 135 disposed on the second interlayer insulating layer 134, and a planarization layer 136 disposed on the second source-drain layer 135.

[0119] Referring to FIG. 8, the light shielding layer 121 is disposed on the second barrier layer 114, and the light shielding layer 121 is used to shield external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of black light shielding material, such as black light shielding metal or black organic material, etc.

[0120] Referring to FIG. 8, the buffer layer 122 is disposed on the light shielding layer 121, and the buffer layer 122 is used to isolate the light shielding layer 121 and the upper metal material. The material of the buffer layer 122 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide film layer or a stacked structure of silicon oxide-silicon nitride.

[0121] Referring to FIG. 8, the first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The material of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polysilicon, for example, the material of the first active layer 123 in the present application can be low-temperature polysilicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0122] Referring to FIG. 8, the first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 are respectively arranged on the corresponding metal layer or semiconductor layer, and are arranged in different layers of metal layer or semiconductor layer; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the second interlayer insulating layer 134 can be inorganic materials combined with silicon and oxygen or organic materials with flatness.

[0123] Referring to FIG. 8, the first gate layer 125, the second gate layer 127, and the third gate layer 131 are respectively arranged on the corresponding insulating layer, and the materials of the first gate layer 125, the second gate layer 127, and the third gate layer 131 can be copper, molybdenum, or molybdenum-titanium alloy, etc., and the material of the three-layer gate layer of the present application can be molybdenum.

[0124] Referring to FIG. 8, the first source-drain layer 133 is arranged on the first interlayer insulating layer 132, and the second source-drain layer 135 is arranged on the second interlayer insulating layer 134, and the materials of the first source-drain layer 133 and the second source-drain layer 135 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal, etc., and the material of the two-layer source-drain layer of the present application can be titanium-aluminum-titanium.

[0125] Referring to FIG. 8, the planarization layer 136 is entirely laid to ensure the flatness of the film layer of the array driving layer 120, and the material of the planarization layer 136 can be inorganic materials combined with silicon and oxygen or organic materials with flatness.

[0126] Referring to FIG. 9 and FIG. 10, FIG. 9 is a partial film layer stacking diagram of the first main part 400a of the present application, and FIG. 10 is a partial film layer stacking diagram of the functional subpart 300a of the present application.

[0127] In the structure of FIG. 9, the first gate layer 125 can include the second main reset control line 423, the main light-emitting control line 424, the main switch control line 425, and the first main reset line 426, and the second main reset control line 423, the main light-emitting control line 424, the main switch control line 425, and the first main reset line 426 all extend along the first direction X, and the first main reset line 426, the main switch control line 425, the main light-emitting control line 424, and the second main reset control line 423 are arranged along the second direction Y and are spaced apart from each other.

[0128] In the structure of FIG. 10, the first gate layer 125 can include a second auxiliary reset control line 323, an auxiliary light-emitting control line 324, an auxiliary switch control line 325, and a first auxiliary reset line 326, all of which extend along the first direction X. The first auxiliary reset line 326, the auxiliary switch control line 325, the auxiliary light-emitting control line 324, and the second auxiliary reset control line 323 are arranged along the second direction Y and are spaced apart from each other.

[0129] Referring to FIG. 9, the second gate layer 127 includes a third main reset line 428, a first portion of a main compensation control line 421, and a first portion of a first main reset control line 422, all of which extend along the first direction X. The first portion of the first main reset control line 422, the first portion of the main compensation control line 421, and the third main reset line 428 are arranged along the second direction Y and are spaced apart from each other. The third main reset line 428 is disposed on a side of the second main reset control line 423 away from a main light-emitting control line 424.

[0130] Referring to FIG. 10, the second gate layer 127 includes a third auxiliary reset line 328, a first portion of an auxiliary compensation control line 321, and a first portion of a first auxiliary reset control line 322, all of which extend along the first direction X. The first portion of the first auxiliary reset control line 322, the first portion of the auxiliary compensation control line 321, and the third auxiliary reset line 328 are arranged along the second direction Y and are spaced apart from each other. The third auxiliary reset line 328 is disposed on a side of the second auxiliary reset control line 323 away from an auxiliary light-emitting control line 324.

[0131] Referring to FIG. 9, the third gate layer 131 includes a second reset signal Vi2, a second portion of the main compensation control line 421, and a second portion of the first main reset control line 422, all of which extend along the first direction X. The first portion of the first main reset control line 422, the first portion of the main compensation control line 421, and the second reset signal Vi2 are arranged along the second direction Y and are spaced apart from each other. The second reset signal Vi2 at least partially overlaps the second main reset control line 423. Meanwhile, the second portion and the first portion of the main compensation control line 421 at least partially overlap each other, and the second portion and the first portion of the first main reset control line 422 at least partially overlap each other. The main compensation control line 421 is disposed between a main switch control line 425 and the main light-emitting control line 424, and the first main reset control line 422 is disposed between the main switch control line 425 and a first main reset line 426.

[0132] Referring to FIG. 10, the third gate layer 131 includes the second reset signal Vi2, the second part of the auxiliary compensation control line 321, the second part of the first auxiliary reset control line 322, the third auxiliary reset line 328, the first part of the auxiliary compensation control line 321, the first part of the first auxiliary reset control line 322, which extend along the first direction X, and the first part of the first auxiliary reset control line 322, the first part of the auxiliary compensation control line 321, and the second reset signal Vi2, which are arranged along the second direction Y and spaced from each other, and the second reset signal Vi2 at least partially overlaps the second auxiliary reset control line 323. Meanwhile, the second part and the first part of the auxiliary compensation control line 321 at least partially overlap, the second part and the first part of the first auxiliary reset control line 322 at least partially overlap, the auxiliary compensation control line 321 is arranged between the auxiliary switch control line 325 and the auxiliary light-emitting control line 324, and the first auxiliary reset control line 322 is arranged between the auxiliary switch control line 325 and the first auxiliary reset line 326.

[0133] Referring to FIGS. 9 and 10, the first active layer 123 includes a switching active part of the switching transistor T2, a driving active part of the driving transistor T1, a second reset active part of the second reset transistor T7, a third reset active part of the third reset transistor T8, a first light-emitting active part of the first light-emitting transistor T5, and a second light-emitting active part of the second light-emitting transistor T6. The second active layer 129 includes a compensation active part of the compensation transistor T3 and a first reset active part of the first reset transistor T4.

[0134] Referring to FIGS. 9 and 10, the first source-drain layer 133 is mainly used for forming sources and drains of at least part of transistors in the second pixel circuit 410 and the first pixel circuit 310.

[0135] Referring to FIGS. 9 and 10, the second source-drain layer 135 includes the data signal line Data, the high-level line VDD, and the fan-out wire FIAA. In the structure of FIG. 9, the data signal line Data is arranged between two second pixel circuits 410, and the fan-out wire is arranged between two data signal lines Data. In the structure of FIG. 10, the data signal line Data is arranged on one side of each first pixel circuit 310, and the high-level line VDD is arranged between two adjacent data signal lines Data.

[0136] Referring to FIG. 1 and FIG. 3, the second display area 400 further includes a second main part 400b in which a plurality of second pixel circuits 410 arranged in a plurality of rows in the first direction X are arranged, and the plurality of rows of second pixel circuits 410 in the second main part 400b do not cross the first display area 300, so that the five main signal lines in the second main part 400b can extend from the non-display sub-area 210 on one side of the display panel 100 to the non-display sub-area 210 on the other side in the first direction X. As for the plurality of rows of second pixel circuits 410 in the first main part 400a, due to the arrangement of the light-transmitting part 300b in the first display area 300, if the main signal lines in the two main signal line groups 420 in the first main part 400a are arranged in the same way as the five main signal lines in the second main part 400b, one main signal line group 420 in the first main part 400a will overlap with the light-transmitting part 300b in the first display area 300, reducing the area of the light-transmitting part 300b and resulting in a decrease in the area ratio of the light-transmitting part 300b in the first display area 300.

[0137] Therefore, the present application can connect at least one main signal line in one main signal line group 420 in the first main part 400a to a main signal line in another main signal line group 420 that transmits the same control signal, and electrically connect it to an auxiliary signal line in the functional sub-area 300a that transmits the same control signal, so as to reduce the number of main signal lines that cross the light-transmitting part 300b, thereby increasing the area ratio of the light-transmitting part 300b in the first display area 300.

[0138] For example, in the functional sub-area 300a and the first main part 400a corresponding to the functional sub-area 300a, at least two main compensation control lines 421 in the first main part 400a are electrically connected to a first parallel node M1 with one auxiliary compensation control line 321 in the functional sub-area 300a; or / and, at least two first main reset control lines 422 in the first main part 400a are electrically connected to a second parallel node M2 with one first auxiliary reset control line 322 in the functional sub-area 300a; or / and, at least two second main reset control lines 423 in the first main part 400a are electrically connected to a third parallel node M3 with one second auxiliary reset control line 323 in the functional sub-area 300a; or / and, at least two main light-emitting control lines 424 in the first main part 400a are electrically connected to a fourth parallel node M4 with one auxiliary light-emitting control line 324 in the functional sub-area 300a.

[0139] That is, in the structures of FIG. 3 and FIG. 12, one of the main compensation control lines 421 in the first main part 400a is directly connected with the auxiliary compensation control line 321 in the corresponding functional subpart 300a, while the other main compensation control line 421 in the first main part 400a is connected with the auxiliary compensation control line 321 of the functional subpart 300a at the first parallel node M1; or / and, one of the first main reset control lines 422 in the first main part 400a is directly connected with the first auxiliary reset control line 322 in the corresponding functional subpart 300a, while the other first main reset control line 422 in the first main part 400a is connected with the first auxiliary reset control line 322 of the functional subpart 300a at the second parallel node M2; or / and, one of the second main reset control lines 423 in the first main part 400a is directly connected with the second auxiliary reset control line 323 in the corresponding functional subpart 300a, while the other second main reset control line 423 in the first main part 400a is connected with the second auxiliary reset control line 323 of the functional subpart 300a at the third parallel node M3; or / and, one of the main light-emitting control lines 424 in the first main part 400a is directly connected with the auxiliary light-emitting control line 324 in the corresponding functional subpart 300a, while the other main light-emitting control line 424 in the first main part 400a is connected with the auxiliary light-emitting control line 324 of the functional subpart 300a at the fourth parallel node M4.

[0140] Please refer to FIG. 3 and FIG. 11 to FIG. 13, in order to improve the area ratio of the light-transmitting part 300b in the first display area 300, both of the main compensation control lines 421 in the first main part 400a are electrically connected with the auxiliary compensation control line 321 in the corresponding functional subpart 300a, both of the first main reset control lines 422 in the first main part 400a are electrically connected with the first auxiliary reset control line 322 in the corresponding functional subpart 300a, both of the second main reset control lines 423 in the first main part 400a are electrically connected with the second auxiliary reset control line 323 in the corresponding functional subpart 300a, and both of the main light-emitting control lines 424 in the first main part 400a are electrically connected with the auxiliary light-emitting control line 324 in the corresponding functional subpart 300a.

[0141] It should be noted that the number of stacked film layers in FIG. 11 and FIG. 13 is the same, and both include the first gate layer 125, the second gate layer 127 and the third gate layer 131, the difference between FIG. 11 and FIG. 13 is that the enlarged areas are different; FIG. 12 includes all the metal conductive layers of the array driving layer of the display panel 100.

[0142] Referring to FIGS. 11-13, the plurality of pixel islands 340 includes a first pixel island 340a and a second pixel island 340b, the first pixel island 340a is disposed adjacent to the first main portion 400a, the second pixel island 340b is disposed adjacent to the first pixel island 340a, and the first pixel island 340a and the second pixel island 340b each include a plurality of first pixel circuits 310.

[0143] In the present embodiment, since the first light emitting device 330 in the second display area 400 has a larger proportion in unit area than the second light emitting device 430 in the first display area 300, in order to reduce the display difference of the transition area between the second display area 400 and the first display area 300 as much as possible, the present application makes the spacing between the first main portion 400a and the first pixel island 340a smaller than the spacing between the first pixel island 340a and the second pixel island 340b.

[0144] Meanwhile, since the spacing between the first main portion 400a and the first pixel island 340a is smaller than the spacing between the first pixel island 340a and the second pixel island 340b, and a certain space is required to connect two main signal lines and one auxiliary signal line, the first parallel node M1 of the present application can be located between the first main portion 400a and the first pixel island 340a, or between the first pixel island 340a and the second pixel island 340b, the second parallel node M2 can be located between the first main portion 400a and the first pixel island 340a, or between the first pixel island 340a and the second pixel island 340b, the third parallel node M3 can be located between the first main portion 400a and the first pixel island 340a, or between the first pixel island 340a and the second pixel island 340b, and the fourth parallel node M4 can be located between the first main portion 400a and the first pixel island 340a, or between the first pixel island 340a and the second pixel island 340b.

[0145] Referring to FIGS. 11-13, the first parallel node M1, the third parallel node M3, and the fourth parallel node M4 are located between the first pixel island 340a and the second pixel island 340b, and the second parallel node M2 is located between the first main portion 400a and the first pixel island 340a.

[0146] It should be noted that since the first parallel node M1, the second parallel node M2, the third parallel node M3, and the fourth parallel node M4 are all in the first display area 300, a plurality of extension lines need to be provided in the first display area 300 to electrically connect the main signal lines and the auxiliary signal lines.

[0147] Referring to FIGS. 11-13, the functional sub-unit 300a further comprises a first extension segment 351, a second extension segment 352, a third extension segment 353 and a fourth extension segment 354 located at the periphery of the first pixel island 340a, the second extension segment 352 is located between the first main unit 400a and the first pixel island 340a, and the first extension segment 351, the third extension segment 353 and the fourth extension segment 354 extend to the side away from the first main unit 400a.

[0148] In the present embodiment, one end of the first extension segment 351 is electrically connected to one of the main compensation control lines 421 in the first main unit 400a, and the other end of the first extension segment 351 is electrically connected to the auxiliary compensation control line 321 in the region where the first parallel node M1 is located; one end of the second extension segment 352 is electrically connected to one of the first main reset control lines 422 in the first main unit 400a, and the other end of the second extension segment 352 is electrically connected to the first auxiliary reset control line 322 in the region where the second parallel node M2 is located; one end of the third extension segment 353 is electrically connected to one of the second main reset control lines 423 in the first main unit 400a, and the other end of the third extension segment 353 is electrically connected to the second auxiliary reset control line 323 in the region where the third parallel node M3 is located; one end of the fourth extension segment 354 is electrically connected to one of the main light-emitting control lines 424 in the first main unit 400a, and the other end of the fourth extension segment 354 is electrically connected to the auxiliary light-emitting control line 324 in the region where the fourth parallel node M4 is located.

[0149] In the present embodiment, the first extension segment 351 and the main compensation control line 421 of the present application are located in the same metal layer, and since the main compensation control line 421 has a first part located in the second gate layer 127 and a second part located in the third gate layer 131, the present application also has a first extension segment 351 located in the second gate layer 127 and a first extension segment 351 located in the third gate layer 131; secondly, the two first extension segments 351 of different layers both extend to the side away from the first main unit 400a, and the two first extension segments 351 of different layers at least partially overlap, and the two first parallel nodes M1 are both located between the first pixel island 340a and the second pixel island 340b.

[0150] Similarly, the present application also has a second extension segment 352 located in the second gate layer 127 and a second extension segment 352 located in the third gate layer 131; in addition, the second extension segment 352 located in the second gate layer 127 is located between the first main unit 400a and the first pixel island 340a, while the second extension segment 352 located in the third gate layer 131 extends to the side away from the first main unit 400a, and is located at the periphery of the first pixel island 340a, i.e. one of the two second parallel nodes M2 is located between the first main unit 400a and the first pixel island 340a, and the other is located between the first pixel island 340a and the second pixel island 340b.

[0151] In the embodiment, the third extension segment 353 and the second main reset control line 423 are both located in the first gate layer 125, and the fourth extension segment 354 and the main light-emitting control line 424 are both located in the first gate layer 125.

[0152] Referring to FIGS. 11-13, the two first extension segments 351 of different layers are both arranged close to the first pixel island 340a, the fourth extension segment 354 is arranged on a side of the first extension segment 351 away from the first pixel island 340a, the third extension segment 353 is arranged on a side of the fourth extension segment 354 away from the first pixel island 340a, and the second extension segment 352 of the third gate layer 131 is arranged between the two first extension segments 351 of different layers and the first pixel island 340a.

[0153] Since a plurality of auxiliary signal lines are arranged between the first pixel island 340a and the second pixel island 340b, if the first extension segment 351, the second extension segment 352, the third extension segment 353, and the fourth extension segment 354 are electrically connected to the corresponding auxiliary signal lines, a technical problem of short circuit of control lines transmitting different control signals will occur.

[0154] Referring to FIG. 12, the functional subpart 300a further includes a first longitudinal segment 361, a second longitudinal segment 362, a third longitudinal segment 363, a fourth longitudinal segment 364, a fifth longitudinal segment 365, and a sixth longitudinal segment 366 extending along the second direction Y, the first longitudinal segment 361, the third longitudinal segment 363, the fourth longitudinal segment 364, the fifth longitudinal segment 365, and the sixth longitudinal segment 366 are arranged between the first pixel island 340a and the second pixel island 340b, and the second longitudinal segment 362 is arranged between the first pixel island 340a and the first main part 400a.

[0155] Referring to FIG. 12, the first extension segment 351 of the second gate layer 127 is electrically connected to the auxiliary compensation control line 321 of the second gate layer 127 through the first longitudinal segment 361, the second extension segment 352 of the second gate layer 127 is electrically connected to the first auxiliary reset control line 322 of the second gate layer 127 through the second longitudinal segment 362, the third extension segment 353 is electrically connected to the second auxiliary reset control line 323 through the third longitudinal segment 363, the fourth extension segment 354 is electrically connected to the auxiliary light-emitting control line 324 through the fourth longitudinal segment 364, the first extension segment 351 of the third gate layer 131 is electrically connected to the auxiliary compensation control line 321 of the third gate layer 131 through the fifth longitudinal segment 365, and the second extension segment 352 of the third gate layer 131 is electrically connected to the first auxiliary reset control line 322 of the third gate layer 131 through the sixth longitudinal segment 366.

[0156] In the embodiment, the sixth longitudinal segment 366 is arranged in the second source-drain layer 135 due to the partial overlap of the first longitudinal segment 361 and the sixth longitudinal segment 366, and the first longitudinal segment 361, the second longitudinal segment 362, the third longitudinal segment 363, the fourth longitudinal segment 364 and the fifth longitudinal segment 365 are arranged in the first source-drain layer 133.

[0157] It should be noted that FIG. 12 is only one embodiment of the present application. If the distance between the first pixel island 340a and the second pixel island 340b is not enough to arrange the five longitudinal segments, the second pixel island 340b can be arranged on the side away from the first pixel island 340a.

[0158] Referring to FIG. 3 and FIG. 12, each auxiliary signal line group 320 further includes an auxiliary switch control line 325, and each main signal line group 420 further includes a main switch control line 425. The auxiliary switch control line 325 and the main switch control line 425 are used to transmit a switch control signal Pscan1, i.e., the auxiliary switch control line 325 and the main switch control line 425 are mainly used to turn on the switch transistor for transmitting the data signal.

[0159] In the embodiment, in the functional sub-unit 300a and the first main unit 400a corresponding to the functional sub-unit 300a, only one main switch control line 425 in the first main unit 400a is electrically connected with one auxiliary switch control line 325 in the functional sub-unit 300a.

[0160] For example, in the structure of FIG. 3, in a first main unit 400a of the present application, one main switch control line 425 is electrically connected with one corresponding auxiliary switch control line 325, another main switch control line 425 in the first main unit 400a is arranged to be insulated from the auxiliary switch control line 325 in the corresponding functional sub-unit 300a, and the main switch control line 425 is directly electrically connected with the main switch control line 425 in the corresponding first main unit 400a on the other side of the first display area 300.

[0161] It should be noted that, since the main switch control line 425 is arranged in the first main unit 400a, the present application needs to arrange a connection segment in the first display area 300 to connect two main switch control lines 425 arranged in the same row.

[0162] Referring to FIG. 12, the functional sub-unit 300a further includes at least one electrically connected segment 371 arranged in the periphery of the plurality of first pixel circuits 310 in the same row. The electrically connected segment 371 is arranged to be insulated from the auxiliary switch control line 325. One end of the electrically connected segment 371 is electrically connected with one main switch control line 425 arranged to be insulated from the five auxiliary signal lines in the first main unit 400a.

[0163] In the embodiment, the electric connection segment 371 is arranged at the outermost side of the plurality of pixel islands 340; meanwhile, since the electric connection segment 371 needs to be connected with the main switch control line 425 in the first main part 400a, and since the main switch control line 425 is located in the first gate layer 125, and the first main reset line 426 is also located in the first gate layer 125, and the first main reset line 426 needs to be electrically connected with the first auxiliary reset line 326, and the first auxiliary reset line 326 is arranged between the electric connection segment 371 and the pixel island 340, therefore, a bridge metal structure is needed to electrically connect the electric connection segment 371 and the main switch control line 425; similarly, since the area between the first pixel circuit 310 and the two rows of second pixel circuits 410 corresponds, that is, the main switch control line 425 which is electrically connected with the auxiliary switch control line 325 in the first main part 400a is not on the same straight line, therefore, the auxiliary switch control line 325 and the main switch control line 425 also need a bridge metal structure to be electrically connected.

[0164] Please refer to FIG. 12, the functional subpart 300a includes a first bridge segment 372 and a second bridge segment 373, the first bridge segment 372 electrically connects a main switch control line 425 which is arranged in insulation with the auxiliary switch control line 325 and the electric connection segment 371, and the second bridge segment 373 electrically connects a main switch control line 425 and the auxiliary switch control line 325, the first bridge segment 372 extends along the first direction X, and the second bridge segment 373 partially extends along the second direction Y, and the second bridge segment 373 is located between the second longitudinal segment 362 and the first pixel island 340a, and the first bridge segment 372 and the second bridge segment 373 are both located in the first source-drain layer 133.

[0165] In the embodiment, the plurality of signal lines include a plurality of reset lines for transmitting reset signals to the first pixel circuit 310 and the second pixel circuit 410, and the plurality of reset lines only extend in the first direction X in the first display area 300, and the plurality of reset lines form a grid structure in the second display area 400.

[0166] For example, please refer to FIG. 12, the plurality of signal lines can include at least two first main reset lines 426, at least two second main reset lines 427 and at least two third main reset lines 428 which are located in the second display area, a first main reset line 426 is connected with the first reset transistor T4 of a row of second pixel circuits 410 which are arranged along the first direction X, a second main reset line 427 is connected with the second reset transistor T7 of a row of second pixel circuits 410 which are arranged along the first direction X, and a third main reset line 428 is connected with the third reset transistor T8 of a row of second pixel circuits 410 which are arranged along the first direction X.

[0167] Referring to FIG. 12, the plurality of signal lines further include a first auxiliary reset line 326, a second auxiliary reset line 327, and a third auxiliary reset line 328 in the first display area. The first auxiliary reset line 326 is connected to the first reset transistor T4 of a row of the first pixel circuit 310 arranged along the first direction X. The second auxiliary reset line 327 is connected to the second reset transistor T7 of a row of the first pixel circuit 310 arranged along the first direction X. The third auxiliary reset line 328 is connected to the third reset transistor T8 of a row of the first pixel circuit 310 arranged along the first direction X.

[0168] In the present embodiment, in the functional sub-portion 300a and the first main portion 400a corresponding to the functional sub-portion 300a, at least two first main reset lines 426 in the first main portion 400a are electrically connected to the fifth parallel node M5 with the first auxiliary reset line 326 in the functional sub-portion 300a. At least two second main reset lines 427 in the first main portion 400a are electrically connected to the sixth parallel node M6 with the second auxiliary reset line 327 in the functional sub-portion 300a. At least two third main reset lines 428 in the first main portion 400a are electrically connected to the seventh parallel node M7 with the third auxiliary reset line 328 in the functional sub-portion 300a.

[0169] In the present embodiment, since two main reset lines need to be electrically connected to the auxiliary reset line corresponding to the same reset signal transmission, the functional sub-portion 300a of the present application further includes a fifth extension segment 355, a sixth extension segment 356, and a seventh extension segment 357. The fifth extension segment 355 and the seventh extension segment 357 are arranged at the periphery of the first pixel island 340a. The sixth extension segment 356 is arranged between the first pixel island 340a and the first main portion 400a.

[0170] In the present embodiment, one end of the fifth extension segment 355 is electrically connected to one of the first main reset lines 426 in the first main portion 400a, and the other end of the fifth extension segment 355 is electrically connected to the first auxiliary reset line 326 in the region where the fifth parallel node M5 is located. One end of the sixth extension segment 356 is electrically connected to one of the second main reset lines 427 in the first main portion 400a, and the other end of the sixth extension segment 356 is electrically connected to the second auxiliary reset line 327 in the region where the sixth parallel node M6 is located. One end of the seventh extension segment 357 is electrically connected to one of the third main reset lines 428 in the first main portion 400a, and the other end of the seventh extension segment 357 is electrically connected to the third auxiliary reset line 328 in the region where the seventh parallel node M7 is located.

[0171] Please refer to FIG. 12, since the first main reset line 426 and the first auxiliary reset line 326 are located in the first gate layer 125, the second main reset line 427 and the second auxiliary reset line 327 are located in the third gate layer 131, and the third main reset line 428 and the third auxiliary reset line 328 are located in the second gate layer 127, when connecting the main reset line with the corresponding auxiliary reset line, it is necessary to cross the metal layer in the same layer, therefore, the fifth extension segment 355, the sixth extension segment 356 and the seventh extension segment 357 are all made of the metal of the first source-drain layer 133.

[0172] In the embodiment, the fifth extension segment 355 can be arranged between the first main part 400a and the second longitudinal segment 362, and the sixth extension segment 356 and the seventh extension segment 357 are both arranged in the periphery of the first pixel island 340a.

[0173] Since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltage signals, the reset lines transmitting the same reset signal can be connected in parallel to form a mesh structure.

[0174] Please refer to FIG. 14 to FIG. 16, the second display area 400 further includes a plurality of first connection segments 441, a plurality of second connection segments 442 and a plurality of third connection segments 443, the plurality of first connection segments 441, the plurality of second connection segments 442 and the plurality of third connection segments 443 are arranged along the first direction X and extend along the second direction Y.

[0175] In the embodiment, each first connection segment 441 is electrically connected with the plurality of first main reset lines 426, and the plurality of first connection segments 441 and the plurality of first main reset lines 426 form a mesh structure; each second connection segment 442 is electrically connected with the plurality of second main reset lines 427, and the plurality of second connection segments 442 and the plurality of second main reset lines 427 form a mesh structure; each third connection segment 443 is electrically connected with the plurality of third main reset lines 428, and the plurality of third connection segments 443 and the plurality of third main reset lines 428 form a mesh structure.

[0176] It should be noted that the second main part 400b also has the plurality of first main reset lines 426, the plurality of second main reset lines 427 and the plurality of third main reset lines 428, and the main reset lines transmitting the same reset signal in the first main part 400a and the second main part 400b are all electrically connected with the longitudinally extending connection segments to form corresponding mesh structures, thereby reducing the impedance of the reset lines and improving the technical problem that the voltage signal on the reset line is attenuated due to the influence of resistance and capacitance.

[0177] Referring to FIGS. 14-16, the plurality of first connection segments 441, the plurality of second connection segments 442, and the plurality of third connection segments 443 are arranged at intervals along the first direction X, and the number of the first connection segments 441 is less than the number of the second connection segments 442, and the number of the third connection segments 443 is less than the number of the second connection segments 442; for example, the interval between two adjacent first connection segments 441 is 8 widths of the second pixel circuit 410, the interval between two adjacent second connection segments 442 is 4 widths of the second pixel circuit 410, and the interval between two adjacent third connection segments 443 is 8 widths of the second pixel circuit 410.

[0178] In this embodiment, since the second reset signal Vi2 is used to reset the potential of the anode in the light-emitting device, when the potential of the anode in the light-emitting device is inaccurate, technical problems of uneven brightness and darkness are easily caused at low gray levels; by arranging a large number of second connection segments 442, the plurality of second connection segments 442 and the plurality of second main reset lines 427 form a more dense mesh structure, further reducing the impedance of the plurality of second main reset lines 427, and reducing the influence of resistance and capacitance on the voltage signal transmitted by the second main reset line 427.

[0179] It should be noted that the bright lines in the horizontal and vertical directions in FIGS. 14-16 are only one wire, and the two lines in the horizontal direction in the figure are the boundary lines of the corresponding wires in the width direction.

[0180] The transmittance of the present application is compared with the relevant comparative examples as follows:

[0181] Parallel scheme of signal line Transmittance of first display area Prior art / 17.5% Comparative example 1 Two compensation control lines transmitting the compensation control signal Nscan1 are parallel in the first display area 18.5% Comparative example 2 Two compensation control lines transmitting the compensation control signal Nscan1 and two light-emitting control lines transmitting the light-emitting control signal EM are parallel in the first display area 19.5% Comparative example 3 Two compensation control lines transmitting the compensation control signal Nscan1, two light-emitting control lines transmitting the light-emitting control signal EM, and two first reset lines transmitting the first reset signal Vi1 are parallel in the first display area 20.5% Comparative example 4 Two compensation control lines transmitting the compensation control signal Nscan1, two light-emitting control lines transmitting the light-emitting control signal EM, two first reset control lines transmitting the first reset control signal Nscan2, two second reset control lines transmitting the second reset control signal Pscan2, two first reset lines transmitting the first reset signal Vi1, two second reset lines transmitting the second reset signal Vi2, and two third reset lines transmitting the third reset signal Vi3 are parallel in the first display area 24.5%

[0182] As can be seen from the above table, when the present scheme is not designed, the transmittance of the first display area 300 is 17.5%.

[0183] In the comparative example 1, when the two compensation control lines transmitting the compensation control signal Nscan1 are connected in parallel in the first display area 300, the transmittance of the display panel of the present application in the first display area 300 increases from 17.5% to 18.5%.

[0184] In the comparative example 2, when the two compensation control lines transmitting the compensation control signal Nscan1 and the two light-emitting control lines transmitting the light-emitting control signal EM are connected in parallel in the first display area 300, the transmittance of the display panel of the present application in the first display area 300 increases from 18.5% to 19.5%.

[0185] In the comparative example 3, when the two compensation control lines transmitting the compensation control signal Nscan1, the two light-emitting control lines transmitting the light-emitting control signal EM and the two first reset lines transmitting the first reset signal Vi1 are connected in parallel in the first display area 300, the transmittance of the display panel of the present application in the first display area 300 increases from 19.5% to 20.5%.

[0186] In the comparative example 4, when the two compensation control lines transmitting the compensation control signal Nscan1, the two light-emitting control lines transmitting the light-emitting control signal EM, the two first reset control lines transmitting the first reset control signal Nscan2, the two second reset control lines transmitting the second reset control signal Pscan2, the two first reset lines transmitting the first reset signal Vi1, the two second reset lines transmitting the second reset signal Vi2 and the two third reset lines transmitting the third reset signal Vi3 are connected in parallel in the first display area 300, the transmittance of the display panel of the present application in the first display area 300 increases from 20.5% to 24.5%.

[0187] It should be noted that the above comparative examples are only examples of the present application, and the transmittance values are approximate values, and the transmittance of the actual product has certain error with the above values.

[0188] The present application also provides a display device, which comprises the display panel described above. The display device can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

[0189] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0190] The technical solutions provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a first display area, which is internally provided with a plurality of first pixel circuits and a plurality of light-transmitting portions, the plurality of light-transmitting portions being located between the plurality of first pixel circuits; a second display area, which is located at the periphery of the first display area, and is internally provided with a plurality of second pixel circuits; and a plurality of signal lines, each of the signal lines being connected with a row of the second pixel circuits, and at least two signal lines transmitting the same control signal being connected with a plurality of the same first pixel circuits. The display panel further comprises a non-display area provided on the side of the second display area away from the first display area, and the non-display area is internally provided with a gate drive circuit; 2. The display panel of claim 1, wherein, wherein the output end of the gate drive circuit is connected with at least one of the signal lines. The first pixel circuit and the second pixel circuit each comprise:

3. The display panel of claim 2, wherein, a switching transistor, the gate of the switching transistor receiving a switching control signal; a driving transistor, the driving transistor and the switching transistor being connected to a first node; a compensation transistor, the compensation transistor and the driving transistor being connected to a second node, and the gate of the compensation transistor receiving a compensation control signal; a first reset transistor, the first reset transistor, the compensation transistor and the driving transistor being connected to a third node, and the gate of the first reset transistor receiving a first reset control signal; a second reset transistor, the second reset transistor being connected to a fourth node, and the gate of the second reset transistor receiving a second reset control signal; a third reset transistor, the third reset transistor and the switching transistor being connected to the first node, and the gate of the third reset transistor receiving the second reset control signal; a first light-emitting transistor, the first light-emitting transistor and the switching transistor being connected to the first node, and the gate of the first light-emitting transistor receiving a light-emitting control signal; wherein the plurality of signal lines are used for transmitting at least one of the compensation control signal, the first reset control signal, the second reset control signal and the light-emitting control signal. The gate drive circuit comprises:

4. The display panel of claim 3, wherein, a first gate circuit, which is provided on both sides of the second display area, and is used for transmitting a compensation control signal; a second gate circuit, which is provided on both sides of the second display area, and is arranged along the second direction with the first gate circuit, and is used for transmitting a first reset control signal; a third gate circuit, which is provided on the first side of the second display area, and is located on the side of the first gate circuit away from the second display area, and is used for transmitting a second reset control signal; a fourth gate circuit, which is provided on the second side of the second display area, and is located on the side of the first gate circuit away from the second display area, and is used for transmitting a light-emitting control signal; a fifth gate circuit, which is provided on both sides of the second display area, and is located between the second display area and the first gate circuit and the second gate circuit, and is used for transmitting a switching control signal. ​ The plurality of signal lines include main compensation control lines, first main reset control lines, second main reset control lines, main light-emitting control lines and main switch control lines in the second display area; one first gate circuit is connected with two main compensation control lines; one second gate circuit is connected with two adjacent first main reset control lines; one third gate circuit is connected with two second main reset control lines; one fourth gate circuit is connected with two main light-emitting control lines; and one fifth gate circuit is connected with one main switch control line.

5. The display panel of claim 4, wherein, The plurality of signal lines further include auxiliary compensation control lines, first auxiliary reset control lines, second auxiliary reset control lines and auxiliary light-emitting control lines in the first display area. At least two main compensation control lines and one auxiliary compensation control line are electrically connected to a first parallel node; or / and, At least two first main reset control lines and one first auxiliary reset control line are electrically connected to the first parallel node; or / and, At least two second main reset control lines and one second auxiliary reset control line are electrically connected to the first parallel node; or / and, At least two main light-emitting control lines and one auxiliary light-emitting control line are electrically connected to the first parallel node.

6. The display panel of claim 5, wherein, The plurality of signal lines further include an auxiliary switch control line in the first display area; one main switch control line is electrically connected with one auxiliary switch control line.

7. The display panel of claim 6, wherein, The first display area further has at least one electrically connected segment of the first pixel circuit periphery in the same row, which is insulated from the auxiliary switch control line; One end of the electrically connected segment is electrically connected with one main switch control line insulated from the auxiliary switch control line in the second display area.

8. The display panel of claim 5, wherein, The first display area is provided with a plurality of pixel islands formed by a plurality of first pixel circuits, and a plurality of gaps are formed between the plurality of pixel islands. The plurality of pixel islands include a first pixel island and a second pixel island; the first pixel island is arranged adjacent to the second display area; the second pixel island is arranged adjacent to the first pixel island; and the first pixel island and the second pixel island each include a plurality of first pixel circuits. The first parallel node is located between the second display area and the first pixel island, or between the first pixel island and the second pixel island; the second parallel node is located between the second display area and the first pixel island, or between the first pixel island and the second pixel island; the third parallel node is located between the second display area and the first pixel island, or between the first pixel island and the second pixel island; and the fourth parallel node is located between the second display area and the first pixel island, or between the first pixel island and the second pixel island.

9. The display panel of claim 8, wherein, The distance between the second display area and the first pixel island is smaller than the distance between the first pixel island and the second pixel island.

10. The display panel of claim 8, wherein, The first parallel node, the third parallel node and the fourth parallel node are located between the first pixel island and the second pixel island, and the second parallel node is located between the second display area and the first pixel island.

11. The display panel of claim 8, wherein, The first display area further comprises a first extension section, a second extension section, a third extension section and a fourth extension section located at the periphery of the first pixel island, the second extension section is located between the second display area and the first pixel island, and the first extension section, the third extension section and the fourth extension section extend away from the second display area. One end of the first extension section is electrically connected to one of the main compensation control lines in the second display area, and the other end of the first extension section is electrically connected to the auxiliary compensation control line in the region where the first parallel node is located. One end of the second extension section is electrically connected to one of the first main reset control lines in the second display area, and the other end of the second extension section is electrically connected to the first auxiliary reset control line in the region where the second parallel node is located. One end of the third extension section is electrically connected to one of the second main reset control lines in the second display area, and the other end of the third extension section is electrically connected to the second auxiliary reset control line in the region where the third parallel node is located. One end of the fourth extension section is electrically connected to one of the main light-emitting control lines in the second display area, and the other end of the fourth extension section is electrically connected to the auxiliary light-emitting control line in the region where the fourth parallel node is located.

12. The display panel of claim 11, wherein, The first extension section is located close to the first pixel island, the fourth extension section is located on the side of the first extension section away from the first pixel island, and the third extension section is located on the side of the fourth extension section away from the first pixel island.

13. The display panel of claim 8, wherein, Each of the pixel islands comprises three first pixel circuits, and each of the first pixel circuits has the same structure. In the second display area, two adjacent second pixel circuits arranged in the first direction are symmetrically arranged with the center line of the two adjacent second pixel circuits as the axis.

14. The display panel of claim 1, wherein, The area of the first pixel circuit is smaller than the area of the second pixel circuit.

15. The display panel of any one of claims 1 to 14, wherein, The plurality of signal lines comprises a plurality of reset lines for transmitting reset signals to the first pixel circuits and the second pixel circuits, the plurality of reset lines only extends in the first direction in the first display area, and the plurality of reset lines forms a grid structure in the second display area.

16. The display panel of claim 15, wherein, The plurality of reset lines comprises a first main reset line, a second main reset line and a third main reset line located in the second display area. The first main reset line is used for transmitting a first reset signal, and is connected to a first reset transistor of the second pixel circuit; the second main reset line is used for transmitting a second reset signal, and is connected to a second reset transistor of the second pixel circuit; and the third main reset line is used for transmitting a third reset signal, and is connected to a third reset transistor of the second pixel circuit. In addition, the plurality of reset lines comprises a first auxiliary reset line, a second auxiliary reset line and a third auxiliary reset line located in the first display area. The first auxiliary reset line is used for transmitting the first reset signal, and is connected with the first reset transistor of the first pixel circuit; the second auxiliary reset line is used for transmitting the second reset signal, and is connected with the second reset transistor of the first pixel circuit; and the third auxiliary reset line is used for transmitting the third reset signal, and is connected with the third reset transistor of the first pixel circuit. At least two of the first main reset lines and one of the first auxiliary reset lines are electrically connected to a fifth parallel node, at least two of the second main reset lines and one of the second auxiliary reset lines are electrically connected to a sixth parallel node, and at least two of the third main reset lines and one of the third auxiliary reset lines are electrically connected to a seventh parallel node.

17. The display panel of claim 16, wherein, The second display area further comprises: A plurality of first connection sections arranged along the first direction and extending along a second direction, each of the first connection sections being electrically connected with the first main reset lines, and the first connection sections and the first main reset lines forming a mesh structure; A plurality of second connection sections arranged along the first direction and extending along a second direction, each of the second connection sections being electrically connected with the second main reset lines, and the second connection sections and the second main reset lines forming a mesh structure; A plurality of third connection sections arranged along the first direction and extending along a second direction, each of the third connection sections being electrically connected with the third main reset lines, and the third connection sections and the third main reset lines forming a mesh structure; The first connection sections, the second connection sections and the third connection sections are arranged at intervals along the first direction, the number of the first connection sections is less than the number of the second connection sections, and the number of the third connection sections is less than the number of the second connection sections.

18. The display panel of claim 17, wherein, The interval between two adjacent first connection sections is 8 widths of the second pixel circuit, the interval between two adjacent second connection sections is 4 widths of the second pixel circuit, and the interval between two adjacent third connection sections is 8 widths of the second pixel circuit.

19. The display panel of claim 16, wherein, The first display area further comprises: A fifth extension section arranged at the periphery of the first pixel island, one end of the fifth extension section being electrically connected with one of the first main reset lines in the second display area, and the other end of the fifth extension section being electrically connected with the first auxiliary reset line in the region where the fifth parallel node is located; A sixth extension section arranged between the first pixel island and the second display area, one end of the sixth extension section being electrically connected with one of the second main reset lines in the second display area, and the other end of the sixth extension section being electrically connected with the second auxiliary reset line in the region where the sixth parallel node is located; A seventh extension section arranged at the periphery of the first pixel island, one end of the seventh extension section being electrically connected with one of the third main reset lines in the second display area, and the other end of the seventh extension section being electrically connected with the third auxiliary reset line in the region where the seventh parallel node is located.

20. A display device comprising: The display device comprises the display panel as claimed in any one of claims 1 to 19.

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