Memory, and method for reading data stored in memory cell of memory

Abstract

The present disclosure relates to a memory. The memory comprises: a chip power source module; a memory array, which comprises a plurality of memory cells; a data output port, which is configured to output data stored in a selected memory cell; and a sensing self-locking module, which is connected to the chip power source module, the memory array and the data output port, and is configured to control the connection duration of a reading path during a reading operation on the basis of a power source voltage output by the chip power source module, and latch an output of the data output port when the connection of the read path ends, wherein the duration from a time when an enable signal for the reading operation changes to a first state to a time when the connection ends prolongs as the power source voltage decreases. In the present disclosure, after the data stored in the selected memory cell is transmitted to the data output port, the output of the data output port is latched to be in a state at the end of connection, so as to prevent the data in the memory cell in a "weak 1" state from changing from "0" to "1" at the data output port due to the fact that the reading time is excessively long, thereby improving the reliability of a reading result.

Description

Memory and method for reading data stored in memory cells of the memory Cross-reference to Related Applications This application claims priority to the Chinese patent application No. 202410965418X, filed on July 18, 2024, entitled “Memory and method for reading data stored in memory cells of the memory”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0001] The present disclosure relates to information storage, and in particular, to a memory and a method for reading data stored in memory cells of the memory. BACKGROUND

[0002] According to whether the stored data will be lost after power failure, the memory can be divided into volatile memory (RAM) and non-volatile memory (NVM). In recent years, the dual requirements of non-volatility and fast access have led to widespread attention to various NVMs.

[0003] NVM generally includes three basic operation modes of programming, erasing and reading. The programming and erasing operations change the initial electrical state of the memory cell, thereby “storing” data. The reading operation distinguishes different states of the memory cell and outputs the reading result. In an ideal state, the selected memory cell and the unselected memory cell of the NVM have obvious state difference after the programming / erasing operation, but in actual production, the memory cell has different degrees of disturb problem after programming / erasing.

[0004] Taking a multi-time programmable (MTP) non-volatile memory as an example: the initial state of the memory cell is “0”, after the programming operation, the electrical state of the memory cell changes, that is, the data “1” is stored; and then the erasing operation can restore the memory cell to the initial state, that is, the data “0” is stored. However, in actual use, the memory cell storing “0” may also exhibit a certain degree of “weak 1” state. This kind of disturb problem may come from two aspects: one is that the bias voltage during programming causes some unselected memory cells to also change to a certain degree of electrical change; the other is that the erasing operation fails to completely restore the memory cell storing “1” to the “0” state. Due to the requirements of “non-volatility” and “multi-time programmable” application environment, the above two disturb problems are often difficult to avoid. The “weak 1” state may cause incorrect reading results. SUMMARY

[0005] Therefore, it is necessary to provide a memory capable of eliminating the influence of the "weak 1" state on the reading result.

[0006] The memory provided by the embodiment of the present disclosure comprises a chip power module configured to supply power to the memory; a memory array comprising a plurality of memory cells; a data output port configured to output data stored in a selected memory cell in the plurality of memory cells; and a sensing self-locking module connected with the chip power module, the memory array and the data output port, configured to control the on duration of a reading path according to a power supply voltage output by the chip power module, and lock the output of the data output port at a state at the end of the on duration; wherein the reading path is a path through which the data output port receives the data stored in the selected memory cell during a reading operation; the duration from the change of an enable signal of the reading operation to the first state to the end of the on duration is prolonged with the decrease of the power supply voltage and shortened with the increase of the power supply voltage, and the end time of the on duration is later than the time when the data stored in the selected memory cell is transmitted to the data output port and earlier than the end time of the first state of the enable signal.

[0007] The memory provided by the embodiment of the present disclosure comprises a chip power module configured to supply power to the memory; a memory array comprising a plurality of memory cells; a data output port configured to output data stored in a selected memory cell in the plurality of memory cells; and a sensing self-locking module connected with the chip power module, the memory array and the data output port, configured to control the on duration of a reading path according to a power supply voltage output by the chip power module, and lock the output of the data output port at a state at the end of the on duration; wherein the reading path is a path through which the data output port receives the data stored in the selected memory cell during a reading operation; the duration from the change of an enable signal of the reading operation to the first state to the end of the on duration is prolonged with the decrease of the power supply voltage and shortened with the increase of the power supply voltage, and the end time of the on duration is later than the time when the data stored in the selected memory cell is transmitted to the data output port and earlier than the end time of the first state of the enable signal.

[0008] In one of the embodiments, the sensing self-locking module comprises a comparison circuit, a first input end of the comparison circuit is configured to input a reference voltage, a second input end of the comparison circuit is configured to input the power supply voltage, and the comparison circuit is configured to compare the power supply voltage with the reference voltage; a gear tuning circuit, an input end of the gear tuning circuit is connected with an output end of the comparison circuit, and the gear tuning circuit is configured to obtain a gear selection signal according to the comparison result output by the comparison circuit; and a delay circuit, a first input end of the delay circuit is connected with an output end of the gear tuning circuit, and the delay circuit is configured to adjust the on duration according to the gear selection signal.

[0009] In one of the embodiments, a second input end of the delay circuit is configured to input the enable signal of the reading operation, and the delay circuit is configured to determine the start time of the on duration of the reading path according to the start time of the first state of the enable signal.

[0010] In one of the embodiments, the memory further comprises a sense amplifier, the read path is a path between an output of the sense amplifier and the data output port, and the sense amplifier is configured to identify the data stored in the selected memory cell and output the identification result to the data output port.

[0011] In one of the embodiments, the memory further comprises a multiplexer, an input of the multiplexer is connected to the memory array, and an output of the multiplexer is connected to the sense amplifier, and the multiplexer is configured to transmit the data stored in the selected memory cell to the sense amplifier.

[0012] In one of the embodiments, the conduction duration is prolonged as the power voltage decreases and shortened as the power voltage increases, the conduction duration is shorter than a first state duration of the enable signal of the read operation and longer than a duration from a starting time of the first state to a time when the data stored in the selected memory cell is transmitted to the data output port.

[0013] In one of the embodiments, the memory is a non-volatile memory.

[0014] In one of the embodiments, the first state is a high level.

[0015] It is also necessary to provide a method for reading data stored in a memory cell of a memory.

[0016] A method for reading data stored in a memory cell of a memory, comprising: obtaining an enable signal and an address signal of a read operation; selecting a memory cell to be read in the memory according to the address signal; transmitting the data stored in the selected memory cell to a data output port through a read path in response to the enable signal; controlling a conduction duration of the read path according to a power voltage of a chip power supply of the memory and locking an output of the data output port in a state at an end of the conduction; wherein a duration from a change of the enable signal to a first state to the end of the conduction is prolonged as the power voltage of the chip power supply decreases and shortened as the power voltage increases, and the end of the conduction is later than a time when the data is transmitted to the data output port and earlier than an end of the first state of the enable signal.

[0017] The method for reading the data stored in the memory unit of the memory, in the reading operation, after the data stored in the selected memory unit is transmitted to the data output port, the output of the data output port is locked in the state at the end of the conduction, avoiding the data of the memory unit in the "weak 1" state caused by the long reading time from changing from "0" to "1" at the data output port, and improving the reliability of the reading result. The moment of the end of the conduction follows the change of the voltage of the chip power supply, avoiding the reading path being closed before the data stored in the selected memory unit is transmitted to the data output port when the voltage of the power supply is low.

[0018] In one of the embodiments, the step of controlling the conduction duration of the reading path according to the power supply voltage of the chip power supply of the memory comprises: comparing the power supply voltage with the reference voltage; selecting a gear according to the comparison result; and adjusting the conduction duration according to the gear.

[0019] In one of the embodiments, the conduction duration is prolonged with the decrease of the power supply voltage and shortened with the increase of the power supply voltage, and the conduction duration is less than the duration of the first state of the enable signal of the reading operation and greater than the duration from the start moment of the first state to the transmission of the data stored in the selected memory unit to the data output port.

[0020] In one of the embodiments, the memory is a non-volatile memory.

[0021] In one of the embodiments, the first state is high level.

[0022] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0024] FIG. 1 is a structural schematic diagram of part of the modules of the memory related to the reading operation in an embodiment of the present application.

[0025] FIG. 2 is a structural schematic diagram of part of the modules of the memory related to the reading operation in another embodiment of the present application.

[0026] FIG. 3 is a structural schematic diagram of part of the modules of the memory related to the reading operation in yet another embodiment of the present application.

[0027] Figure 4 is a timing diagram of a read operation in an embodiment of the present application.

[0028] Figure 5 is a structural diagram of the sensing self-locking module 130 in an embodiment of the present application.

[0029] Figure 6 is a flow chart of a method of reading data stored in a memory cell of a memory in an embodiment of the present application.

[0030] Figure 7 is a flow chart of a sub-step of step S640 in an embodiment of the present application. DETAILED DESCRIPTION

[0031] For the purpose of promoting an understanding of the disclosure, the present disclosure will now be described in greater detail with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] When the read time is long enough, the memory cell in a "weak 1" state is often identified as "1" (the correct identification result should be "0").

[0035] To improve the reliability of read results, one method is to screen out chips with more obvious "weak 1" conditions through a more stringent Margin Read step in the testing process. Margin Read is a step in the chip testing process, and the purpose is to screen out chips with storage cells that do not meet the requirements. By setting the screening conditions of Margin Read to be more stringent, chips with obvious "weak 1" performance can be screened out. However, this method narrows the range of qualified chips, and the storage cells screened out will inevitably cause yield loss of the product.

[0036] The present application provides a memory capable of eliminating the influence of "weak 1" state on read results. FIG. 1 is a structural schematic diagram of part of modules of the memory related to read operation in an embodiment of the present application, including a chip power module (for example, IP power, Internet protocol power) 110, a memory array 120, a sensing self-locking module 130, and a data output port 140. The memory can be a non-volatile memory (NVM). The chip power module 110 is used to power each module of the memory. The memory array 120 includes a plurality of storage cells. In a read operation, the memory selects the corresponding storage cells through address decoders, word lines, bit lines, and other circuits, and then transmits the data stored in the selected storage cells to the data output port 140 through a read path, and outputs the data stored in the selected storage cells by the data output port 140. The sensing self-locking module 130 is connected with the chip power module 110, the memory array 120, and the data output port 140, and is used to control the conduction time of the read path during the read operation according to the power voltage output by the chip power module 110, and lock the output DOUT of the data output port 140 at the state at the end of the conduction (or at the moment before the end of the conduction) of the read path until the next cycle.

[0037] The inductive self-locking module 130 controls the on duration of the read path according to the power supply voltage. The on duration is extended as the power supply voltage decreases and shortened as the power supply voltage increases. The on duration ends later than the time when the data stored in the selected memory cell is transmitted to the data output port 140 and earlier than the end of the first state of the enable signal RD. The time from the beginning of the change of the enable signal RD to the first state to the end of the on duration of the read path is denoted as Tl. In one embodiment of the present application, Tl is extended as the power supply voltage decreases and shortened as the power supply voltage increases. This is because the change of the power supply voltage has a significant impact on the time (i.e. the memory information reading time Taa) when the data stored in the selected memory cell is transmitted to the data output port 140. The reading speed is faster when the power supply voltage is higher, i.e. Taa is smaller. When the power supply voltage is lower, Taa is significantly extended. Engineers can obtain the approximate range of Taa under different power supply voltages in specific memories according to experience and actual tests, and design the inductive self-locking module 130 to make the end of the on duration of the read path later than the time when the data stored in the selected memory cell is transmitted to the data output port 140. In one embodiment of the present application, the first state of the enable signal RD is high. In other embodiments, the first state of the enable signal RD can also be low.

[0038] The above memory sets the inductive self-locking module. After the data stored in the selected memory cell is transmitted to the data output port 140 during the reading operation, the output DOUT of the data output port 140 is locked in the state at the end of the on duration of the read path, avoiding the data of the memory cell in the "weak 1" state changing from "0" to "1" at the data output port due to the excessively long reading time, and improving the reliability of the reading result. The end of the on duration follows the change of the voltage of the chip power supply, avoiding the read path being closed before the data stored in the selected memory cell is transmitted to the data output port when the power supply voltage is low. Some memory cells in the "weak 1" state can not be screened out, thereby improving the product yield.

[0039] Fig. 2 is a structural schematic diagram of part of the modules of the memory related to the reading operation in another embodiment of the present application, which further includes a sense amplifier 150 relative to the structure shown in Fig. 1. In the embodiment shown in Fig. 2, the read path is the path between the output end of the sense amplifier 150 and the data output port 140. The sense amplifier 150 is used to identify the data stored in the selected memory cell (i.e. identify whether the stored data is "0" or "1"), and output the identification result to the data output port 140.

[0040] Figure 3 is a schematic diagram of a portion of the memory of another embodiment of the application, which further comprises a multiplexer 160 (MUX) relative to the structure shown in Figure 2. The multiplexer 160 is connected to the memory array 120 at its input and to the sense amplifier 150 at its output, and is used to transfer the data stored in the selected memory cell to the sense amplifier 150. The memory shown in Figure 3 can be a multi-time programmable (MTP) non-volatile memory.

[0041] Figure 4 is a timing diagram of a read operation in an embodiment of the application. In the figure, RD is the enable signal of the read operation, Trh is the width (duration) of the high level in one cycle of RD, and Trl is the width (duration) of the low level in one cycle of RD. DOUT is the output result of the read operation at the data output port 140. Taa is the storage information read time (i.e. the duration of the transfer of the data stored in the memory cell to the data output port 140). SALAT is the control signal of the sense latch module, and Tlat is the width of the high level in one cycle of the SALAT signal. ADD is the address signal, and the address decoding circuit in the memory can select the memory cell for reading the stored data according to the ADD. When RD becomes high (i.e. at the time corresponding to the leftmost vertical dashed line in Figure 4), the circuits related to the read operation in the memory start to work, and the data stored in the memory cell is transferred to the sense amplifier 150 via the multiplexer 160. At the same time, the SALAT signal changes from low to high, and the read path from the sense amplifier 150 to the data output port 140 is opened. After Taa, the data read by the sense amplifier 150 is transferred to the data output port 140 as the output result DOUT, and the data output port 140 starts to output valid data. After the duration of the read path reaches Tlat, the read path is closed, and DOUT is latched as the result at this moment. In the current read cycle (i.e. one Trh plus one Trl), the result read (output) by the sense amplifier 150 will no longer affect DOUT, thereby avoiding the read error that can be caused by the "weak 1" state.

[0042] Referring to FIG. 5, in an embodiment of the present application, the inductive self-locking module 130 comprises a comparison circuit 132, a gear trim circuit 134 and a delay circuit 136. The first input terminal of the comparison circuit 132 is used to input a reference voltage Vref, and the second input terminal is connected to the chip power module 110 to input a power voltage, so as to compare the power voltage with the voltage value of the reference voltage. The input terminal of the gear trim circuit 134 is connected to the output terminal of the comparison circuit 132, and is used to obtain a gear selection signal according to the comparison result output by the comparison circuit 132. The first input terminal of the delay circuit 136 is connected to the output terminal of the gear trim circuit 134, and is used to adjust the on duration of the read path according to the gear selection signal. In the embodiment shown in FIG. 5, the second input terminal of the delay circuit 136 is used to input an enable signal RD of the read operation. The delay circuit 136 is configured to determine the starting time of the read path conduction according to the starting time of the first state of RD, that is, the delay circuit 136 controls the read path to be conducted when it detects that RD becomes the first state, and adjusts the on duration of the read path according to the gear selection signal.

[0043] In the embodiment shown in FIG. 5, the process of generating the SALAT signal is as follows: the comparison circuit compares the power voltage with the reference voltage Vref, and the comparison result enters the gear trim circuit 134 to generate a gear selection signal. At the same time, the enable signal RD of the read operation enters the delay circuit 136, and the delay circuit 136 generates a delay of different gears according to the gear selection signal to generate the SALAT signal, thereby improving the flexibility of the control signal. Wherein: Taa

[0044] In an embodiment of the present application, the enable signal RD is first changed from low to high during the read operation, the multiplexer 160 is opened, and the data stored in the storage unit selected by the address signal ADD reaches the sense amplifier 150 through the multiplexer 160. At the same time, the enable signal RD enters the delay circuit 136, and the delay circuit 136 generates a delay of different gears according to the gear selection signal generated by the gear trim circuit 134 to generate the SALAT signal, and the read path between the sense amplifier 150 and the data output port 140 is opened. After the enable signal RD is changed from low to high, the data stored in the selected storage unit is judged and output by the sense amplifier 150, the recognition result is output to the data output port 140 through the read path, and the result DOUT of this read operation is obtained. After another (Tlat-Taa) time, the SALAT signal is changed from high to low, the read path is closed, and DOUT is locked in the state at this moment. In the current read cycle, the subsequent recognition result of the sense amplifier 150 will no longer affect DOUT.

[0045] The application provides a method for reading data stored in a memory cell of a memory. FIG. 6 is a flow chart of the method for reading data stored in a memory cell of a memory according to an embodiment of the application, including the following steps S610-S650.

[0046] In step S610, an enable signal and an address signal of a read operation are obtained.

[0047] When the read operation arrives, the memory will receive the enable signal RD and the address signal ADD.

[0048] In step S620, the memory cell to be read is selected according to the address signal.

[0049] The address decoder of the memory can decode the address signal ADD and then select the corresponding memory cell.

[0050] In step S630, the data stored in the selected memory cell is transmitted to the data output port through the read path in response to the enable signal.

[0051] When the enable signal RD changes to the first state, the read path starts to conduct, and the data stored in the selected memory cell is transmitted to the data output port through the read path. In one embodiment of the application, the first state of the enable signal RD is high; in other embodiments, the first state of the enable signal RD can also be low.

[0052] In step S640, the conduction duration of the read path is controlled according to the power supply voltage of the chip power supply.

[0053] The duration from the start of the change of the enable signal RD to the first state to the end of the conduction of the read path (i.e. the closing of the read path) is prolonged with the decrease of the power supply voltage of the chip power supply and shortened with the increase of the power supply voltage. Moreover, the end time of the conduction of the read path is later than the data transmission time to the data output port and earlier than the end time of the first state of the enable signal.

[0054] In step S650, the output of the data output port is locked in the state at the end of the conduction of the read path.

[0055] After the read path is closed, the output of the data output port is locked in the state at the end of the conduction of the read path until the next cycle arrives.

[0056] The method for reading the data stored in the memory cell of the memory, in the reading operation, after the data stored in the selected memory cell is transmitted to the data output port, the output of the data output port is locked in the state at the end of the conduction, avoiding the data of the memory cell in the "weak 1" state caused by the long reading time from changing from "0" to "1" at the data output port, and improving the reliability of the reading result. The moment of the end of the conduction changes with the voltage of the chip power supply, avoiding the reading path being closed before the data stored in the selected memory cell is transmitted to the data output port when the voltage of the power supply is low.

[0057] Referring to FIG. 7, in an embodiment of the present application, the step S640 comprises steps S642-S646.

[0058] In step S642, the power supply voltage is compared with the reference voltage.

[0059] In an embodiment of the present application, the power supply voltage of the chip power supply and the reference voltage can be input to one input terminal of the voltage comparator.

[0060] In step S644, the gear is selected according to the comparison result.

[0061] In an embodiment of the present application, the gear is selected according to the output of the voltage comparator.

[0062] In step S646, the conduction duration is adjusted according to the gear.

[0063] In an embodiment of the present application, the conduction duration is prolonged with the decrease of the power supply voltage and shortened with the increase of the power supply voltage, the conduction duration is less than the duration of the first state of the enable signal of the reading operation and greater than the duration from the start of the first state to the transmission of the data stored in the selected memory cell to the data output port.

[0064] It should be understood that, although each step in the flowchart of the present application is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart of the present application can comprise multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0065] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0066] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present disclosure.

[0067] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A memory, comprising: a chip power module configured to supply power to the memory; a memory array comprising a plurality of memory cells; a data output port configured to output data stored in a selected memory cell of the plurality of memory cells; a sensing self-locking module connected with the chip power module, the memory array and the data output port, and configured to control a turn-on duration of a read path according to a supply voltage output by the chip power module, and lock an output of the data output port at a state at the end of the turn-on; wherein the read path is a path through which the data output port receives the data stored in the selected memory cell during a read operation; a duration from a first state of an enable signal of the read operation to the end of the turn-on is prolonged as the supply voltage decreases and shortened as the supply voltage increases; and the end of the turn-on is later than a time when the data stored in the selected memory cell is transmitted to the data output port and earlier than an end of the first state of the enable signal.

2. The memory of claim 1, wherein, the sensing self-locking module comprises: a comparison circuit, a first input of the comparison circuit is configured to input a reference voltage, a second input of the comparison circuit is configured to input the supply voltage, and the comparison circuit is configured to compare the supply voltage with the reference voltage; a gear trimming circuit, an input of the gear trimming circuit is connected with an output of the comparison circuit, and the gear trimming circuit is configured to obtain a gear selection signal according to a comparison result output by the comparison circuit; a delay circuit, a first input of the delay circuit is connected with an output of the gear trimming circuit, and the delay circuit is configured to adjust the turn-on duration according to the gear selection signal.

3. The memory of claim 2, wherein, a second input of the delay circuit is configured to input the enable signal of the read operation, and the delay circuit is configured to determine a start time of the turn-on of the read path according to a start time of the first state of the enable signal. 4.The memory of any one of claims 1-3, further comprising a sense amplifier, the read path is a path between an output of the sense amplifier and the data output port, the sense amplifier is configured to identify the data stored in the selected memory cell and output an identification result to the data output port. 5.The memory of claim 4, further comprising a multiplexer, an input of the multiplexer is connected with the memory array, and an output of the multiplexer is connected with the sense amplifier, the multiplexer is configured to transmit the data stored in the selected memory cell to the sense amplifier. 6.The memory of any one of claims 1-5, wherein the turn-on duration is prolonged as the supply voltage decreases and shortened as the supply voltage increases, the turn-on duration is shorter than a duration of the first state of the enable signal of the read operation and longer than a duration from a start time of the first state to a time when the data stored in the selected memory cell is transmitted to the data output port.

7. The memory of any one of claims 1-6, wherein, The memory is a non-volatile memory.

8. The memory of any one of claims 1-7, wherein, The chip power module includes an Internet Protocol (IP) power.

9. The memory of any one of claims 1-8, wherein, The first state of the enable signal is a high level; or, the first state of the enable signal is a low level.

10. The memory of any one of claims 1-9, wherein, The memory is configured to select the corresponding memory cell through an address decoder, a word line, and a bit line.

11. A method for reading data stored in a memory cell of a memory, comprising: obtaining an enable signal and an address signal of a read operation; selecting a memory cell to be read in the memory according to the address signal; transmitting data stored in the selected memory cell to a data output port through a read path in response to the enable signal; controlling a conduction duration of the read path according to a power voltage of a chip power of the memory; latching an output of the data output port at the end of the conduction of the read path; wherein the duration from the enable signal changing to the first state to the end of the conduction is prolonged as the power voltage of the chip power decreases and shortened as the power voltage increases, the end of the conduction is later than the time when the data is transmitted to the data output port and earlier than the end of the first state of the enable signal.

12. The method of reading data stored by memory cells of a memory as recited in claim 11, wherein, The step of controlling the conduction duration of the read path according to the power voltage of the chip power of the memory comprises: comparing the power voltage with a reference voltage; selecting a gear according to the comparison result; adjusting the conduction duration according to the gear.

13. The method for reading data stored in a memory cell of a memory according to claim 11 or 12, wherein, the conduction duration is prolonged as the power voltage decreases and shortened as the power voltage increases, the conduction duration is shorter than the duration of the first state of the enable signal of the read operation and longer than the duration from the start of the first state to the time when the data stored in the selected memory cell is transmitted to the data output port.

14. The method of reading data stored by memory cells of a memory according to any one of claims 11-13, wherein, The method further comprises determining the start time of the conduction of the read path according to the start time of the first state of the enable signal.

15. The method of reading data stored by memory cells of a memory as recited in claim 11, wherein, The step of transmitting data stored in the selected memory cell to a data output port through a read path in response to the enable signal comprises: identifying the data stored in the selected memory cell in response to the enable signal and outputting the identification result to the data output port.

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