Junction field-effect transistor

Abstract

The present disclosure relates to a junction field-effect transistor (JFET), comprising: a substrate; a shallow trench isolation structure; a well region, at least partially located below the shallow trench isolation structure and at least partially located above the substrate; a plurality of deep trench structures, wherein one deep trench structure is arranged at intervals in the width direction of a conductive channel, the depth of each deep trench structure is greater than the depth of the well region, thereby dividing the well region into a plurality of regions, each deep trench structure comprises an insulating layer located on the trench wall of a deep trench and an isolation region gate located in the deep trench and surrounded by the insulating layer, and the shallow trench isolation structure surrounds the deep trench structures; a source region, directly connected to the well region; a drain region, directly connected to the well region, wherein the shallow trench isolation structure is at least partially located between the source region and the drain region, and the deep trench structures are located between the source region and the drain region; and a channel gate, located on the shallow trench isolation structure between the source region and the drain region and located above the surface of the conductive channel. In the present disclosure, a JFET having different cut-off voltages can be formed in one die.

Description

Junction Field-Effect Transistor Cross-references to related applications This application claims to have been filed with the Chinese Patent Office on July 19, 2024, application number 2024109718181, invention. Priority is given to the Chinese patent application entitled “Junctional Field Effect Transistor Device Structure”, the entire contents of which are incorporated herein by reference. Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to a junction field-effect transistor (JFET). Background Technology

[0002] Forming high-voltage JFET (Junction Field-Effect Transistor) devices with different cutoff voltages within a single die (DIE) is a challenge in the development of BCD (Bipolar-Complementary Metal Oxide Semiconductor-Double-Diffused Metal Oxide Semiconductor, Bipolar-CMOS-DMOS) process platforms. This is because the cutoff voltage of a JFET device is determined by the doping concentration of the channel. A traditional approach to achieving multiple cutoff voltages involves adding multiple JFET device channel injection photomasks, significantly increasing manufacturing costs and reducing the market competitiveness of the process platform. Summary of the Invention

[0003] Therefore, it is necessary to provide a junction field-effect transistor that can be formed in a die (DIE) with different cutoff voltages.

[0004] A junction field-effect transistor (JFET) includes: a substrate; a shallow trench isolation structure; a well region, at least partially located below the shallow trench isolation structure and at least partially located above the substrate, a portion of the well region serving as a channel region of the JFET and a portion serving as a drift region of the JFET; a plurality of deep trench structures, each deep trench structure being spaced at intervals along the width of a conductive channel, the depth of each deep trench structure being greater than the depth of the well region, thereby dividing the well region into a plurality; each deep trench structure including an insulating layer located on the trench wall of the deep trench structure and an isolation gate located in the deep trench structure and surrounded by the insulating layer; the shallow trench isolation structure surrounding each deep trench structure in its cross-section; a source region directly connected to the well region; a drain region directly connected to the well region; the shallow trench isolation structure being at least partially located between the source region and the drain region, and each deep trench structure being located between the source region and the drain region; and a channel gate located on the shallow trench isolation structure between the source region and the drain region and above the surface of the conductive channel.

[0005] In the aforementioned junction field-effect transistor, the well region is divided into multiple conductive channels by deep trench structures. The width of each conductive channel is the spacing between adjacent deep trench structures. The cutoff voltage of each JFET is affected by the width of the corresponding conductive channel. Therefore, by designing the spacing between adjacent deep trench structures, JFETs with different cutoff voltages can be formed in a single die.

[0006] In one embodiment, each of the deep trench structures extends along the length of the conductive channel.

[0007] In one embodiment, the isolation region gate and the channel gate are made of polysilicon.

[0008] In one embodiment, the gate of each isolation region is grounded.

[0009] In one embodiment, the junction field-effect transistor (JFET) includes a runway region, a football field region located within the runway region, and a rectangular region on each side of the runway region. The direction of the line connecting the two sides is the length direction of the conductive channel, and the direction of the line connecting the two ends of the runway region is the width direction of the conductive channel. The football field region is the voltage withstand region of the drift region. The channel region is located on both sides of the drift region, and the rectangular regions at least partially overlap with the drift region. The drain region is located in the football field region and extends along the width direction of the conductive channel. The source region is provided in each of the two rectangular regions, and each deep trench structure is located between the source region and the drain region. Each deep trench structure is at least partially located in one of the two rectangular regions. The JFET also includes an arc-shaped deep trench isolation structure at each end of the runway region. Each end of each deep trench isolation structure is connected to the outermost deep trench structure in the rectangular region, and the insulating material in each deep trench isolation structure is integrated with the insulating layer in the connected deep trench structure to form a device peripheral isolation region.

[0010] In one embodiment, the portion of the well region located outside the two deep trench isolation structures is integrated with the well regions surrounding the two source regions.

[0011] In one embodiment, the portion of the shallow trench isolation structure located on the drift region serves as a field oxygen layer.

[0012] In one embodiment, the junction field-effect transistor further includes a drift region field plate distributed in a ring along the raceway region, the drift region field plate being at least partially located on the field oxide layer, the drift region field plate being made of the same material as the channel gate and being integrally connected to the channel gate.

[0013] In one embodiment, the source region, drain region, and well region are doped with the same type.

[0014] In one embodiment, the source region, drain region, and well region are N-type regions, and the substrate is a P-type region.

[0015] In one embodiment, the gate material of the isolation region is N-type doped polysilicon.

[0016] In one embodiment, the bottom of the isolation region gate of each of the deep trench structures is connected to the substrate. Attached Figure Description

[0017] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0018] Figure 1 is a layout of a junction field-effect transistor in one embodiment of this application.

[0019] Figure 2a is a layout of a portion of the structure in Figure 1, and Figure 2b is also a layout of a portion of the structure in Figure 1.

[0020] Figure 3 is a cross-sectional view along line A-A' in Figure 1.

[0021] Figure 4 is a cross-sectional view along line B-B' in Figure 1.

[0022] Figure 5 is a cross-sectional view along line C-C' in Figure 1.

[0023] Figure 6 is a cross-sectional view along line D-D' in Figure 1. Detailed Implementation

[0024] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. The term "connection" in this specification, if referring to the transmission of electrical signals or data between connected circuits, modules, units, etc., should be understood as "electrical connection," "communication connection," etc. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that “at least one” means one or more, and “a plurality” means two or more. “At least a portion of an element” means part or all of an element. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Embodiments of this disclosure are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of this disclosure.

[0030] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0031] An exemplary JFET device with adjustable cutoff voltage (taking an N-channel JFET device as an example) has N-wells in the channel region arranged in a strip shape along the current flow direction, and the width of the N-wells determines the cutoff voltage of the device. High-voltage P-wells surround the strip-shaped high-voltage N-wells to help deplete the high-voltage N-wells and achieve pinch-off cutoff in the channel region. However, in this type of JFET device, the high-voltage N-wells and high-voltage P-wells are distributed adjacent to each other, requiring a long furnace tube pushing process. The doping concentration of the strip-shaped high-voltage N-wells in the channel is easily affected by the diffusion concentration of the high-voltage P-wells, leading to unstable cutoff voltage characteristics of the JFET high-voltage device and affecting mass production.

[0032] This disclosure presents a novel layout design for junction field-effect transistors (JFETs). By adjusting the width between deep trench isolation (DTI) layers, different cutoff voltage requirements can be achieved. The process cost is low and the fabrication method is simple.

[0033] This disclosure provides a junction field-effect transistor, including:

[0034] Substrate 110;

[0035] Shallow Trench Isolation (STI) 140;

[0036] Well region 120 is at least partially located below shallow trench isolation structure 140 and at least partially located above substrate 110, with a portion of well region 120 serving as channel region of junction field-effect transistor and a portion serving as drift region of junction field-effect transistor.

[0037] Multiple deep trench structures 150 are provided at intervals along the channel width direction. The depth of each deep trench structure 150 is greater than the depth of the well region 120, thereby dividing the well region 120 into multiple sections. Each deep trench structure 150 includes an insulating layer 152 located on the trench wall of the deep trench structure 150 and an isolation gate 154 located in the deep trench structure 150 and surrounded by the insulating layer 152. Shallow trench isolation structures 140 surround each deep trench structure 150 in their cross-section (e.g., the cross-section in the XZ plane as shown in FIG. 4, and / or, the cross-section in the YZ plane as shown in FIG. 5). The deep trench structures 150 serve to assist in channel depletion.

[0038] Source region 132 is directly connected to well region 120;

[0039] Drain region 134 is directly connected to well region 120; shallow trench isolation structure 140 is at least partially located between source region 132 and drain region 134, and each deep trench structure 150 is located between source region 132 and drain region 134.

[0040] The channel gate 136 is located on the shallow trench isolation structure 140 between the source region 132 and the drain region 134, and is located above the conductive channel surface.

[0041] In the aforementioned junction field-effect transistor (JFET), the well region 120 is divided into multiple conductive channels by deep trench structures 150. The width of each conductive channel is the spacing between adjacent deep trench structures 150. The cutoff voltage of each JFET is affected by the width of the corresponding conductive channel. Therefore, by designing the spacing between adjacent deep trench structures 150, JFETs with different cutoff voltages can be formed in a single die. Figure 1 is a layout of a junction field-effect transistor according to an embodiment of this application. Figure 2a is a layout of a portion of the structure in Figure 1, and Figure 2b is also a layout of a portion of the structure in Figure 1, with additional structures compared to Figure 2a. Figure 3 is a cross-sectional view along line A-A' in Figure 1 (the dashed line in Figure 3 represents the boundary between the channel region and the drift region), Figure 4 is a cross-sectional view along line B-B' in Figure 1, Figure 5 is a cross-sectional view along line C-C' in Figure 1, and Figure 6 is a cross-sectional view along line D-D' in Figure 1. The structures in all the above figures are symmetrical from left to right, therefore some structures are labeled only on one side. Furthermore, the dimensional proportions of each structure in the sectional view are not necessarily the same as those of each structure in Figure 1.

[0042] In one embodiment of this application, each deep trench structure 150 extends along the length direction of the conductive channel (i.e., the X-axis direction in FIG2a).

[0043] In one embodiment of this application, the isolation gate 154 and the channel gate 136 are made of polysilicon.

[0044] In one embodiment of this application, the isolation region gate 154 is grounded and the channel gate 136 is connected to the gate potential, so as to jointly control the opening and closing of the conductive channel, that is, control the opening and closing of the JFET.

[0045] In one embodiment of this application, the junction field-effect transistor (JFET) includes a runway region (e.g., the annular region shown in FIG1) in a plane (i.e., the shape of the cross-section in the XY plane as shown in FIG1, 2a, and 2b), a football field region located within the runway region, and a rectangular region on each side of the runway region. The football field region serves as the voltage withstand region of the drift region, and the rectangular regions at least partially overlap with the drift region. The two sides of the runway region refer to the left and right sides in FIG1. ​​The two ends of the runway region are the upper and lower ends of the runway region in FIG1. ​​The drain region 134 is located in the football field region and extends along the width direction of the conductive channel (i.e., the Y-axis direction in FIG1). The source region 132 is provided in each of the two rectangular regions, and each deep trench structure 150 is located between the source region 132 and the drain region 134. In FIG1, the source region 132 is located near the edge of the two rectangular regions in the X-axis direction. Referring to FIG2a, each deep trench structure 150 is at least partially located in one of the two rectangular regions. The junction field-effect transistor also includes a deep trench isolation structure 151 that is arc-shaped on the plane at each end of the raceway region. Each end of the deep trench isolation structure 151 is connected to the outermost deep trench structure 150 of a rectangular region. The insulating material in each deep trench isolation structure 151 is integrated with the insulating layer 152 in the deep trench structure 150 to which it is connected, and together they form the peripheral isolation region of the device, which isolates the device (JFET) inside the peripheral isolation region from the device or circuit outside the region (insulation isolation).

[0046] In one embodiment of this application, the portion of the well region 120 located outside the two deep trench isolation structures 151 (see Figures 1, 2a and 2b) is integrated with the well region 120 surrounding the two source regions 132.

[0047] In one embodiment of this application, the junction field-effect transistor includes a drift region field plate 137 arranged in a ring along the raceway region. In another embodiment, the portion of the shallow trench isolation structure 140 located on the drift region serves as a field oxide layer (while the portion of the shallow trench isolation structure 140 located on the channel region houses the channel gate 136). The drift region field plate 137 is located on this field oxide layer, and the material of the drift region field plate 137 is the same as that of the channel gate 136, and they are integrally connected. The field oxide layer and the drift region field plate 137 together form a field plate structure, which helps the drift region exhaust its breakdown voltage.

[0048] In one embodiment of this application, the source region 132, drain region 134, and well region 120 have the same doping type. In the embodiment shown in FIG3, the source region 132, drain region 134, and well region 120 are N-type regions, and the substrate 110 is a P-type region. The source region 132 and drain region 134 are located in the well region 120. Further, the source region 132 and drain region 134 are N+ regions, and the well region 120 is a high-voltage N-well (HV N-well), with the doping concentration of the source region 132 and drain region 134 being greater than the doping concentration of the well region 120. The area enclosed by the dotted line in FIG1, FIG2a, and FIG2b is the N+ implantation region, used for ion implantation of the source region 132 and drain region 134.

[0049] In one embodiment of this application, the isolation region gate 154 is made of N-type doped polysilicon.

[0050] In one embodiment of this application, the bottom of each deep trench structure 150 is not provided with an insulating layer 152, thereby connecting the bottom of the isolation gate 154 to the substrate 110.

[0051] In one embodiment of this application, a junction field-effect transistor (JFET) is fabricated in a single well region 120, divided into a channel region and a drift region, as shown in Figure 1. As shown in Figure 2a, the drain region 134 and source region 132 of the JFET are formed in the active region, while other structures of the JFET are formed in the region with shallow trench isolation structures 140. In the channel region, multiple deep trench structures 150 are spaced apart, dividing the well region 120 (i.e., the high-voltage N-well HNV) into several strip-shaped N-type channels. As shown in Figure 2b, the deep trench structures 150 (not shown in Figure 2b) are filled with highly doped N-type polysilicon material to form the isolation gate 154. A conventional MOS (Metal-Oxide-Semiconductor) gate poly layer is deposited above each strip-shaped N-type channel to form the channel gate 136. The isolation region gate 154 is grounded, and the channel gate 136 is connected to the gate potential, which together control the JFET device to turn on or off.

[0052] Figure 3 is a cross-sectional view along line A-A' in Figure 1, showing the JFET current conduction path. The JFET current conduction path is formed throughout the entire well region 120 (high-voltage N-well HNV). The portion of the shallow trench isolation structure 140 above the channel region is used to prevent gate oxide breakdown caused by excessive Vgs (gate-source voltage) bias, while the portion above the drift region (i.e., the field oxide layer) is used to help meet the high breakdown voltage requirements of the device. In the JFET's on-state, the operating current flows from the source through the N-type channel into the drift region and finally flows out through the drain. Figure 4 is a cross-sectional view along line B-B' in Figure 1, showing the deep trench structure 150 of the JFET channel region. The deep trench structure 150 is designed primarily to regulate the device's cutoff voltage and help deplete the N-type channel; no current flows through the deep trench structure 150 when the JFET is on.

[0053] Figure 5 is a cross-sectional view along line C-C' in Figure 1, showing the channel structure distribution perpendicular to the current conduction path. In Figure 5, high-voltage N-wells (HVN) and deep trench structures 150 are alternately distributed, with each high-voltage N-well channel flanked by adjacent deep trench structures 150. When Vgs < 0, under the combined action of the channel gate 136 and the isolation gate 154, the N-type impurities in the channel region are rapidly depleted. After complete depletion, the channel closes, and the device is in the off state. When Vgs > 0, N-type impurities accumulate in the channel region, the channel conducts, and current flows from the source through the channel region and drift region to the drain. Within the channel region, the width of the N-type channel determines the magnitude of the JFET device's cutoff voltage. By adjusting the spacing width of the deep trench structures 150, N-type channels with different width distributions can be obtained, thereby changing the cutoff voltage of the high-voltage JFET.

[0054] As shown in Figures 2a and 2b, in the drift region, the polysilicon gate is distributed in a ring along the high-voltage N-well, forming a drift region field plate 137, which helps the drift region to deplete quickly and improves the device's breakdown voltage characteristics. In addition, a deep trench isolation structure (DTI) 151 is provided at the outer edge of the channel region and the drift region to isolate the entire JFET device from the outside world. Figure 6 is a cross-sectional view along line D-D' in Figure 1, showing the drift region structure distribution of the JFET in the conduction channel width direction. The deep trench isolation structure 151 divides the high-voltage N-well (HVN) into two parts. The high-voltage N-well located inside the deep trench isolation structure 151 is the device's drift region, bearing the device's high voltage; the high-voltage N-well located outside the deep trench isolation structure 151 is connected to the high-voltage N-well around the source region 132 and is always in a zero-bias state. This structure can effectively shield the JFET device from interference from external leakage current. On the other hand, by utilizing the strong high voltage withstand capability of DTI, it helps to optimize the voltage withstand size of the peripheral junction in the channel width direction, thereby achieving a smaller layout area.

[0055] The junction field-effect transistor (JFET) of this application has a simple fabrication method and is compatible with conventional processes. In one embodiment of this application, the JFET is obtained by performing high-voltage N-well implantation push-in, active region exposure, shallow trench isolation (STI) etching and filling, MOS gate oxide poly deposition, deep trench isolation etching and polysilicon filling, followed by N+ implantation of the active region source / drain and subsequent conventional process steps.

[0056] Based on the foregoing embodiments, the junction field-effect transistor fabrication process of this application is simple, the resulting JFET device has stable cutoff voltage characteristics, and the JFET device is provided with a deep trench isolation (DTI) region around it, which helps to shield the JFET device from the influence of external circuit noise and leakage current.

[0057] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A junction field effect transistor, comprising: a substrate; a shallow trench isolation structure; a well region, at least partially located below the shallow trench isolation structure and at least partially located above the substrate, a portion of the well region serving as a channel region of the junction field effect transistor and a portion of the well region serving as a drift region of the junction field effect transistor; a plurality of deep trench structures, each of the deep trench structures being located at a distance from each other in a direction of a width of a conductive channel, a depth of each of the deep trench structures being greater than a depth of the well region, thereby separating the well region into a plurality of regions; each of the deep trench structures comprising an insulating layer located on a wall of the deep trench structure and an isolation region gate located in the deep trench structure and surrounded by the insulating layer; the shallow trench isolation structure surrounding each of the deep trench structures in a cross section of the shallow trench isolation structure; a source region directly connected to the well region; a drain region directly connected to the well region, the shallow trench isolation structure being at least partially located between the source region and the drain region, each of the deep trench structures being located between the source region and the drain region; a channel gate located on the shallow trench isolation structure between the source region and the drain region and located above a surface of the conductive channel.

2. The junction field-effect transistor of claim 1, wherein, each of the deep trench structures extending in a length direction of the conductive channel.

3. The junction field-effect transistor of claim 1 or 2, wherein a material of the isolation region gate and the channel gate being polysilicon.

4. The junction field-effect transistor according to any one of claims 1 to 3, wherein each of the isolation region gates being grounded.

5. The junction field-effect transistor according to any one of claims 1 to 4, wherein the junction field effect transistor comprising, in a plan view, a racetrack region, a football field region located in the racetrack region, and a rectangular region located on each side of the racetrack region, a direction of a line between the two sides of the racetrack region being the length direction of the conductive channel, a direction of a line between two ends of the racetrack region being the width direction of the conductive channel, the football field region being a voltage withstanding region of the drift region, the channel region being located on each side of the drift region, and the rectangular region at least partially overlapping the drift region; the drain region being located in the football field region and extending in the width direction of the conductive channel, the source region having one of the source regions located in each of the two rectangular regions, and each of the deep trench structures being located between the source region and the drain region, each of the deep trench structures being at least partially located in one of the two rectangular regions; the junction field effect transistor further comprising, on each end of the racetrack region, a deep trench isolation structure having an arc shape in a plan view; each of the deep trench isolation structures having the outermost deep trench structure of the rectangular region connected to each end of the deep trench isolation structure, and an insulating material in each of the deep trench isolation structures being integrated with the insulating layer in the deep trench structure connected to the deep trench isolation structure, thereby forming a device peripheral isolation region.

6. The junction field-effect transistor of claim 5, wherein, a portion of the shallow trench isolation structure located on the drift region serving as a field oxide layer.

7. The junction field effect transistor of claim 6, further comprising a drift region field plate annularly distributed along the racetrack region, the drift region field plate being at least partially located on the field oxide layer, a material of the drift region field plate being the same as the channel gate and being integrated with the channel gate.

8. The junction field-effect transistor according to any one of claims 1 to 7, wherein a doping type of the source region, the drain region, and the well region being the same.

9. The junction field-effect transistor of claim 8, wherein, the source region, the drain region, and the well region being N-type regions, and the substrate being a P-type region.

10. The junction field-effect transistor according to any one of claims 1 to 9, wherein, The material of the isolation region gate is N-type doped polysilicon.

11. The junction field-effect transistor according to any one of claims 1 to 10, wherein The bottom of the isolation region gate of each deep trench structure is connected with the substrate.

12. The junction field-effect transistor of claims 1-11, comprising: A plurality of sub-transistors, each of which has a cutoff voltage related to the corresponding width thereof on the conductive channel.

13. The junction field-effect transistor of claim 12, wherein, The plurality of sub-transistors have different cutoff voltages.

14. The junction field-effect transistor of any one of claims 5-7, wherein, The portion of the well region outside the two deep trench isolation structures is integrated with the portion of the well region around the source region.

15. The junction field-effect transistor of claim 7, wherein, The drift region field plate and the field oxide layer jointly form a field plate structure.

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