Bump electroplating method

Abstract

The present application discloses a bump electroplating method, comprising: placing a wafer in an electroplating apparatus, the wafer having a plurality of openings; and providing a pulse control signal to the electroplating apparatus, so as to control the electroplating apparatus to perform electroplating in the openings to form bumps, and within one pulse period, a peak duration t1 is greater than a trough duration t2, and both the peak duration t1 and the trough duration t2 are greater than 1 second. Providing a pulse control signal to the electroplating apparatus allows electroplating solution in smaller-sized openings time for replenishment and recovery within the trough duration t2 during the electroplating process, and improves bump coplanarity without reducing the electroplating rate.

Description

bump plating method Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a bump plating method. Background Technology

[0002] Copper pillar bump technology is a next-generation chip interconnect technology commonly used in integrated circuit packaging processes to connect chips (dies) to substrates. Benefiting from the properties of copper, copper pillar bumps offer superior conductivity, thermal performance, and reliability. The manufacturing process of copper pillar bumps requires a close integration of photolithography and electroplating processes. In general, thick-film photolithography is first used to obtain a mask for the copper pillar bump pattern, forming the opening to be filled. Then, electroplating is used to fill the opening with metallic copper, resulting in a copper pillar bump of a certain height.

[0003] Figure 1 shows a top view of an exemplary wafer. Multiple chips 1000 are formed on wafer 100, which are then connected to a substrate or other packaging structure in subsequent packaging processes. With the development of semiconductor packaging technology, copper pillar bumping technology faces new challenges. Due to the integration of different types of chips and the different functions of different I / O signal pins within the same chip, copper pillar bumps of different sizes are required within each chip 1000. Correspondingly, in the manufacturing process of copper pillar bumps, forming copper pillar bumps of different sizes requires filling openings of different sizes with metallic copper, which places increasingly higher demands on electroplating equipment and processes. Because the electroplating rates differ in openings of different sizes, this results in height differences in the copper pillar bumps formed in openings of different sizes. Furthermore, as the electroplating rate increases and the current density increases, this height difference becomes more significant, causing the coplanarity index of the copper pillar bumps to fail to meet process requirements, affecting subsequent soldering processes. To improve the coplanarity of copper pillar bumps, it is usually necessary to reduce the current density of electroplating and slow down the electroplating rate, which leads to a decrease in production efficiency.

[0004] Therefore, how to provide a bump plating method that improves the coplanarity of copper pillar bumps without affecting the plating rate has become a technical problem that needs to be solved.

[0005] Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a bump electroplating method that improves the coplanarity of bumps without affecting the electroplating rate.

[0007] To achieve the above and other related objectives, one aspect of this application proposes a bump plating method, comprising: placing a wafer in an electroplating apparatus, the wafer having a plurality of openings; providing a pulse control signal to the electroplating apparatus to control the electroplating apparatus to electroplat in the openings to form bumps, wherein within one pulse cycle, the peak duration t1 is greater than the trough duration t2, and both the peak duration t1 and the trough duration t2 are greater than 1 second.

[0008] In some embodiments, the pulse control signal is a pulse current density signal, and the peak value of the pulse current density signal is 10 to 50 ASD.

[0009] In some embodiments, the peak value of the pulse current density signal is 20–50 ASD.

[0010] In some embodiments, the peak value of the pulse current density signal is 20–40 ASD.

[0011] In some embodiments, the trough value of the pulse current density signal is 0 to 5 ASD.

[0012] In some embodiments, the duration t1 of the wave crest is in the range of 1 second < t1 ≤ 4 seconds, and the duration t2 of the wave trough is in the range of 1 second < t2 ≤ 2 seconds.

[0013] In some embodiments, the peak duration t1 is 3 ± 3 * 20% seconds, and the trough duration t2 is 1.5 ± 1.5 * 20% seconds.

[0014] In some embodiments, the peak duration t1 is 4±4*20% seconds, and the trough duration t2 is 2±2*20% seconds.

[0015] In some embodiments, the pulse current density signal has multiple peak values, which gradually increase from one peak to the next.

[0016] In some embodiments, the bump includes a copper pillar bump.

[0017] As described above, this application provides a bump plating method. By providing a pulse control signal to the plating apparatus, the plating solution in the smaller opening has time to be renewed and restored during the trough duration t2 of the plating process. This compensates for the difference in mass transfer efficiency between the smaller and larger openings, thereby reducing the height difference between different bumps on the same chip. This improves the coplanarity (COP) of the bumps without reducing the plating rate. In other words, the bump plating method of this application can also increase the plating rate without worsening the coplanarity of the bumps.

[0018] Overview of the attached figures

[0019] The features and performance of this application are further described by the following embodiments and accompanying drawings.

[0020] Figure 1 shows a top view of an exemplary wafer;

[0021] Figures 2a to 2f show exemplary flowcharts for manufacturing copper pillar bumps;

[0022] Figure 3 shows a flowchart of the bump electroplating method of this application;

[0023] Figure 4 shows a schematic diagram of an exemplary electroplating apparatus;

[0024] Figure 5 shows the waveform of the pulse control signal in Embodiment 1 of this application;

[0025] Figure 6 shows the waveform of the pulse control signal according to Embodiment 2 of this application; and

[0026] Figure 7 shows the waveform of the pulse control signal in another embodiment of this application.

[0027] Preferred embodiments of this application

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or adjusted based on different viewpoints and applications without departing from the spirit of this application.

[0029] It should be noted that the accompanying drawings are only schematic representations of the basic concept of this application. Although the drawings only show components related to this application and are not drawn according to the actual number, shape and size of the components, the shape, quantity and proportion of each component can be arbitrarily adjusted in actual implementation, and the layout of the components may also be more complex.

[0030] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0031] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0032] In the description of this application, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two components. They can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0033] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another.

[0034] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., which may be used to indicate the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0035] The process of manufacturing copper pillar bumps is described below with reference to Figures 2a-2f, which are exemplary flowcharts for manufacturing copper pillar bumps. First, in step one, as shown in Figure 2a, a wafer 100 is provided, having multiple metal pads 101, such as aluminum pads. Furthermore, the copper pillar bump packaging structure can cause significant structural stress on the wafer 100. Therefore, before manufacturing the copper pillar bumps, a PI (Polyimide) film is typically grown on the surface of the wafer 100 to reduce the stress on the wafer 100. In step two, as shown in Figure 2b, an UBM (Under bump metallurgy) is deposited on the wafer 100 using sputtering or other physical vapor deposition methods. The UBM includes a barrier layer and a seed layer. The barrier layer is located below the seed layer and is typically Ti or TiW. The seed layer covers the barrier layer and is typically copper or other metal. The barrier layer serves to prevent the metal pads 101 and the seed layer from diffusing into each other, while simultaneously forming a strong bond with both the metal pads 101 and the seed layer. Step three, as shown in Figure 2c, involves using photolithography to create the pattern to be electroplated, forming the opening 103. Typically, a certain thickness of photoresist 102 is spin-coated onto the wafer 100, and after pre-baking, exposure, and development, the pattern to be electroplated is created. Step four, as shown in Figure 2d, involves electroplating copper into the opening 103 to form copper pillar bumps 104. Step five, as shown in Figure 2e, involves depositing solder 105 on top of the copper pillar bumps 104. Finally, step six, as shown in Figure 2f, involves subsequent processes such as resist removal, UBM etching, and solder reflow to form the complete copper pillar bump package structure. It should be understood that the above process is merely illustrative; copper pillar bumps include various types, and for example, some types of copper pillar bumps do not require solder deposition.

[0036] Referring to Figures 2c and 2d, this example shows two openings 103 of different sizes formed on wafer 100, denoted as opening 103a and opening 103b, respectively. Because the size of opening 103b is larger than that of opening 103a, the deposition rate of the copper pillar bumps 104b within opening 103b is greater than that within opening 103a during electroplating. This results in the height of the copper pillar bumps 104b being greater than the height of the copper pillar bumps 104a, thus creating a height difference between the different copper pillar bumps 104.

[0037] The Coplanarity (COP) value is typically used to represent the height difference between different copper pillar bumps 104 on the same die. The COP value is the difference between the maximum and minimum heights of the copper pillar bumps 104 on the same die. To improve the interconnect reliability and product yield, the COP value should be controlled within a reasonable range, ideally as small as possible; that is, the height difference between different copper pillar bumps 104 on the same die should be minimized. Generally, the COP value is positively correlated with the current density during the electroplating process; that is, the higher the current density, the higher the COP value. Therefore, to meet the coplanarity requirement of the copper pillar bumps 104, it is usually necessary to reduce the current density, which leads to a decrease in the electroplating rate and significantly affects production efficiency.

[0038] To address the aforementioned problems, this application proposes a bump plating method. Referring to Figures 3 and 4, Figure 3 shows a flowchart of the bump plating method of this application, and Figure 4 shows a schematic diagram of an exemplary plating apparatus. The bump plating method includes: placing a wafer 100 in an plating apparatus 200, the wafer 100 having a plurality of openings 103 (see openings 103 in Figure 2c); providing a pulse control signal to the plating apparatus 200 to control the plating apparatus 200 to plating in the openings 103 to form bumps (see copper pillar bumps 104 in Figure 2d), wherein within one pulse cycle, the peak duration t1 is greater than the trough duration t2, and both the peak duration t1 and the trough duration t2 are greater than 1 second (s). As shown in Figure 4, the electroplating apparatus 200 includes an electroplating tank 201 and an electroplating fixture 204. The electroplating tank 201 contains an electroplating solution 202 and an anode 203. The electroplating fixture 204 is connected to the negative terminal of a power supply, and the anode 203 is connected to the positive terminal of the power supply. The wafer 100 is held by the electroplating fixture 204 and placed in the electroplating tank 201 for electroplating. It should be understood that the anode 203 can be implemented in various ways, such as a single anode, a dual anode, or a multi-anode configuration.

[0039] Referring to Figures 5 and 6 below, Figure 5 shows the waveform of the pulse control signal in Embodiment 1 of this application, and Figure 6 shows the waveform of the pulse control signal in Embodiment 2 of this application. Specifically, in Embodiments 1 and 2, the pulse control signal is a pulse current density signal with a square wave waveform and a duty cycle of 2 / 3. The plated bump is a copper pillar bump 104 (see the copper pillar bump 104 in Figure 2d). In Embodiment 1, the peak value is 30 ASD, the trough value is 0, and the equivalent current density is 20 ASD (as shown by the dashed line in Figure 5, which is equivalent to a constant current density of 20 ASD). In Embodiment 2, the peak value is 20 ASD, the trough value is 0, and the equivalent current density is 13 ASD (as shown by the dashed line in Figure 6, which is equivalent to a constant current density of 13 ASD).

[0040] Optionally, in other embodiments, the peak value of the current density is between 10 and 50 ASD. Preferably, considering that the peak value affects the plating rate, in some embodiments, the peak value of the current density is between 20 and 50 ASD. More preferably, considering that the plating solution can only withstand a limited current density, in some embodiments, the peak value of the current density is between 20 and 40 ASD. Optionally, in some embodiments, the pulse control signal can also be a pulse current signal, that is, the vertical axis of the waveform of the pulse control signal represents the current magnitude.

[0041] Referring to Figure 2d, during the electroplating process, the mass transfer efficiency of the plating solution varies in the openings 103. The smaller opening 103a has a lower mass transfer efficiency, while the larger opening 103b has a higher efficiency. This results in different plating rates for the copper pillar bumps 104 in openings 103 of different sizes, leading to height differences between different copper pillar bumps 104 on the same chip. In some embodiments of this application, by providing a pulse current density signal with a trough value of 0 to the electroplating apparatus, the current density is 0 during the trough duration t2 of the electroplating process, temporarily interrupting the plating. This allows the plating solution in the smaller opening 103a time to be refreshed and restored, compensating for the difference in mass transfer efficiency between the smaller and larger openings 103a and 103b, thereby reducing the height differences between different copper pillar bumps 104 on the same chip and improving the coplanarity of the copper pillar bumps 104. Furthermore, the equivalent current density can be increased by increasing the peak value or duty cycle of the pulse current density signal, thereby maintaining the plating rate. Therefore, the coplanarity of the copper pillar bumps 104 can be improved under the condition of the same equivalent current density (i.e., the same electroplating rate).

[0042] Optionally, in some embodiments, the mass transfer efficiency of the electroplating solution is high (e.g., high electroplating solution concentration, high electroplating solution temperature, etc.), and the current density is reduced only intermittently, which is sufficient to allow the electroplating solution in the small opening 103a to have time to be renewed and recovered. Therefore, the trough value of the pulse current density signal may not be zero, but a small current density (relative to the peak value) close to 0. For example, the trough value of the pulse current density signal is 0 to 5 ASD.

[0043] Referring to Figures 5 and 6, within one pulse cycle, the peak duration t1 in Figure 5 is 3 seconds and the trough duration t2 is 1.5 seconds; the peak duration t1 in Figure 6 is 4 seconds and the trough duration t2 is 2 seconds. Under the experimental conditions shown in Table 1, multiple sets of experiments were conducted using the ECP ap equipment from ACM Research, and the experimental results are shown in Table 2.

[0044] Table 1

[0045] Table 2

[0046] Referring to Table 2, control group 1 used a constant current density of 20 ASD for electroplating, while control group 2 and Example 1 both used a pulsed current density with a peak value of 30 ASD, a trough value of 0, and an equivalent current density of 20 ASD for electroplating. Within one pulse cycle, the peak duration t1 of the pulsed current density in control group 2 was 0.5 seconds, and the trough duration t2 was 0.25 seconds; in Example 1, the peak duration t1 was 3 seconds, and the trough duration t2 was 1.5 seconds. Control group 3 used a constant current density of 13 ASD for electroplating, while Example 2 used a pulsed current density with a peak value of 20 ASD, a trough value of 0, and an equivalent current density of 13 ASD for electroplating. Within one pulse cycle, the peak duration t1 of the pulsed current density in Example 2 was 4 seconds, and the trough duration t2 was 2 seconds. In addition, COP refers to the difference between the maximum and minimum heights of copper pillar bumps on the same chip. It reflects the coplanarity of copper pillar bumps on the same chip. The smaller the COP value, the better the coplanarity of copper pillar bumps on the same chip.

[0047] As shown in Table 2, under the same constant current density and equivalent current density, the COP value of the copper pillar bump in Example 1 is 6.04 μm, which is lower than the COP values ​​in Control Group 1 and Control Group 2. That is, using the electroplating method in Example 1, compared to Control Group 1 and Control Group 2, a copper pillar bump with better coplanarity can be obtained with the same equivalent current density (i.e., constant electroplating rate). Similarly, in Example 2, the COP value of the copper pillar bump is 1.64 μm, while the COP value of the copper pillar bump in Control Group 3 is 3.49 μm. Compared to Control Group 3, using Example 2, a copper pillar bump with better coplanarity can be obtained with the same electroplating rate.

[0048] Furthermore, among control groups 1, 2, and 1 example, control group 1 had the highest COP value at 7.28 μm, while control group 2's COP value was between that of control group 1 and 1 example, at 7.02 μm. It can be seen that control group 1, which uses conventional constant current density electroplating, exhibits a significant problem with poor coplanarity. Control group 2, which uses pulsed current density electroplating, shows some improvement in coplanarity, but still falls short of 1 example. This indicates that pulsed current density alone cannot effectively improve the coplanarity of copper pillar bumps on the same chip. The peak duration t1 and trough duration t2 of the pulsed current density signal must also meet certain conditions. On one hand, the trough duration t2 needs to be greater than 1 second to allow sufficient time for the plating solution in the small opening to be renewed and recovered. On the other hand, the peak duration t1 needs to be greater than 1 second and greater than the trough duration t2 to maintain the equivalent current density and meet the plating rate requirements. Only in this way can the coplanarity of the copper pillar bumps be improved without reducing the plating rate. Furthermore, since the coplanarity of the copper pillar bumps is strongly correlated with the electroplating rate, the coplanarity of the copper pillar bumps decreases as the electroplating rate increases. Therefore, the electroplating rate can be increased by using the bump electroplating method of this application without worsening the coplanarity of the copper pillar bumps.

[0049] It should be understood that the above embodiments one and two are merely examples of this application. In some embodiments, the peak duration t1 ranges from 1 second < t1 ≤ 4 seconds, and the trough duration t2 ranges from 1 second < t2 ≤ 2 seconds. Those skilled in the art can select the values ​​of t1 and t2 according to actual needs.

[0050] Furthermore, in some embodiments, the peak duration t1 can be approximately 3 seconds, and the trough duration t2 can be approximately 1.5 seconds; in other embodiments, the peak duration t1 can be approximately 4 seconds, and the trough duration t2 can be approximately 2 seconds. It should be understood that the modifiers "approximately," "approximately," or "generally" used to modify numbers in this application indicate that the numbers are allowed to vary by ±20%. In other words, in some embodiments, the peak duration t1 is 3 ± 3 * 20% seconds, such as 2.7 seconds, 2.9 seconds, 3.3 seconds, etc., and the trough duration t2 is 1.5 ± 1.5 * 20% seconds, such as 1.3 seconds, 1.6 seconds, 1.7 seconds, etc.; in other embodiments, the peak duration t1 is 4 ± 4 * 20% seconds, such as 3.6 seconds, 3.7 seconds, 4.4 seconds, etc., and the trough duration t2 is 2 ± 2 * 20% seconds, such as 1.8 seconds, 2.1 seconds, 2.2 seconds, etc. Accordingly, in some embodiments, the numerical parameters used in this application are approximate values, which may be changed according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should take into account a specified number of significant digits and adopt a general method of digit preservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as accurately as feasible.

[0051] Optionally, as shown in Figure 7, which illustrates the waveform of the pulse control signal in other embodiments of this application. In some embodiments, the pulse current density signal has multiple peak values, which gradually increase from beginning to end. In these embodiments, during the electroplating process, electroplating is initially performed with a smaller current density. This allows the plating solution more time to diffuse in the smaller opening and also allows the seed layer to be repaired, reducing its resistance. This further improves the coplanarity of the copper pillar bumps. Furthermore, the gradual increase in current density maintains the equivalent current density, meeting the requirements for the electroplating rate.

[0052] It should be understood that in other possible embodiments, the plated bumps may also be other metal bumps, such as gold bumps.

[0053] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or adjust the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or adjustments made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A bump plating method characterized by, The method comprises: placing a wafer in an electroplating device, the wafer having a plurality of openings; providing a pulse control signal to the electroplating device to control the electroplating device to electroplate in the openings to form bumps, wherein a peak duration t1 is greater than a valley duration t2 in a pulse cycle, and both the peak duration t1 and the valley duration t2 are greater than 1 second.

2. The method of claim 1, wherein: the pulse control signal is a pulse current density signal, and a peak value of the pulse current density signal is 10-50 ASD.

3. The method of claim 2, wherein: the peak value of the pulse current density signal is 20-50 ASD.

4. The method of claim 2, wherein: the peak value of the pulse current density signal is 20-40 ASD.

5. The method of any one of claims 2-4, wherein: a valley value of the pulse current density signal is 0-5 ASD.

6. The method of claim 1, wherein: the peak duration t1 is in a range of 1 second < t1 < 4 seconds, and the valley duration t2 is in a range of 1 second < t2 < 2 seconds.

7. The method of claim 1, wherein: the peak duration t1 is 3 ± 3*20% seconds, and the valley duration t2 is 1.5 ± 1.5*20% seconds.

8. The method of claim 1, wherein: the peak duration t1 is 4 ± 4*20% seconds, and the valley duration t2 is 2 ± 2*20% seconds.

9. The method of claim 2, wherein: the pulse current density signal has a plurality of peak values, and the plurality of peak values gradually increase from front to back.

10. The method of claim 1, wherein: the bumps comprise copper pillar bumps.

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