Current-mode DC-DC conversion circuit

Abstract

Embodiments of the present disclosure provide a current-mode DC-DC conversion circuit, comprising: a ramp voltage generation module, for generating a ripple voltage on the basis of a voltage difference between a switch node and an output voltage node, acquiring an on current of a lower power transistor when the lower power transistor is turned on, determining an alternating-current component of a ramp voltage on the basis of the ripple voltage, and determining a direct-current component of the ramp voltage on the basis of the on current; an error amplifier module, outputting an error voltage on the basis of an output voltage and a reference voltage; a pulse width modulation comparison module, configured to output a pulse width modulation signal to a control module on the basis of the ramp voltage and the error voltage; and a control module, outputting a control signal on the basis of the pulse width modulation signal and a clock signal. In the embodiments of the present disclosure, the ramp voltage is obtained by adding the direct-current component of the ramp voltage and the alternating-current component of the ramp voltage, and a test process of the ramp voltage does not limit the minimum on time of an upper power transistor.

Description

A current-mode DC-DC converter circuit

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024109719540, filed on July 19, 2024, entitled “A Current-Mode DC-DC Conversion Circuit”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit technology, and more specifically, to a current-mode DC-DC conversion circuit. Background Technology

[0004] The current-mode DC-DC converter circuit includes a voltage outer loop circuit and a current inner loop circuit. The voltage outer loop circuit samples the output voltage, compares the sampled voltage with the reference voltage, and outputs it through an error amplifier. The current inner loop circuit samples the current of the upper power transistor and forms a current ramp signal. It compares the current ramp signal with the output signal of the error amplifier. When the current ramp signal is greater than the output signal of the error amplifier, the upper power transistor is turned off.

[0005] In related technologies, when the upper power transistor is turned on, the current flowing through the upper power transistor in the current-mode DC-DC converter circuit has relatively large noise. Specifically, since no current flows through the upper power transistor when it is turned off, the voltage of the switching node will rise rapidly to a large value when the upper power transistor is first turned on, and the voltage of the switching node will also have a process of amplitude reduction and oscillation. Therefore, the current-mode DC-DC converter circuit needs a certain amount of time to establish the DC operating point, and in order to ensure the accuracy of sampling, it is necessary to avoid the noise during the upper power transistor's turn-on phase. This time is also known as the leading edge blanking (LEB) time. The existence of the leading edge blanking time will affect the sampling time of the upper power transistor current by the inner current loop circuit, and thus affect the minimum conduction time of the upper power transistor. Summary of the Invention

[0006] The embodiments described in this disclosure provide a current-mode DC-DC conversion circuit.

[0007] According to the present disclosure, a current-mode DC-DC converter circuit is provided, including: a ramp voltage generation module, an error amplifier module, a pulse width modulation comparison module, and a control module;

[0008] The ramp voltage generation module is configured to generate a ripple voltage based on the voltage difference between the switching node and the output voltage node, and to collect the conduction current of the lower power transistor when it is turned on. The module is also configured to determine the AC component of the ramp voltage based on the ripple voltage and the DC component of the ramp voltage based on the conduction current. The switching node is electrically connected to the first end of the output inductor, and the output voltage node is electrically connected to the second end of the output inductor.

[0009] The error amplifier module is configured to output an error voltage based on the output voltage of the output voltage node and the reference voltage;

[0010] The pulse width modulation comparison module is configured to output a pulse width modulation signal to the control module based on the ramp voltage and the error voltage.

[0011] The control module is configured to output a control signal based on the pulse width modulation signal and the clock signal.

[0012] In some embodiments of this disclosure, the ramp voltage generation module includes a first voltage determination unit, a second voltage determination unit, and a ramp voltage determination unit;

[0013] The first voltage determination unit is configured to acquire the switching voltage of the switching node and the output voltage of the output voltage node, and generate a ripple voltage based on the voltage difference between the output voltage and the switching voltage, wherein the ripple voltage is the first voltage.

[0014] The second voltage determination unit is configured to acquire the on-current of the lower power transistor when the lower power transistor is turned on, and determine the second voltage based on the on-current;

[0015] The ramp voltage determination unit is configured to determine the AC component of the ramp voltage based on the first voltage and the DC component of the ramp voltage based on the second voltage, and to superimpose the AC component and the DC component to obtain the ramp voltage.

[0016] In some embodiments of this disclosure, the first voltage determination unit includes a first resistor and a first capacitor. A first end of the first resistor is electrically connected to the switching node, a second end of the first resistor is electrically connected to a first end of the first capacitor, and a second end of the first capacitor is electrically connected to the output voltage node.

[0017] In some embodiments of this disclosure, the second voltage determination unit includes a current amplifier, a first switch, a second resistor, and a second capacitor. The first input terminal of the current amplifier is electrically connected to the first terminal of the lower power transistor, the second input terminal of the current amplifier is electrically connected to a ground node, the power supply terminal of the current amplifier is electrically connected to a power supply voltage node, the output terminal of the current amplifier is electrically connected to the first terminal of the first switch and the first terminal of the second resistor, the second terminal of the second resistor is electrically connected to a fixed voltage node, the second terminal of the first switch is electrically connected to the first terminal of the second capacitor, the control terminal of the first switch is electrically connected to the control terminal of the lower power transistor, and the second terminal of the second capacitor is electrically connected to a ground node.

[0018] In some embodiments of this disclosure, the second resistor is an adjustable resistor.

[0019] In some embodiments of this disclosure, the ramp voltage determination unit includes a third resistor and a third capacitor. The first terminal of the third resistor receives the second voltage output by the second voltage determination unit, the first terminal of the third capacitor receives the first voltage output by the first voltage determination unit, and the second terminal of the third resistor is electrically connected to the second terminal of the third capacitor.

[0020] In some embodiments of this disclosure, the ramp voltage determination unit further includes a buffer, a first end of which receives a first voltage output by the first voltage determination unit, and a second end of which is electrically connected to the first end of the third capacitor.

[0021] In some embodiments of this disclosure, a slope compensation voltage generation module is also included;

[0022] The ramp compensation voltage generation module is configured to output a ramp compensation voltage to the pulse width modulation comparison module based on the sampled voltage when the upper power transistor is turned on.

[0023] The pulse width modulation comparison module is further configured to sum the ramp compensation voltage and the ramp voltage and compare the sum with the error voltage to obtain the pulse width modulation signal.

[0024] In some embodiments of this disclosure, the slope compensation voltage generation module includes a fourth resistor, a fourth capacitor, and a second switch. The first end of the fourth resistor is electrically connected to the output voltage node, the second end of the fourth resistor is electrically connected to the first end of the fourth capacitor and the first end of the second switch, the second end of the fourth capacitor and the second end of the second switch are electrically connected to the ground node, and the control terminal of the second switch is electrically connected to the control terminal of the upper power transistor.

[0025] In some embodiments of this disclosure, the error amplifier module includes a transconductance amplifier, a fifth resistor, a fifth capacitor, and a sixth capacitor. The positive input terminal of the transconductance amplifier is electrically connected to a reference voltage node, the inverting input terminal of the transconductance amplifier is electrically connected to an output voltage node, the power supply terminal of the transconductance amplifier is electrically connected to a power supply voltage node, the output terminal of the transconductance amplifier is electrically connected to a first terminal of the fifth resistor and a first terminal of the sixth capacitor, the second terminal of the fifth resistor is electrically connected to a first terminal of the fifth capacitor, and the second terminals of the fifth capacitor and the sixth capacitor are electrically connected to a ground node.

[0026] In some embodiments of this disclosure, the error amplifier module is configured to integrate the difference between the output voltage of the output voltage node and the reference voltage of the reference voltage node and then output the error voltage.

[0027] In the current-mode DC-DC converter circuit provided in this embodiment, the ramp voltage generation module generates a ripple voltage based on the voltage difference between the switching node and the output voltage node, and acquires the on-state current of the lower power transistor when it is turned on. It also determines the AC component of the ramp voltage based on the ripple voltage and the DC component based on the on-state current. The error amplifier module outputs an error voltage based on the output voltage and the reference voltage. The pulse width modulation (PWM) comparison module outputs a PWM signal to the control module based on the ramp voltage and the error voltage. The control module outputs a control signal based on the PWM signal and the clock signal. In this embodiment, the ramp voltage is obtained by summing the DC component and the AC component of the ramp voltage. The DC component of the ramp voltage is determined based on the on-state current when the lower power transistor is turned on, and the AC component is determined based on the ripple voltage generated by the voltage difference between the switching node and the output voltage node. In other words, the AC component of the ramp voltage is related to the ripple voltage. The DC component of the ramp voltage is not detected during the conduction of the upper power transistor. Therefore, the detection process of the DC component in the ramp voltage does not limit the minimum conduction time of the upper power transistor. Since the ripple voltage is determined based on the voltage difference between the switching node and the output voltage node, the output voltage of the output voltage node is very stable, and the noise of the switching voltage of the switching node does not propagate to the connection node of the first resistor and the first capacitor. Therefore, the noise of the ripple voltage determined based on the switching node and the output voltage node can be ignored. That is, the ripple voltage determined based on the switching node and the output voltage node does not require LEB time. Therefore, the AC component of the ramp voltage does not limit the minimum conduction time of the upper power transistor. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0029] Figure 1 is a schematic diagram of a current-mode DC-DC conversion circuit provided in an embodiment of this disclosure;

[0030] Figure 2 is a schematic diagram of another current-mode DC-DC conversion circuit provided in an embodiment of this disclosure;

[0031] Figure 3 is a schematic diagram of another current-mode DC-DC conversion circuit provided in an embodiment of this disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0034] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0035] Unless otherwise expressly indicated by the context, the singular form of words used in this disclosure includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited in this disclosure. Where the term “example” is used in this disclosure, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0036] Based on the problems existing in related technologies, this disclosure provides a current-mode DC-DC conversion circuit. Figure 1 is a schematic diagram of the structure of a current-mode DC-DC conversion circuit provided in this disclosure. As shown in Figure 1, it includes: a ramp voltage generation module 10, an error amplifier module 20, a pulse width modulation comparison module 30, and a control module 40. The ramp voltage generation module 10 is configured to generate a ripple voltage based on the voltage difference between the switching node SW and the output voltage node OUT, and to acquire the on-state current of the lower power transistor ML when it is turned on, and to determine the ramp voltage based on the ripple voltage. The AC component of the slope voltage is determined based on the conduction current. The switching node SW is electrically connected to the first terminal of the output inductor Lout, and the output voltage node OUT is electrically connected to the second terminal of the output inductor Lout. The error amplifier module 20 is configured to output an error voltage Vea based on the output voltage of the output voltage node OUT and the reference voltage. The pulse width modulation comparator module 30 is configured to output a pulse width modulation signal to the control module based on the slope voltage Vramp and the error voltage Vea. The control module 40 is configured to output a control signal to the power module based on the pulse width modulation signal and the clock signal.

[0037] Specifically, the current-mode DC-DC conversion circuit provided in this embodiment includes a ramp voltage generation module 10. On the one hand, when the lower power transistor ML is turned on, the ramp voltage generation module 10 collects the conduction current of the lower power transistor ML and determines the DC component of the ramp voltage based on the conduction current of the lower power transistor ML. On the other hand, it generates a ripple voltage, i.e., the ripple voltage of the output inductor, based on the voltage difference between the switching node SW and the output voltage node OUT, and determines the AC component of the ramp voltage based on the ripple voltage of the output inductor. Then, the ramp voltage Vramp is obtained by summing the DC component and the AC component of the ramp voltage.

[0038] In this embodiment, the ramp voltage Vramp is obtained by summing the DC component and the AC component of the ramp voltage. The DC component of the ramp voltage is determined based on the on-current of the lower power transistor ML when it is turned on, and the AC component is determined based on the ripple voltage of the output inductor. The DC component of the ramp voltage is not detected during the conduction of the upper power transistor; therefore, the detection process of the DC component of the ramp voltage does not limit the minimum on-time of the upper power transistor. Since the ripple voltage is determined based on the voltage difference between the switching node and the output voltage node, the output voltage of the output voltage node is very stable, and the noise of the switching voltage of the switching node does not propagate to the connection node of the first resistor and the first capacitor. Therefore, the noise of the ripple voltage determined based on the switching node and the output voltage node can be ignored. That is, the ripple voltage determined based on the switching node and the output voltage node does not require LEB time; therefore, the detection process of the AC component of the ramp voltage also does not limit the minimum on-time of the upper power transistor.

[0039] In this embodiment, the error amplifier module 20 obtains the output voltage of the output voltage node OUT, and then determines the error voltage Vea by obtaining the difference between the output voltage of the output voltage node OUT and the reference voltage of the reference voltage node Ref. Then, the pulse width modulation comparison module 30 compares the ramp voltage Vramp output by the ramp voltage generation module 10 and the error voltage Vea output by the error amplifier module 20, and outputs a pulse width modulation signal to the control module 40. Finally, the control module 40 outputs a control signal based on the pulse width modulation signal and the clock signal to control the on and off states of the upper power transistor MH and the lower power transistor ML.

[0040] Specifically, the error amplifier module 20 integrates the difference between the output voltage of the output voltage node OUT and the reference voltage of the reference voltage node Ref, and outputs the error voltage Vea. The pulse width modulation comparison module 30 compares the ramp voltage Vramp and the error voltage Vea. When the ramp voltage Vramp is greater than the error voltage Vea, it outputs a high-level signal. When the ramp voltage Vramp is less than the error voltage Vea, it outputs a low-level signal. The control module 40 determines the on and off states of the upper power transistor MH and the lower power transistor ML based on the received pulse width modulation signal and clock signal.

[0041] In the current-mode DC-DC converter circuit provided in this embodiment, the ramp voltage generation module is configured to generate a ripple voltage based on the voltage difference between the switching node and the output voltage node, and to acquire the on-current of the lower power transistor when it is turned on. It also determines the AC component of the ramp voltage based on the ripple voltage and the DC component of the ramp voltage based on the on-current. The error amplifier module is configured to output an error voltage based on the output voltage and the reference voltage. The pulse width modulation comparator module is configured to output a pulse width modulation signal to the control module based on the ramp voltage and the error voltage. The control module is configured to output a control signal based on the pulse width modulation signal and the clock signal. In this embodiment, the ramp voltage is obtained by summing the DC component and the AC component of the ramp voltage. The DC component of the ramp voltage is determined based on the on-current of the lower power transistor when it is turned on, and the AC component of the ramp voltage is determined based on the ripple voltage generated by the voltage difference between the switching node and the output voltage node. In other words, the AC component of the ramp voltage is related to the ripple voltage. The DC component of the ramp voltage is not detected during the conduction of the upper power transistor. Therefore, the detection process of the DC component in the ramp voltage does not limit the minimum conduction time of the upper power transistor. Since the ripple voltage is determined based on the voltage difference between the switching node and the output voltage node, the output voltage of the output voltage node is very stable, and the noise of the switching voltage of the switching node will not be transmitted to the connection node of the first resistor and the first capacitor. Therefore, the noise of the ripple voltage determined based on the switching node and the output voltage node can be ignored. That is, the ripple voltage determined based on the switching node and the output voltage node does not require LEB time. Therefore, the detection process of the AC component in the ramp voltage does not limit the minimum conduction time of the upper power transistor.

[0042] Based on the above embodiments, Figure 2 is a schematic diagram of another current-mode DC-DC conversion circuit provided in this disclosure. Specifically, as shown in Figure 2, the ramp voltage generation module 10 includes a first voltage determination unit 11, a second voltage determination unit 12, and a ramp voltage determination unit 13. The first voltage determination unit 11 is configured to collect the switching voltage of the switching node SW and the output voltage of the output voltage node OUT, and generate a ripple voltage based on the voltage difference between the output voltage and the switching voltage. The ripple voltage is the first voltage V1. The second voltage determination unit 12 is configured to collect the conduction current of the lower power transistor ML when the lower power transistor ML is turned on, and determine the second voltage V2 based on the conduction current. The ramp voltage determination unit 13 is configured to determine the AC component of the ramp voltage based on the first voltage V1, and determine the DC component of the ramp voltage based on the second voltage V2, and superimpose the AC component and the DC component to obtain the ramp voltage.

[0043] As a specific implementation, referring to Figure 2, the first voltage determination unit 11 includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is electrically connected to the switch node SW, the second end of the first resistor R1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the output voltage node OUT.

[0044] As shown in Figure 2, the first voltage determination unit 11 includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is electrically connected to the switching node SW, and the second end of the first capacitor C1 is electrically connected to the output voltage node OUT. The first voltage determination unit 11 outputs the ripple voltage after filtering the sampling voltage of the sampling node with the output voltage of the output voltage node. The output voltage of the output voltage node is very stable, and the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 are set to be large. Therefore, the noise of the switching voltage of the switching node will not be conducted to the node connected by the first resistor and the first capacitor. That is, the noise of the ripple voltage (i.e., the first voltage) output by the first voltage determination unit can be ignored. Therefore, the ripple voltage determined based on the switching node and the output voltage node does not require LEB time, and the detection process of the AC component in the ramp voltage does not limit the minimum conduction time of the power transistor.

[0045] Furthermore, in this embodiment, by connecting the first resistor R1 and the first capacitor C1 in parallel across the output inductor Lout, when the upper power transistor MH is turned on, the capacitor charges, and the slope of the current flowing through the output inductor satisfies:

[0046] When the lower power transistor ML is turned on, the capacitor discharges through the output inductor, and the slope of the current flowing through the output inductor satisfies:

[0047] The rising slope of the ripple voltage also satisfies:

[0048] The ripple voltage's decreasing slope also satisfies:

[0049] In other words, the ripple voltage (first voltage) collected by the first resistor R1 and the first capacitor C1 can well represent the current information of the output inductor.

[0050] Furthermore, when the ripple voltage of the output inductor is small, the gain of the AC component in the ramp voltage is small, the system bandwidth of the current-mode DC-DC converter is large, and the transient response of the current-mode DC-DC converter is fast. Therefore, by adjusting the resistance value of the first resistor and the capacitance value of the first capacitor, the current-mode DC-DC converter can be guaranteed to have a large bandwidth and a fast transient response.

[0051] As a specific implementation, referring to Figure 2, the second voltage determination unit 12 includes a current amplifier Ai, a first switch K1, a second resistor R2, and a second capacitor C2. The first input terminal of the current amplifier Ai is electrically connected to the first terminal of the lower power transistor ML, the second input terminal of the current amplifier Ai is electrically connected to the ground node, the power supply terminal of the current amplifier Ai is electrically connected to the power supply voltage node VCC, the output terminal of the current amplifier Ai is electrically connected to the first terminal of the first switch K1 and the first terminal of the second resistor R2, the second terminal of the second resistor R2 is electrically connected to the fixed voltage node U0, the second terminal of the first switch K1 is electrically connected to the first terminal of the second capacitor C2, the control terminal of the first switch K1 is electrically connected to the control terminal of the lower power transistor ML, and the second terminal of the second capacitor C2 is electrically connected to the ground node.

[0052] As shown in Figure 2, the current amplifier Ai collects the conduction current of the lower power transistor ML when it is turned on. Then, the conduction current of the lower power transistor ML collected by the current amplifier Ai is multiplied by the fixed gain and then summed with the voltage of the fixed voltage node to obtain the second voltage. Since the fixed gain value is small and the change in the conduction current of the lower power transistor ML is small, the second voltage obtained by collecting the conduction current of the lower power transistor ML can reflect the average value of the conduction current of the lower power transistor ML when it is turned on.

[0053] As one specific implementation method, the second resistor R2 is an adjustable resistor.

[0054] By setting the second resistor R2 as an adjustable resistor, the gain of the average current of the output inductor can be adjusted by changing the resistance value, thereby achieving adjustable output voltage, that is, adjustable DC component of the ramp voltage. Adjusting the DC component of the ramp voltage avoids the difficulties caused by excessively small DC component gain in multi-phase parallel applications.

[0055] As a specific implementation, referring to Figure 2, the ramp voltage determination unit 13 includes a third resistor R3 and a third capacitor C3. The first end of the third resistor R3 receives the second voltage V2 output by the second voltage determination unit 12, and the first end of the third capacitor C3 receives the first voltage V1 output by the first voltage determination unit 11. The second end of the third resistor R3 is electrically connected to the second end of the third capacitor C3.

[0056] After the first voltage V1 is determined by the first voltage determination unit 11, the first voltage V1 is filtered by the third capacitor C3. Taking into account the characteristics of the capacitor in the filter circuit, the DC component of the first voltage V1 is isolated, while the AC component is allowed to pass through, resulting in the AC component of the ramp voltage. After the second voltage V2 is determined by the second voltage determination unit 12, the second voltage V2 is filtered by the third resistor R3. Taking into account the characteristics of the resistor in the filter circuit, the AC component of the second voltage V2 is isolated, while the DC component is allowed to pass through, resulting in the DC component of the ramp voltage. Then, the DC and AC components of the ramp voltage are combined to obtain the ramp voltage Vramp, which is then output to the pulse width modulation comparison module 30.

[0057] Based on the above embodiment, referring to Figure 2, the ramp voltage determination unit 13 further includes a buffer. The first end of the buffer receives the first voltage V1 output by the first voltage determination unit 11, and the second end of the buffer is electrically connected to the first end of the third capacitor C3.

[0058] The ramp voltage determination unit 13 also includes a buffer. The buffer is set between the first voltage V1 output by the first voltage determination unit 11 and the first terminal of the third capacitor C3 to avoid the load effect of the third capacitor C3 and the third resistor R3 on the sampling of the ripple voltage of the output inductor collected by the first capacitor C1 and the first resistor R1.

[0059] Based on the above embodiments, Figure 3 is a schematic diagram of another current-mode DC-DC conversion circuit provided in this disclosure. As shown in Figure 3, the current-mode DC-DC conversion circuit further includes: a slope compensation voltage generation module 50; the slope compensation voltage generation module 50 is configured to output a slope compensation voltage Vslope to the pulse width modulation comparison module 30 according to the sampling voltage when the upper power transistor MH is turned on.

[0060] The slope compensation voltage generation module 50 includes a fourth resistor R4, a fourth capacitor C4, and a second switch K2. The first end of the fourth resistor R4 is electrically connected to the output voltage node OUT. The second end of the fourth resistor R4 is electrically connected to the first end of the fourth capacitor C4 and the first end of the second switch K2. The second end of the fourth capacitor C4 and the second end of the second switch K2 are electrically connected to the ground node. The control end of the second switch K2 is electrically connected to the control end of the upper power transistor MH.

[0061] By setting up a slope compensation voltage generation module 50, when the upper power transistor MH is turned on, the slope compensation voltage generation module 50 outputs a slope compensation voltage Vslope. Then, the pulse width modulation comparison module 30 sums the slope compensation voltage Vslope with the slope voltage Vramp and compares it with the error voltage Vea to avoid subharmonic oscillation of the inductor current.

[0062] Specifically, when the upper power transistor MH is turned on, the second switch K2 is turned off, and the slope compensation voltage generation module 50 generates the slope compensation voltage through the fourth resistor R4 and the fourth capacitor C4.

[0063] Based on the above embodiments, referring to Figure 2 or Figure 3, the error amplifier module 20 includes a transconductance amplifier, a fifth resistor R5, a fifth capacitor C5, and a sixth capacitor C6. The positive input terminal of the transconductance amplifier is electrically connected to the reference voltage node Ref, the inverting input terminal of the transconductance amplifier is electrically connected to the output voltage node OUT, the power supply terminal of the transconductance amplifier is electrically connected to the power supply voltage node VCC, the output terminal of the transconductance amplifier is electrically connected to the first terminal of the fifth resistor R5 and the first terminal of the sixth capacitor C6, the second terminal of the fifth resistor R5 is electrically connected to the first terminal of the fifth capacitor C5, and the second terminals of the fifth capacitor C5 and the sixth capacitor C6 are electrically connected to the ground node.

[0064] By setting up the error amplifier module 20, the error amplifier module 20 receives the output voltage and integrates the error between the output voltage and the reference voltage to obtain the error voltage.

[0065] It should be noted that in the current-mode DC-DC conversion circuit provided in this embodiment, the power transistor includes an upper power transistor and a lower power transistor. The control terminals of the upper power transistor and the lower power transistor are electrically connected to the output terminal of the control module, respectively. The first terminal of the upper power transistor is electrically connected to the power supply voltage node, the second terminal of the upper power transistor is electrically connected to the second terminal of the lower power transistor, and the first terminal of the lower power transistor is electrically connected to the first input terminal of the current amplifier.

[0066] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0067] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. Moreover, the sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0068] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0069] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A current mode DC-DC conversion circuit, comprising: The slope voltage generating module, the error amplifier module, the pulse width modulation comparison module and the control module; The slope voltage generating module is configured to generate a ripple voltage according to a voltage difference between a switching node and an output voltage node, collect a turn-on current of a lower power tube when the lower power tube is turned on, and determine an alternating current component of a slope voltage according to the ripple voltage and a direct current component of the slope voltage according to the turn-on current, the switching node being electrically connected to a first end of an output inductor, and the output voltage node being electrically connected to a second end of the output inductor. The error amplifier module is configured to output an error voltage according to an output voltage of the output voltage node and a reference voltage. The pulse width modulation comparison module is configured to output a pulse width modulation signal to the control module according to the slope voltage and the error voltage. The control module is configured to output a control signal according to the pulse width modulation signal and a clock signal.

2. The current mode DC-DC conversion circuit according to claim 1, wherein, The slope voltage generating module includes a first voltage determining unit, a second voltage determining unit and a slope voltage determining unit. The first voltage determining unit is configured to collect a switching voltage of the switching node and an output voltage of the output voltage node, and generate a ripple voltage according to a voltage difference between the output voltage and the switching voltage, the ripple voltage being a first voltage. The second voltage determining unit is configured to collect a turn-on current of the lower power tube when the lower power tube is turned on, and determine a second voltage according to the turn-on current. The slope voltage determining unit is configured to determine an alternating current component of a slope voltage according to the first voltage, and determine a direct current component of the slope voltage according to the second voltage, and superimpose the alternating current component and the direct current component to obtain the slope voltage.

3. The current mode DC-DC conversion circuit according to claim 2, wherein, The first voltage determining unit includes a first resistor and a first capacitor, a first end of the first resistor being electrically connected to the switching node, a second end of the first resistor being electrically connected to a first end of the first capacitor, and a second end of the first capacitor being electrically connected to the output voltage node.

4. The current mode DC-DC conversion circuit according to claim 2, wherein The second voltage determining unit includes a current amplifier, a first switch, a second resistor and a second capacitor, a first input end of the current amplifier being electrically connected to a first end of the lower power tube, a second input end of the current amplifier being electrically connected to a ground node, a power supply end of the current amplifier being electrically connected to a power supply voltage node, an output end of the current amplifier being electrically connected to a first end of the first switch and a first end of the second resistor respectively, a second end of the second resistor being electrically connected to a fixed voltage node, a second end of the first switch being electrically connected to a first end of the second capacitor, a control end of the first switch being electrically connected to a control end of the lower power tube, and a second end of the second capacitor being electrically connected to the ground node.

5. The current mode DC-DC conversion circuit according to claim 4, wherein The second resistor is an adjustable resistor.

6. The current mode DC-DC conversion circuit according to claim 2, wherein The slope voltage determination unit comprises a third resistor and a third capacitor, a first end of the third resistor receives the second voltage output by the second voltage determination unit, a first end of the third capacitor receives the first voltage output by the first voltage determination unit, and a second end of the third resistor is electrically connected with a second end of the third capacitor.

7. The current mode DC-DC conversion circuit of claim 6, wherein, The slope voltage determination unit further comprises a buffer, a first end of the buffer receives the first voltage output by the first voltage determination unit, and a second end of the buffer is electrically connected with the first end of the third capacitor.

8. The current mode DC-DC conversion circuit according to claim 1, further comprising a slope compensation voltage generation module. The slope compensation voltage generation module is configured to output a slope compensation voltage to the pulse width modulation comparison module according to the sampling voltage when the upper power tube is turned on. The pulse width modulation comparison module is further configured to compare the sum of the slope compensation voltage and the slope voltage with the error voltage to obtain a pulse width modulation signal.

9. The current mode DC-DC conversion circuit of claim 8, wherein, The slope compensation voltage generation module comprises a fourth resistor, a fourth capacitor and a second switch, a first end of the fourth resistor is electrically connected with the output voltage node, a second end of the fourth resistor is respectively electrically connected with a first end of the fourth capacitor and a first end of the second switch, a second end of the fourth capacitor and a second end of the second switch are respectively electrically connected with a ground node, and a control end of the second switch is electrically connected with a control end of the upper power tube.

10. The current mode DC-DC conversion circuit of claim 1, wherein, The error amplifier module comprises a transconductance amplifier, a fifth resistor, a fifth capacitor and a sixth capacitor, a positive input end of the transconductance amplifier is electrically connected with the reference voltage node, a negative input end of the transconductance amplifier is electrically connected with the output voltage node, a power supply end of the transconductance amplifier is electrically connected with the power supply voltage node, an output end of the transconductance amplifier is respectively electrically connected with a first end of the fifth resistor and a first end of the sixth capacitor, a second end of the fifth resistor is electrically connected with the first end of the fifth capacitor, and a second end of the fifth capacitor and a second end of the sixth capacitor are electrically connected with the ground node.

11. The current mode DC-DC conversion circuit of claim 1, wherein, The error amplifier module is configured to output the error voltage by integrating the difference between the output voltage of the output voltage node and the reference voltage of the reference voltage node.

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