Memory expansion system and method, switch, and memory pool

Abstract

Provided in the embodiments of the present disclosure are a memory expansion system and method, a switch, and a memory pool. The system comprises: computing nodes supporting a compute express link protocol, a switch, and a memory pool. The switch comprises a switching chip and a controller for managing the switching chip. Processors in the computing nodes are connected to upstream-facing ports of the switching chip. The memory pool comprises a plurality of expansion memory media, and the plurality of expansion memory media are respectively connected to different downstream-facing ports of the switching chip. The controller is used to configure a correspondence between upstream-facing ports and downstream-facing ports of the switching chip, so as to reflect a memory that can be expanded and used by the processors in the computing nodes.

Description

Memory expansion systems, methods, switches, and memory pools Cross-references to related applications

[0001] This disclosure claims priority to Chinese patent application No. 202410950095.7, filed on July 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of cloud storage technology, and in particular to a memory expansion system, method, switch, and memory pool. Background Technology

[0003] With the continuous surge in data volume, data centers are facing a massive increase in server usage. However, current server technology is encountering a bottleneck in memory architecture: the growth in the number of memory channels cannot keep pace with the growth in the number of CPU cores, leading to a decrease in the available memory bandwidth per CPU core. This is especially true as the growth rate of memory capacity slows down, further exacerbating the inability to meet the demands of CPU cores and limiting their processing performance. Simultaneously, various user applications running on servers (such as database applications) experience significant memory resource idleness during periods of low traffic due to dynamic traffic fluctuations, resulting in wasted resources and costs.

[0004] Therefore, there is an urgent need to provide a solution that can flexibly adapt to the memory requirements of different processors. Summary of the Invention

[0005] This disclosure provides a memory expansion system, method, switch, and memory pool to achieve distributed device linkage.

[0006] In a first aspect, embodiments of this disclosure provide a memory expansion system, the system comprising: a first computing node, a switch, and a memory pool, wherein the switch includes a switching chip and a controller for managing the switching chip; the first computing node, the switch, and the memory pool all support a high-speed interconnect protocol; the first computing node is any one of a plurality of computing nodes supporting the high-speed interconnect protocol; a processor in the first computing node is connected to an uplink port of the switching chip; the memory pool includes a plurality of extended memory media, the plurality of extended memory media being respectively connected to different downlink ports of the switching chip; and the controller is used to configure the correspondence between the uplink ports and downlink ports of the switching chip, the correspondence being used to reflect the extended memory media that the processor in the first computing node can expand to use.

[0007] Secondly, this disclosure provides a memory expansion method applied to a switch supporting a high-speed interconnect protocol. The switch includes a switching chip and a controller for managing the switching chip. The switching chip includes an uplink port for connecting a processor in a first computing node and a downlink port for connecting multiple extended memory media in a memory pool supporting the high-speed interconnect protocol. The first computing node is any one of multiple computing nodes supporting the high-speed interconnect protocol. The method includes: the controller receiving memory expansion requirement information corresponding to a processor in the first computing node; the controller determining, based on the memory expansion requirement information, an extended memory media allocated to the processor in the first computing node in the memory pool, to configure a correspondence between the uplink and downlink ports of the switching chip, the correspondence reflecting the extended memory media that the processor in the first computing node can expand to use.

[0008] Thirdly, embodiments of this disclosure provide a switch that supports a high-speed computer interconnect protocol. The switch includes a switching chip and a controller for managing the switching chip. The switching chip includes an uplink port for connecting processors in multiple computing nodes and a downlink port for connecting multiple extended memory media in a memory pool, the multiple extended memory media supporting the high-speed computer interconnect protocol. The controller is used to configure the correspondence between the uplink and downlink ports of the switching chip, the correspondence being used to reflect the extended memory media that can be expanded and used by the processors in the multiple computing nodes.

[0009] Fourthly, embodiments of this disclosure provide a memory pool, which includes multiple extended memory media supporting high-speed computer interconnect protocols. The multiple extended memory media are respectively connected to different downlink ports of a switching chip. Different uplink ports of the switching chip are connected to processors in multiple computing nodes. A controller is used to manage the switching chip and configure the correspondence between the uplink ports and downlink ports of the switching chip. The correspondence is used to reflect the extended memory media that can be expanded and used by the processors in the multiple computing nodes.

[0010] The memory expansion scheme provided in this disclosure includes a compute node, a switch, and a memory pool supporting the Compute Express Link (CXL) protocol. The switch includes a switching chip and a controller for managing the switching chip. The memory pool includes multiple extended memory media, each connected to a different downstream port of the switching chip via a bus with a defined bandwidth. The processor in the compute node is connected to an upstream port of the switching chip via a bus with a defined bandwidth. The controller configures the correspondence between the upstream and downstream ports of the switching chip to enable the processor in the compute node to expand the memory available in the memory pool. This scheme provides a shared CXL-compliant memory pool for multiple compute nodes and a separate CXL-compliant switch, allowing for flexible expansion of the memory used by the processor in the compute node. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 is a schematic diagram of the composition architecture of the memory expansion system provided in an embodiment of this disclosure;

[0013] Figure 2 is an application diagram of the memory configuration process of the controller in the switch provided in the embodiments of this disclosure;

[0014] Figure 3 is a flowchart of a memory expansion method provided in an embodiment of this disclosure;

[0015] Figure 4 is a schematic diagram of a memory expansion device provided in an embodiment of this disclosure;

[0016] Figure 5 is a schematic diagram of the structure of a switch provided in an embodiment of this disclosure. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0019] The following detailed description of some embodiments of this disclosure is provided in conjunction with the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features can be combined with each other. Furthermore, the timing of the steps in the following method embodiments is merely an example and not a strict limitation.

[0020] First, some concepts involved in the embodiments of this disclosure will be explained.

[0021] CXL protocol: A high-speed serial protocol that allows for fast and reliable data transmission between different components within a computer system.

[0022] Just a Bunch of Memory (JBOM): A pool of storage media that support the CXL protocol. Because these storage media support the CXL protocol, they can be used as extended memory media, and therefore can be called extended memory media.

[0023] Double Data Rate SDRAM (DDR): This is what we usually refer to as memory chips.

[0024] Solid-state drive (SSD): A type of storage medium.

[0025] E3.S / E3.L: These are two packaging specifications for storage media, such as E3.S form factor SSDs.

[0026] The memory expansion scheme provided in the embodiments of this disclosure is described in detail below.

[0027] Figure 1 is a schematic diagram of the composition architecture of the memory expansion system provided in this embodiment of the present disclosure. As shown in Figure 1, the memory expansion system includes: multiple computing nodes supporting the CXL protocol (such as CN1, CN2...CN8 shown in Figure 1), a switch, and a memory pool. The switch includes a switching chip and a controller for managing the switching chip. The memory pool includes multiple extended memory media, such as JBOM11, JBOM12..., JBOM21, JBOM22... shown in Figure 1.

[0028] The extended memory media in the memory pool can actually be various types of storage media such as DDR and SSD, and their packaging form can be E3.S or E3.L, etc.

[0029] Each compute node contains multiple processors. In this article, the processors in the compute node mainly refer to CPUs, which will be directly described as CPUs in the following text. This is not a limitation and applies to any processor type that needs to use memory.

[0030] In addition, in this embodiment of the disclosure, the interface protocol that supports memory expansion can be the CXL protocol or other types of protocols, and is not limited thereto; CXL is used as an example for illustration only.

[0031] It can be seen that the architecture of this memory expansion system is based on the CXL protocol, and realizes a flexible memory expansion scheme for the CPU in the computing node by separating memory from the computing node.

[0032] The memory expansion system in this embodiment includes the following three layers: a compute node layer, a switch layer, and a memory pool layer. The compute node layer corresponds to the aforementioned multiple compute nodes, the switch layer corresponds to the aforementioned at least one switch chip and controller, and the memory pool layer corresponds to a memory pool containing multiple extended memory media.

[0033] In practical applications, a switch may include at least one switching chip, such as the two switching chips SW1 and SW2 shown in Figure 1. The controller is used to centrally manage these switching chips. In practical applications, the controller may be a CPU or the like. The controller may be located within one of the switching chips or may be located independently of each switching chip within the switch.

[0034] It should be noted that, in this embodiment of the disclosure, the term "switch application" is understood to mean a functional layer—the switch layer—and should not be limited to a single physical device. Therefore, multiple switching chips may reside within the same physical device or in different physical devices.

[0035] As shown in Figure 1, each switching chip has multiple uplink ports and multiple downlink ports. For example, the uplink ports on SW1 include SW1_u1, SW1_u2, ..., and the downlink ports on SW1 include SW1_d1, SW1_d2, ... . The uplink ports on SW2 include SW2_u1, SW2_u2, ..., and the downlink ports on SW2 include SW2_d1, SW2_d2, ... . The uplink ports are used to connect to the compute nodes, specifically to the processors (CPUs) within the compute nodes, while the downlink ports are used to connect to the extended memory media in the memory pool.

[0036] Each compute node contains multiple CPUs. When memory expansion is needed for a particular CPU, it can be connected to an uplink port on the switch chip. In practical applications, the CPU can be connected to a nearby available uplink port.

[0037] The memory pool includes multiple extended memory media that are used as memory and all support the CXL protocol. This means that the connection method between these extended memory media and the downstream port of the switching chip must comply with the CXL protocol.

[0038] Similarly, both switches and compute nodes support the CXL protocol, which means that the connection method between the CPU and the switching chip and the memory access method in the compute node must comply with the CXL protocol.

[0039] Specifically, as shown in Figure 1, a CPUx in any computing node can be connected to an uplink port of a switching chip via a bus with a set bandwidth, and this bus supports the CXL protocol, such as the CXL x16 bus shown in the figure. Similarly, any extended memory medium in the memory pool can be connected to a downlink port of a switching chip via a bus with a set bandwidth, and this bus supports the CXL protocol, such as the CXL x4 bus shown in the figure.

[0040] As shown in the example in Figure 1, the same uplink or downlink port on a switching chip can connect to a CPU or memory expansion medium. The same memory expansion medium can only be connected to one downlink port of the switching chip. However, the same CPU can be connected to different uplink ports of the same switching chip, or different uplink ports of different switching chips. For example, in the case of the two switching chips illustrated in Figure 1, a CPU in CN1 can be connected to different uplink ports of the two switching chips.

[0041] In practical applications, the number of CPUs and extended memory that can be connected is limited by the number of switching chips in the switch and the number of ports on each switching chip.

[0042] For example, a switch chip has 256 ports, 128 of which are uplink ports and 128 are downlink ports. If the bus used to connect to the CPU is a CXL x16 bandwidth bus, then 128 / 16 = 8 CPUs can be connected to the uplink ports. If the bus used to connect to the extended memory media is a CXL x4 bandwidth bus, then 128 / 4 = 32 extended memory media can be connected to the uplink ports. In practical applications, the bandwidth of the bus can be set according to actual needs, such as selecting an appropriate bus bandwidth based on the CPU's memory access speed.

[0043] In the aforementioned memory expansion system architecture, the controller used to manage each switching chip can be used to configure the correspondence between the uplink and downlink ports of the switching chip, thereby determining the expandable memory medium that the CPU in the computing node can use based on this correspondence.

[0044] Taking a CPUx in the first computing node CN1 shown in Figure 1 as an example, assuming that CPUx is connected to the uplink port SW1_u1 of SW1, and the controller configures the uplink port SW1_u1 to correspond to the downlink ports SW1_d1 and SW1_d2 of SW1, then it means that CPUx connected to the uplink port SW1_u1 of SW1 can use JBOM11 and JBOM12 connected to the downlink ports SW1_d1 and SW1_d2 of SW1 as external extended memory. This would form the following correspondence: CN1_CPUx——SW1_u1——SW1_d1+SW1_d2——JBOM11+JBOM12.

[0045] Of course, if CPUx is also connected to an uplink port of SW2, and the controller is configured to correspond to one or more downlink ports of SW2, then there will be another correspondence for CPUx (CPUx -- the uplink port of SW2 -- the downlink port of SW2 -- the extended memory medium connected to the downlink port), which is used to reflect the memory that CPUx can expand and use in the memory pool.

[0046] Therefore, it can be seen that by configuring the correspondence between the uplink and downlink ports of the switching chip, the controller can meet the expansion requirements of different memory capacities of the CPUs in different computing nodes.

[0047] After the controller completes the configuration of the above correspondence, it can send the correspondence to the CPU in the corresponding computing node, such as CPUx in CN1 in the example above. Then CPUx can access (write and read data) the extended memory medium allocated to it.

[0048] Specifically, based on this correspondence, CPUx can trigger a memory access request to the extended memory medium allocated to it, send the memory access request to the corresponding switching chip SW1, and then send the memory access request to the extended memory medium corresponding to CPUx through the switching chip SW1.

[0049] In practical applications, after configuring the aforementioned correspondence, the controller sends this correspondence and address allocation rules to CPUx. CPUx can then allocate address information to the extended memory medium it is assigned to based on these rules. Afterward, CPUx can directly access the extended memory medium. Thus, the memory access request can carry the address information of the extended memory medium, allowing CPUx to directly access it. It should be noted, however, that this memory access request actually passes through the physically existing device SW1 before reaching the extended memory medium.

[0050] In the above scheme, a dedicated CXL switching chip is used as a memory expansion method. A memory pool based on the CXL protocol is set up, and centralized management by the controller enables centralized allocation of extended memory media in the memory pool by CPUs in several computing nodes, thereby achieving the memory expansion goal for CPUs in each computing node. Moreover, the extended memory media in the memory pool uses standard E3.S / E3.L form factor packaging, which allows for flexible plugging and unplugging, achieving the goal of flexible expansion and allocation of memory configuration.

[0051] The following examples illustrate several configuration scenarios where the controller provides available extended memory media for the CPU in the computing node.

[0052] Figure 2 is an application diagram of the memory configuration process of the controller in the switch provided in the embodiment of this disclosure. As shown in Figure 2, the switch is provided with a network interface S that is interconnected with each computing node. Similarly, each computing node also has a corresponding network interface, such as the network interfaces C1 and C2 of the first computing node CN1 and the second computing node CN2 shown in Figure 2.

[0053] In practical applications, the network interface can be a Gigabit Ethernet (GE) interface of a certain bandwidth, such as a 25GE interface, but is not limited to this.

[0054] Therefore, there are two types of connections that can exist between the computing node and the switch: one is a connection between the CPU and the switching chip via the CXL bus, and the other is a network connection between these network interfaces, such as an Ethernet connection. The CXL bus connection is used for CPU data access to the extended memory medium, while the Ethernet connection can be used to configure the extended memory medium available to the CPU, that is, to configure the uplink and downlink port mapping of the switching chip. It should be noted that the communication connection used for this configuration is not limited to the above-mentioned network connection; other types of communication connection forms are also possible.

[0055] The following example, using the first compute node CN1 and the second compute node CN2 among multiple compute nodes, illustrates the configuration of the controller for expanding the memory medium of the CPU in the compute node.

[0056] The first scenario.

[0057] The controller receives memory expansion requirement information corresponding to CPUx in the first computing node CN1 through the network interface S, and determines the expansion memory medium allocated to CPUx in the first computing node CN1 in the memory pool based on the memory expansion requirement information, so as to configure the correspondence between CPUx and the expansion memory medium.

[0058] In practical applications, a user's application may use one or more computing nodes. During a certain phase of the application's operation, when the CPUs on these computing nodes require a larger amount of memory, and the local memory of the computing nodes is insufficient to support this, a memory expansion requirement arises. Therefore, all or part of the CPUs in the computing nodes can be connected to the switching chip in the switch provided in this embodiment of the disclosure, so as to complete the memory expansion for that CPU by managing the controller of the switching chip and the memory pool connected to the downlink port of the switching chip.

[0059] Specifically, the switch can provide a configuration interface, which users can remotely log in to through the first computing node CN1. In the configuration interface, the user inputs the memory expansion requirement information, and then the first computing node CN1 sends the memory expansion requirement information to the network interface S in the switch through the network interface C1. The controller obtains the memory expansion requirement information through the network interface S.

[0060] The memory expansion requirement information may include the identification information of the CPUx that needs memory expansion and the required expansion capacity. Therefore, the controller determines which uplink port on which switch chip the CPUx is connected to based on the CPUx's identification information, and determines the number of expansion memory media to be allocated and the downlink port on the switch chip to which the allocated expansion memory media is connected, based on the memory capacity, thus establishing a correspondence between the uplink port corresponding to the CPUx and the downlink port corresponding to the allocated expansion memory media.

[0061] It should be noted that, generally speaking, the same extended memory medium can only be allocated to one CPU at a time.

[0062] Additionally, it should be noted that, for example, if based on the memory capacity required by CPUx, the storage capacity that each extended memory medium can provide, and the number of remaining allocatable extended memory mediums in the memory pool, it is determined that the remaining allocatable extended memory mediums are insufficient to meet the required memory capacity, then the actual number of extended memory mediums allocated to CPUx, i.e., the storage capacity of the allocated extended memory, will be less than the required memory capacity.

[0063] In addition, the controller can also allocate memory based on the priority settings of different applications, processing the memory expansion requests triggered by the compute nodes corresponding to those applications on a priority-based basis. That is, it prioritizes allocating memory to compute nodes corresponding to high-priority applications as needed.

[0064] The second scenario.

[0065] The controller receives the load information corresponding to CPUx in the first computing node CN1 through the network interface S, and adjusts the extended memory medium allocated to CPUx in the first computing node CN1 according to the load information to update the above correspondence.

[0066] In practical applications, the load of the application corresponding to the first computing node CN1 is dynamic. The application can track its load changes and send this load information to the switch. The controller then adjusts the amount of extended memory allocated to its CPUx based on this load information; for example, increasing the amount when the load increases and decreasing it when the load decreases. This allows different applications to fully utilize the shared extended memory resources in the memory pool, improving resource utilization. The aforementioned load information can be the application's predicted load level over a future period and the corresponding expected additional memory capacity.

[0067] The third scenario.

[0068] The controller receives a correspondence adjustment request through the network interface S, and adjusts the correspondence between CPUx in the first computing node CN1 and the target extended memory medium according to the correspondence adjustment request, so that CPUy in the second computing node CN2 can access the target extended memory medium.

[0069] In practical applications, a user's application may need to utilize CPUs across multiple computing nodes to process tasks. For example, database applications often require hundreds of CPUs, while a single computing node may not have enough CPUs to support this. Therefore, the database application needs to occupy several computing nodes, with the numerous CPUs within these nodes collaboratively completing the database-related tasks. During the coordinated task processing, there may be situations where one CPU needs to use the data processing results of another CPU, and these results can be stored in its corresponding extended memory. This creates a data access requirement between different CPUs.

[0070] The traditional solution is often this: one CPU uploads its data processing results to a shared space via a network, and another CPU accesses that shared space via a network connection when it needs to use it. This results in the establishment of network connections and the consumption of network traffic.

[0071] The solution provided in this embodiment can achieve data transfer between different CPUs without using any data traffic.

[0072] Specifically, in this embodiment, it is assumed that an application occupies the first computing node CN1 and the second computing node CN2. For ease of description, it is only assumed that one CPU in each of these two computing nodes has undergone memory expansion using the method described in the previous embodiment, namely CPUx and CPUy as shown in Figure 2. Furthermore, it is assumed that the expanded memory medium corresponding to CPUx is JBOM1, and the expanded memory medium corresponding to CPUy is JBOMb. The controller will send the "correspondence" between these two CPUs to the application, so that the application can know the allocation of the expanded memory medium for each CPU. This correspondence is the correspondence between the uplink port connected to the CPU and the downlink port connected to the expanded memory medium allocated to it, as mentioned above.

[0073] Based on this, after CPUx writes a data processing result to its corresponding JBOMa, the application knows that CPUy needs to use this data processing result for subsequent processing. Therefore, it sends a mapping adjustment request to the network interface S of the switch. This request instructs that the extended memory medium JBOMa corresponding to CPUx be reassigned to CPUy. Consequently, the controller adjusts the mapping between CPUx and the extended memory medium JBOMa to the mapping between CPUy and the extended memory medium JBOMa, enabling CPUy to access the data in the extended memory medium JBOMa. In this way, by modifying the mapping, the data in the JBOMa can be moved without incurring additional network connections and network traffic, allowing CPUy to access the data in the JBOMa.

[0074] Figure 3 is a flowchart of a memory expansion method provided in an embodiment of this disclosure. The method is applied to a switch supporting the CXL protocol. The switch includes a switching chip and a controller for managing the switching chip. The switching chip includes an uplink port for connecting to a processor in a first computing node and a downlink port for connecting to multiple extended memory media in a memory pool supporting the CXL protocol. The first computing node is any one of multiple computing nodes supporting the CXL protocol. As shown in Figure 3, the method may include steps 301 to 303.

[0075] 301. The controller receives memory expansion requirement information corresponding to the processor in the first computing node.

[0076] 302. The controller determines the extended memory medium allocated to the processor in the first computing node from the memory pool based on the memory expansion requirement information.

[0077] 303. The controller configures the mapping between the uplink and downlink ports of the switching chip, which is used to reflect the expandable memory available to the processor in the first computing node.

[0078] As mentioned above, the switch includes a network interface that interconnects with the first computing node, through which the aforementioned memory expansion requirement information is received.

[0079] Alternatively, the method may further include: the controller receiving load information corresponding to the processor in the first computing node through the aforementioned network interface, and adjusting the extended memory medium allocated to the processor in the first computing node according to the load information, so as to update the correspondence between the processors in the first computing node.

[0080] Alternatively, the method further includes: in response to a correspondence adjustment request, the controller adjusts the correspondence between the processor in the first computing node and the target extended memory medium to the correspondence between the processor in the second computing node and the target extended memory medium according to the correspondence adjustment request, so that the processor in the second computing node can access the target extended memory medium, wherein the second computing node is a computing node among a plurality of computing nodes that corresponds to the same user application as the first computing node.

[0081] The execution process of this embodiment can be referred to the relevant descriptions in the other embodiments above, and will not be repeated here.

[0082] The memory expansion apparatus of one or more embodiments of this disclosure will be described in detail below. Those skilled in the art will understand that these apparatuses can be configured using commercially available hardware components through the steps taught in this solution.

[0083] Figure 4 is a schematic diagram of a memory expansion device provided in an embodiment of this disclosure. This memory expansion device is applied to a switch supporting the CXL protocol. The switch includes a switching chip and a controller for managing the switching chip. The switching chip includes an uplink port for connecting to a processor in a first computing node and a downlink port for connecting to multiple extended memory media in a memory pool supporting the CXL protocol. The first computing node is any one of the multiple computing nodes supporting the CXL protocol. As shown in Figure 4, the device includes: a receiving module 11, an allocation module 12, and a configuration module 13.

[0084] The receiving module 11 is used to receive memory expansion requirement information corresponding to the processor in the first computing node.

[0085] The allocation module 12 is used to determine, in the memory pool, the extended memory medium to be allocated to the processor in the first computing node based on the memory expansion requirement information.

[0086] Configuration module 13 is used to configure the correspondence between the uplink port and the downlink port of the switching chip, the correspondence being used to reflect the extended memory medium that the processor in the first computing node can expand to use.

[0087] The device shown in Figure 4 can perform the steps executed by the controller in the foregoing embodiments. For detailed execution process and technical effects, please refer to the description in the foregoing embodiments, which will not be repeated here.

[0088] In one possible design, the structure of the device shown in Figure 4 can be implemented as an electronic device: a switch. This switch supports high-speed computer interconnection protocols, as shown in Figure 5. The switch includes switching chips and a controller for managing the switching chips. In practical applications, as shown in Figure 5, the number of switching chips can be one or more.

[0089] Each switching chip includes uplink ports for connecting processors in multiple computing nodes and downlink ports for connecting multiple extended memory media in a memory pool. For example, the uplink ports of the two switching chips illustrated in Figure 5 are SW1_u1, SW1_u2… and SW2_u1, SW2_u2…, and the downlink ports are SW1_d1, SW1_d2… and SW2_d1, SW2_d2….

[0090] Among them, multiple extended memory media support high-speed computer interconnect protocols.

[0091] The controller is used to configure the mapping between the uplink and downlink ports of the switching chip. This mapping reflects the extended memory media that can be used by the processors in multiple computing nodes.

[0092] In addition, this disclosure provides a memory pool that includes multiple extended memory media supporting high-speed computer interconnect protocols, and the multiple extended memory media are respectively connected to different downlink ports of a switching chip.

[0093] The different uplink ports of the switching chip are connected to processors in multiple computing nodes.

[0094] The controller used to manage the switching chip can configure the mapping between the uplink and downlink ports of the switching chip. This mapping reflects the extended memory media that can be scalably used by processors in multiple computing nodes.

[0095] In addition, embodiments of this disclosure provide a non-transitory machine-readable storage medium storing executable code, which, when executed by a processor of an electronic device, enables the processor to at least implement the memory expansion method provided in the foregoing embodiments.

[0096] The device embodiments described above are merely illustrative. The network elements described as separate components may or may not be physically separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of a necessary general-purpose hardware platform, or by a combination of hardware and software. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a computer product. This disclosure can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory extension system, characterized by, The application relates to a computer system comprising: a first computing node, a switch and a memory pool, the switch comprising a switch chip and a controller for managing the switch chip, the first computing node, the switch and the memory pool all supporting a computer high-speed interconnection protocol, the first computing node being any one of a plurality of computing nodes supporting the computer high-speed interconnection protocol; a processor in the first computing node being connected to an uplink port of the switch chip; the memory pool comprising a plurality of extended memory media, the plurality of extended memory media being respectively connected to different downlink ports of the switch chip; the controller being configured to configure a correspondence between the uplink port and the downlink port of the switch chip, the correspondence reflecting an extended memory medium that can be extendedly used by the processor in the first computing node.

2. The system of claim 1, wherein, the controller being further configured to send the correspondence to the processor in the first computing node; the switch chip being configured to, in response to a memory access request triggered by the processor in the first computing node based on the correspondence, send the memory access request to the extended memory medium corresponding to the processor according to address information of the extended memory medium corresponding to the processor contained in the memory access request.

3. The system of claim 1, wherein, the switch comprising a network interface interconnected with the first computing node; the controller being configured to receive memory extension demand information corresponding to the processor in the first computing node through the network interface, determine an extended memory medium allocated to the processor in the first computing node in the memory pool according to the memory extension demand information, and configure the correspondence.

4. The system of claim 1, wherein, the switch comprising a network interface interconnected with the first computing node; the controller being further configured to receive load information corresponding to the processor in the first computing node through the network interface, adjust the extended memory medium allocated to the processor in the first computing node according to the load information, and update the correspondence.

5. The system of claim 1, wherein, the switch comprising a network interface interconnected with a second computing node, wherein the second computing node is a computing node corresponding to the first computing node in the plurality of computing nodes and corresponding to a same application program; the controller being further configured to receive a correspondence adjustment request through the network interface, and adjust a correspondence between the processor in the first computing node and a target extended memory medium to a correspondence between a processor in the second computing node and the target extended memory medium according to the correspondence adjustment request, so that the processor in the second computing node can access the target extended memory medium.

6. A memory extension method, characterized by, The application relates to a computer system comprising: a first computing node, a switch and a memory pool, the switch comprising a switch chip and a controller for managing the switch chip, the first computing node, the switch and the memory pool all supporting a computer high-speed interconnection protocol, the first computing node being any one of a plurality of computing nodes supporting the computer high-speed interconnection protocol; the method comprising: The controller receives memory extension demand information corresponding to the processors in the first computing node; The controller determines, according to the memory extension demand information, extension memory media allocated to the processors in the first computing node in the memory pool to configure a correspondence between the uplink ports and the downlink ports of the switch chip, the correspondence reflecting the extension memory media that the processors in the first computing node can extend to use.

7. The method of claim 6, wherein, The switch includes a network interface connected with the first computing node, and the memory extension demand information is received through the network interface.

8. The method of claim 7, wherein, The method further includes: The controller receives load information corresponding to the processors in the first computing node through the network interface; According to the load information, the extension memory media allocated to the processors in the first computing node are adjusted to update the correspondence.

9. The method of claim 6, wherein, The method further includes: In response to a correspondence adjustment request, the controller adjusts, according to the correspondence adjustment request, the correspondence between the processors in the first computing node and the target extension memory media to the correspondence between the processors in a second computing node and the target extension memory media, so that the processors in the second computing node can access the target extension memory media, where the second computing node is a computing node corresponding to the same user application as the first computing node in the plurality of computing nodes.

10. A switch, characterized by The switch supports a computer high-speed interconnection protocol, and includes a switch chip and a controller for managing the switch chip; The switch chip includes uplink ports for connecting processors in a plurality of computing nodes, and includes downlink ports for connecting a plurality of extension memory media in a memory pool, and the plurality of extension memory media supports a computer high-speed interconnection protocol; The controller is configured to configure a correspondence between the uplink ports and the downlink ports of the switch chip, and the correspondence reflects the extension memory media that the processors in the plurality of computing nodes can extend to use.

11. A memory pool, characterized by The memory pool includes a plurality of extension memory media supporting a computer high-speed interconnection protocol, and the plurality of extension memory media are respectively connected with different downlink ports of the switch chip; Different uplink ports of the switch chip are connected with processors in a plurality of computing nodes; The controller for managing the switch chip configures a correspondence between the uplink ports and the downlink ports of the switch chip, and the correspondence reflects the extension memory media that the processors in the plurality of computing nodes can extend to use.

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