Photosensitive element array for detecting time-related image data and peripheral readout circuit therefor

Abstract

The present invention relates to the field of dynamic vision sensors, and relates in particular to a photosensitive element array for detecting time-related image data. The photosensitive element array is composed of R rows × C columns of units. Each unit comprises: a light sensor having a dynamic range compression characteristic, the light sensor autonomously converting, without any external control, a high-dynamic-range incident light signal into a low-dynamic-range output voltage signal; a plurality of voltage sampling storage units, the stored voltages being obtained by sampling the output voltage signal of the light sensor at different time points; and a voltage readout circuit, configured to read out, simultaneously or in a time-division manner, the voltages in the voltage sampling storage units to the periphery of the photosensitive element array. The present invention further relates to a peripheral readout circuit for the photosensitive element array. The peripheral readout circuit comprises a row scanning and timing control module, C amplifiers, and C analog-to-digital converters capable of sensing field-of-view activity, wherein each analog-to-digital converter adjusts the number of effective conversion cycles in each conversion on the basis of the amplitude of a visual signal sensed by units in a column corresponding to the analog-to-digital converter.

Description

A photosensitive element array and its peripheral readout circuit for detecting time-related image data. Technical Field

[0001] This invention belongs to the field of dynamic vision sensor technology, and relates to a photosensitive element array for detecting time-related image data and its peripheral readout circuit. Background Technology

[0002] Current image and video generation relies on electronic image sensors, particularly those based on CMOS technology. Their operation involves reading out the voltage values ​​of all pixels in the entire sensing plane after photoelectric conversion, frame by frame. However, this readout method generates a large amount of redundant data in machine vision applications, especially when the activity level in the sensor's field of view is low, as most pixels repeatedly output previous readout values. This redundancy not only increases the readout power consumption of the image sensor, but also makes this readout method impractical due to bandwidth limitations when high-speed, high-resolution readout is required. Furthermore, the large amount of sensor-generated data increases the energy consumption and latency of backend processing, limiting its application in intelligent scenarios within machine vision.

[0003] Dynamic vision sensors overcome the trade-off between readout power consumption and limited data bandwidth inherent in traditional image sensors. The relevant original patent is US20080135731. The key feature of this patent is that pixels no longer simply store voltage values ​​obtained from photocurrent integration. Instead, they autonomously detect changes in light intensity within their field of view by amplifying the voltage obtained from photocurrent conversion via a transconductance amplifier, followed by a process similar to asynchronous delta modulation. Specifically, only pixels that detect changes in light intensity autonomously output data, reducing redundancy in sensor output data and the bandwidth requirements. Furthermore, the sparse readout and transmission of effective data reduces sensor power consumption. Despite the advantages of dynamic vision sensors over traditional image sensors, their significant drawbacks include: 1. The large number of elements per pixel makes it difficult to reduce pixel size, resulting in a larger chip area and increased cost compared to image sensors at the same resolution; 2. The excessive number of elements per pixel within a limited pixel size restricts element size, leading to increased analog non-ideal characteristics of the elements, increased mismatch between pixels, and reduced fidelity in converting light intensity changes to digital output; 3. Event-based sampling and encoding methods cannot optimally utilize the sensor's output bandwidth. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a photosensitive element array and its peripheral readout circuit for detecting time-related image data, while retaining and improving the advantages of dynamic vision sensors and solving their existing defects.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] On one hand, the present invention provides a photosensitive element array for detecting time-related image data, comprising R rows × C columns of units, each unit including:

[0007] A light sensor with dynamic range compression features can autonomously convert incident light signals with high dynamic range into output voltage signals with low dynamic range without any external control.

[0008] Several voltage sampling and storage units are provided, and the stored voltages are obtained by sampling the output voltage signal of the optical sensor at different time points.

[0009] The voltage readout circuit reads the voltage in the voltage sampling storage unit simultaneously or in time-division manner to the periphery of the unit array.

[0010] Furthermore, the dynamic range compression characteristic of the optical sensor is presented in an approximately logarithmic input-output relationship, that is, the output voltage of the optical sensor is approximately linearly related to the logarithm of the input light intensity.

[0011] Optionally, the unit includes a pinned photodiode, an inverting amplifier, a transmission gate transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus ,in:

[0012] The anode of the pinned photodiode is grounded, and the cathode is connected to the source of the transmission gate transistor; the gate of the transmission gate transistor is connected to a high-level voltage V. high The drain of the first N-type transistor is connected to the source of the first N-type transistor and the input stage of the inverting amplifier; the drain of the first N-type transistor is connected to the power supply voltage, and its gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor; the drain of the second N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the third N-type transistor and the drain of the fifth N-type transistor; the gate of the third N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the fourth N-type transistor; the gate of the fourth N-type transistor is connected to the first bias voltage V. bias1 The source of the fifth N-type transistor is grounded; the gate of the fifth N-type transistor is connected to SH, and its source is connected to the upper plate of the first capacitor C1, the upper plate of the second capacitor C2, the drain of the eighth N-type transistor, and the gate of the ninth N-type transistor; the lower plate of the first capacitor C1 is connected to the drain of the sixth N-type transistor; the lower plate of the second capacitor C2 is connected to the drain of the seventh N-type transistor; and the gate of the sixth N-type transistor is connected to the second sampling control signal SH. s1 The source is connected to the reference voltage V.ref The gate of the seventh N-type transistor is connected to the third sampling control signal SH. s2 Source connected to V ref The gate of the eighth N-type transistor is connected to the reset signal RST, and the source is connected to V. ref The drain of the ninth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the tenth N-type transistor; the gate of the tenth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus .

[0013] Optionally, the unit includes a photodiode, an inverting amplifier, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus ,in:

[0014] The anode of the photodiode is grounded, and the cathode is connected to the source of the first N-type transistor and the input stage of the inverting amplifier. The drain of the first N-type transistor is connected to the power supply voltage, and its gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor. The drain of the second N-type transistor is connected to the power supply voltage, and its source is connected to the drains of the third and fourth N-type transistors. The gate of the third N-type transistor is connected to the first bias voltage V. bias1 The source of the fourth N-type transistor is grounded; the gate of the fourth N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the fifth N-type transistor, the drain of the sixth N-type transistor, the drain of the seventh N-type transistor, and the gate of the eighth N-type transistor; the gate of the fifth N-type transistor is connected to the second sampling control signal SH. s1 The source of the sixth N-type transistor is connected to the upper plate of the first capacitor C1; the gate of the sixth N-type transistor is connected to the third sampling control signal SH. s2 The source of the seventh N-type transistor is connected to the upper plate of the second capacitor C2; the gate of the seventh N-type transistor is connected to the reset signal RST, and the source is connected to the reference voltage V. ref The lower plate of the first capacitor is grounded; the lower plate of the second capacitor is grounded; the drain of the eighth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the ninth N-type transistor; the gate of the ninth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus .

[0015] Furthermore, the high level V of each unit high First bias voltage V bias1 Reference voltage V ref The first sampling control signal SH is common to all units, and the voltage bus V is read out. bus The second sampling control signal SH is shared by each column of cells. s1 Third sampling control signal SHs2 The reset signal RST and the read selection signal SEL are shared by each row of cells.

[0016] Furthermore, by analyzing signals SH and SH... s1 SH s2 The timing control of RST and SEL reads the voltages stored in C1 and C2 in the cell row by row into the column-parallel V. bus superior.

[0017] Furthermore, the timing control steps are as follows:

[0018] At time t 0_0 At the start of the first signal sampling phase, SH changes from low to high, and the SH of all rows... s2 Also, from low to high, all rows of SH s1 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C2;

[0019] At time t 1_0 The first signal sampling phase ends and the first signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s2 Also, the values ​​of RST and SEL in the first row change from high to low;

[0020] At time t 2_0 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior;

[0021] At time t 3_0 The RST in the first line changes from low to high, and the SH in the first line... s2 From high to low;

[0022] At time t 4_0 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior;

[0023] At time t 5_0 SH in the first line s1 And SEL changes from high to low;

[0024] At time t 6_0 In the second row, RST and SEL change from low to high;

[0025] At time t 7_0 The RST in the second line changes from high to low, and the SH in the second line... s2From low to high, the voltage stored on C2 in all cells of the second row is read out to the column-parallel V. bus superior;

[0026] At time t 8_0 The RST in the second line changes from low to high, and the SH in the second line... s2 From high to low;

[0027] At time t 9_0 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior;

[0028] At time t 10_0 SH in the second line s1 And SEL changes from high to low;

[0029] This process continues until all the voltages stored in C2 and C1 in all cells are read out line by line; then, at time t... 0_1 At the start of the second signal sampling phase, SH changes from low to high, and the SH of all rows... s1 Also, from low to high, all rows of SH s2 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C1;

[0030] At time t 1_1 The second signal sampling phase ends and the second signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s1 Also, the values ​​of RST and SEL in the first row change from high to low;

[0031] At time t 2_1 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior;

[0032] At time t 3_1 The RST in the first line changes from low to high, and the SH in the first line... s1 From high to low;

[0033] At time t 4_1 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior;

[0034] At time t 5_1 SH in the first line s2 And SEL changes from high to low;

[0035] At time t 6_1 In the second row, RST and SEL change from low to high;

[0036] At time t 7_1 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior;

[0037] At time t 8_1 The RST in the second line changes from low to high, and the SH in the second line... s1 From high to low;

[0038] At time t 9_1 The RST in the second line changes from high to low, and the SH in the second line... s2 From low to high, the voltage stored on C2 in all cells of the second row is read out to the column-parallel V. bus superior;

[0039] At time t 10_1 SH in the second line s2 And SEL changes from high to low;

[0040] This process continues until all the voltages stored in C1 and C2 in all cells are read out line by line; then, at time t... 0_2 Repeated at time t 0_0 The sequence of events continued until the photosensitive element array was manually stopped.

[0041] On the other hand, the present invention provides a peripheral readout circuit for a photosensitive element array, including a line scanning and timing control module, C amplifiers, and C analog-to-digital converters that can sense field of view activity.

[0042] The row scanning and timing control module is used to control the signal sampling and signal readout of any of the photosensitive element arrays described above.

[0043] The C amplifiers are used to amplify the C columns V in the photosensitive element array, respectively. bus The difference between the signals stored in C1 and C2 read from the amplifier; the amplifier has two input ports, each receiving V. bus The differential output is the amplified difference between the two signal voltage values ​​stored in a unit read sequentially from the previous unit.

[0044] The C analog-to-digital converters that can sense visual field activity convert the analog signals output by the C amplifiers into digital signals respectively; the analog-to-digital converters adjust the number of effective conversion cycles in each conversion according to the amplitude of the visual signal sensed by the unit in the corresponding column.

[0045] Further, the analog-to-digital converter for perceiving the field of view activity includes the following modules: a digital-to-analog converter DAC, a differential DAC, a comparator, a SAR logic, and several switches; the SAR logic is the SAR logic for perceiving the field of view activity, and the threshold for perceiving the field of view activity is built-in or an externally input parameter.

[0046] Further, in the analog-to-digital converter for perceiving the field of view activity, the differential output of the amplifier is directly compared in size by the comparator to obtain the value of the highest bit, the i-th bit, of the output of the analog-to-digital converter; the analog-to-digital converter samples the differential output of the amplifier, and the outputs of the (i - 1)-th bit to the 0-th bit of the analog-to-digital converter are cleared; according to the threshold parameter for perceiving the field of view activity built-in or externally input by the SAR logic, the k-th bit of the DAC and the differential DAC is controlled by the SAR logic to flip, where 0 ≤ k < i; according to the output result of the comparator, it is judged whether the absolute value of the difference between the output of the DAC before the k-th bit flip and the output of the differential DAC is greater than or equal to 2 k ×V LSB , where V LSB is the voltage value corresponding to the lowest bit of the output of the analog-to-digital converter; if not, the output of the current k-th bit of the analog-to-digital converter is retained, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the 0-th bit; if so, it is further judged whether k is equal to i - 1; if equal, the output of the current k-th bit of the analog-to-digital converter is retained, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the 0-th bit; if not, that is, k < i - 1, it is further judged whether k is greater than or equal to a set threshold k th ; if greater than or equal to, the SAR logic controls the analog-to-digital converter to convert from the (i - 1)-th bit to the 0-th bit; if less than, the k-th bit of the DAC and the differential DAC is controlled by the SAR logic to be restored, k = k + 1, the k-th bit of the DAC and the differential DAC is controlled by the SAR logic to flip, and then it loops back to the previous step of judging whether the absolute value of the difference between the output of the DAC before the k-th bit flip and the output of the differential DAC is greater than or equal to 2 k ×V LSB step.

[0047] Further, in the analog-to-digital converter for perceiving the field of view activity, the capacitor bottom plates of the DAC and the differential DAC are respectively connected to the positive reference voltage V ref+ , the negative reference voltage V ref- , or the common-mode voltage V CM through a switching switch. The switching switch corresponding to the DAC is controlled by the control signal D SAR+ [i - 1:0] at the output end of the SAR logic, and the switching switch corresponding to the differential DAC is controlled by the differential control signal D SAR-[i-1:0] Control, the capacitive bottom plate of the DAC is connected to the output terminal V of the amplifier through a sampling switch Ao+ , the capacitive bottom plate of the differential DAC is connected to the differential output terminal V of the amplifier through a differential sampling switch Ao- ; the capacitive top plate V of the DAC DAC+ is connected to the positive terminal of the comparator and is selectively connected to V through a reset switch Ao+ or V CM , the capacitive top plate V of the differential DAC DAC- is connected to the negative terminal of the comparator and is selectively connected to V through a differential reset switch Ao- or V CM ; the output of the comparator is connected to the first input terminal of the SAR logic, and the clock input terminal of the comparator is connected to the gated clock output terminal of the SAR logic; the data at the second input terminal of the SAR logic is the threshold θ for sensing the activity of the field of view ADC , and the result output terminal of the SAR logic provides the final digital output D of the analog-to-digital converter OUT [i:0]. [i:0].

[0048] Further, under the specific architecture of the analog-to-digital converter for sensing the activity of the field of view described above, its working principle is as follows:

[0049] The capacitive top plate and capacitive bottom plate of the DAC are connected to V Ao+ , the capacitive top plate and capacitive bottom plate of the differential DAC are connected to V Ao- , the comparator makes a comparison, and the SAR logic obtains the output D of the highest bit according to the result of the comparator OUT [i];

[0050] The capacitive top plate of the DAC and the capacitive top plate of the differential DAC are respectively disconnected from V Ao+ and V Ao- and are connected together to V CM ;

[0051] The capacitive top plates of the DAC and the differential DAC are both disconnected from V CM ;

[0052] The capacitive bottom plate of the DAC and the capacitive bottom plate of the differential DAC are respectively disconnected from V Ao+ and V Ao- and are connected together to V CM ;

[0053] The outputs D OUT [i-1:0] of the i-1th to 0th bits of the SAR logic are cleared;

[0054] If θ ADC = k, the SAR logic controls the analog-to-digital converter to start conversion from the kth bit accordingly, 0 ≤ k < i, and the kth bits of the capacitive bottom plates of the DAC and the differential DAC are respectively connected to Vref+ and V ref- After connection, the comparator compares V. DAC+ and V DAC- The value after stabilization;

[0055] If the comparator output is the same as the result when comparing the i-th bit, then retain D. OUT [k], then transform from the (k-1)th bit to the 0th bit to get D. OUT The value of [k-1:0];

[0056] If the comparator output is the opposite of the result when comparing the i-th bit, then further determine whether k is equal to i-1; if so, retain D. OUT [k], then transform from the (k-1)th bit to the 0th bit to get D. OUT If the value of [k-1:0] is not found, then it is further determined whether k is greater than or equal to a set threshold k. th If it is greater than or equal to, then convert from the (i-1)th bit to the 0th bit to obtain D. OUT The value of [i-1:0]; if it is less than, the k-th bit of the DAC and differential DAC is restored under SAR logic control, then k = k + 1, the k-th bit of the DAC and differential DAC is flipped under SAR logic control, and the loop continues to the previous comparator comparison V. DAC+ and V DAC- The steps to obtain the stable value.

[0057] Furthermore, the peripheral readout circuit of the photosensitive element array also includes a top-level control unit, whose output control signals control the line scanning and timing control module, C amplifiers, and C analog-to-digital converters that sense activity, thereby controlling the frame rate of the photosensitive element array, the gain of the amplifiers, and the threshold θ for the analog-to-digital converters to sense the activity in the field of view. ADC The resolution of the analog-to-digital converter is adjusted.

[0058] Furthermore, the peripheral readout circuit of the photosensitive element array also includes a digital signal processor; the input of the digital signal processor is connected to the outputs of C analog-to-digital converters capable of sensing field-of-view activity. ADC and for O ADC The sparsity is statistically analyzed; the top-level control unit is based on O ADC The sparsity statistics are set with θ ADC The digital signal processor is also used for O ADC The compressed output is then used as the final output of the sensor.

[0059] Furthermore, the digital signal processor supports O ADC The sparsity is statistically analyzed, and the top-level control unit is based on O. ADC The sparsity statistics are set with θ ADCThe specific steps are as follows:

[0060] The energy consumption distribution E required by the analog-to-digital converter at different bit widths was obtained through simulation or actual measurement. ADC The bit width starts from the 0th bit, with a minimum of 1 bit and a maximum of i-1 bits;

[0061] The output O of the analog-to-digital converter that can sense field of view activity in column C ADC The absolute values ​​of O are distributed statistically, and the method is as follows: ADC The range of values ​​is divided into 0, 1, 2~3, 4~7, ..., 2 k-1 ~2 k -1, k≤i-1, O ADC If the absolute value of a value in the range appears once, the count for that range is incremented by one; the count is expressed in terms of T. ADC For the time window, S ADC The distribution DIS is obtained by taking a moving average over a time step. ADC ;

[0062] According to distribution E ADC DIS ADC The pre-field-of-view activity sensing threshold θ, which minimizes the average analog-to-digital converter power consumption, was calculated using an optimized SAR algorithm for sensing field-of-view activity. pre ;

[0063] With T θ For the time window, S θ Find θ for the time step pre The moving average yields the distribution θ μpre If k-1 < θ μpre If ≤k, then set θ ADC =k.

[0064] Furthermore, the top-level control unit also adjusts the frame rate r of the two-dimensional pixel array based on the field of view activity. FPS Adjustments will be made, specifically including:

[0065] O ADC The absolute values ​​of the values ​​in the range are 0, 1, 2~3, 4~7, ..., 2 k-1 ~2 k -1,2 i-1 -1, k≤i-1, O ADC If the absolute value of a value in the range appears once, the count for that range is incremented by one; the count is expressed in terms of T. ADC For the time window, S ADC The distribution DIS is obtained by taking a moving average over a time step. ADC ;

[0066] Request DIS ADCThey tend to be distributed in 0 and 2 respectively. i-1 The weighted averages p1 and p2 on -1, with T FR For time window, S FR Calculate the moving average for the time step to obtain p. μ1 p μ2 ;

[0067] If p μ1 Greater than or equal to the set upper limit threshold p th1U , and p μ2 Less than or equal to the set lower threshold p th2L If the frame rate is greater than the minimum value, then let the frame rate r FPS Decrease Δ FRD If p μ1 Less than or equal to the set lower threshold p th1L , or p μ2 Greater than or equal to the set upper limit threshold p th2U If the frame rate is less than the maximum value, then let the frame rate r FPS Increase Δ FRU Frame rate changes in T FRS The time step is defined as the interval after each frame rate change, at least within time T. FRS It remains unchanged within.

[0068] The beneficial effects of this invention are as follows: This invention possesses the advantages of traditional event-triggered dynamic vision sensors compared to general image sensors, such as high dynamic range, fast response, sparse effective data output, and low power consumption. Simultaneously, compared to traditional event-triggered dynamic vision sensors, this invention significantly reduces the number of transistors in each unit of the photosensitive element array, allowing for a substantial reduction in unit size and chip cost; the fidelity of the signal converted from analog light intensity changes detected by each unit to digital output via an analog-to-digital converter is higher because it does not rely on matching the analog characteristics of the transistors within the unit, and the analog-to-digital converter around the array has a much larger area budget than the units to improve conversion accuracy; traditional analog-to-digital conversion data encoding combined with sparse data compression requires less data transmission bandwidth than event-triggered data encoding methods, saving data transmission energy and enabling the transmission of more effective data within a given bandwidth.

[0069] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0070] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0071] Figure 1 is a schematic diagram of the photosensitive element array structure for detecting time-related image data as described in Example 1;

[0072] Figure 2 is a schematic diagram of the photosensitive element array structure for detecting time-related image data as described in Example 2;

[0073] Figure 3 is a schematic diagram of the photosensitive element array structure for detecting time-related image data as described in Example 3;

[0074] Figure 4 is a schematic diagram of the photosensitive element array structure for detecting time-related image data as described in Example 4;

[0075] Figure 5 is a possible signal timing diagram of the photosensitive element array described in Example 5;

[0076] Figure 6 is another possible signal timing diagram of the photosensitive element array described in Example 6;

[0077] Figure 7 is a schematic diagram of the photosensitive element array and its peripheral readout circuit structure for detecting time-related image data as described in Example 7.

[0078] Figure 8 is a schematic diagram of the analog-to-digital converter structure that is sensitive to signal activity as described in Example 8;

[0079] Figure 9 is a first type of SAR logic flowchart of the analog-to-digital converter that can sense field of view activity as described in Example 8;

[0080] Figure 10 is a second SAR logic flowchart of the analog-to-digital converter that can sense field of view activity as described in Example 8;

[0081] Figure 11 is a third SAR logic flowchart of the analog-to-digital converter that can sense field of view activity as described in Example 8;

[0082] Figure 12 is a schematic diagram of the photosensitive element array and its peripheral readout circuit structure for detecting time-related image data as described in Example 9.

[0083] Figure 13 is a schematic diagram of the photosensitive element array and its peripheral readout circuit structure for detecting time-related image data as described in Example 10.

[0084] Figure 14 shows the threshold θ for perceived field of view activity. ADC The calculation flowchart;

[0085] Figure 15 is a flowchart of the process for adjusting the frame rate of a two-dimensional pixel array. Detailed Implementation

[0086] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0087] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0088] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0089] Example 1:

[0090] This embodiment provides a photosensitive element array for detecting time-related image data. The array consists of R rows × C columns of units, each unit including a photosensitive sensor with dynamic range compression characteristics, several voltage sampling and storage units, and a voltage readout circuit. The photosensitive sensor autonomously converts a high dynamic range incident light signal into a low dynamic range output voltage signal without any external control. In this embodiment, the dynamic range compression characteristic is presented as an approximately logarithmic input-output relationship, meaning the output voltage of the photosensitive sensor is approximately linearly related to the logarithm of the input light intensity.

[0091] Specifically, as shown in Figure 1, a unit consists of a pinned photodiode, an inverting amplifier, a transmission gate transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus The structure consists of: the anode of the pinned photodiode is grounded, and the cathode is connected to the source of the transmission gate transistor; the gate of the transmission gate transistor is connected to a high-level voltage V. high The drain of the first N-type transistor is connected to the source of the first N-type transistor and the input stage of the inverting amplifier; the drain of the first N-type transistor is connected to the power supply voltage, and its gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor; the drain of the second N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the third N-type transistor and the drain of the fifth N-type transistor; the gate of the third N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the fourth N-type transistor; the gate of the fourth N-type transistor is connected to the first bias voltage V. bias1 The source of the fifth N-type transistor is grounded; the gate of the fifth N-type transistor is connected to SH, and its source is connected to the upper plate of the first capacitor C1, the upper plate of the second capacitor C2, the drain of the eighth N-type transistor, and the gate of the ninth N-type transistor; the lower plate of the first capacitor C1 is connected to the drain of the sixth N-type transistor; the lower plate of the second capacitor C2 is connected to the drain of the seventh N-type transistor; and the gate of the sixth N-type transistor is connected to the second sampling control signal SH. s1 The source is connected to the reference voltage V. ref The gate of the seventh N-type transistor is connected to the third sampling control signal SH. s2 Source connected to V ref The gate of the eighth N-type transistor is connected to the reset signal RST, and the source is connected to V. ref The drain of the ninth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the tenth N-type transistor; the gate of the tenth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus The high level V of each unit high First bias voltage V bias1 Reference voltage V ref The first sampling control signal SH is common to all units, and the voltage bus V is read out. bus The second sampling control signal SH is shared by each column of cells. s1 Third sampling control signal SH s2 The reset signal RST and the read selection signal SEL are common to each row cell. By controlling signals SH and SH... s1 SH s2 The timing control of RST and SEL reads the voltages stored in C1 and C2 in the cell row by row into the column-parallel V. bus superior.

[0092] Example 2:

[0093] This embodiment provides a photosensitive element array for detecting time-related image data, as shown in Figure 2. Unlike the photosensitive element array in Embodiment 1, each unit consists of a photodiode, an inverting amplifier, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus The structure comprises: the anode of the photodiode is grounded, and the cathode is connected to the source of the first N-type transistor and the input stage of the inverting amplifier; the drain of the first N-type transistor is connected to the power supply voltage, and its gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor; the drain of the second N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the third N-type transistor and the drain of the fourth N-type transistor; the gate of the third N-type transistor is connected to the first bias voltage V. bias1 The source of the fourth N-type transistor is grounded; the gate of the fourth N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the fifth N-type transistor, the drain of the sixth N-type transistor, the drain of the seventh N-type transistor, and the gate of the eighth N-type transistor; the gate of the fifth N-type transistor is connected to the second sampling control signal SH. s1 The source of the sixth N-type transistor is connected to the upper plate of the first capacitor C1; the gate of the sixth N-type transistor is connected to the third sampling control signal SH. s2 The source of the seventh N-type transistor is connected to the upper plate of the second capacitor C2; the gate of the seventh N-type transistor is connected to the reset signal RST, and the source is connected to the reference voltage V. ref The lower plate of the first capacitor is grounded; the lower plate of the second capacitor is grounded; the drain of the eighth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the ninth N-type transistor; the gate of the ninth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus The high level V of each unit high First bias voltage V bias1 Reference voltage V ref The first sampling control signal SH is common to all units, and the voltage bus V is read out. bus The second sampling control signal SH is shared by each column of cells. s1 Third sampling control signal SH s2 The reset signal RST and the read selection signal SEL are common to each row cell. By controlling signals SH and SH... s1 SH s2 The timing control of RST and SEL reads the voltages stored in C1 and C2 in the cell row by row into the column-parallel V. bus superior.

[0094] Example 3:

[0095] This embodiment provides a photosensitive element array for detecting time-related image data, as shown in Figure 3. Unlike the photosensitive element array in Embodiment 1, each unit consists of a photodiode, an inverting amplifier, a first P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus The structure comprises: a photodiode with its anode grounded, a cathode connected to the source of a first P-type transistor and the input stage of an inverting amplifier; the drain of the first P-type transistor connected to the output stage of the inverting amplifier and the gate of a first N-type transistor, with the gate connected to a first bias voltage V. bias1 The drain of the first N-type transistor is connected to the power supply voltage, and its source is connected to the drains of the second and fourth N-type transistors; the gate of the second N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the third N-type transistor; the gate of the third N-type transistor is connected to the second bias voltage V. bias2 The source of the fourth N-type transistor is grounded; the gate of the fourth N-type transistor is connected to SH, and its source is connected to the upper plate of the first capacitor C1, the upper plate of the second capacitor C2, the drain of the seventh N-type transistor, and the gate of the eighth N-type transistor; the lower plate of the first capacitor C1 is connected to the drain of the fifth N-type transistor; the lower plate of the second capacitor C2 is connected to the drain of the sixth N-type transistor; and the gate of the fifth N-type transistor is connected to the second sampling control signal SH. s1 The source is connected to the reference voltage V. ref The gate of the sixth N-type transistor is connected to the third sampling control signal SH. s2 Source connected to V ref The gate of the seventh N-type transistor is connected to the reset signal RST, and the source is connected to V. ref The drain of the eighth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the ninth N-type transistor; the gate of the ninth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus The high level V of each unit high First bias voltage V bias1 Second bias voltage V bias2 Reference voltage V ref The first sampling control signal SH is common to all units, and the voltage bus V is read out. bus The second sampling control signal SH is shared by each column of cells. s1 Third sampling control signal SH s2 The reset signal RST and the read selection signal SEL are common to each row cell. By controlling signals SH and SH... s1 SHs2 The timing control of RST and SEL reads the voltages stored in C1 and C2 in the cell row by row into the column-parallel V. bus superior.

[0096] Example 4:

[0097] This embodiment provides a photosensitive element array for detecting time-related image data, as shown in Figure 4. Unlike the photosensitive element array in Embodiment 1, each unit consists of a photodiode, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a first capacitor C1, a second capacitor C2, and a column readout voltage bus V. bus The photodiode is composed of the following components: its anode is grounded, and its cathode is connected to the source of the first N-type transistor and the gate of the second N-type transistor; the drain of the first N-type transistor is connected to the power supply voltage, and its gate is connected to the first bias voltage V. bias1 The drain of the second N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the third and fourth N-type transistors; the gate of the third N-type transistor is connected to the second bias voltage V. bias2 The source of the fourth N-type transistor is grounded; the gate of the fourth N-type transistor is connected to the first sampling control signal SH, and its source is connected to the drain of the fifth N-type transistor, the drain of the sixth N-type transistor, the drain of the seventh N-type transistor, and the gate of the eighth N-type transistor; the gate of the fifth N-type transistor is connected to the second sampling control signal SH. s1 The source of the sixth N-type transistor is connected to the upper plate of the first capacitor C1; the gate of the sixth N-type transistor is connected to the third sampling control signal SH. s2 The source of the seventh N-type transistor is connected to the upper plate of the second capacitor C2; the gate of the seventh N-type transistor is connected to the reset signal RST, and the source is connected to the reference voltage V. ref The lower plate of the first capacitor is grounded; the lower plate of the second capacitor is grounded; the drain of the eighth N-type transistor is connected to the power supply voltage, and its source is connected to the drain of the ninth N-type transistor; the gate of the ninth N-type transistor is connected to the readout selection signal SEL, and its source is connected to the column readout voltage bus V. bus The high level V of each unit high First bias voltage V bias1 Second bias voltage V bias1 Reference voltage V ref The first sampling control signal SH is common to all units, and the voltage bus V is read out. bus The second sampling control signal SH is shared by each column of cells. s1 Third sampling control signal SH s2 The reset signal RST and the read selection signal SEL are common to each row cell. By controlling signals SH and SH... s1 SHs2 The timing control of RST and SEL reads the voltages stored in C1 and C2 in the cell row by row into the column-parallel V. bus superior.

[0098] Example 5:

[0099] As shown in Figure 5, this embodiment provides a possible timing control step for a photosensitive element array used to detect time-related image data as described in any of Embodiments 1-4:

[0100] At time t 0_0 At the start of the first signal sampling phase, SH changes from low to high, and the SH of all rows... s2 Also, from low to high, all rows of SH s1 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C2;

[0101] At time t 1_0 The first signal sampling phase ends and the first signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s2 Also, the values ​​of RST and SEL in the first row change from high to low;

[0102] At time t 2_0 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior;

[0103] At time t 3_0 The RST in the first line changes from low to high, and the SH in the first line... s2 From high to low;

[0104] At time t 4_0 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior;

[0105] At time t 5_0 SH in the first line s1 And SEL changes from high to low;

[0106] At time t 6_0 In the second row, RST and SEL change from low to high;

[0107] At time t 7_0 The RST in the second line changes from high to low, and the SH in the second line... s2 From low to high, the voltage stored on C2 in all cells of the second row is read out to the column-parallel V.bus superior;

[0108] At time t 8_0 The RST in the second line changes from low to high, and the SH in the second line... s2 From high to low;

[0109] At time t 9_0 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior;

[0110] At time t 10_0 SH in the second line s1 And SEL changes from high to low;

[0111] This process continues until the voltages stored in C2 and C1 in all rows of cells have been read; then, at time t... 0_1 At the start of the second signal sampling phase, SH changes from low to high, and the SH of all rows... s1 Also, from low to high, all rows of SH s2 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C1;

[0112] At time t 1_1 The second signal sampling phase ends and the second signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s1 Also, the values ​​of RST and SEL in the first row change from high to low;

[0113] At time t 2_1 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior;

[0114] At time t 3_1 The RST in the first line changes from low to high, and the SH in the first line... s1 From high to low;

[0115] At time t 4_1 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior;

[0116] At time t 5_1 SH in the first line s2 And SEL changes from high to low;

[0117] At time t6_1 In the second row, RST and SEL change from low to high;

[0118] At time t 7_1 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior;

[0119] At time t 8_1 The RST in the second line changes from low to high, and the SH in the second line... s1 From high to low;

[0120] At time t 9_1 The RST in the second line changes from high to low, and the SH in the second line... s2 From low to high, the voltage stored on C2 in all cells of the second row is read out to the column-parallel V. bus superior;

[0121] At time t 10_1 SH in the second line s2 And SEL changes from high to low;

[0122] This process continues until the voltages stored in C1 and C2 in all rows of cells are read; then, at time t... 0_2 Repeated at time t 0_0 The sequence of events continued until the photosensitive element array was manually stopped.

[0123] Example 6:

[0124] As shown in Figure 6, this embodiment provides another possible timing control step for the photosensitive element array used to detect time-related image data as described in any of Embodiments 1-4. The difference from the previous timing control step is that the top and bottom ends of the photosensitive element array are read out row by row simultaneously, instead of sequentially reading out row by row from the top to the bottom. This halves the array's readout time, at the cost of doubling the readout circuitry surrounding the array. In this architecture, V in each column... bus It also needs to be divided into two halves, that is, from the first row to the R / 2th row is V. bus_top From row R / 2+1 to row R, V bus_btm .

[0125] At time t 0_0 At the start of the first signal sampling phase, SH changes from low to high, and the SH of all rows... s2 Also, from low to high, all rows of SH s1 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C2;

[0126] At time t1_0 The first signal sampling phase ends and the first signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s2 Also, RST and SEL in the first and Rth rows change from high to low;

[0127] At time t 2_0 The RST values ​​in the first and Rth rows change from high to low, and the SH values ​​in the first and Rth rows change from high to low. s2 From low to high, the voltages stored on C2 in all cells of the first row and Rth row are read out to the column-parallel V. bus_top and V bus_btm superior;

[0128] At time t 3_0 The RST values ​​in the first and Rth rows change from low to high, and the SH values ​​in the first and Rth rows change from low to high. s2 From high to low;

[0129] At time t 4_0 The RST values ​​in the first and Rth rows change from high to low, and the SH values ​​in the first and Rth rows change from high to low. s1 From low to high, the voltages stored in C1 of all cells in the first and R rows are read out to the column-parallel V. bus_top and V bus_btm superior;

[0130] At time t 5_0 The first and R lines of SH s1 And SEL changes from high to low;

[0131] At time t 6_0 In the second and R-1 rows, RST and SEL change from low to high;

[0132] At time t 7_0 The RST values ​​in the second and R-1 rows change from high to low, and the SH values ​​in the second and R-1 rows change from high to low. s2 From low to high, the voltage stored on C2 in all cells of the second row and R-1 row is read out to the column-parallel V. bus_top and V bus_btm superior;

[0133] At time t 8_0 The RST values ​​in the second and R-1 rows change from low to high, and the SH values ​​in the second and R-1 rows change from low to high. s2 From high to low;

[0134] At time t 9_0 The RST values ​​in the second and R-1 rows change from high to low, and the SH values ​​in the second and R-1 rows change from high to low. s1 From low to high, the voltages stored in C1 of all cells in the second row and R-1 row are read out to the column-parallel V. bus_topand V bus_btm superior;

[0135] At time t 10_0 SH in the second and R-1 lines s1 And SEL changes from high to low;

[0136] This process continues until the voltages stored in C2 and C1 in all rows of cells have been read; then, at time t... 0_1 At the start of the second signal sampling phase, SH changes from low to high, and the SH of all rows... s1 Also, from low to high, all rows of SH s2 RST and SEL remain low, and the photoelectric conversion signals in all units are sampled onto C1;

[0137] At time t 1_1 The second signal sampling phase ends and the second signal readout phase begins. SH changes from high to low, and the SH values ​​of all rows change accordingly. s1 Also, RST and SEL in the first and Rth rows change from high to low;

[0138] At time t 2_1 The RST values ​​in the first and Rth rows change from high to low, and the SH values ​​in the first and Rth rows change from high to low. s1 From low to high, the voltages stored in C1 of all cells in the first and R rows are read out to the column-parallel V. bus_top and V bus_btm superior;

[0139] At time t 3_1 The RST values ​​in the first and Rth rows change from low to high, and the SH values ​​in the first and Rth rows change from low to high. s1 From high to low;

[0140] At time t 4_1 The RST values ​​in the first and Rth rows change from high to low, and the SH values ​​in the first and Rth rows change from high to low. s2 From low to high, the voltages stored on C2 in all cells of the first row and Rth row are read out to the column-parallel V. bus_top and V bus_btm superior;

[0141] At time t 5_1 The first and R lines of SH s2 And SEL changes from high to low;

[0142] At time t 6_1 In the second and R-1 rows, RST and SEL change from low to high;

[0143] At time t 7_1 The RST values ​​in the second and R-1 rows change from high to low, and the SH values ​​in the second and R-1 rows change from high to low. s1From low to high, the voltages stored in C1 of all cells in the second row and R-1 row are read out to the column-parallel V. bus_top and V bus_btm superior;

[0144] At time t 8_1 The RST values ​​in the second and R-1 rows change from low to high, and the SH values ​​in the second and R-1 rows change from low to high. s1 From high to low;

[0145] At time t 9_1 The RST values ​​in the second and R-1 rows change from high to low, and the SH values ​​in the second and R-1 rows change from high to low. s2 From low to high, the voltage stored on C2 in all cells of the second row and R-1 row is read out to the column-parallel V. bus_top and V bus_btm superior;

[0146] At time t 10_1 SH in the second and R-1 lines s2 And SEL changes from high to low;

[0147] This process continues until the voltages stored in C1 and C2 in all rows of cells are read; then, at time t... 0_2 Repeated at time t 0_0 The sequence of events continued until the photosensitive element array was manually stopped.

[0148] Example 7:

[0149] This embodiment provides a peripheral readout circuit connected to any of the photosensitive element arrays described in embodiments 1-4, as shown in Figure 7. This peripheral readout circuit includes a row scanning and timing control module, amplifiers, and an analog-to-digital converter capable of sensing field-of-view activity. The row scanning and timing control module provides the row readout signal timing to the photosensitive element array; the number of amplifiers is the same as the number of columns in the photosensitive element array, and the input of each amplifier is connected to the readout voltage bus V of each column of units. bus The connection is such that each amplifier has two input ports, each receiving V. bus The two signal voltage values ​​stored in a unit are read sequentially, and the differential output is the difference between the two signal voltage values ​​after amplification; the number of analog-to-digital converters that can sense the field of view activity is the same as the number of amplifiers, used to convert the analog signals output by each amplifier into digital signals. ADC Furthermore, these analog-to-digital converters can adjust the number of effective conversion cycles in each conversion based on the amplitude of the visual signal perceived by the cells in the corresponding column.

[0150] Example 8:

[0151] The analog-to-digital converter structure capable of sensing the field of view activity provided in Embodiment 7 is shown in FIG. 8 and includes a digital-to-analog converter DAC, a differential DAC, a comparator, a successive approximation register (SAR) logic, and several switches; the SAR logic is the SAR logic capable of sensing the field of view activity, and the threshold θ of the field of view activity sensing ADC As a parameter of the SAR logic, it can be built-in or an externally input parameter.

[0152] Optionally, as shown in FIG. 9, the SAR operation logic of the analog-to-digital converter capable of sensing the field of view activity provided in this embodiment is as follows: The differential output of the amplifier is directly compared in size by the comparator to obtain the value D OUT [i] of the highest bit, the i-th bit, of the analog-to-digital converter output; the analog-to-digital converter samples the differential output of the amplifier, and the outputs of the i-1-th bit to the 0-th bit of the analog-to-digital converter D OUT [i-1:0] are cleared; according to the threshold parameter θ of the field of view activity sensing built in or externally input by the SAR logic ADC , the k-th bit of the DAC and the differential DAC is flipped under the control of the SAR logic, 0 ≤ k < i; according to the output result of the comparator, it is judged whether the absolute value of the difference between the DAC output and the differential DAC output before the k-th bit is flipped is greater than or equal to 2 k ×V LSB , where V LSB is the voltage value corresponding to the lowest bit, the 0-th bit, of the analog-to-digital converter output. If not, the output of the current k-th bit of the analog-to-digital converter is retained, and then the SAR logic controls the analog-to-digital converter to convert from the k-1-th bit to the 0-th bit, and the output values of the i-1-th bit to the k+1-th bit remain 0; if so, the SAR logic controls the analog-to-digital converter to convert from the i-1-th bit to the 0-th bit.

[0153] Optionally, as shown in FIG. 10, the SAR operation logic of another analog-to-digital converter capable of sensing the field of view activity provided in this embodiment is as follows: The differential output of the amplifier is directly compared in size by the comparator to obtain the value D OUT [i] of the highest bit, the i-th bit, of the analog-to-digital converter output; the analog-to-digital converter samples the differential output of the amplifier, and the outputs of the i-1-th bit to the 0-th bit of the analog-to-digital converter are cleared; according to the threshold parameter θ of the field of view activity sensing built in or externally input by the SAR logic ADC , the k-th bit of the DAC and the differential DAC is flipped under the control of the SAR logic, 0 ≤ k < i; according to the output result of the comparator, it is judged whether the absolute value of the difference between the DAC output and the differential DAC output before the k-th bit is flipped is greater than or equal to 2 k ×V LSB , where V LSBis the voltage value corresponding to the least significant bit of the output of the analog-to-digital converter; if not, retain the output of the current k-th bit of the analog-to-digital converter, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the 0-th bit, while the output values of the (i - 1)-th bit to the (k + 1)-th bit remain 0; if so, further determine whether k is equal to i - 1; if equal, retain the output of the current k-th bit of the analog-to-digital converter, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the 0-th bit; if not equal, that is, k < i - 1, then the k-th bit of the DAC and differential DAC is restored under the control of the SAR logic, then let k = k + 1, the k-th bit of the DAC and differential DAC is flipped under the control of the SAR logic, and then loop back to the previous step of judging whether the absolute value of the difference between the DAC output and the differential DAC output before the k-th bit flip is greater than or equal to 2 k ×V LSB step

[0154] Optionally, as shown in FIG. 11, the SAR operation logic of the third analog-to-digital converter capable of sensing the field of view activity degree provided in this embodiment is as follows: the differential output of the amplifier is directly compared by a comparator to obtain the value D OUT [i] of the highest significant bit, the i-th bit, of the output of the analog-to-digital converter; the analog-to-digital converter samples the differential output of the amplifier, and the outputs of the (i - 1)-th bit to the 0-th bit of the analog-to-digital converter are cleared; according to the threshold parameter θ ADC for sensing the field of view activity degree built into the SAR logic or externally input, the k-th bit of the DAC and differential DAC is flipped under the control of the SAR logic, 0 ≤ k < i; according to the output result of the comparator, judge whether the absolute value of the difference between the DAC output and the differential DAC output before the k-th bit flip is greater than or equal to 2 k ×V LSB where V LSB is the voltage value corresponding to the least significant bit of the output of the analog-to-digital converter; if not, retain the output of the current k-th bit of the analog-to-digital converter, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the (0)-th bit; if so, further determine whether k is equal to i - 1; if equal, retain the output of the current k-th bit of the analog-to-digital converter, and then the SAR logic controls the analog-to-digital converter to convert from the (k - 1)-th bit to the (0)-th bit; if not equal, that is, k < i - 1, then further determine whether k is greater than or equal to a set threshold k th ; if greater than or equal to, the SAR logic controls the analog-to-digital converter to convert from the (i - 1)-th bit to the 0-th bit; if less than, the k-th bit of the DAC and differential DAC is restored under the control of the SAR logic, k = k + 1, the k-th bit of the DAC and differential DAC is flipped under the control of the SAR logic, and then loop back to the previous step of judging whether the absolute value of the difference between the DAC output and the differential DAC output before the k-th bit flip is greater than or equal to 2 k ×V LSBThe steps.

[0155] In this embodiment, the field of view activity of the visual sensor is quantified based on the statistical characteristics of the digital signal output of the analog-to-digital converter; in particular, the statistical characteristics focus on whether the digital signal output of the analog-to-digital converter corresponding to each pixel is 0.

[0156] Optionally, the specific structure of the analog-to-digital converter capable of sensing field-of-view activity can be such that the capacitor base plates of the DAC and the differential DAC are respectively connected to a positive reference voltage V via switching switches. ref+ Negative reference voltage V ref- Or common-mode voltage V CM The switching switch corresponding to the DAC is controlled by the control signal D at the output of the SAR logic control terminal. SAR+ [i-1:0] control, the switching switch corresponding to the differential DAC is controlled by the differential control signal D at the output of the SAR logic differential control terminal. SAR- [i-1:0] control, the DAC's capacitor base is connected to the amplifier's output terminal V via a sampling switch. Ao+ The differential DAC's capacitor baseplate is connected to the amplifier's differential output terminal V via a differential sampling switch. Ao- ; The top plate of the DAC capacitor V DAC+ Connected to the positive terminal of the comparator, and selected to be connected to V via a reset switch. Ao+ Or V CM The differential DAC's top capacitor V DAC- Connected to the negative terminal of the comparator, and selected to be connected to V via a differential reset switch. Ao- Or V CM The comparator's output is connected to the first input of the SAR logic, and the comparator's clock input is connected to the gated clock output of the SAR logic. The second input of the SAR logic is the threshold θ for the perceived field of view activity. ADC The output of the SAR logic provides the final digital output D of the analog-to-digital converter. OUT [i:0].

[0157] In actual operation, the aforementioned analog-to-digital converter (ADC) structure involves the DAC's top and bottom capacitor plates interacting with V. Ao+ The differential DAC's top and bottom capacitor plates are connected to V. Ao- The circuit is connected, the comparator performs the comparison, and the SAR logic obtains the highest bit output D based on the comparator result. OUT [i]; The capacitor top plate of the DAC and the capacitor top plate of the differential DAC are respectively connected to V Ao+ and V Ao- Disconnect, and together with V CM Connected; the capacitor top plates of both the DAC and the differential DAC are connected to V. CM Disconnect; the capacitor base plates of the DAC and the differential DAC are respectively connected to V.Ao+ and V Ao- are disconnected and are connected together with V CM ; The outputs D OUT [i - 1:0] of the i - 1st to 0th bits of the SAR logic are cleared; If θ ADC = k, the SAR logic controls the analog - to - digital converter to start conversion from the kth bit accordingly, 0 ≤ k < i, and the kth - bit capacitor bottom plates of the DAC and the differential DAC are respectively connected to V ref+ and V ref- ; After being connected, the comparator compares the stable values of V DAC+ and V DAC- ; If the output result of the comparator is the same as the result when comparing the ith bit, then D OUT [k] is retained, and then the values of D OUT [k - 1:0] are obtained by converting from the (k - 1)th bit to the 0th bit; If the output result of the comparator is opposite to the result when comparing the ith bit, then it is further determined whether k is equal to i - 1; If so, D OUT [k] is retained, and then the values of D OUT [k - 1:0] are obtained by converting from the (k - 1)th bit to the 0th bit; If not, it is further determined whether k is greater than or equal to a set threshold k th ; If it is greater than or equal to, the values of D OUT [i - 1:0] are obtained by converting from the (i - 1)th bit to the 0th bit; If it is less than, the kth bit of the DAC and the differential DAC is restored under the control of the SAR logic, k = k + 1, the kth bit of the DAC and the differential DAC is flipped under the control of the SAR logic, and it loops back to the step of the previous comparator comparing the stable values of V DAC+ and V DAC- .

[0158] Example 9:

[0159] This example provides a peripheral read - out circuit connected to the photosensitive element array described in any one of Examples 1 - 4. As shown in Figure 12, the difference from Example 7 is that the peripheral read - out circuit further includes a top - layer control unit, and the control signals output by it control the row - scanning and timing control module, C amplifiers, and C analog - to - digital converters for perceiving activity, to adjust the frame rate r FPS of the photosensitive element array, the gain g VGA of the amplifier, and the field - of - view activity perception threshold θ ADC .

[0160] Example 10:

[0161] This embodiment provides a peripheral readout circuit connected to any of the photosensitive element arrays described in Embodiments 1-4, as shown in Figure 13. The difference from Embodiment 7 is that the peripheral readout circuit further includes a digital signal processor (DSP), whose inputs are connected to the outputs of C activity-sensing analog-to-digital converters (ADCs). ADC and for O ADC The sparsity is statistically analyzed; the top-level control unit is based on O ADC Sparsity statistics S O Set θ ADC The digital signal processor is also used for O ADC After compression, it becomes the final output O of the sensor. sensor Specifically, through O ADC Sparsity statistics S O The detection and analysis revealed that if O ADC If the proportion of data with a value of 0 remains above a set threshold for a period of time, the control unit reduces the frame rate to decrease the O value. ADC The proportion of data with a value of 0 in the middle reduces the overall power consumption of the sensor. Meanwhile, the control unit, based on S... O To set θ ADC This can also achieve the goal of saving power consumption of the analog-to-digital converter. In this embodiment, the control unit and the digital signal processor have an external control parameter port P. program It can be used to select different sparsity detection algorithms, different data compression algorithms, key parameters involved in these algorithms, and the perceptual field of view activity threshold θ that have been implemented in digital signal processing units. ADC and frame rate r FPS Adjustment algorithms, etc.

[0162] Digital signal processor for O ADC The method for statistically analyzing sparsity is as follows: determine the number of O values ​​within a set range of values ​​over a given time window. ADC The number of data points accounts for a percentage of the total O ADC What are the proportions of the data points? In this embodiment, as shown in Figure 14, the distribution E of the conversion energy consumption required by the analog-to-digital converter at different bit widths is obtained through simulation or actual measurement. ADC The bit width, starting from bit 0, is at least 1 bit and at most i-1 bits; the output O of the analog-to-digital converter that can sense field of view activity in column C. ADC The absolute values ​​of O are distributed statistically, and the method is as follows: ADC The range of values ​​is divided into 0, 1, 2~3, 4~7, ..., 2 k-1 ~2 k -1, k≤i-1, O ADCIf the absolute value of a value in the range appears once, the count for that range is incremented by one; the count is expressed in terms of T. ADC For the time window, S ADC The distribution DIS is obtained by taking a moving average over a time step. ADC According to distribution E ADC DIS ADC The pre-field-of-view activity sensing threshold θ, which minimizes the average analog-to-digital converter power consumption, was calculated using an optimized SAR algorithm for sensing field-of-view activity. pre ; with T θ For the time window, S θ Find θ for the time step pre The moving average yields the distribution θ μpre If k-1 < θ μpre If ≤k, then set θ ADC =k. Where the time window T ADC T θ Time step S ADC S θ It is set and configurable by humans.

[0163] Optionally, the frame rate of the two-dimensional pixel array can also be adjusted according to the field of view activity of the visual sensor, as shown in Figure 15, by adjusting the O... ADC The absolute values ​​of the values ​​in the range are 0, 1, 2~3, 4~7, ..., 2 k-1 ~2 k -1,2 i-1 -1, k≤i-1, O ADC If the absolute value of a value in the range appears once, the count for that range is incremented by one; the count is expressed in terms of T. ADC For the time window, S ADC The distribution DIS is obtained by taking a moving average over a time step. ADC ; Request DIS ADC They tend to be distributed in 0 and 2 respectively. i-1 The weighted averages p1 and p2 on -1, with T FR For time window, S FR Calculate the moving average for the time step to obtain p. μ1 p μ2 If p μ1 Greater than or equal to the set upper limit threshold p th1U , and p μ2 Less than or equal to the set lower threshold p th2L If the frame rate is greater than the minimum value, then let the frame rate r FPS Decrease Δ FRD If p μ1 Less than or equal to the set lower threshold p th1L , or p μ2Greater than or equal to the set upper limit threshold p th2U If the frame rate is less than the maximum value, then let the frame rate r FPS Increase Δ FRU Frame rate changes in T FRS The time step is defined as the interval after each frame rate change, at least within time T. FRS It remains unchanged within the time window T. FR Time step S FR Frame rate decrement Δ FRD Frame rate increment Δ FRU Furthermore, all upper and lower thresholds are set manually based on data simulation or measurement experiments.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An array of photosensitive elements for detecting time-dependent image data, characterized by: consists of R rows and C columns of cells, each cell comprising: a light sensor with dynamic range compression feature, which converts incident light signal of high dynamic range into output voltage signal of low dynamic range autonomously without any external control; a number of voltage sampling storage units, the stored voltage is obtained by sampling the output voltage signal of the light sensor at different time points; a voltage readout circuit, which reads out the voltage in the voltage sampling storage units to the periphery of the cell array simultaneously or time-divisionally.

2. The photosensitive element array for detecting time-dependent image data according to claim 1, characterized by: The dynamic range compression feature of the light sensor presents an input-output relationship in approximate logarithm, i.e. the output voltage of the light sensor and the logarithm of the input light intensity present an approximate linear relationship.

3. The photosensitive element array for detecting time-dependent image data according to claim 2, characterized by: The unit comprises a pinned photodiode, an inverting amplifier, a transfer electrode gate transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, a first capacitor C1, a second capacitor C2, a column readout voltage bus V bus wherein: The anode of the pinning photodiode is grounded, and the cathode is connected to the source of the transfer gate transistor; the gate of the transfer gate transistor is connected to a high level V high , and the drain is connected to the source of the first N-type transistor and the input stage of the inverting amplifier; the drain of the first N-type transistor is connected to a power supply voltage, and the gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor; the drain of the second N-type transistor is connected to a power supply voltage, and the source is connected to the drain of the third N-type transistor and the drain of the fifth N-type transistor; the gate of the third N-type transistor is connected to a first sampling control signal SH, and the source is connected to the drain of the fourth N-type transistor; the gate of the fourth N-type transistor is connected to a first bias voltage V bias1 , and the source is grounded; the gate of the fifth N-type transistor is connected to SH, and the source is connected to the upper plate of a first capacitor C1, the upper plate of a second capacitor C2, the drain of an eighth N-type transistor, and the gate of a ninth N-type transistor; the lower plate of the first capacitor C1 is connected to the drain of a sixth N-type transistor; the lower plate of the second capacitor C2 is connected to the drain of a seventh N-type transistor; the gate of the sixth N-type transistor is connected to a second sampling control signal SH s1 , and the source is connected to a reference voltage V ref ; the gate of the seventh N-type transistor is connected to a third sampling control signal SH s2 , and the source is connected to V ref ; the gate of the eighth N-type transistor is connected to a reset signal RST, and the source is connected to V ref ; the drain of the ninth N-type transistor is connected to a power supply voltage, and the source is connected to the drain of a tenth N-type transistor; the gate of the tenth N-type transistor is connected to a readout selection signal SEL, and the source is connected to a column readout voltage bus V bus .

4. The photosensitive element array for detecting time-dependent image data according to claim 2, characterized by: The unit comprises a photodiode, an inverting amplifier, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a first capacitor C1, a second capacitor C2, a column readout voltage bus V bus wherein: The anode of the photodiode is connected to ground, the cathode is connected to the source of the first N-type transistor and the input stage of the inverting amplifier; the drain of the first N-type transistor is connected to the power supply voltage, the gate is connected to the output stage of the inverting amplifier and the gate of the second N-type transistor; the drain of the second N-type transistor is connected to the power supply voltage, the source is connected to the drain of the third N-type transistor and the drain of the fourth N-type transistor; the gate of the third N-type transistor is connected to the first bias voltage V bias1 , the source is connected to ground; the gate of the fourth N-type transistor is connected to the first sampling control signal SH, the source is connected to the drain of the fifth N-type transistor, the drain of the sixth N-type transistor, the drain of the seventh N-type transistor and the gate of the eighth N-type transistor; the gate of the fifth N-type transistor is connected to the second sampling control signal SH s1 , the source is connected to the upper plate of the first capacitor C1; the gate of the sixth N-type transistor is connected to the third sampling control signal SH s2 , the source is connected to the upper plate of the second capacitor C2; the gate of the seventh N-type transistor is connected to the reset signal RST, the source is connected to the reference voltage V ref ; the lower plate of the first capacitor is connected to ground; the lower plate of the second capacitor is connected to ground; the drain of the eighth N-type transistor is connected to the power supply voltage, the source is connected to the drain of the ninth N-type transistor; the gate of the ninth N-type transistor is connected to the readout selection signal SEL, the source is connected to the column readout voltage bus V bus .

5. The photosensitive element array for detecting time-dependent image data according to claim 3, wherein: high level V high , first bias voltage V bias1 , reference voltage V ref , first sampling control signal SH is common to all cells, readout voltage bus V bus is common to each column of cells, second sampling control signal SH s1 , third sampling control signal SH s2 , reset signal RST, readout selection signal SEL is common to each row of cells.

6. The photosensitive element array for detecting time-dependent image data according to claim 5, characterized by: The voltages stored in C1 and C2 in the unit are read out row by row to the column-parallel V bus by the timing control of the signals SH, SH s1 , SH s2 , RST, and SEL.

7. The photosensitive element array for detecting time-dependent image data of claim 6, wherein: The timing control steps are as follows: At time t 0_0 , the first signal sampling phase begins, SH goes from low to high, SH s2 of all rows also goes from low to high, SH s1 , RST, and SEL remain low, and the photoelectrically converted signal in all cells is sampled onto C2. At time t 1_0 , the first signal sampling phase ends, the first signal readout phase begins, SH goes from high to low, SH of all rows s2 also goes from high to low, RST and SEL of the first row go from low to high; At time t 2_0 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior; at time t 3_0 , the RST of the first row changes from low to high, and the SH s2 of the first row changes from high to low; At time t 4_0 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior; At time t 5_0 , the SH s1 and SEL of the first row go from high to low; At time t 6_0 RST and SEL of the second row go from low to high; At time t 7_0 , the RST of the second row goes from high to low, the SH of the second row goes from low to high, and the voltage stored on C2 in all cells of the second row is read out to the column parallel V s2 ; and bus , the voltage stored on C2 in all cells of the second row is read out to the column parallel V At time t 8_0 , the RST of the second row changes from low to high, and the SH s2 of the second row changes from high to low; At time t 9_0 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior; At time t 10_0 , the SH s1 of the second row goes from high to low; and so on until all the cells in a row have their stored voltages read out on C2 and C1; then, at time t 0_1 , the second signal sampling phase begins, SH goes from low to high, SH s1 of all rows also goes from low to high, SH s2 , RST, SEL remain low, and the photoelectrically converted signal in all the cells is sampled on C1; At time t 1_1 , the second signal sampling phase ends, the second signal readout phase begins, SH goes from high to low, SH of all rows s1 also goes from high to low, RST and SEL of the first row go from low to high; At time t 2_1 The RST in the first line changes from high to low, and the SH in the first line... s1 From low to high, the voltage stored in C1 of all cells in the first row is read out to the column-parallel V. bus superior; at time t 3_1 , the RST of the first row changes from low to high, and the SH s1 of the first row changes from high to low; At time t 4_1 The RST in the first line changes from high to low, and the SH in the first line... s2 From low to high, the voltage stored on C2 in all cells of the first row is read out to the column-parallel V. bus superior; At time t 5_1 , the SH s2 and SEL of the first row go from high to low; At time t 6_1 RST and SEL of the second row go from low to high; At time t 7_1 The RST in the second line changes from high to low, and the SH in the second line... s1 From low to high, the voltage stored in C1 of all cells in the second row is read out to the column-parallel V. bus superior; At time t 8_1 , the RST of the second row changes from low to high, and the SH s1 of the second row changes from high to low; At time t 9_1 The RST in the second line changes from high to low, and the SH in the second line... s2 From low to high, the voltage stored on C2 in all cells of the second row is read out to the column-parallel V. bus superior; At time t 10_1 , the SH s2 of the second row goes from high to low; And so on, until all the cells have been read row by row, storing the voltages on C1 and C2; then, at time t 0_2 , the timing is repeated from time t 0_0 , until the array is manually stopped.

8. A peripheral sense circuit for an array of photosensitive elements, characterized by: comprising a row scanning and timing control module, C amplifiers and C analog-digital converters capable of sensing field of view activity; the row scanning and timing control module is used to control the signal sampling and signal readout of the light sensitive element array as claimed in any one of claims 1-7; The C amplifiers are used to amplify C columns of V bus The difference between the signals stored in C1 and C2 is amplified; the amplifier has two input ports, which respectively receive V bus The difference between the signals stored in C1 and C2 is amplified; the amplifier has two input ports, which respectively receive V the C analog-digital converters capable of sensing field of view activity respectively convert the analog signals output by the C amplifiers into digital signals; the analog-digital converters adjust the number of effective conversion periods in each conversion according to the amplitude of the visual signal sensed by the cells in the corresponding column.

9. The peripheral sense circuit for an array of photosensitive elements of claim 8, wherein: The analog-digital converter capable of sensing field of view activity comprises the following modules: digital-analog converter DAC, differential DAC, comparator, SAR logic and a number of switches; the SAR logic is the SAR logic capable of sensing field of view activity, and the threshold value of the field of view activity is built-in or an externally input parameter.

10. The peripheral sense circuit for an array of photosensitive elements of claim 9, wherein: In the analog-digital converter capable of sensing field of view activity, the differential output of the amplifier is directly compared by the comparator to obtain the value of the highest i-th bit of the output of the analog-digital converter; The analog-to-digital converter samples the differential output of the amplifier and the i-1th to 0th bit output of the analog-to-digital converter is cleared; according to the threshold parameter of the perceived field of view activity built-in or externally input by the SAR logic, the kth bit of the DAC and the differential DAC is controlled to flip by the SAR logic, 0≤k k ×V LSB , wherein V LSB is the voltage value corresponding to the lowest bit output by the analog-to-digital converter; if not, the output of the current kth bit of the analog-to-digital converter is retained, and then the SAR logic controls the analog-to-digital converter to convert from the k-1th bit to the 0th bit; if yes, it is further judged whether k is equal to i-1; if equal, the output of the current kth bit of the analog-to-digital converter is retained, and then the SAR logic controls the analog-to-digital converter to convert from the k-1th bit to the 0th bit; if not equal, i.e., k th ; if greater than or equal to, the SAR logic controls the analog-to-digital converter to convert from the i-1th bit to the 0th bit; if less than, the kth bit of the DAC and the differential DAC is controlled to restore by the SAR logic, k=k+1, the kth bit of the DAC and the differential DAC is controlled to flip by the SAR logic, and then the step of judging whether the absolute value of the difference between the DAC output and the differential DAC output before the kth bit flips is greater than or equal to 2 according to the output result of the comparator is repeated k ×V LSB .

11. The peripheral sense circuit for an array of photosensitive elements of claim 9, wherein: In the analog-to-digital converter (ADC) capable of sensing field-of-view activity, the capacitor base plates of the DAC and the differential DAC are respectively connected to a positive reference voltage V via switching. ref+ Negative reference voltage V ref- Or common-mode voltage V CM The switching switch corresponding to the DAC is controlled by the control signal D at the output of the SAR logic control terminal. SAR+ [i-1:0] control, the switching switch corresponding to the differential DAC is controlled by the differential control signal D at the output of the SAR logic differential control terminal. SAR- [i-1:0] control, the DAC's capacitor base is connected to the amplifier's output terminal V via a sampling switch. Ao+ The differential DAC's capacitor baseplate is connected to the amplifier's differential output terminal V via a differential sampling switch. Ao- ; The capacitor top plate V of the DAC DAC+ Connected to the positive terminal of the comparator, and selected to be connected to V via a reset switch. Ao+ Or V CM The differential DAC's top capacitor V DAC- Connected to the negative terminal of the comparator, and selected to be connected to V via a differential reset switch. Ao- Or V CM The comparator's output is connected to the first input of the SAR logic, and the comparator's clock input is connected to the gated clock output of the SAR logic. The second input of the SAR logic is the threshold θ for the perceived field of view activity. ADC The output of the SAR logic provides the final digital output D of the analog-to-digital converter. OUT [i:0].

12. The peripheral sense circuit for an array of photosensitive elements of claim 11, wherein: In the analog-digital converter capable of sensing field of view activity, The capacitor top plate and the capacitor bottom plate of the DAC are connected to V Ao+ The capacitor top plate and the capacitor bottom plate of the differential DAC are connected to V Ao- The comparator compares, and the SAR logic gets the output D of the most significant bit according to the result of the comparator OUT [i]; The capacitive top plate of the DAC and the capacitive top plate of the differential DAC are respectively connected to V Ao+ and V Ao- are disconnected and together connected to V CM . The capacitive top plates of both the DAC and the differential DAC are connected to V CM off; The capacitive backplane of the DAC and the capacitive backplane of the differential DAC are respectively connected to V Ao+ and V Ao- are disconnected and together connected to V CM . Output D of the i-1th bit to the 0th bit of the SAR logic OUT [i-1:0] clear; If θ ADC = k, the SAR logic controls the analog-to-digital converter to convert from the kth bit, 0≤ k < i, the capacitive bottom plate of the DAC and the differential DAC are connected to V ref+ and V ref- respectively, and the comparator compares the values of V DAC+ and V DAC- after they are stabilized. If the comparator output is the same as the result of comparing the ith bit, then keep D OUT [k], and then convert from the k-1th bit to the 0th bit to get D OUT the value of [k-1:0] If the comparator output is opposite to the result of comparing the ith bit, further determine whether k is equal to i-1; if yes, keep D OUT [k], and then convert from the (k-1)th bit to the 0th bit to obtain D OUT ; if not, further determine whether k is greater than or equal to a set threshold k th ; if yes, convert from the (i-1)th bit to the 0th bit to obtain D OUT ; if less than, the kth bit of the DAC and the differential DAC is reset under the control of the SAR logic, then let k=k+1, the kth bit of the DAC and the differential DAC is flipped under the control of the SAR logic, and the cycle is repeated until the comparator compares V DAC+ and V DAC- stabilized value.

13. The peripheral readout circuit of the photosensitive element array as described in claim 8, characterized in that: A top-level control unit is also included, whose output control signals control the row scanning and timing control module, the C amplifiers, and the C analog-to-digital converters for activity sensing, and adjust the frame rate of the photosensitive element array, the gain of the amplifiers, the threshold value θ of the sensing field of view activity of the analog-to-digital converters, and the resolution of the analog-to-digital converters. ADC , and the resolution of the analog-to-digital converters.

14. The peripheral sense circuit for an array of photosensitive elements of claim 13, wherein: Also included is a digital signal processor; an input of the digital signal processor is connected to an output O of the C analog-to-digital converters that sense the activity of the C perceptual fields of view ADC and the sparsity of O ADC is counted The top layer control unit sets θ according to the sparsity statistical result of O ADC ; the digital signal processor is further used for compressing O ADC and outputting the compressed O ADC as the final output of the sensor.

15. The peripheral sense circuit for an array of photosensitive elements of claim 14, wherein: The digital signal processor counts the sparsity of O ADC The top control unit sets θ ADC according to the sparsity counting result of O ADC The specific steps are as follows: The distribution E of the conversion energy required by the analog-to-digital converter at different bit widths is obtained through simulation or actual measurement ADC wherein the bit width is from the 0th bit, and is at least 1 bit and at most i-1 bits. The output O of the analog-to-digital converter that can sense field of view activity in column C ADC The absolute values ​​of O are distributed statistically, and the method is as follows: ADC The range of values ​​is divided into 0, 1, 2~3, 4~7, ..., 2 k-1 ~2 k -1, k≤i-1, O ADC If the absolute value of a value in the range appears once, the count for that range is incremented by one; the count is expressed in terms of T. ADC For the time window, S ADC The distribution DIS is obtained by taking a moving average over a time step. ADC ; According to the distribution E ADC , DIS ADC and the SAR algorithm optimizes the perceived threshold of the pre-FOV activity θ that minimizes the average ADC energy consumption pre ; T θ is a time window, S θ is a time step, and the moving average of θ pre is a distribution θ μpre ; if k - 1 < θ μpre ≤ k, then set θ ADC = k.

16. The peripheral sense circuit for an array of photosensitive elements of claim 14, wherein: The top-level control unit also adjusts the frame rate r of the two-dimensional pixel array as a function of the field activity FPS adjusting, in particular comprising: The absolute value of the value in O ADC is divided into the ranges 0, 1, 2-3, 4-7,..., 2 k-1 -2 k -1, 2 i-1 -1, k≤i-1, O ADC The absolute value of the value in O ADC appears in a certain range once, then the statistical number of this range is incremented by one; the statistics is moving average with T ADC as the time window and S ADC as the time step to obtain the distribution DIS DIS ADC respectively, are distributed on 0 and 2 i-1 -1 with weighted average p1, p2, respectively, moving average over time window T FR and time step S FR gives p μ1 , p μ2 ; If p μ1 Greater than or equal to the set upper limit threshold p th1U , and p μ2 Less than or equal to the set lower threshold p th2L If the frame rate is greater than the minimum value, then let the frame rate r FPS Decrease Δ FRD If p μ1 Less than or equal to the set lower threshold p th1L , or p μ2 Greater than or equal to the set upper limit threshold p th2U If the frame rate is less than the maximum value, then let the frame rate r FPS Increase Δ FRU Frame rate changes in T FRS The time step is defined as the interval after each frame rate change, at least within time T. FRS It remains unchanged within.

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