Solar cell and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductor devices, and provides a solar cell and a manufacturing method therefor. The solar cell comprises a silicon substrate, a semiconductor layer, and a transparent conductive layer, wherein the semiconductor layer is formed on the silicon substrate, and the semiconductor layer has a porous structure; and the transparent conductive layer is located on the surface of the semiconductor layer distant from the silicon substrate and is in contact with the porous structure. The semiconductor layer of the present application has a porous structure, which can increase the contact area between the semiconductor layer and the transparent conductive layer, thereby optimizing current transmission characteristics, reducing energy consumption during current collection, and improving the battery efficiency.

Description

Solar cells and their manufacturing methods

[0001] This application claims priority to Chinese application No. 202410961507.7, filed on July 16, 2024, entitled "Solar Cell and Method of Manufacturing Thereof", and Chinese patent application No. 202411231916.8, filed on September 3, 2024, entitled "Solar Cell and Method of Manufacturing Thereof". Technical Field

[0002] This application relates to the field of semiconductor device technology, and more specifically, to a solar cell and a method for manufacturing the same. Background Technology

[0003] Heterojunction solar cells have advantages such as high conversion efficiency and simple fabrication structure. Conventional heterojunction solar cells are prepared by depositing intrinsic amorphous silicon layers on both sides of a silicon substrate, followed by depositing doped amorphous silicon films with different doping types, then fabricating a transparent conductive film on the doped amorphous silicon film, and finally metallizing the surface of the transparent conductive film to obtain a metal electrode.

[0004] Current transport resistance has a significant impact on the performance of heterojunction solar cells. To reduce current transport resistance and improve cell output performance, the contact structure between the metal electrode and the transparent conductive film can be improved. For example, a seed layer can be formed on the surface of the metal electrode and the transparent conductive film to improve adhesion, or novel materials such as alloys can be used as the metal electrode material. However, there is still a need to further reduce current transport resistance. Summary of the Invention

[0005] In view of the above, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a solar cell and a method for manufacturing the same.

[0006] To achieve the above objectives, the technical solution of this application is as follows:

[0007] According to one embodiment of this application, a solar cell is provided, comprising: a silicon substrate; a semiconductor layer disposed on the silicon substrate, the semiconductor layer having a porous structure; and a transparent conductive layer disposed on the surface of the semiconductor layer away from the silicon substrate and in contact with the porous structure.

[0008] According to another aspect of this application, a method for manufacturing a solar cell is provided, comprising: forming a semiconductor layer on a silicon substrate; laser-processing the semiconductor layer to form a porous structure, wherein the semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; and forming a transparent conductive layer on the surface of the laser-processed semiconductor layer away from the silicon substrate.

[0009] According to the embodiments of this application, the solar cell provided by this application has a porous structure in its semiconductor layer, which can increase its contact area with the transparent conductive layer, thereby improving current transmission characteristics, reducing energy consumption in the current collection process, and improving battery efficiency.

[0010] According to the embodiments of this application, the porous structure of the semiconductor layer is formed by laser processing of the semiconductor layer. It only requires adding the operation of applying laser to the semiconductor layer on the basis of the original battery process, which has the advantage of simple operation. Attached Figure Description

[0011] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 is a partial structural schematic diagram of a solar cell according to an embodiment of this application;

[0013] Figure 2A is a scanning electron microscope (SEM) image of the surface of the doped amorphous silicon layer after the first laser treatment under laser condition 1 according to an embodiment of this application.

[0014] Figures 2B and 2C are magnified microscopic SEM images of the doped amorphous silicon layer in Figure 2A, respectively.

[0015] Figures 2D to 2F are scanning electron microscope (SEM) images of the surface of the doped amorphous silicon layer after the first laser treatment under laser conditions 2 to 4, respectively.

[0016] Figure 3 is a test result of the contact resistance of the doped polycrystalline silicon layer 103 after being subjected to the first laser according to an embodiment of this application;

[0017] Figure 4A is a cross-sectional transmission electron microscope (TEM) image of the doped amorphous silicon layer after the first laser treatment under laser condition 1 according to an embodiment of this application.

[0018] Figures 4B and 4C are magnified TEM images of different locations in Figure 4A, respectively.

[0019] Figures 4D and 4E are magnified TEM images of different grain portions in Figure 4A, respectively.

[0020] Figure 5 is a side view of the overall structure of the solar cell according to an embodiment of this application;

[0021] Figure 6 is a schematic diagram showing the positional relationship between the edge portion and the main body portion of the first type doped amorphous silicon layer or the second type doped amorphous silicon layer in the embodiments of this application.

[0022] Figure 7 is a side view of the overall structure of a solar cell according to another embodiment of this application;

[0023] Figure 8 is a schematic diagram of the manufacturing process of the solar cell according to an embodiment of this application;

[0024] Figures 9A to 9E are schematic diagrams of the fabrication process of a solar cell according to another embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components. All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0027] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "over," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0028] For solar cells, to reduce contact resistance and thus improve cell performance, improvements are typically made to the contact structure between, for example, the metal electrode and the transparent conductive film layer. However, improvements to the contact structure between the transparent conductive film layer and the semiconductor layer are less frequently considered. In realizing the concept of this application, it was discovered that laser treatment of the amorphous silicon layer can create a porous structure. Further experiments verified that laser treatment of the amorphous silicon layer to create a porous structure effectively reduces the current transport characteristics between the amorphous silicon layer and the transparent conductive layer, thereby improving cell performance.

[0029] Therefore, a solar cell based on a semiconductor layer and a transparent conductive layer with an improved structure is proposed. The solar cell of this embodiment mainly includes a silicon substrate, a semiconductor layer, and a transparent conductive layer, wherein: the semiconductor layer is located on the silicon substrate and has a porous structure; the transparent conductive layer is located on the surface of the semiconductor layer away from the silicon substrate and is in contact with the porous structure. Here, the "semiconductor layer" can be a silicon semiconductor layer, and its material can include at least one of amorphous silicon, microcrystalline silicon, or nanocrystalline silicon, preferably amorphous silicon. For ease of understanding, the following description will use an amorphous silicon semiconductor layer as an example, which can include amorphous silicon, and further may include microcrystalline silicon and / or nanocrystalline silicon, etc.

[0030] Specifically, according to one aspect of the present application, a solar cell is provided. FIG1 is a partial structural schematic diagram of the solar cell of the present application embodiment. As shown in FIG1, the solar cell of the present application embodiment mainly includes a silicon substrate 101, an amorphous silicon layer 102 and a transparent conductive layer 103, wherein: the amorphous silicon layer 102 is located on the silicon substrate 101 and has a porous structure; the transparent conductive layer is located on the surface of the amorphous silicon layer 102 away from the silicon substrate 101 and is in contact with the porous structure.

[0031] According to embodiments of this application, the silicon substrate 101 can be an N-type or P-type crystalline silicon substrate, such as a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. Cells based on monocrystalline silicon substrates have higher conversion efficiency compared to other types, such as polycrystalline silicon cells. An N-type crystalline silicon substrate is obtained by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type crystalline silicon substrate is obtained by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials.

[0032] According to embodiments of this application, the amorphous silicon layer 102 may be at least partially doped or undoped, and when doped, the doping type may be N-type or P-type, which can be determined based on the cell type and the doping type of the silicon substrate. Similar to the silicon substrate 101, different doping types are obtained by introducing donor impurities or acceptor impurities into the host material of the amorphous silicon layer 102.

[0033] According to embodiments of this application, the material of the transparent conductive layer 103 is not particularly limited. For example, a transparent conductive oxide (TCO) can be used, specifically indium tin oxide (ITO), tungsten-doped tin oxide (VTTO), indium tungsten oxide (IWO), indium molybdenum oxide (IMO), or tin oxide fluoride (TOF), etc., and is not limited to these. The transparent conductive layer 103 is conformally formed on the amorphous silicon layer 102 and covers the porous structure of the amorphous silicon layer 102 to form a relatively close contact with the amorphous silicon layer 102.

[0034] According to the embodiments of this application, the solar cell type of this application is mainly applicable to heterojunction cell types, which can be bifacial heterojunction (HJT) cells, back contact heterojunction (HBC) cells, hybrid HBC cells, such as hybrid cells combining TBC (TopCon-Back Contact) and HJT, etc. Any cell that uses an amorphous silicon layer and a transparent conductive layer should be applicable.

[0035] According to embodiments of this application, the applicant discovered through experiments that laser treatment of an amorphous silicon layer can create a porous structure. It is speculated that the laser energy is absorbed by the film layer, causing its temperature to rise, resulting in a molten state and the escape of hydrogen from the film, thus creating the porous structure. Therefore, it is proposed to use laser treatment on the amorphous silicon layer 103 to create a porous structure in the amorphous silicon layer 102. Because the amorphous silicon layer 102 has a porous structure, the contact area with the transparent conductive layer can be increased, thereby reducing the current transmission resistance between it and the transparent conductive layer 104. This reduces energy loss during current collection and improves battery efficiency.

[0036] According to an embodiment of this application, the amorphous silicon layer 102 may include a second structural layer 102b and a first structural layer 102a disposed sequentially along a direction away from the silicon substrate 101; wherein, the first structural layer 102a is configured to have a first porous structure, the first porous structure having a plurality of first pores disposed through it, the plurality of first pores being used to expose the second structural layer.

[0037] For ease of explanation, the surface morphology of the amorphous silicon layer 102 is observed by scanning electron microscopy (SEM). Figure 2A is a SEM image of the surface of the amorphous silicon layer in this embodiment after the first laser treatment under laser condition 1. Figures 2B and 2C are magnified microscopic SEM images of the amorphous silicon layer in Figure 2A, respectively. As shown in Figures 2A-2C, the dark area is the second structural layer 102b, and the light area is the first structural layer 102a, showing a clear porous structure.

[0038] According to an embodiment of this application, the through-hole morphology of the first structural layer 102a of the amorphous silicon layer 102 enables the transparent conductive layer 104 to contact the first structural layer 102a and the second structural layer 102b respectively, thereby increasing the contact area with the transparent conductive layer 104 while ensuring that the process of forming the porous morphology of the first structural layer 102a will not adversely affect the layer structure located below the second structural layer 102b.

[0039] According to embodiments of this application, the second structural layer 102b can be non-porous or porous. Preferably, as shown in FIG2C, the second structural layer 102b is configured to have a second porous structure, and the pore size of the second porous structure is smaller than the pore size of the first porous structure. More preferably, as circled in FIG2C, the second structural layer 102b has a plurality of second pores, which are exposed from a plurality of first pores, thereby forming a layered nested porous structure between the first structural layer 102a and the second structural layer 102b.

[0040] According to an embodiment of this application, the second structural layer 102b is configured to have a second porous structure and forms a layered nested porous structure with the first structural layer 102a, which can further increase the contact area with the transparent conductive layer 104, thereby helping to reduce the current transmission resistance and improve battery efficiency.

[0041] According to an embodiment of this application, optionally, the pore size of the first porous structure is less than or equal to 1 μm, for example, it can be less than 1 μm, less than 0.8 μm, less than 0.5 μm, less than 0.3 μm, less than 0.1 μm, and preferably less than or equal to 0.3 μm.

[0042] According to embodiments of this application, optionally, the pore size of the second porous structure is less than or equal to 300 nm, for example, it can be less than 0.3 μm, less than 0.1 μm, less than 0.08 μm, less than 0.06 μm, less than 0.04 μm, and preferably less than or equal to 0.3 μm.

[0043] It should be noted that the “pore diameter” of the first porous structure or the second porous structure refers to the pore diameter range of the main pores of the porous structure. For a pore, the pore diameter can be the diameter of the pore after its shape along the surface direction is equivalent to a circle. The main pores can be 50% or more, preferably 80% or more, and more preferably 90% or more of the total number of pores.

[0044] According to embodiments of this application, by controlling the aperture of the amorphous silicon layer 102 within the aforementioned range, it is more beneficial to improve contact resistance and enhance battery efficiency.

[0045] According to an embodiment of this application, the first structural layer 102a has an island structure formed by a plurality of first pores. Further optionally, the first pores of the first porous structure are formed within the island structure. Experiments have shown that when the first structural layer 102a has an island structure, it exhibits a lower contact resistance with the transparent conductive layer 103. Preferably, the size of the island structure is less than or equal to 2 μm, thereby ensuring fewer defects while increasing current collection efficiency.

[0046] According to embodiments of this application, optionally, the material of the first structural layer 102a may include amorphous silicon, and may further include nanocrystalline silicon, but the possibility of including microcrystalline silicon is less, or less than that of not including microcrystalline silicon; the material of the second structural layer 102b may include amorphous silicon.

[0047] According to an embodiment of this application, as shown in FIG1, the amorphous silicon layer 102 of this application may include an intrinsic amorphous silicon layer 1021 and a doped amorphous silicon layer 1022, wherein the intrinsic amorphous silicon layer 1021 is located between the silicon substrate 101 and the doped amorphous silicon layer 1022. This film structure can be used to form a back surface field when the doping type of the doped amorphous silicon layer 1022 and the silicon substrate 101 is the same, and can be used to form a PN junction when the doping type of the doped amorphous silicon layer 1022 and the silicon substrate 101 is different.

[0048] It is understandable that when the amorphous silicon layer 102 includes the intrinsic amorphous silicon layer 1021, the porous structure of the amorphous silicon layer 102 does not extend into the intrinsic amorphous silicon layer 1021, but is mainly located in the doped amorphous silicon layer 1022. Therefore, it will not adversely affect the passivation effect of the intrinsic amorphous silicon layer 1021.

[0049] According to embodiments of this application, optionally, the thickness of the intrinsic amorphous silicon layer 1021 can be 5–30 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc., and the thickness of the doped amorphous silicon layer 1022 can be 10–45 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc. It should be noted that, unless otherwise specified, "thickness" generally refers to the dimension along the direction perpendicular to the surface of the silicon substrate.

[0050] According to embodiments of this application, the thickness of the intrinsic amorphous silicon layer 1021 has a significant impact on contact resistance and passivation effect. Specifically, on the one hand, the thicker the intrinsic amorphous silicon layer 1021, the higher the contact resistance, the greater the current collection loss, and the lower the battery efficiency. On the other hand, within a suitable thickness range, the thicker the intrinsic amorphous silicon layer 1021, the better the passivation effect, the less carrier recombination, and the higher the battery efficiency. Since the doped amorphous silicon layer 1022 of this application employs a porous structure, the contact resistance is reduced, thereby freeing up space for thickening the intrinsic amorphous silicon layer 1021, thus improving the passivation effect.

[0051] The thickness of the doped amorphous silicon layer 1022 is within the aforementioned range. On the one hand, since the light absorption intensity of the film layer decreases exponentially with depth, if the film layer is thicker, the interface temperature between the silicon substrate and the intrinsic amorphous silicon layer will be lower when the surface film layer reaches the same high temperature, resulting in weaker passivation damage. This avoids the situation where, when the thickness is too thin, the temperature of the silicon substrate 101 and the intrinsic amorphous silicon layer 1021 becomes too high during laser processing, leading to a poor passivation effect. On the other hand, as the film layer thickens, it helps to slow down heat dissipation and is also more conducive to achieving high temperatures on the film layer surface.

[0052] According to embodiments of this application, the surface of the silicon substrate 101 has a polished area with a pyramidal base structure, which can be obtained through texturing and polishing processes; wherein, the amorphous silicon layer 102 is located above the polished area of ​​the silicon substrate 101. Experiments have shown that a polished surface with a pyramidal base structure on the surface of the silicon substrate 101 is conducive to the formation of porous structures, while the formation of porous structures is difficult to observe when the surface is textured. However, this is not a limitation; the surface of the silicon substrate 101 can also be an untextured and unpolished surface.

[0053] According to embodiments of this application, the solar cell may further include an electrode 104 located on the surface of the transparent conductive layer 103. The electrode 104 may be made of materials such as silver, copper, silver-clad copper, or aluminum, and may be patterned using processes such as vacuum evaporation, electroplating, or screen printing.

[0054] In some exemplary embodiments, to more clearly illustrate the various film layers of the solar cell of this application, a monocrystalline silicon wafer is used as the silicon substrate 101, and one surface of the silicon substrate 101 is a polished surface with a pyramidal base structure. An intrinsic amorphous silicon layer 1021 and a P-type doped amorphous silicon layer are sequentially deposited on the polished surface of the silicon substrate 101. Then, the P-type doped amorphous silicon layer with a thickness of 10-40 nm is processed using the first laser of laser condition 1 to form a P-type doped amorphous silicon layer with a porous structure, resulting in a silicon wafer suitable for inspection by scanning electron microscopy (SEM), and the inspection results are shown in Figures 2A-2C. Further, SiN and Pt layers are sequentially deposited on the surface of the doped amorphous silicon layer 1022 to obtain a silicon wafer suitable for inspection by transmission electron microscopy (TEM).

[0055] In some other exemplary embodiments, the laser condition 1 used can be adjusted to laser condition 2 to laser condition 4 respectively. The specific parameters of laser condition 1 to laser condition 4 are shown in Table 1 below, thereby forming a corresponding amorphous silicon layer 102 on the silicon substrate 101.

[0056] Table 1

[0057] The surface microstructure of the amorphous silicon layer 102 after laser conditions 1 to 4 was observed using a scanning electron microscope. Figures 2D to 2F are scanning electron microscope (SEM) images of the surface of the amorphous silicon layer 102 after the first laser treatment under laser conditions 2 to 4, respectively. As shown in Figures 2A to 2F, a clearly layered porous structure was observed in the amorphous silicon layer 102 under different laser conditions. This is because after the laser is absorbed by the film layer, the film layer temperature increases, causing hydrogen to escape from the film layer and creating a porous structure. Furthermore, the porous morphology differs under different laser conditions.

[0058] Furthermore, as shown in Figures 2A-2C, the porous morphology at the base structure differs from other locations. This is because the porous morphology is affected by the laser energy density and film temperature. The base edge of the polished surface of the silicon substrate 101 has steps that affect the optical path, thus influencing the laser energy density and film temperature. However, the base structure does not affect the overall porous morphology distribution over a larger area.

[0059] As shown in Figures 2C to 2F, the amorphous silicon layer 102 was observed to have a layered nested morphology under laser conditions 1, 3, and 4. That is, there are smaller pores in the second structural layer 102b under the first structural layer 102a. Under laser condition 2, it is difficult to observe the porous structure of the second structural layer 102b in the doped polycrystalline silicon layer 103. Its pore size is much smaller than 0.1 μm, which can be a non-porous morphology.

[0060] The contact resistance of the amorphous silicon layer 102 under no laser treatment and after first laser treatment under laser conditions 1 to 4 was tested using current-voltage tests. Specifically, tests were conducted on a bi-symmetrical P-type doped amorphous silicon / intrinsic amorphous silicon / P-type doped amorphous silicon / TCO layer / electrode structure. The results showed that the contact resistance of the amorphous silicon layer 102 after first laser treatment under different laser conditions all exhibited a significant decrease. Figure 3 shows the contact resistance test results of the amorphous silicon layer 102 after first laser treatment, with a TCO layer covering it and a metal electrode formed, according to an embodiment of this application. It illustrates the contact resistance of the amorphous silicon layer 102 after the more preferred laser condition 1 treatment. As shown in Figure 3, compared to no laser treatment, the contact resistance of the amorphous silicon layer 102 after first laser treatment under laser condition 1 shows a significant decrease. As can be seen from the comparison of Figures 2C to 2F, the amorphous silicon layer 102 after the first laser treatment under laser condition 1 has the following distinct structure compared to other laser conditions, which is beneficial to the reduction of contact resistance: the first structural layer 102a has an island structure formed by the separation of the first pores, and further, some of the first pores are formed in the island structure.

[0061] The cross-sectional microstructure of the amorphous silicon 102 after laser conditions 1 to 4 was observed using transmission electron microscopy (TEM). Figure 4A is a TEM image of the cross-section of the doped amorphous silicon layer after the first laser treatment under laser condition 1 according to the embodiment of this application. Figures 4B and 4C are magnified TEM images of different locations in Figure 4A. Figures 4D and 4E are magnified TEM images of different grain portions in Figure 4A, respectively. SiN is the protective layer used during the test. As shown in Figures 4A to 4E, although the porous morphology at the cross-section is not obvious, it can still be observed that the amorphous silicon layer 102 has undergone morphological changes after the first laser treatment. Furthermore, the P-type doped amorphous silicon layer has a layered structure, namely, a first structural layer 102a and a second structural layer 102b. As shown in Figure 4B, the rectangular frame indicates the intrinsic amorphous silicon layer 1021 (i.e., ia-Si) and the second structural layer 102b (i.e., pa-Si). Above the rectangular frame is the first structural layer 102a (i.e., pa-Si). As shown in Figures 4B and 4C, the first structural layer 102a exhibits circular grain portions, while the grain portions shown in Figures 4D and 4E exhibit an ordered lattice structure. This indicates that the amorphous silicon in the first structural layer 102a has undergone partial crystallization, and this ordered lattice structure is nanocrystalline silicon. It can be seen that the material of the first structural layer 102a can include not only retained amorphous silicon but also crystallized nanocrystalline silicon. This is where laser treatment of amorphous silicon layers is superior to treatment of nanocrystalline and microcrystalline silicon layers. This allows the amorphous silicon layer to partially crystallize, achieving a current collection effect similar to that of nanocrystalline and microcrystalline silicon layers, while also retaining the advantages of fast deposition rate and low cost of amorphous silicon layers.

[0062] According to an embodiment of this application, taking a bifacial heterojunction solar cell as an example, the solar cell of this application will be further explained. Figure 5 is a side view of the overall structure of the solar cell of this application embodiment. As shown in Figure 5, the silicon substrate 101 includes a first surface 101a and a second surface 101b opposite to each other. The amorphous silicon layer 102 includes a first-type doped amorphous silicon layer 1022a located on the first surface 101a of the silicon substrate 101. The solar cell also includes a second-type doped amorphous silicon layer 1022b located on the second surface 101b of the silicon substrate 101. Here, the doping types of the first and second types are opposite. For example, the first-type doped amorphous silicon layer 1022a can be an N-type doped amorphous silicon layer, and the second-type doped amorphous silicon layer 1022b can be a P-type doped amorphous silicon layer. Alternatively, the polarities of the two can be interchanged. Preferably, the silicon substrate 101 is an N-type substrate, and the first-type doped amorphous silicon layer 1022a is a P-type substrate.

[0063] Figure 6 is a schematic diagram showing the positional relationship between the edge portion and the main body portion of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer according to an embodiment of this application. As shown in Figure 6, the first-type doped amorphous silicon layer 1022a and / or the second-type doped amorphous silicon layer 1022b respectively include a main body portion A and an edge portion B surrounding the periphery of the main body portion. The main body portion A has a porous structure, and the edge portion B has a non-porous structure. Since the edge portion B is thinner and has more defects, and the electron-hole recombination rate is higher, by setting the edge portion B to have a non-porous structure, on the one hand, the damage caused by laser processing to the thinner edge portion can be reduced to ensure the passivation effect; on the other hand, the defects of the edge portion can be further isolated to suppress carrier recombination.

[0064] According to an embodiment of this application, more preferably, the first surface 101a of the silicon substrate 101 is a polished surface with a pyramidal base structure, which can serve as a backlight surface. The first type-doped amorphous silicon layer 1022a has a porous structure, that is, the main body portion A has a porous structure, and the edge portion B has a non-porous structure. The second surface 101b of the silicon substrate 101 is a textured surface with a pyramidal structure, which can serve as a light-receiving surface. The second type-doped amorphous silicon layer 1022b has a non-porous structure. This results in higher light utilization on the light-receiving surface, while reducing contact resistance on the backlight surface, thereby improving battery efficiency.

[0065] According to an embodiment of this application, the solar cell of this application may further include a first transparent conductive layer 103a and a second transparent conductive layer 103b, wherein the first transparent conductive layer 103a is located on the first surface 101a of the first type doped amorphous silicon layer 1022a away from the silicon substrate 101, and is in contact with the porous structure of the main body portion A in the first type doped amorphous silicon layer 1022a; the second transparent conductive layer 103b is located on the second surface 101b of the second type doped amorphous silicon layer 1022b away from the silicon substrate 101.

[0066] According to embodiments of this application, the solar cell of this application may further include a first intrinsic amorphous silicon layer 1021a, a second intrinsic amorphous silicon layer 1021b, a first electrode 104a, and a second electrode 104b, wherein the first intrinsic amorphous silicon layer 1021a is located between the silicon substrate 101 and the first type doped amorphous silicon layer 1022a, forming an amorphous silicon layer 102 with the first type doped amorphous silicon layer 1022a; the second intrinsic amorphous silicon layer 1021b is located between the silicon substrate 101 and the second type doped amorphous silicon layer 1022b, forming another amorphous silicon layer 102' with the second type doped amorphous silicon layer 1022b; the first electrode 104a is located on the first transparent conductive layer 103a, and the second electrode 104b is located on the second transparent conductive layer 103b.

[0067] According to the embodiments of this application, taking a hybrid back-contact heterojunction cell as an example, the solar cell of this application will be further explained. Figure 7 is a side view of the overall structure of a solar cell according to another embodiment of this application. As shown in Figure 7, the silicon substrate 101 includes a first surface 101a and a second surface 101b opposite to each other. The first surface includes a first region 101a' and a second region 101a" that are spaced apart from each other. The amorphous silicon layer 102 includes a first type doped amorphous silicon layer 1022a located in the first region 101a' of the silicon substrate 101. The solar cell also includes a second type doped polycrystalline silicon layer 1023 located in the second region 101a of the silicon substrate 101.

[0068] In this design, a first-type doped amorphous silicon layer 1022a extends over a second-type doped polycrystalline silicon layer 1023, overlapping with it. The overlapping portion between the first-type doped amorphous silicon layer 1022a and the second-type doped polycrystalline silicon layer 1023 has a non-porous structure. The location corresponding to this overlapping portion is indicated by the rectangular frame. It can be understood that the portion of the first-type doped amorphous silicon layer 1022a other than the overlapping portion has a porous structure. By setting the first-type doped amorphous silicon layer 1022a at the overlapping portion to have a non-porous structure, leakage current between the first-type doped amorphous silicon layer 1022a and the second-type doped polycrystalline silicon layer 1023 is improved.

[0069] According to an embodiment of this application, the solar cell of this application further includes a transparent conductive layer 103 located on the surface of a first region 101a' of a first type-doped amorphous silicon layer 1022a that is away from the silicon substrate 101 and on the surface of a second region 101a" of a second type-doped polycrystalline silicon layer 1023 that is away from the silicon substrate 101, and in contact with the porous structure in the first type-doped amorphous silicon layer 1022a. It can be understood that the transparent conductive layer 103 here is a patterned layer structure.

[0070] According to embodiments of this application, the solar cell further includes an intrinsic amorphous silicon layer 1021, a tunneling oxide layer 105, and an electrode 104. The intrinsic amorphous silicon layer 1021 is located between a silicon substrate 101 and a first-type doped amorphous silicon layer 1022a, the tunneling oxide layer 105 is located between the silicon substrate 101 and a second-type doped polycrystalline silicon layer 1023, and the electrode 104 is located on a transparent conductive layer 103. A heterojunction can be formed from the intrinsic amorphous silicon layer 1021, the first-type doped amorphous silicon layer 1022a, and the silicon substrate 101, while a tunneling oxide passivation structure can be formed from the tunneling oxide layer 105 and the second-type doped polycrystalline silicon layer 1023.

[0071] According to an embodiment of this application, the intrinsic amorphous silicon layer 1021 extends over the second type-doped polycrystalline silicon layer 1023 to overlap with it. In this case, the intrinsic amorphous silicon layer 1021 located between the first type-doped amorphous silicon layer 1022a and the second type-doped polycrystalline silicon layer 1023 serves as an insulator. If the thickness of the intrinsic amorphous silicon layer 1021 is thinner, its lateral wall thickness is also thinner, resulting in poorer insulation and consequently, higher leakage current, reducing battery efficiency. Here, "lateral" refers to the direction from the sidewall of the first type-doped amorphous silicon layer 1022a to the sidewall of the second type-doped polycrystalline silicon layer 1023.

[0072] Based on this, the porous structure of the first type doped amorphous silicon layer 1022a helps to reduce contact resistance, thereby freeing up space for thickening the intrinsic amorphous silicon layer 1021, which improves both passivation and leakage current. This achieves a balance between contact resistance, passivation effect and leakage current suppression, resulting in a significantly better battery efficiency.

[0073] According to an embodiment of this application, in the solar cell shown in FIG7, the tunneling oxide layer 105 can be replaced with the intrinsic amorphous silicon layer 1021, and the second type doped polycrystalline silicon layer 1023 can be replaced with the second type doped amorphous silicon layer 1022b, thereby forming a solar cell of the HBC cell type.

[0074] According to embodiments of this application, the solar cell further includes a passivation antireflection layer formed on the second surface 101b of the silicon substrate 101 for surface passivation and to improve light utilization. As shown in FIG7, the passivation antireflection layer may, for example, sequentially include a third intrinsic amorphous silicon layer 106 and a silicon nitride layer 107, but is not limited thereto; for example, it may also include silicon nitride (SiNx) or an aluminum oxide / SiNx stacked film, etc.

[0075] According to some embodiments of this application, a method for manufacturing a solar cell is also provided. Figure 8 is a schematic diagram of the manufacturing process of a solar cell according to an embodiment of this application. As shown in Figure 8, the method for manufacturing a solar cell according to an embodiment of this application mainly includes operations S801 to S803.

[0076] In operation S801, a semiconductor layer is formed on a silicon substrate.

[0077] In operation S802, the first laser is used to process the semiconductor layer, so that the semiconductor layer forms a porous structure.

[0078] In operation S803, a transparent conductive layer is formed on the surface of the laser-treated semiconductor layer away from the silicon substrate. The meaning of "semiconductor layer" is the same as described above, and the following explanation will further illustrate this by taking an amorphous silicon layer as an example of a semiconductor layer.

[0079] According to the embodiments of this application, this application uses a laser to process the amorphous silicon layer, thereby forming a porous structure in the amorphous silicon layer. It only requires adding the operation of applying a laser to the amorphous silicon layer on the basis of the original battery process, which has the advantage of simple operation.

[0080] According to embodiments of this application, the wavelength of the laser is 325–532 nm, for example, 325 nm, 350 nm, 400 nm, 450 nm, 500 nm, or 532 nm; the pulse width is on the order of picoseconds to nanoseconds; and the energy density is 200–6000 mJ / cm². 2 For example, it can be 200mJ / cm 2 500mJ / cm 2 1000mJ / cm 2 2000mJ / cm 2 3000mJ / cm 2 4000mJ / cm 2 5000mJ / cm 2 6000mJ / cm 2 The laser overlap rate is 60% to 95%, for example, it can be 60%, 65%, 70%, 75%, 80%, 85%, 90%, or 95%.

[0081] According to the embodiments of this application, in order to further understand the overall fabrication process of the solar cell of this application, a specific method for fabricating a hybrid back-contact heterojunction cell as shown in FIG. 7 will be described as an example. FIG. 9A to FIG. 9E are schematic diagrams of the fabrication process of a solar cell according to another embodiment of this application. As shown in FIG. 9A to 9E, the manufacturing method of the solar cell of this application includes operations S901 to S905.

[0082] In operation S901, a tunneling oxide layer 905 and a type-doped polysilicon layer 9023 are formed on the first surface 901a of the silicon substrate 901.

[0083] In operation S902, the tunneling oxide layer 905 and the second type doped polysilicon layer 9023 are patterned, and the tunneling oxide layer 905 and the second type doped polysilicon layer 9023 are retained on the second region 901a” of the first surface 901a.

[0084] In operation S903, the areas of the first surface 901a other than the second region 901a” are texturized and polished to obtain a polished surface containing a pyramid base structure.

[0085] In operation S904, an intrinsic amorphous silicon layer 9021 and a first-type doped amorphous silicon layer 9022a are sequentially formed on the polished surface, and the first-type doped amorphous silicon layer 9022a is processed using a first laser. Preferably, the boundary of the processed layer does not reach the boundary of the adjacent second-type doped polycrystalline silicon layer 9023, and there is a certain distance between the boundary of the first laser processing of the first-type doped amorphous silicon layer 9022a and the boundary of the second-type doped polycrystalline silicon layer 9023, for example, it can be 50-200 micrometers.

[0086] In operation S905, a patterned transparent conductive layer 903 and an electrode 904 are fabricated on the surfaces of a first-type doped amorphous silicon layer 903a and a second-type doped polycrystalline silicon layer 9023 that have undergone laser treatment.

[0087] According to an embodiment of this application, as shown in FIG9A, operation S901 may specifically include: (1) Polishing: Polishing the silicon substrate 901 on both sides to make its surface smooth. (2) First chemical vapor deposition (CVD1): Depositing a tunneling oxide layer 905 and a polycrystalline silicon or amorphous silicon layer 9031 sequentially on the first surface 901a of the double-sided polished silicon substrate 901 using a chemical vapor deposition method. The deposition conditions are not the key to this application and will not be described in detail here. (3) Doping: Using a diffusion process to transform the polycrystalline silicon or amorphous silicon layer 9031 into a type II doped polycrystalline silicon layer 9023. The diffusion conditions are not the key to this application and will not be described in detail here.

[0088] It is understandable that different doping types and diffusion processes will form different doping sources 9032 on the surface of the type II doped polysilicon layer 9023. For example, the phosphorus diffusion process will form phosphorus silicon glass on the surface of the type II doped polysilicon layer 9023, and the boron diffusion process will form borosilicate glass on the surface of the type II doped polysilicon layer 9023.

[0089] According to an embodiment of this application, as shown in FIG9B, operation S902 may specifically include:

[0090] (1) First wet process (wet process 1): Wet process to remove dopant source 9032, for example, by acid washing process to remove phosphosilicate glass or borosilicate glass.

[0091] (2) Second chemical vapor deposition (CVD2): A mask layer 908 is deposited on the surface of the second type doped polysilicon layer 9023 away from the silicon substrate 101 using a chemical vapor deposition method. For example, a silicon nitride layer can be deposited. The deposition conditions are not the key to this application and will not be described in detail here.

[0092] (3) Second laser processing (laser2): A second laser is used to perform laser ablation on the tunneling oxide layer 905, the type-2 doped polysilicon layer 9023, and the mask layer 908, removing the tunneling oxide layer 905 and the type-2 doped polysilicon layer 9023 from the remaining areas of the first surface 901a, excluding the second region 901a". The laser ablation conditions are not critical to this application and will not be described in detail here.

[0093] According to an embodiment of this application, as shown in FIG9C, operation S903 may specifically include:

[0094] (1) Second wet process (wet process 2): The first surface 901a except the second region 901a” and the second surface 901b of the silicon substrate are wet texturized by means of double-sided texturization. For example, wet texturization can be carried out using an alkaline bath.

[0095] (2) Second chemical vapor deposition (CVD2-2): A passivation antireflection layer is deposited on the wet-textured second surface 901b of the silicon substrate 901 using a chemical vapor deposition method, for example, a third intrinsic amorphous silicon layer 906 and a silicon nitride layer 907 are deposited sequentially.

[0096] (3) Second wet process (wet process 2-2): Alkali polishing is performed on the areas of the first surface 901a except for the second region 901a” using a chain equipment to obtain a polished surface, and the mask layer on the surface of the second type doped polysilicon layer 9023 is removed by acid washing using a chain equipment.

[0097] According to an embodiment of this application, as shown in FIG9D, operation S904 may specifically include:

[0098] (1) Third Chemical Vapor Deposition (CVD3): An intrinsic amorphous silicon layer 9021 and a first-type doped amorphous silicon layer 9022a are sequentially deposited on the polished surface of the silicon substrate 901 and the surface of the second-type doped polycrystalline silicon layer 9023 using chemical vapor deposition. The intrinsic amorphous silicon layer 9021 forms an isolation region between the first-type doped amorphous silicon layer 9022a and the second-type doped polycrystalline silicon layer 9023, thus providing insulation.

[0099] (2) Laser and Third Wet Processing: First, a third laser is used to remove the intrinsic amorphous silicon layer 9021 and the first type doped amorphous silicon layer 9022a from the surface of the second type doped polycrystalline silicon layer 9023. The retained first type doped amorphous silicon layer 9022a overlaps with the second type doped polycrystalline silicon layer 9023, and this overlap reduces damage to the second type doped polycrystalline silicon layer 9023 during subsequent opening of the transparent conductive layer in the isolation region. Second, a first laser is used to process the remaining portion of the first type doped amorphous silicon layer 9022a, excluding the overlap, to form a porous structure. Third, acid washing is used to remove the silicon oxide formed on the film surface after the third and first laser treatments.

[0100] According to an embodiment of this application, as shown in FIG9E, operation S905 specifically includes: physical vapor deposition (PVD): a transparent conductive layer 903 is deposited on the exposed surface of the second type doped polycrystalline silicon layer 9023 and the exposed surface of the first type doped amorphous silicon layer 9022a after the first laser treatment using physical vapor deposition. The deposition conditions are not the key to this application and will not be described in detail here.

[0101] According to an embodiment of this application, continuing as shown in FIG9E, after operation S905, the following may also be included:

[0102] (1) Insulation treatment (TCO insulation): The transparent conductive layer 903 located at the isolation position between the first type doped amorphous silicon layer 9022a and the second type doped polycrystalline silicon layer 9023 is removed, for example by laser film opening.

[0103] (2) Screen printing: Electrodes 904 were fabricated on the transparent conductive layer 903 by screen printing, resulting in a solar cell with the structure shown in Figure 7.

[0104] According to the embodiments of this application, the solar cell obtained by the above manufacturing method is based on the porous structure of the first type doped amorphous silicon, which reduces the contact resistance with the transparent conductive layer, thereby providing space for the thickening of the intrinsic amorphous silicon layer. Thus, the effects of contact resistance, passivation effect and leakage current can be taken into account, thereby optimizing the cell efficiency.

[0105] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized by, The solar cell comprises: a silicon substrate; a semiconductor layer located on the silicon substrate, the semiconductor layer having a porous structure, the semiconductor layer comprising at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon; and a transparent conductive layer located on a surface of the semiconductor layer distal to the silicon substrate and in contact with the porous structure.

2. The solar cell according to claim 1, characterized in that, The semiconductor layer comprises a second structure layer and a first structure layer arranged in sequence in a direction distal to the silicon substrate; wherein the first structure layer is configured to have a first porous structure, the first porous structure having a plurality of first pores arranged therethrough, the plurality of first pores being configured to expose at least a portion of the second structure layer.

3. The solar cell according to claim 2, characterized in that, The second structure layer is configured to have a second porous structure, the second porous structure having a pore size smaller than a pore size of the first porous structure.

4. The solar cell according to claim 3, characterized in that, The second porous structure comprises a plurality of second pores exposed from the plurality of first pores.

5. The solar cell of claim 2, wherein The first structure layer has an island structure formed by the plurality of first pores.

6. The solar cell according to claim 5, characterized in that, Some of the first pores are formed in the island structure, and / or a size of the island structure is less than or equal to 2 μm.

7. The solar cell of claim 3, wherein The first porous structure has a pore size less than or equal to 1 μm, and the second porous structure has a pore size less than or equal to 300 nm.

8. The solar cell according to any one of claims 2 to 7, characterized in that, The first structure layer comprises amorphous silicon and nanocrystalline silicon, and the second structure layer comprises amorphous silicon.

9. The solar cell of claim 1, wherein, A surface of the silicon substrate has a polishing region comprising pyramid base structures; wherein the semiconductor layer is located on the polishing region of the silicon substrate.

10. The solar cell of claim 1, wherein The semiconductor layer comprises: an intrinsic amorphous silicon layer and a doped amorphous silicon layer, the intrinsic amorphous silicon layer being located between the silicon substrate and the doped amorphous silicon layer; wherein the intrinsic amorphous silicon layer has a thickness of 5-30 nm, and the doped amorphous silicon layer has a thickness of 10-45 nm.

11. The solar cell according to any one of claims 1 to 7, 9 to 10, characterized in that, The solar cell is a bifacial heterojunction cell or a back contact heterojunction cell.

12. The solar cell of claim 11, wherein, The silicon substrate comprises opposite first and second surfaces; The semiconductor layer comprises a first-type doped amorphous silicon layer located on the first surface of the silicon substrate; The solar cell further comprises a second-type doped amorphous silicon layer located on the second surface of the silicon substrate; wherein the first-type doped amorphous silicon layer and / or the second-type doped amorphous silicon layer each comprises a main portion and a peripheral portion surrounding a periphery of the main portion, the main portion having a porous structure, and the peripheral portion having a non-porous structure.

13. The solar cell of claim 11, wherein, The silicon substrate comprises opposite first and second surfaces, the first surface comprising first and second regions arranged in sequence in a direction distal to the silicon substrate; The semiconductor layer comprises a first-type doped amorphous silicon layer located on the first region of the silicon substrate; The solar cell further comprises a second-type doped polycrystalline silicon or amorphous silicon layer located on the second region of the silicon substrate; The first type of doped amorphous silicon layer extends onto the second type of doped polysilicon or amorphous silicon layer to form an overlap with the second type of doped polysilicon or amorphous silicon layer, and the first type of doped amorphous silicon in the overlapping part between the first type of doped amorphous silicon layer and the second type of doped polysilicon or amorphous silicon layer is a non-porous structure.

14. A method for manufacturing a solar cell, characterized by, The manufacturing method comprises: forming a semiconductor layer on a silicon substrate; processing the semiconductor layer by using a first laser to make the semiconductor layer form a porous structure; forming a transparent conductive layer on the surface of the laser-processed semiconductor layer away from the silicon substrate.

15. The manufacturing method according to claim 14, wherein The laser has a wavelength of 325-532 nm, a pulse width of picosecond to nanosecond order of magnitude, and an energy density of 200-6000 mJ / cm 2 .

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