Manufacturing method for integrated optics devices with a poled element

Abstract

A method for manufacturing integrated optics devices (2) is described. Each device (2) comprises electrical contact pads (20) and at least one poled optical element (12a, 12b). The method includes forming, on a wafer (24), first structures of a plurality of the devices (2) in a two-dimensional array of device regions (26). Within each device region (26), the first structures of one of the devices (2) are formed. These first structures comprise at least some of the contact pads (20) of the device (2), electrodes (16a, 16b, 16c) electrically connected to the contact pads (20), and an unpoled dielectric or semiconducting material (14a, 14b) between the electrodes (16a, 16b, 16c). For poling the material, at least one group (50) of the devices (2) is contacted by means of a contact member (28). The contact member (28) comprises a plurality of electrically conductive contact elements (32), and the contact elements (32) are brought into electrical contact with at least part of the contact pads (20). The group (50) is then heated in order to increase a temperature of the material (14a, 14b), to a poling temperature. At the same time, a voltage is applied to the electrodes (16a, 16b, 16c) by means of the contact member (28), thereby poling the material (14a, 14b).

Description

[0001] Manufacturing method for integrated optics devices with a poled element

[0002] Technical Field

[0003] The invention relates to a method for manufacturing integrated optics devices using an electrical poling step for creating a poled optical element of the devices.

[0004] Background Art

[0005] Integrated optics devices with poled optical elements are, e.g., used as electro-optical modulators, optical frequency converters, or electrical field detectors. For example, W. Heni et al., DOI: 10.1364 / OE.23.029746 and WO2023088561 Al describe optical modulators based on Mach-Zehnder Interferometers.

[0006] In this type of devices, a material having a first-order electro-optical effect ("Pockels effect") is provided. In order to exhibit such an effect, the material needs to have a non-centrosymmetric internal structure.

[0007] In some applications, this non-centrosymmetric is achieved by using a poled material, where polar chromophores of the material are at least partially aligned. Poling is achieved by temporarily heating the material to at least its glass temperature while applying an electrical field, see, e.g., the reference W. Heni et al. as cited above.

[0008] Other types of integrated optics devices comprising poled elements include converters between an optical signal and a radio signal, such as described in WO2018172302A1, or optical frequency doublers or frequency mixers based on second-order non-linear optical effects.

[0009] For large-scale manufacturing, a plurality of such devices can be manufactured on a wafer. US 2014 / 0086523 Al describes an example of such a method. Here, the poled elements are electro-optical polymers, and they are poled by means of dedicated metal leads. The leads have to be at least partially removed after poling, which renders the method complex.

[0010] Disclosure of the Invention The problem to be solved by the present invention is to provide a method for manufacturing integrated optics devices with poled elements that scales well even for large manufacturing volumes.

[0011] This problem is solved by the method of claim 1.

[0012] Accordingly, a method is provided for manufacturing integrated optics devices, where each device comprises electrical contact pads and at least one poled optical element. The method comprises as least the following steps:

[0013] A) Forming, on a wafer, "first structures" of a plurality of the devices in a two-dimensional array of device regions. Within each device region, the first structures of one of the devices are formed. These first structures comprise at least some of the contact pads of the device, electrodes electrically connected to the contact pads, and at least one unpoled dielectric or semiconducting material arranged between the electrodes.

[0014] B) Contacting at least one "group" of the (now partially formed) devices. This group comprises at least several of the devices, i.e., of the device regions. Contacting takes place by means of a contact member. The contact member has a plurality of electrically conductive contact elements, and the contact elements are brought into direct contact (i.e., into mechanical contact) with at least part of the contact pads of at least some of the devices of the group, e.g., all of the devices of the group.

[0015] C) Heating, in order to temporarily increase the temperature of the dielectric or semiconducting material of at least part of the device regions of the group to a poling temperature while applying, by means of the contact member, a voltage to the electrodes, thereby poling the material.

[0016] The method is based on the understanding that a direct contacting of the contact pads of several devices in the array of device regions on the wafer obviates the need for dedicated poling lines, or at least reduces their number, thereby simplifying the process and the structures to be integrated on the wafer. Since the group being contacted comprises several devices and device regions, the method scales well for manufacturing large numbers of devices.

[0017] Steps B) and C) may at least partially overlap. In some embodiments, heating may start before contact is established. Alternatively, contacting may take place before heating starts. Or the moments of contacting and the starting time of heating may coincide.

[0018] In some embodiments, there is only one such "group" on the wafer, i.e. the group includes all of the devices (i.e., of the devices to be poled) on the wafer. In this case, all the devices on the wafer are contacted in a single contacting step only. If, in this case, all of the devices of the group are heated together to the poling temperature, a single poling step can be used.

[0019] In other embodiments, there may be N groups 1 ... N of devices, with N > 1. In this case, the method comprises subsequently contacting and heating and poling the dielectric or semiconducting materials in each group, i.e., the method iterates through all groups subsequently, and for each group it carries out the above steps B and C. This reduces the number of devices that have to be contacted at a time, thereby simplifying the contact member design and the contacting process.

[0020] The poling temperature may be close to or above the glass temperature of the material, in the sense that the poling temperature is at least Tgt - 10°C, in particular at least Tgt - 5°C, with Tgt being the glass-transition temperature of the material.

[0021] Brief Description of the Drawings

[0022] The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings, wherein:

[0023] Fig. 1 shows an example of a single integrated optics device,

[0024] Fig. 2 shows a first example of a plurality of the devices integrated on a wafer,

[0025] Fig. 3 shows a first example of a contact member as it may, e.g., be used for the wafer of Fig. 2,

[0026] Fig. 4 illustrates how the contact member may contact the devices during poling,

[0027] Fig. 5 shows a second example of a plurality of the devices integrated on a wafer (the figure only shows a section of the wafer),

[0028] Fig. 6 shows a second example of a contact member as it may, e.g., be used for the wafer of Fig. 5,

[0029] Fig. 7 illustrates some steps for manufacturing integrated optics devices,

[0030] Fig. 8 shows, with a common time-axis t, the temperature T, poling voltage U, and electrode current I during poling,

[0031] Fig. 9 shows a support with several heating elements,

[0032] Fig. 10 illustrates a wiring example for a contact member (showing only a subset of the contact elements). Modes for Carrying Out the Invention

[0033] Integrated Optics Devices

[0034] As mentioned, integrated optics devices with poled optical elements are, e.g., used as electro-optical modulators, optical frequency converters, or electrical field detectors. For example, W. Heni et al., DOI: 10.1364 / OE.23.029746 and WO2023088561 Al describe optical modulators based on Mach-Zehnder Interferometers

[0035] Fig. 1 shows an example of such a device 2, as it is, e.g., shown in Fig. 1 of WO2023088561A1.

[0036] Device 2 may comprise one or more optical input terminals 4 and optical output terminals 6 connected by one or more waveguides 8a - 8d. In the shown embodiment, the waveguides 8a - 8d form a Mach-Zehnder interferometer 10 with two arms. One or more poled optical elements 12a, 12b is / are arranged in one or both arms of the interferometer 10. Each poled optical element 12a, 12b comprises a poled dielectric or semiconducting material 14a, 14b arranged between electrodes 16a, 16b, 16c. The poled dielectric material 14a, 14b is located, at least in part, in a gap 18a, 18b between the electrodes 16a, 16b, 16c.

[0037] As described in WO2023088561 Al, the poled material in the gap is used as an electro-optic modulator. The light in the waveguides 8c, 8d is coupled, at least in part, into the poled material, and a voltage applied over the respective electrodes 16a, 16b, 16c is used to modulate the phase if the light and, therefore, the transmission of the Mach-Zehnder interferometer.

[0038] The material 14a, 14b with its adjacent electrodes may, e.g., form a plasmonic waveguide or a non-plasmonic waveguide.

[0039] In some embodiments, though, the present method relates to manufacturing devices where material the 14a, 14b with its adjacent electrodes forms a plasmonic waveguide.

[0040] To apply the voltages to the electrodel6a, 16b, 16c, device 2 comprises contact pads 20a, 20b, 20c, which are electrically connected to the electrodes 16, 16b, 16c by means of conducting lines 28a, 28b, 28c.

[0041] In operation of device 2, the contact pads 20a, 20b, 20c are used to apply defined voltages over the gaps 18a, 18b in order to operate the interferometer as a modulator. The electrical fields in the gaps 18a, 18b change the refractive index of the poled material 14a, 14b, thereby tuning the interferometer as known to the skilled person.

[0042] It must be noted that Fig. 1 shows only one of numerous embodiments of a device 2 as it can be manufactured by the present method. For example, WO2023088561A1 shows further embodiments in Figs. 12 and 14. Similar interferometer geometries may, e.g., also be used in optical switches, demultiplexers, or multiplexers.

[0043] And, as mentioned above, other types of integrated optics devices with poled elements include converters between optical signals and radio signals, such as described in WO2018172302A1, or optical frequency doublers or frequency mixers based on second-order non-linear optical effects.

[0044] Another type of device is a ring resonator, such as, e.g., described by Eppenberger et al. in Nature Photonics | Volume 17 | April 2023 | 360-367 (https: / / doi.org / 10.1038 / s41566-023-01161-9).

[0045] Generally, in order to, e.g., exhibit a linear electro-optic effect or second-order nonlinear optical effects, a material needs to be non-centro-symmetric along the applied electrical field and / or light polarization.

[0046] Material 14a, 14b may be an organic material. Such materials typically comprise non-centrosymmetric chromophore molecules or side groups that need to be at least partially aligned to create the desired asymmetry, and such alignment can be achieved by heating the material at least to a poling temperature Tp, such as to at least 10°C below the glass-transition temperature Tgr, and applying an electrical field with a DC component, which causes the chromophores dipoles to align along the field lines. Once the temperature falls back far enough below the glass-transition temperature Tgr, the positions of the chromophores will be "frozen".

[0047] Material 14a, 14b may comprise an organic dye, organic electro-op- tic polymers, chromophores, or composite materials thereof. In particular, it may include at least one of the following compounds: disperse red 1 (DR1), SEOIOO, SEO125, SEO250, GigOptixM3, JRD1, YLD124, HLD, AJCKL1, Perkinamine. It may also include any of these compounds in a host material, such as poly methyl methacrylate (PMMA), such as DR1 in PMMA or amorphous polycarbonate (APC), e g., AJCKL1 in APC.

[0048] Hence, in more general terms, the material 14a, 14b is an organic material, and the poled optical element 12a, 12b comprises the organic material.

[0049] For improved handling, mechanical stability, thermal stability, rotational stability and / or performance, the chromophores may be side groups of or embedded in a polymer, i.e., the material may comprise a polymer. Further, as mentioned, device 2 may comprise one or more waveguides 8a - 8d coupled to the poled element 12a, 12b. This optical waveguide(s) is / are part of the "first structures" of the device 2.

[0050] In interferometric devices, such as shown in Fig. 1, there may be two waveguides 8c, 8d forming two arms of an interferometer, and at least one of them is coupled to a poled element 12a, 12b.

[0051] Other devices, such as RF generators or frequency doublers or mixers, may comprise only one waveguide coupled to the poled element.

[0052] When manufacturing large numbers of devices, methods for poling the material 14a, 14b should be used that easily scale and are simple to implement. Such methods are described in the following sections.

[0053] Wafer-Level Poling

[0054] All the methods are based on forming a plurality of the devices 2 on a wafer 24 and poling the material 14a, 14b before dicing the wafer 24.

[0055] Fig. 2 schematically shows such a wafer 24 with an array of the devices 2 integrated thereon. Each device 2 is located within a device region 26. Device region 26 may be defined, e.g., as a convex hull of all elements or the device or as a minimum rectangle (as shown) enclosing all elements of the device.

[0056] The device regions 26 form a two-dimensional array, or several such arrays, on wafer 24.

[0057] The two-dimensional array on the wafer 24 may contain a plurality of identical devices 2. In other embodiments, at least some of the devices 2 may differ from each other.

[0058] If different devices 2 are arranged on wafer 24, they may, e.g., be arranged alternatingly. Alternatively, they may be arranged in spatially separated groups, with each group comprising only the same type of device.

[0059] The steps of the method are illustrated in Fig. 7.

[0060] In a first step SI, "first structures" of the devices 2 are formed in the device regions 26. These first structures may, e.g., include the following elements:

[0061] - At least some of the contact pads 20a, 20b, 20c of the device. To simplify the subsequent poling step, there may be at least one contact pad for each of the electrodes 16, 16b, 16c between which the material 14a, 14b is arranged. In an embodiment as shown in Fig. 1, with three electrodes 16a, 16b, 16c forming two gaps 18a, 18b for the material 14a, 14b, there may be three contact pads 20a, 20b, 20c. In order to simplify manufacturing, the first structures may comprise all of the contact pads 20a, 20b, 20c of the device. - The electrical leads (connectors) 28a, 28b, 28c connecting the contact pads 20a, 20b, 20c to the electrodes 16a, 16b, 16c.

[0062] - The material 14a, 14b arranged between the electrodes 16a, 16b, 16c. This material is deposited on wafer 24 in its unpoled state.

[0063] - Optionally, the first structures also include one or more waveguides 8a - 8d of device 2. In order to simplify manufacturing, the first structures include all waveguides 8a - 8d of device 2.

[0064] Methods for forming the elements of the first structure are, e.g., described in WO2023088561A1 or WO2018172302A1.

[0065] In particular, the material 14a, 14b may be applied and structured using techniques that leave it unpoled, such as coating and structuring steps or printing steps.

[0066] In a next step S2 (Fig. 7), a group of the devices 2 (i.e., of the first structures of the devices) is contacted by means of a contact member 28.

[0067] Fig. 3 shows an embodiment of such a contact member 28. It may comprise an insulating carrier plate 30, such as a plate of, e.g., glass, ceramics, or plastics, which carries a plurality of electrically conductive contact elements 32. The contact elements 32 protrude over a bottom side 34 of plate 30. They may, e.g., extend through plate 30 and be wired on top side 36 of plate 30. Alternatively, carrier plate 30 may be metallic, but the contact elements 32 are electrically insulated from it, e.g., by being placed in insulating sleeves.

[0068] The contact elements 32 may, e.g., be conductive pins or conductive bumps protruding over bottom side 34.

[0069] The contact elements 32 are arranged in a geometrical pattern matching the pattern of the contact pads 20 to be contacted.

[0070] There may be different types 32a, 32b, 32c of contact elements for being connected to different contact pads 20a, 20b, 20c. The different types of contact elements 32 may, e.g., be used to apply different voltages. There may also be fewer contact elements than contact pads.

[0071] For step S2 (and step S3 as described below), wafer 24 is placed on a support 38 as shown in Fig. 4. The contact pads 20 of the devices, which contact pads 20 are arranged on a first side 40 of wafer 24, are facing away from support 38. The opposite second side 42 of wafer 24 rests against support 38.

[0072] For contacting, contact member 28 is moved in respect to the wafer (for example, contact member 28 is moved towards wafer, or the support including wafer is moved towards the contact member 28), with its bottom side 34 facing first side 40. The contact elements 32 are brought into mechanical contact with the contact pads 20 as shown in Fig. 4.

[0073] To do so, the geometry (i.e., the locations) of the contact elements 32 must, as mentioned, match the geometry of the contact pads 20. Optical alignment marks and / or image recognition may be used to align the contact member 28 and the wafer 24 to each other, with an accuracy of, e.g., < 100 pm, better < 50 pm, ideally < 25 pm (in-plane). Rotational alignment is performed to match this accuracy on > 75% of the devices, better > 90%, ideally > 99%.

[0074] In the example of Figs. 1 and 2, where there are three contact pads 20a, 20b, 20c per device 2 that need to be contacted, there must be a set of, e.g., three contact elements 32a, 32b, 32c, at matching locations, on contact member 28. And there must be one such set for each device 2 of the group to be contacted, with the arrangement of the sets of contact elements matching the arrangement of the devices 2 on the wafer 24 that are to be contacted.

[0075] Contact member 28 may also be made from a second wafer or from a sub-element of a wafer or from a printed circuit board or from another type of substate. This substrate contains a distribution network with contact elements, matching the pattern of the contact pads 20 to be contacted.

[0076] By using contact elements such as bumps, balls, solder balls, or other conducting elements, or by direct contact of the electrodes of the substrate containing the distribution network, the respective poling voltages may be applied to the contact pads 20.

[0077] Alternatively, the wafer might be structured in such a way, that it contains cantilever or other extending structures to contact the electrodes, e.g. fabricated in a MEMS fabrication process.

[0078] Now, wafer 24 is heated, at least partially (see below), for heating the material 14a, 14b of at least part of the devices 2 to the poling temperature Tp. At the same time, voltages are applied, by means of the contact elements 32, to the electrodes 16a, 16b, 16c, in order to pole the material 14a, 14b in the gaps 18a, 18b, thereby forming the poled optical elements 12a, 12b. Next, the temperature is lowered to freeze the poling.

[0079] Note that, for expediting the process, the heating of the wafer 24 may start even before contacting the contact elements 32a, 32b, 32c. Hence, the steps of "contacting" and "heating" may start in any order, i.e., contacting may begin before heating, heating may start before contacting, or heating and contacting may begin at the same time. As described in more detail below, the present method may pole all (desired) devices 2 on wafer 24 in a single step S3, or groups of devices 2 may be poled sequentially. In the latter case, steps S2 and S3 may be repeated and a test S4 may be performed for checking if all devices 2 have been subjected to the poling process.

[0080] Once all the desired devices 2 on wafer 24 have been poled, wafer 24 may be subject to further processing steps.

[0081] In particular, optionally, "second structures" may be formed on the devices 2 of wafer 24 as indicated by step S5. Such second structures may, e.g., comprise protective layers, such as one or more of the protective structures described in WO2023088561A1. This, e.g., allows adding structures that could not withstand the poling temperatures and / or voltages or that would interfere with the poling process.

[0082] Hence, in some embodiments, the present method may comprise, after poling the material 14a, 14b of the devices 2, a step of adding at least one coating layer to the devices 2. In some embodiments at least one coating layer may be added to the device 2 and, afterwards be removed again at least partially locally in order to access, e.g., optical interfaces or contacting electrodes.

[0083] In a next step S6, the devices 2 may be tested. This includes using a dedicated test head (not sown) for contacting each device 2, or at least a sample of the devices 2, electrically as well as (optionally, if required) optically, and testing its performance in order to identify defective devices or to categorize devices based on the tested parameters (binning) such as insertion loss or modulation performance.

[0084] Finally, in step S7, wafer 24 may be diced to separate the individual devices 2.

[0085] It must be noted that the order of steps S5 - S7 may be changed. For example, the devices 2 may also be tested after dicing, and even the second structures may be formed individually on the devices 2 after dicing (e.g., as part of a packaging process). Or the testing of the devices may be performed prior to the formation of the second structures.

[0086] In yet another embodiment, which allows for faster processing, testing step S6 at least start during the loop of steps S2 - S4. In other words, while some groups still need to be subject to contacting, heating, and poling (steps S2, S3) or are in the poling process, other groups (that have already been subject to steps S2, S3) may already be tested (step S6), e.g., by means of a probe head independent from contact member 38. Global v.s. Local Poling

[0087] As mentioned, the devices 2 are poled at the wafer level, i.e., while they are still part of the wafer 24 when the material 14a, 14b is being poled.

[0088] In some embodiments, all devices 2 may be poled at the same time. In other embodiments, the devices 2 may distributed among several groups, with the groups being poled sequentially. These variants are described in more detail in the following.

[0089] In the embodiment shown in Figs. 2 and 3, contact member 28 has enough contact elements 32 to contact all devices 2 on wafer 24 in one go. Hence, there is only one group 50 of devices 2, and all devices in that group are being poled in one single step.

[0090] This allows to quickly pole all devices 2 on a wafer 24. Having a single group 50 allows to heat all the wafer, which makes it easier to maintain a homogeneous temperature distribution over the whole group.

[0091] Figs. 5 and 6, on the other hand, illustrate an embodiment using group-wise poling with several groups 50.

[0092] Here, devices 2 of the device array on the wafer 24 are grouped into several groups 50 (while in the embodiment of Figs. 2 and 3 there was only one such group), with the groups 50 being poled sequentially.

[0093] There are N such groups, with N > 1, in particular with N > 4.

[0094] Each group 50 comprises a plurality of devices 2. The number M of devices 2 and therefore of device regions 26 per group is much larger than 1. For making poling more efficient, M may be at least 16, in particular at least 100.

[0095] Since each group 50 will be heated individually while the neighboring groups are kept at lower temperatures, the groups may have "compact" (i.e., not too elongate) shape because this simplifies to maintain a homogeneous temperature distribution over a group being heated. Hence, if XI and X2 are the perpendicular extensions (i.e., the lengths, e.g., in mm) of each group along the plane of the wafer 24, e.g., along the directions of the array of devices 2, XI :X2 may be in the range of 0.25 ... 4, in particular in the range of 0.5 ... 2.

[0096] For the same reasons, each group 50 may comprise an array of several rows and of several columns of device regions 26.

[0097] For improving temperature homogeneity within a group 50 when heating it while keeping the neighboring groups 50 at a lower temperature, the wafer 24 and the device regions 26 may be structured such that the thermal conductance between adjacent device regions 26 within one group is larger than the thermal conductance between adjacent device regions 26 of neighboring groups 50. In the example of Fig. 5, for example, the thermal conductance between the adjacent device regions 26a, 26b that belong to the same group 50 is larger than the thermal conductance between adjacent device regions 26a, 26c that belong to different groups 50.

[0098] Such differences in thermal conductance can be achieved in various manners, for example:

[0099] - Slots and / or trenches 52 may be provided in wafer 24 between neighboring groups 50. In this context, a trench is a groove formed in wafer 24 that extends along the edges of the groups 50 but does not go all the way through the thickness of wafer 24. A slot is an elongate opening extending along the edges of the groups 50 that goes all the way through the thickness of the wafer 24. If slots are used, suitable bridges 54 (shown in dotted lines in Fig. 5) may be provided for interconnecting the sections of the wafer belonging to different groups 50.

[0100] - The distances DI between adjacent device regions 26 within one group 50 may be smaller than the distance D2 between adjacent device regions 26 of neighboring groups. For good thermal separation, D2 may be at least twice as large as DI.

[0101] - There may be device regions 26 between the groups 50 that contain unused devices and / or devices where a poor yield is expected.

[0102] If there are several groups 50 of devices 2, steps S2 - S4 of Fig. 7, i.e., contacting and heating / poling, are sequentially performed for all of them.

[0103] In some embodiments, in order to prevent a depoling of already poled devices 2, when a given group is at the poling temperature, the temperature difference between the device regions 26 of the given group 50 and the device regions of the other groups 50 may be at least 20°C, in particular at least 50°C.

[0104] To better control such temperature differences, the method may include the step of heating one group 50 while actively cooling at least some of the neighboring groups 50 of the one group 50. In this context, "actively cooling" may, e.g., comprise any of cooling with a pumped cooling fluid, a heat pump, or a Peltier device.

[0105] For more details about heating and cooling the groups, reference is made to the next section.

[0106] Temperature Control

[0107] As mentioned above, poling requires to increase the temperature of the material 14a, 14b of the devices 2 to be poled to the poling- temperature, which may be close to the glass-transition temperature Tgt of the material, such as no more than 10°C, in particular no more than 5°C below it.

[0108] For many typical electro-optic organic materials, the glass-transition temperature Tgt is between 100 and 250 °C.

[0109] For quick poling, the poling temperature Tp may be close to the glass-transition temperature as defined above or be at least equal to Tgt .

[0110] The poling temperature may even be up to 10°C above Tgt, i.e., Tp < Tgt + 10°C. At such higher temperatures, poling may be easier, but the temperatures should not be too high because t. Too high temperatures may cause the material to degrade, reduce the efficiency of the poling process, slow the poling cycle down, and / or it may damage other components that are already integrated on wafer 24.

[0111] The actual temperature may vary. For some devices, it may be above or below the average ideal poling temperature. This way, individual devices may not be poled ideally, but in average more devices may be closer to their ideal poling temperature. Also, the optimal poling temperature may slightly differ from device to device.

[0112] Fig. 8 (A) qualitatively shows the temperature profile of the material 14a, 14b during poling. As can be seen, the material 14a, 14b is heated and reaches its poling temperature at time tO. Fig. 8 (B) illustrates that the voltage between the electrodes 16a, 16b, 16c next to the material 14a, 14b may already be switched on before reaching the poling temperature Tgt for reasons which are explained below.

[0113] Heating is maintained up to a time tl. Then, temperature T is allowed to drop back, but the electrical field may be maintained up to a time t2 after time tl in order to reduce the material's tendency to depolarize.

[0114] At time t2, for example, the actual temperature may be at least 30°, in particular at least 50°, beneath the poling temperature Tp.

[0115] The time tl - tO during which the material 14a, 14b is at or above a the poling temperature tp may be at least 1 s for good poling.

[0116] For accurate temperature control, the temperature in wafer 24 may be measured, e.g., using a temperature sensor integrated in wafer 24 and contacted by contact member 28. The temperature sensor may be integrated by using a material with a known temperature-dependent resistivity, for example Platinum, or a material used during the forming of the first structures (SI).

[0117] Hence, in some embodiments, the method may comprise measuring a temperature in the wafer 24 by means of contacting, with the contact member 28, a temperature sensor arranged in or on the wafer 24. In that case, the temperature sensor may be used to determine the time when the poling temperature has been reached.

[0118] In some embodiments, though, the temperature T may be controlled by measuring the current I through the electrodes 16a, 16b and / or 16b, 16c during poling. This current I is shown, qualitatively, in Fig. 8 (C). To measure it, in particular around the time when reaching the poling temperature Tp, the voltage U, or a fraction of the voltage U, is switched on early in the heating cycle, at a time before tO.

[0119] As can be seen from Fig. 8 (C), as temperature T is about to reach the poling temperature Tp, current I starts to rise. It is currently believed that this may be because the dipoles in the material 14a, 14b are being aligned, which results in an electrical current. As a larger percentage of the dipoles are poled, the poling rate decreases and current I drops again.

[0120] The time when the electric field poling occurs can be detected accurately by an increase in current I. At that time, or shortly before or after it, heating may be reduced and / or completely switched off.

[0121] Hence, the method may comprise monitoring the current I flowing through the electrodes 16a, 16b and / or 16b, 16c while heating the material 14a, 14b. Heating may, e.g., be reduced or switched off at a time interval At = tl - tO after detecting a rise exceeding a given slope and / or peak in the current I. At may, for example, be in a range up to 60 seconds.

[0122] Hence, in more general terms, the method may comprise the step of monitoring, while heating, the current I through at least some of the electrodes 16a - 16c and controlling the heating as a function of the current I. For example, the heating may be switched off or reduced at a given time interval At upon detecting a rise or a peak in the current. This may include immediately switching off or reducing or actively increasing the current I upon detecting the rise or peak (i.e., At = 0), or time interval At may be larger than zero.

[0123] In one embodiment, the total current flowing through all electrodes of the currently heated group 50 may be measured. This provides a strong, easy-to- measure signal. A short-circuit in a single device 2, though, may affect such a measurement. (For dealing with short-circuits, see below.)

[0124] In another embodiment, the current though only a proper subset or several proper subsets of the electrodes of the current group may be measured.

[0125] For example, such a subset may comprise, or even consist of, electrodes of device regions 26 at an edge of the group. This is based on the understanding that devices 2 close to the edge of a group 50 may be the last one to reach the poling temperature Tp. Another possible device region 26 might be in the center of the group, where a maximum temperature is reached, or in between the center and the edge, where approximately 50% of devices will experience a lower temperature and 50% of devices will experience a higher temperature.

[0126] In some embodiments, a predefined power profile (e.g., a current profile or a voltage profile) may be used for heating. Such a profile may, e.g., have been derived from calibration measurements that were performed while measuring the temperature and adjusting the profile until it generates a desired temperature profile. This predefined power profile is then stored and used during manufacturing, which may obviate the need to monitor the temperature during poling.

[0127] Even though such a predefined power profile may be used in combination with any type of heaters (i.e., with heaters that are external from wafer 24 or integrated in wafer 24), it has best reliability when being used by feeding the power profile to one or more on-wafer heaters 57 (see below) integrated in wafer 24 because, in that case, the heat transfer between the heater and the material to be poled is subject to only small manufacturing variations.

[0128] In this case, monitoring the temperature or the poling current may, optionally, be dispensed with.

[0129] Hence, in some embodiments, the method may comprise heating of at least part of the device regions 26 of the group 50 by feeding a predefined power profile to a heater 57, in particular to at least one on-wafer heater 57 integrated in the wafer 24.

[0130] Wafer 24 and, in particular the material 14a, 14b, may be heated from the first side 40 and / or from the second side 42 of wafer 24. As mentioned, the first side 40 is defined as being the side of the contact pads 20 while the second side 42 is the side opposite to the first side 40.

[0131] In a simple implementation, for heating from the second side 42 of the wafer, support 38 may be heated. Such heating may, e.g., be implemented by resistive heating (see the schematic resistor 56 in Fig. 4). It may also be implemented using one or more Peltier devices and / or a heated fluid being circulated through support 38.

[0132] In another embodiment, for heating from the second side 42, laser irradiation 58 or non-coherent light may be used (see the schematic illustration in Fig. 4). If support 38 is transparent for the light used in this irradiation, its energy can be directly transferred to wafer 24.

[0133] Steering optics 60 may be used to deflect the irradiation. This may, e.g., be used in combination with sequentially heating several groups 50, in which case steering optics 60 may be used to direct the heating energy to the group to be heated.

[0134] In another embodiment, the irradiation can be fed through light guides or a window in support 38.

[0135] In another embodiment, the irradiation can be fed through light guides or a window in the contact member 28., or the light source might be implemented in or next to the contact member.

[0136] Hence, in more general terms, the method may comprise sending light irradiation 58 into support 38.

[0137] In some embodiments, the wafer 24, a group 50 or a device area 26 may contain an on-wafer heater as schematically shown under reference number 57 in Fig. 4. The heater 57 may be implemented by a local CMOS heater spiral or by using heater materials or conductive materials provided in the layer stack of the forming of the first structures. In some embodiments, the heater may be implemented using a BEOL processes, such as a metal, metal-oxide or metal-nitride heaters; in others embodiments, front-end processes are used to implement the heater, such as doped silicon. This way, local heating can be implemented. In this case, the contact member 28 will contain contacting contact elements independent from the poling contact elements, in order to supply electrical power to the on-wafer heaters.

[0138] Hence, in some embodiments, the wafer 24 may comprise at least one on-wafer heater 57, and the method may comprise heating the heater by feeding, through the contact member 28, a current to the heater 75.

[0139] If several groups 50 are to be heated sequentially, support 38 may also be equipped with several heating elements 62 as shown in Fig. 9. There may be N heating elements corresponding to the number of groups 50 to be heated sequentially. The heating elements 62 can be heated individually. They are located at the locations of the groups 50. In this case, the method comprises subsequently heating the heating elements 62.

[0140] In some embodiments, the heating elements 62 may be Peltier devices. In this case, the method may comprise heating one group while cooling at least some of the neighboring groups of the one group by means of sending currents in opposite directions through the Peltier devices at the one group and the Peltier devices at the at least some neighboring groups. In this case, "currents in opposite directions" are to be understood such that the current heats the wafer-facing side of the Peltier device at the one group while the current cools the wafer-facing side of the Peltier device at the neighboring group(s). In other embodiments, heating may take place, at least in part, from first side 40 of wafer 24.

[0141] In that case, for example, contact member 28 can be heated, e.g., by means of resistive heating as schematically shown by a resistor 64 in Fig. 4.

[0142] Hence, the method may comprise heating contact member 28, thereby heating the group 50. This allows heating the group 50 locally by just bringing the contact member 28 close to it.

[0143] The heat from contact member 28 may be transferred to wafer 24 through the contact elements 32, through thermal radiation, and / or through thermally conductive pads arranged at the bottom side 34 of contact member 28 (not shown) or via a thermally conductive but electrically insulating materials, such as a high-boiling point liquids or thermally conductive insulators.

[0144] When heating a group 50, at least some of the device regions 26 within the group 50 should reach the poling temperature Tp so they can be poled. The temperature of some other device regions 26 of the group may, however, stay below Tgt. This may, e.g., be the case for device regions 26 at the edge of the group. These devices may, e.g., be discarded.

[0145] For better efficiency, though, the method may comprise heating to temporarily increase the temperature of all of the devices of the group 50 to the poling temperature Tp. At the same time, the voltage is applied to the electrodes 16a, 16b, 16c by means of the contact member 28, thereby poling the material 14a, 14b in all of the device regions 26 of the group.

[0146] In some embodiments, the method may include actively cooling the group 50 at least after poling the material, optionally even during part of the poling process. This allows to accelerate the process and to "freeze" the material into its poled state more quickly. Actively cooling may, e.g., be carried out by the means described in the previous section.

[0147] Applying Voltage

[0148] The contact elements 32 must be able to feed the poling voltage to the electrodes of the devices. In the example of Fig. 2, there are three such electrodes 16a, 16b, 16c per device 2 and, therefore, there are three types of contact elements 32a, 32b, 32c. Other devices may need only two electrodes, and the number of different types of contact elements 32 would therefore only be two.

[0149] In yet other embodiments, there may be less types of contact elements than electrodes in case some of the electrodes are connected to inter-device lines feeding voltages on or through wafer 24. In some embodiments, the applied voltage may have, during a heating cycle, have an AC component in addition to a DC component. This reduces the risk of a breakdown in the material to be poled even if large fields are applied.

[0150] For a strong effect, the AC component may have an amplitude as large as the DC component. For example, the applied voltage over a material to be poled may be pulsed, i.e., it may vary, in time, between values of zero and one or more maximum values.

[0151] Hence, in more general terms, the method may comprise, during one heating cycle, a repetitive modulating, such as a pulsing, of the voltage while poling a given instance of the material between its electrodes. For example, the method may comprise pulsing the voltage while poling the material or modulating the voltage to have a DC component with an added AC component. In this case, the amplitude of the AC component may be at least equal to the DC component.

[0152] Further, the applied voltage or peak-voltage, respectively, may be constant, or it may, e.g., depend on the impedance of the element to be poled. For example, instead of applying a given voltage or peak voltage, a current or peak current may be applied, over at least some or all of the poling process.

[0153] Fig. 10 illustrates a possible wiring of contact member 28 for feeding three voltages Ul, U2, U3 to the three types of contact elements 32a, 32b, 32c (if all of the contact elements are to be used).

[0154] As can be seen, there may be one voltage feed bus 70a, 70b, 70c per voltage and per type of contact element. For at least some of the contact elements 32a, 32c, resistors Ra, Rc may be arranged between the voltage feed bus 70a, 70b, 70c and the contact elements 32a, 32c.

[0155] These resistors prevent the voltages Ul, U2, and U3 from dropping significantly if there is a short circuit or high currents caused by transients in one or a few of the devices that have to be poled.

[0156] In some embodiments, the resistors Ra, Rc may be used as resistors to sense or measure the current. Thus, voltage / current control might by locally implemented on the probe wafer / contact member.

[0157] In the embodiment of Fig. 10, there are resistors between the voltage feed buses 70a, 70c and the contact elements 32a, 32c, with the contact elements 32a, 32c feeding voltages to the outer two electrodes 16a, 16c of the three electrodes 16a, 16b, 16c. Alternatively, there may be resistors only between feed bus 70b and the contact elements 32b for the central electrode 16b, or there may be resistors between all three feed busses 70a, 70b, 70c and their attributed contact elements 32a, 32b, 32c. If there are only two contacts, both or only one of them may be contacted via a resistor.

[0158] Further, or alternatively, there may be current limiting diodes or circuits between at least some of the contact elements and the feed busses to prevent reduction or break-down of the voltages Ul, U2, and U3 in case the electrical source cannot provide necessary electrical power.

[0159] Hence, more generally, contact member 28 may comprise one or more voltage feed busses 70a, 70b, 70c and a plurality of current limiters, such as resistors Ra, Rc or current limiting diodes or circuits, between at least one of the voltage feed buses 70a, 70b, 70c and contact elements 32a, 32b, 32c attributed to the at least one of the voltage feed busses. For poling, a voltage is applied to the attributed contact elements 32a, 32b, 32c through the at least one voltage feed bus 70a, 70b, 70c and the resistors Ra, Rc.

[0160] If resistors are used, the resistance of the resistors Ra, Rc may be selected to be large enough to prevent excessive current flow in the presence of a short circuit but small enough to exhibit a too large voltage drop during the current peak while poling. Hence, it may, e.g., be selected to be between the minimum resistance Rmin of the material 14a, 14b during poling but larger than Rmin / 100.

[0161] For example, the resistance of the resistors may be between 10 kQ and 1 MO.

[0162] In some embodiments, the electric current is not limited by a current limiting resistor, diode or circuit. In this case, the electrical source as well as the contact member and voltage feed bus may be designed to allow for currents of a multiple of the maximum poling current per device times the number of devices. In case of a short circuit in one or multiple devices, the electrical source can supply the respective short-circuit current while maintaining the desired voltage. The poling process can continue. Individual short-circuited devices might act as a fuse, or the electrical lead may be designed in such a way that it acts as electrical fuse. In case of a short-circuit, the increased current provided by the electrical source will melt or destroy the on- chip fuse and disconnect the short circuit.

[0163] The applied voltages may depend on the distance between the electrodes 16a and 16b or 16b and 16c, or the combination of these distances. In one group 50, there may be devices with different electrode distances. These devices may be contacted with different voltages U. For examples, some devices may have a distance between the electrodes of 100 nm while other devices may have a distance between the electrodes of 150 nm. In this case, the voltage applied between the electrodes of device with 150nm may be 1.5 times higher than the voltage applied to the device with 100 nm.

[0164] In an embodiment such as shown in Fig. 1, where at least two sections of material 14a, 14b between at least three electrodes 16a, 16b, 16c are arranged electrically in series, the poling voltage may also be applied to the outmost electrodes 14a, 14c only while leaving the center electrode(s) at floating potential. In this case, a higher poling voltage may be used to account for the voltage being divided among the sections of material.

[0165] In some embodiments, a device may comprise different electro-optical or nonlinear-optical elements, e.g., a double-gap interferometer as shown in Fig. 1 and a ring modulator, with these two elements requiring different voltages during poling.

[0166] In some embodiments, the applied voltage may not be a constant voltage. For example, the applied voltage may be controlled to generate a desired current, or, as mentioned, the applied voltage may be fed through a resistor or other element that generates a current-dependent voltage drop.

[0167] Notes

[0168] In the examples above, wafer 24 is placed on support 38 beneath it and then contacted by contact member 28 from above. In other embodiments, contact member 28 may also act as a support, in which case first side 40 and the contact elements 32 are arranged to face downwards.

[0169] As mentioned above, the present method obviates the need for dedicated poling lines, or at least reduces their number. For example, the devices may not comprise dedicated poling lines at all. In another embodiment, there may still be a dedicated poling lines that are connected to a subset of the electrodes, which already simplifies the geometry of the wafer design.

[0170] In some examples, several neighboring individual devices may be interconnected with local poling lines, and only one of them will be contacted by the contact member.

[0171] In the examples above, only a single contact member is used for processing the whole wafer. In other embodiments, two or more contact members may be used, which process the wafer concurrently. Each contact member goes step- by-step through unpoled areas until all of them are poled. In this case, several areas of the wafer are heated concurrently.

[0172] While there are shown and described presently preferred embodiments of the invention, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.

Claims

Claims1. A method for manufacturing integrated optics devices (2), wherein each device (2) comprises electrical contact pads (20) and at least one poled optical element (12a, 12b), and wherein the method comprises forming, on a wafer (24), first structures of a plurality of the devices (2) in a two-dimensional array of device regions (26), wherein, within each device region, the first structures of one of the devices (2) are formed, with the first structures comprising at least some of the contact pads (20) of the device (2), electrodes (16a, 16b, 16c) electrically connected to the contact pads (20), and at least one unpoled dielectric or semiconducting material (14a, 14b) between the electrodes (16a, 16b, 16c), contacting at least one group (50) of several the devices (2) by means of a contact member (28), wherein the contact member (28) comprises a plurality of electrically conductive contact elements (32), and wherein the contact elements (32) are brought into direct contact with at least part of the contact pads (20) of at least some of the devices (2) of the group (50), heating, in order to temporarily increase a temperature of the material (14a, 14b) of at least part of the device regions (26) of the group (50) to a poling temperature, while applying, by means of the contact member (28), voltage to the electrodes (16a, 16b, 16c), thereby poling the material (14a, 14b).

2. The method of claim 1 wherein the poling temperature (Tp) is at least Tgt - 10°C, in particular at least Tgt - 5°C, with Tgt being the glass-transition temperature of the material (14a, 14b).

3. The method of any of the preceding claims wherein the material (14a, 14b) is an organic material, and the poled optical element (12a, 12b) comprises an organic material.

4. The method of any of the preceding claims wherein material (14a, 14b) comprises a polymer.

5. The method of any of the preceding claims wherein each device (2) comprises an optical waveguide (8a - 8d), in particular a plasmonic optical waveguide, coupled to the poled element (12a, 12b).

6. The method of any of the preceding claims wherein there is only one group (50) of devices (2) on the wafer (24).

7. The method of any of the claims 1 to 5 wherein there are N groups (50) 1 ... N of devices (2), with N > 1, and the method comprises subsequently contacting and heating and poling the materials (14a, 14b) in each group (50).

8. The method of claim 7 wherein, when a given group (50) is at the poling temperature (Tp), a temperature difference between the device regions (26) of the given group (50) and the device regions of other groups (50) is at least 20°C, in particular at least 50°C.

9. The method of claim 8 comprising heating one group (50) while actively cooling at least some of the neighboring groups (50) of the one group (50).

10. The method of any of the claims 7 to 9 wherein a thermal conductance between adjacent device regions (26) within one group (50) is larger than a thermal conductance between adjacent device regions (26) of neighboring groups (50).

11. The method of claim 10 comprising at least one of slots and trenches (52) in said wafer (24) between all neighboring groups (50).

12. The method of any of the claims 10 or 11 wherein a distance (DI) between adjacent device regions (26) within one group (50) is smaller than a distance (D2) between adjacent device regions (26) of neighboring groups (50).

13. The method of any of the preceding claims comprising the step of contacting the wafer (24) with the contact member (28) from a first side (40) of the wafer (24) while heating the wafer (24) from a second side (42) of the wafer.

14. The method of claim 13 where, at said second side, the wafer (24) rests against a support (38), wherein the support (38) is heated.

15. The method of any of the claims 7 to 12 and of claim 14 wherein the support (38) comprises N heating elements (62) located at said groups (50), wherein the method comprises subsequently heating said heating elements (62).

16. The method of claims 9 and 15 wherein the heating elements (62) are Peltier devices, wherein the method comprises sending currents in opposite directions through a Peltier device at the one group (50) and through a thermopile at at least one neighboring group (50).

17. The method of any of the preceding claims comprising the step of heating the wafer (24) by means of light irradiation (58).

18. The method of any of the claims 13 to 16 and of claim 17 wherein, at said second side, the wafer (24) rests against a support (38), wherein the light irradiation (58) is sent into and / or through the support (38).

19. The method of any of the preceding claims comprising the step of contacting the wafer (24) with the contact member (28) from a first side (40) of the wafer (24) while heating the wafer (24) from the first side (40).

20. The method of claim 19 comprising heating the contact member (28), thereby heating the group (50).

21. The method of any of the preceding claims, wherein the wafer comprises at least one on-wafer heater (57), and wherein the method comprises heating the heater (57) by feeding, through the contact member (28), a current to the heater (57).

22. The method of any of the preceding claims wherein the group (50) comprises at least 16 device regions (26), in particular at least 100 device regions (26).

23. The method of any of the preceding claims wherein, if XI and X2 are perpendicular extensions of each group (50) along a plane of the wafer (24), X1:X2 is in a range of 0.25 ... 4, in particular 0.5 ... 2.

24. The method of any of the preceding claims comprising, after poling the material (14a, 14b) of the devices (2), adding at least one coating layer to said devices (2).

25. The method of any of the preceding claims further comprising heating, in order to temporarily increase the temperature of all of the devices (2) of the group (50) to the poling temperature (Tp) while applying, by means of the contact member (28), the voltage to the electrodes (16a, 16b, 16c), thereby poling the material (14a, 14b).

26. The method of any of the preceding claims comprising monitoring, while heating, a current (I) through the electrodes (16a, 16b, 16c) and controlling the heating as a function of the current.

27. The method of claim 26 comprising switching off or reducing the heating at a given time interval (At) upon detecting a rise and / or peak in the current (I).

28. The method of any of the claims 26 or 27 comprising measuring a total current flowing through all electrodes (16a, 16b, 16c) of the group (50).

29. The method of any of the claims 26 or 27 comprising measuring a current though only at least one proper subset of the electrodes (16a, 16b, 16c) of the group (50).

30. The method of claim 29 wherein the subset comprises, in particular consists of, electrodes (16a, 16b, 16c) in device regions (26) at least at one of an edge of the group (50) and a center of the group (50).

31. The method of any of the preceding claims comprising measuring a temperature in the wafer (24) by means of electrically contacting, with the contact member (28), a temperature sensor arranged in or on the wafer (24).

32. The method of any of the preceding claims wherein the contact member (28) comprises one or more voltage feed busses (70a, 70b, 70c) and a plurality of current limiters (Ra, Rc) between at least one of the voltage feed buses (70a,70b, 70c) and contact elements (32) attributed to the at least one of the voltage feed busses (70a, 70b, 70c), wherein, for poling, a voltage (Ul, U2, U3) is applied to the attributed contact elements (32a, 32b, 32c) through the at least one voltage feed bus (70a, 70b, 70c) and the current limiters (Ra, Rc).

33. The method of any of the preceding claims comprising repetitive modulating the voltage while poling the material (14a, 14b).

34. The method of claim 33 comprising at least one of: pulsing the voltage while poling the material (14a, 14b), and modulating the voltage to have a DC component and an AC component, with an amplitude of the AC component being at least equal to the DC component while poling the material (14a, 14b).

35. The method of any of the preceding claims comprising actively cooling the group (50) at least after poling the material (14a, 14b).

36. The method of any of the preceding claims comprising heating of at least part of the device regions (26) of the group (50) by feeding a predefined power profile to a heater (57), in particular to at least one on-wafer heater (57) integrated on the wafer (24).

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