Converter controller with improved specification function for the pulse frequency

Abstract

A converter controller (4) repeatedly receives a new target value (I*) for an electrical variable (I) at a sampling frequency (fS) from a higher-level control device (5). The converter controller (4) determines control signals (C) for semiconductor switches (6) of a converter (2) at a pulse frequency (fP) and controls the semiconductor switches (6) accordingly at the pulse frequency (fP) such that the converter (2) provides the electrical variable (I) corresponding to the respective target value (I*) to a load (1) supplied with electrical energy via the converter (2). The converter controller (4) receives a desired value (fW) for the pulse frequency (fP) via an interface (10), and the converter controller (4) determines the pulse frequency (fP) in such a way that the pulse frequency (fP) is as close as possible to the desired value (fW) for the pulse frequency (fP) and satisfies the condition: pulse frequency (fP) = n1 / n2 x sampling frequency (fS), where n1 and n2 are natural numbers and n2 does not exceed a specified maximum value (n2max).

Description

[0001] Description

[0002] Inverter control with improved pulse frequency specification

[0003] The present invention relates to an operating method for a converter control system,

[0004] - wherein the inverter control repeatedly receives a new setpoint for an electrical quantity from a higher-level control unit at a sampling frequency,

[0005] - wherein the inverter control determines control signals for semiconductor switches of an inverter using a pulse frequency and controls the semiconductor switches accordingly with the pulse frequency, so that the inverter provides the electrical quantity corresponding to the respective setpoint to a load supplied with electrical energy via the inverter,

[0006] - where the inverter control receives a desired value for the pulse frequency via an interface.

[0007] The electrical quantity is typically a current. In some cases, however, it can also be a voltage. The load can be, in particular, an electric machine. The control signals can be, in particular, pulse-width modulated. The pulse frequency can be specified to the inverter control via the interface. These facts apply both in the prior art and within the scope of the present invention.

[0008] The present invention further refers to a control program, wherein the control program comprises commands which, when executed by a converter control, cause the converter control to execute such an operating procedure.

[0009] The present invention further relates to a converter control, wherein the converter control is programmed with such a control program, so that the converter control executes such an operating procedure during operation.

[0010] The items mentioned are generally known.

[0011] It is known in the prior art to set the pulse frequency such that the quotient of pulse frequency and sampling frequency is a (positive or negative) power of 2. Thus, if—for example—the sampling frequency is 8 kHz, the pulse frequency using this method could be, for example, 2 kHz, 4 kHz, 8 kHz, 16 kHz, or 32 kHz. While this method of specifying the pulse frequency offers some flexibility, it is rather imprecise. For example, there are no intermediate values ​​between 4 kHz and 8 kHz or between 8 kHz and 16 kHz to which the pulse frequency could be set.

[0012] It is also known in the prior art to set the pulse frequency continuously or quasi-continuously, i.e., to any or nearly any value, optionally within a predetermined range. For example, with this approach, at a sampling frequency of 8 kHz, the pulse frequency can be set by an operator completely continuously or in small steps of 1 Hz. The possibility of continuous or quasi-continuous setting can be limited to a predetermined range, for example, between 4 kHz and 8 kHz.

[0013] While this method of setting the pulse frequency is very flexible, there is a risk that an unfavorable pulse frequency setting may negatively affect the load control. In particular, so-called beat frequencies can occur. The possible beat frequencies are given by the difference between k1 times the pulse frequency and k2 times the sampling frequency, where k1 and k2 are natural numbers. If fB (where B stands for beat) denotes the beat frequency, fP the pulse frequency, and fS (where S stands for sample) the sampling frequency, then fB = |k1fP - k2fS|. Therefore, with an unfavorable pulse frequency choice, the beat frequency can become very low.If, for example, the sampling frequency is 8 kHz and the pulse frequency is set to 5.999 kHz or 6.001 kHz, a beat frequency of 4 Hz could result. This is because 4 x 6.001 kHz - 3 x 8 kHz equals 4 Hz.

[0014] The same applies, because only the amplitude matters, to 4 x 5.999 kHz - 3 x 8 kHz. Here too, a beat frequency of 4 Hz can occur. Therefore, if, for example, a pulse frequency of 6.000 kHz is to be set, the pulse frequency must be set very precisely to avoid beat frequencies.

[0015] The object of the present invention is to provide a means by which, on the one hand, a relatively fine adjustment of the pulse frequency is possible, while on the other hand, low-frequency beats are reliably avoided. This object is achieved by an operating method with the features of claim 1. Advantageous embodiments of the operating method are the subject of dependent claims 2 to 9.

[0016] According to the invention, an operating method of the type mentioned above is designed by:

[0017] - that the inverter control determines the pulse frequency in such a way that the pulse frequency is as close as possible to the desired value for the pulse frequency and that the condition pulse frequency = n1 / n2 x sampling frequency is met,

[0018] - where n1 and n2 are natural numbers and n2 does not exceed a predetermined maximum value.

[0019] The condition pulse frequency = n1 / n2 x sampling frequency ensures that the frequency of a beat is at a value of 1 / n2 x sampling frequency or an integer multiple thereof. The ability to freely choose n1 allows the (actual) pulse frequency to be at least close to the desired value. By specifying a sufficiently large maximum value, a sufficient number of permissible values ​​are allowed within a given frequency interval.

[0020] It is possible for the inverter control to offer permissible values ​​for the desired pulse frequency within a continuum of values ​​via the interface. Alternatively, it is possible for the inverter control to offer permissible values ​​for the desired pulse frequency only as discrete values ​​that can be used directly and immediately as the pulse frequency. Which of these two approaches is used can be decided based on the specific circumstances. In both cases, the specification can be limited to a predefined range of values.

[0021] Preferably, the inverter control outputs the pulse frequency via the interface. This ensures that the unit specifying the desired pulse frequency knows the actual pulse frequency.

[0022] Preferably, the predetermined maximum value is at least 5, in particular at least 9, and / or at most 20. Even a value of 5 achieves a gradation of the permissible pulse frequency values, albeit a relatively coarse one. A value of 9 achieves a relatively fine gradation of the permissible pulse frequency values. A value of 20, in conjunction with the sampling frequency, ensures that the frequency of any beat frequency adheres to a predetermined minimum value – namely, 1 / 20 of the sampling frequency.

[0023] Alternatively, the inverter control can receive the maximum value or minimum distance that each integer multiple of the pulse frequency should maintain from each integer multiple of the sampling frequency via the interface. In this case, the inverter unit can be specified the minimum frequency that a beat frequency must exhibit. If the maximum value is specified, the specifying unit indirectly determines the predetermined minimum value of any beat frequency; if the minimum distance is specified, it does so directly.

[0024] The inverter control usually receives the sampling frequency from the higher-level control unit.

[0025] The interface can be, in particular, a user interface through which the inverter control unit communicates with an operator. In this case, the operator specifies parameters for the inverter unit (for example, the desired pulse frequency), and the inverter unit sends output to the operator via the interface.

[0026] Preferably, the inverter control sets the pulse frequency using a phase-locked loop (PLL). This ensures that the pulse frequency actually corresponds to the desired value of n1 / n2 x sampling frequency.

[0027] The problem is further solved by a control program with the features of claim 10. According to the invention, when executed by the inverter control, the commands of the control program cause the inverter control to execute an operating method according to the invention.

[0028] The problem is further solved by a converter control unit with the features of claim 11. According to the invention, the converter control unit is programmed with the commands of a control program according to the invention, so that the converter control unit executes an operating procedure according to the invention during operation.

[0029] The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more readily understandable in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings. Here, FIG. 1 shows a schematic block diagram,

[0030] FIGS. 2 to 6 Flowcharts and

[0031] FIG 7 is a block diagram.

[0032] As shown in FIG. 1, an electrical load 1 is supplied with electrical energy from an electrical energy source 3 via an inverter 2. The electrical load 1 is typically an electric machine. The electrical energy source 3 can be a battery or another DC source, or an AC source, in particular a single-phase AC network or – as shown in FIG. 1 – a multi-phase AC network. The inverter 2 is controlled by an inverter controller 4.

[0033] During operation, the inverter control unit 4 continuously receives a new setpoint I* for an electrical quantity I from a higher-level control unit 5. The respective setpoint I* can, for example, be a current setpoint, and the electrical quantity I a current. This setpoint is received at a sampling frequency fS of, for example, 8 kHz. During operation, the inverter control unit 4 also determines control signals C for semiconductor switches 6 of the inverter 2 and controls the semiconductor switches 6 accordingly. Typically, the inverter 2 has several semiconductor switches 6, for example, a total of six semiconductor switches 6 for three switching bridges, each comprising two semiconductor switches 6. The control signals C are determined such that the electrical quantity I supplied by the inverter 4 to the load 1 corresponds to the respective setpoint I*.The control signals C are determined taking into account the respective setpoint I*. The determination of the control signals C and the control of the semiconductor switches 6 are carried out using a pulse frequency fP. The pulse frequency fP can, for example, be in the range between 2 kHz and 16 kHz.

[0034] The higher-level control unit 5 not only specifies a new setpoint I* at each sampling frequency fS. It also receives values ​​at the same sampling frequency fS, for example, a value for the electrical quantity I and / or a sensor signal x from a sensor 7, by means of which a state of the load 1 is detected. The sensor signal x can, for example, be a position value or a speed value, and the sensor 7 a corresponding encoder.

[0035] The inverter controller 4 is programmed with a control program 8. The control program

[0036] 8 comprises commands 9 which, when executed by the inverter control 4, cause the inverter control 4 to execute an operating procedure that includes the measures described above and also the measures additionally explained below in conjunction with FIG. 2. Programming the inverter control 4 with the control program 5 thus causes the inverter control 4 to execute such an operating procedure during operation.

[0037] According to FIG. 2, the inverter control 4 is first informed of the sampling frequency fS in step S1. For example, the inverter control 4 can receive the sampling frequency fS from the higher-level control unit 5. In step S2, the inverter control 4 receives a desired value fW for the pulse frequency fP. The desired value fW is received via an interface 10. The interface 10 can, for example, be an operator interface through which the inverter control 4 communicates with an operator 11. The operator 11 can thus specify the desired value fW via the operator interface 10.

[0038] In step S3, the inverter control 4 determines the pulse frequency fP. This determination is performed such that the pulse frequency fP is as close as possible to the desired value fW for the pulse frequency fP and also has a (precise) rational ratio to the sampling frequency fS. The pulse frequency fP is thus determined such that the condition fP = n1 / n2 x fS is satisfied. Here, n1 and n2 are natural numbers. n1 can have any value (but of course, it must be positive). n2, on the other hand, has a minimum of 1 and a maximum of a predetermined value n2max. The predetermined maximum value n2max must be sufficiently high. Typically, the predetermined maximum value n2max is at least 5. Preferably, the maximum value n2max is greater than 5 and at least 9. However, typically, the maximum value n2max is at most 20.

[0039] The specific values ​​used for n1 and n2 – for example, 4 and 7 – are therefore determined by the inverter control unit 4 itself. Only the range within which the numerical value n2 must lie is fixed.

[0040] In step S4, the inverter control 4 outputs the pulse frequency fP via interface 10. Step S4 is optional and is therefore only shown as a dashed line in FIG. 2.

[0041] According to FIG. 2, the inverter control 4 executes steps S5 to S7, building upon step S3 or step S4. In step S5, the inverter control 4 receives a new setpoint I*. In step S6, the inverter control 4 determines the control signals C. In step S7, the inverter control 4 controls the semiconductor switches 6 according to the determined control signals C. Step S5 is repeated continuously with a sampling cycle time TS, where the sampling cycle time TS is equal to the reciprocal of the sampling frequency fS. Steps S6 and S7 are repeated continuously with a pulse cycle time TP, where the pulse cycle time TP is equal to the reciprocal of the pulse frequency fP.

[0042] The desired value fW for the pulse rate fP can be specified in various ways.

[0043] For example, as shown in FIG. 3, step S2 of FIG. 2 can be implemented as steps S11 and S12. In step S11, the inverter control 4 offers the operator 11, for example, permissible values ​​for the desired value fW for the pulse frequency fP within a value continuum or a quasi-value continuum via interface 10. As shown in FIG. 3, the value continuum can be limited to a predetermined value range extending from a minimum frequency fmin to a maximum frequency fmax. In step S12, the inverter control receives the value fW specified via interface 10.

[0044] Alternatively, as shown in FIG. 4, step S2 of FIG. 2 can be implemented as steps S21 to S23. In step S21, the inverter control 4 determines permissible values ​​fWi for the desired value fW for the pulse frequency fP. The inverter control 4 traverses a specific range of values ​​for the number n1 and also for the number n2, determining a permissible value fWi = n1 / n2 x fS for each pair of natural numbers n1 and n2. The range of values ​​for n2 extends from 1 to the maximum value n2max. The range of values ​​for n1 extends from 1 to a (further) maximum value. This further maximum value can alternatively be independent of the respective value for n2 or dependent on the respective value for n2. Thus, in step S21, the inverter control 4 determines discrete values ​​fWi that the pulse frequency fP can assume.In step S22, the inverter control 4 offers the operator 11, for example, the determined permissible values ​​fWi for selection via interface 10. If necessary, the determined permissible values ​​fWi can be limited to a predetermined frequency range between the minimum and maximum frequencies fmin and fmax. In step S23, the inverter control 4 receives the desired value fW via interface 10. In the configuration according to FIG. 4, step S3 of FIG. 2 is degenerate. This is because the determination of the possible pulse frequencies fP was already carried out in step S21. The inverter control 4 can therefore directly and without modification accept the value fW specified in step S23 as the pulse frequency fP.

[0045] In many cases, the maximum value n2max of the inverter controller 4 is fixed. However, it is also possible for the inverter controller 4 to receive the maximum value n2max via interface 10. For example, as shown in FIG. 5, a step S31 may be present after step S1. In step S31, the inverter controller 4 receives the maximum value n2max. Alternatively, step S31 could also be executed before step S1 or after step S2.

[0046] It is possible to freely specify the maximum value n2max. However, often a lower and / or upper limit for the maximum value n2max is defined within the inverter control 4. If – purely as an example – the lower limit for the maximum value n2max is 4 and the upper limit for the maximum value n2max is 50, the maximum value n2max can be specified as needed via interface 10, but only between a value of 4 and a value of 50.

[0047] Equivalent to directly specifying the maximum value n2max, as shown in FIG. 6, is the case if the inverter control 4 receives a minimum distance öfmin via interface 10 in step S41. The minimum distance öfmin specifies the distance that each integer multiple of the pulse frequency fP should maintain from each integer multiple of the sampling frequency fS. For arbitrary natural numbers k1, k2, the relationship |k1fP-k2fS| > öfmin should therefore hold.

[0048] In this case, the inverter control 4 can determine the maximum value n2max from the sampling frequency fS and the specified minimum interval öfmin. The inverter control 4 only needs to calculate the quotient of the sampling frequency fS and the specified minimum interval öfmin in step S42 and take the integer part of this result. If, for example, the sampling frequency fS is 8 kHz and the minimum interval öfmin is specified as 850 Hz, the quotient yields a value of slightly over 9.4. The integer part, and thus the maximum value n2max, is therefore 9 in this case. Steps S41 and S42 can alternatively be executed before step S1, between steps S1 and S2, or after step S2. The pulse frequency fP must not only be determined precisely, but it must also be maintained precisely. For this purpose, the inverter control 4 can have a phase-locked loop 12, as shown in FIG. 7.In this case, the phase-locked loop 12 is fed clock signals clk, clk', which oscillate at the sampling frequency fS and the pulse frequency fP. Clock multiplication is performed via multipliers 13, to which the natural numbers n1 and n2 are fed. The output signals of the multipliers 13 are fed to an error detection device 14, which in turn drives a voltage-controlled oscillator 15. The voltage-controlled oscillator 15 generates the clock signal clk, which oscillates at the pulse frequency fP. With the exception of the voltage-controlled oscillator 15, the phase-locked loop 11 can be implemented analogously or digitally, as required. The voltage-controlled oscillator 15 is always implemented analogously.

[0049] The present invention has many advantages. On the one hand, a fairly fine, though not arbitrary, gradation of the pulse frequency fP is possible. If the maximum value n2max for the natural number n2 is 9, then, with a sampling frequency fS of 8 kHz, the following pulse frequencies fP are possible in the range between 4 kHz and 8 kHz – in addition to 4 kHz and 8 kHz (the pulse frequencies given are rounded to the nearest 10 Hz):

[0050] 4.44 kHz (for n1 = 5 and n2 = 9) 6.22 kHz (for n1 = 7 and n2 = 9)

[0051] 4.57 kHz (for n1 = 4 and n2 = 7) 6.40 kHz (for n1 = 4 and n2 = 5)

[0052] 4.80 kHz (for n1 = 3 and n2 = 5) 6.67 kHz (for n1 = 5 and n2 = 6)

[0053] 5.00 kHz (for nl = 5 and n2 = 8) 6.86 kHz (for n1 = 6 and n2 = 7)

[0054] 5.33 kHz (for nl = 2 and n2 = 3) 7.00 kHz (for nl = 7 and n2 = 8)

[0055] 5.71 kHz (for nl = 5 and n2 = 7) 7.11 kHz (for nl = 8 and n2 = 9)

[0056] 6.00 kHz (for n1 = 3 and n2 = 4)

[0057] Nevertheless, for each of the specified pulse frequencies fP, it is achieved that any beat frequency has a frequency of at least 8 kHz - 7.11 kHz = 0.89 kHz or generally of fS / n2max.

[0058] Although the invention has been further illustrated and described in detail by the preferred embodiments, the invention is not limited by the disclosed examples and other variations can be derived from them by a person skilled in the art without departing from the scope of protection of the invention. List of reference numerals

[0059] 1 Last

[0060] 2 inverters

[0061] 3 Energy source

[0062] 4 Inverter control

[0063] 5 higher-level control unit

[0064] 6 semiconductor switches

[0065] 7 Sensor

[0066] 8 Tax program

[0067] 9 commands

[0068] 10 Interface

[0069] 11 Operator

[0070] 12 phase-locked loop

[0071] 13 Multipliers

[0072] 14 Fault detection device

[0073] 15 voltage-controlled oscillator

[0074] C Control signals clk, clk' Clock signals fmax Maximum frequency fmin Minimum frequency fP Pulse frequency fS Sampling frequency fW Desired value fWi Permissible values

[0075] I electrical quantity

[0076] I* Setpoint n1 , n2 natural numbers n2max Maximum value

[0077] S1 to S42 steps

[0078] TP, TS cycle times x sensor signal öfmin minimum distance

Claims

Patent claims 1. Operating procedure for a converter control (4), - wherein the inverter control (4) receives a new setpoint (I*) for an electrical quantity (I) repeatedly from a higher-level control unit (5) at a sampling frequency (fS), - wherein the inverter control (4) determines control signals (C) for semiconductor switches (6) of an inverter (2) at a pulse frequency (fP) and controls the semiconductor switches (6) accordingly at the pulse frequency (fP), so that the inverter (2) provides the electrical quantity (I) corresponding to the respective setpoint (I*) to a load (1) supplied with electrical energy via the inverter (2), - wherein the inverter control (4) receives a desired value (fW) for the pulse frequency (fP) via an interface (10), characterized by , - that the inverter control (4) determines the pulse frequency (fP) in such a way that the pulse frequency (fP) is as close as possible to the desired value (fW) for the pulse frequency (fP) and fulfills the condition pulse frequency (fP) = n1 / n2 x sampling frequency (fS), - where n1 and n2 are natural numbers and n2 does not exceed a predetermined maximum value (n2max).

2. Operating method according to claim 1, characterized in that the inverter control (4) offers permissible values ​​for the desired value (fW) for the pulse frequency (fP) within a value continuum for selection via the interface (10).

3. Operating method according to claim 1, characterized in that the inverter control (4) offers permissible values ​​(fWi) for the desired value (fW) for the pulse frequency (fP) via the interface (10) only as discrete values ​​for selection, which can be used directly and immediately as pulse frequency (fP).

4. Operating method according to claim 1, 2 or 3, characterized in that the inverter control (4) outputs the pulse frequency (fP) via the interface (10).

5. Operating method according to one of claims 1 to 4, characterized in that the predetermined maximum value (n2max) is at least 5, in particular at least 9, and / or at most 20.

6. Operating method according to one of claims 1 to 4, characterized in that the inverter control (4) receives the maximum value (n2max) or a minimum distance (öfmin) that each integer multiple of the pulse frequency (fP) is to maintain from each integer multiple of the sampling frequency (fS) via the interface (10).

7. Operating method according to one of the above claims, characterized in that the inverter control (4) receives the sampling frequency (fS) from the higher-level control unit (5).

8. Operating method according to one of the above claims, characterized in that the interface (10) is an operator interface via which the inverter control (4) communicates with an operator (11).

9. Operating method according to one of the above claims, characterized in that the inverter control (4) sets the pulse frequency (fP) by means of a phase-locked loop (12).

10. Control program, wherein the control program comprises commands (9) which, when executed by a converter control (4), cause the converter control (4) to execute an operating procedure according to one of the above claims.

11. Inverter control, wherein the inverter control is programmed with a control program (8) according to claim 10, such that the inverter control performs an operating procedure according to one of claims 1 to 9 during operation.

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