Control of quantum informatics processes

Abstract

Apparatus for controlling a quantum informatics apparatus (QIA) that comprises quantum systems and devices operative to control quantum states of the quantum systems includes plural of instruction queuing units (IQUs). Each of the IQUs comprises a data processor, a queue, and queue control logic. Each IQU is associated with a corresponding device. Each queue is configured to hold micro- instructions for controlling the corresponding device and an associated time point. The data processor is configured to insert micro-instructions for controlling the device into the queue based on process program execution instructions. The queue control logic is configured to release the micro-instructions for controlling the corresponding device at times based on the time points. The design of the apparatus is readily scalable. Dedicated data processors for processing program execution instructions for each device reduces the possibility of conflicts.

Description

CONTROL OF QUANTUM INFORMATICS PROCESSESCross-Reference to Related Application

[0001] This application claims priority from US application No. 63 / 671 ,906 filed 16 July 2024 and entitled CONTROL OF QUANTUM INFORMATICS PROCESSES which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No. 63 / 671 ,906 filed 16 July 2024 and entitled CONTROL OF QUANTUM INFORMATICS PROCESSES which is hereby incorporated herein by reference for all purposes.Field

[0002] This disclosure relates to methods and apparatus for controlling quantum informatics processes.Background

[0003] Quantum informatics (“QI”) is a rapidly developing field. Quantum informatics involves storing and / or manipulating information represented by the state of one or more quantum systems. Quantum informatics includes the field of computing. Quantum information may, for example, be represented by the states of quantum systems as diverse as photons, Josephson junctions (superconducting qubits), the intrinsic spins of subatomic particles (e.g. electrons, atomic nuclei) or of quasi particles (e.g. holes, excitons), trapped ions, trapped neutral atoms and other physical systems that have quantum states that can be used to store information.

[0004] Since quantum systems can exist in superpositions of different quantum states, the stored information may be defined by a particular superposition of quantum states. For example, a quantum system may have first and second quantum basis states: |i l > and |i 2 >. Information may be stored in the quantum system by setting the system to a quantum state given by the superposition: a|i l > +p |i 2 > where a and p are complex valued coefficients. For example, the quantum system may comprise a spin % particle, e.g. an electron, which has two basis spin states which may be represented as |T) and |i) (spin up and spin down respectively). For example, the spin up state may be associated with the value “1” or “TRUE” and the spin down state may be associated with the value “0” or “FALSE” or vice versa. At a given time, the quantum system may be in either one of these basis spin states or ina quantum superposition of these basis spin states.

[0005] Quantum information represented by the quantum state of a quantum system may be manipulated in various ways such as by one or more of: applying quantum gates to the quantum system, allowing the quantum system to interact with another quantum system in a defined manner, making a measurement on the quantum system, causing the quantum system to be entangled with another quantum system, making measurements on another quantum system that is entangled with the quantum system etc.

[0006] Algorithms have been developed for performing a wide range of calculations by quantum informatics processing. Such quantum algorithms promise dramatic improvements in speed as compared to conventional digital computing. The predicted speed improvement becomes more significant as the “size” of the problem increases.

[0007] As the field of quantum informatics advances, the demands for quantum informatics apparatus capable of performing computations on larger sets of quantum information drives the need for quantum informatics apparatus that includes larger and larger numbers of quantum systems together with apparatus for managing and manipulating quantum information stored in those quantum systems. The number of quantum systems desired in a quantum informatics apparatus increases rapidly as the quantum informatics apparatus is scaled up to handle larger problems. Four factors that tend to increase the desired number of quantum systems are: the size of the problems that the apparatus is designed to process, quantum error correction, the use of quantum entanglement to facilitate operations on two or more quantum systems (especially when the quantum systems in the quantum informatics apparatus are not all in close physical proximity to one another), and the use of additional quantum systems which may act as ancilla qubits and / or client / broker systems to facilitate computations and / or preserve fidelity of quantum information.

[0008] A problem with storing information in the quantum state of a quantum system is that the information can become randomized as a result of external interactions in a process called “decoherence”. “Noise” of any type including exposure to light, other electromagnetic radiation, fluctuating electric or magnetic fields or thermal energy can increase the rate of decoherence. Coupling a quantum system to interact with other quantum systems or devices can reduce isolation of the quantum system and can increase the rate of decoherence (and reduce the characteristic time over which decoherence occurs). Decoherence of quantum states can cause errors in quantumcomputations.

[0009] Various quantum error correction schemes exist. Many of these schemes involves representing quantum information in the quantum states of plural quantum systems. In some quantum error correction schemes, every logical qubit specified by an algorithm may be implemented by some number, typically three or more, physical qubits that are controlled to have the same or different quantum states.

[0010] Two or more quantum systems are “entangled” when “the quantum state of any one of the entangled quantum systems cannot be described independently of the state of the other one(s) of the entangled quantum systems.

[0011] When two quantum systems are entangled, the results of measurements on the two quantum systems are correlated. For example, two electrons may have an entangled state which forces measurements of the spins of the two electrons relative to a particular axis to yield the same result. Such a state may be represented as: \ = a|TT) + p|U).

[0012] Quantum entanglement may be exploited in various useful ways. For example, entanglement may be applied for: transferring a quantum state from one quantum system to another over an arbitrary distance using a protocol for quantum teleportation, quantum error correction, applying two qubit quantum gates to quantum systems that are separated by arbitrary distances using protocols for teleporting controlled gates, measurement based computing, and so on. As a result, quantum entanglement has become a key resource for quantum informatics and quantum communication.

[0013] Entangled quantum systems may, for example, be applied to transfer and manipulate quantum information in quantum informatics networks. Quantum entanglement can be used to facilitate interactions between quantum systems even where the quantum systems are separated by large distances. Depending on the construction of a quantum informatics apparatus, many quantum systems may be needed to generate quantum entanglement to support execution of desired algorithms.

[0014] There is a general need for solutions to problems inherent in scaling quantum informatics apparatus to incorporate larger numbers of quantum systems.Summary

[0015] The present technology has a number of aspects. These include, without limitation, quantum informatics apparatus and related methods and apparatus forcontrolling quantum systems to execute quantum informatics programs.

[0016] One aspect of the present technology provides a control system for a quantum informatics apparatus (QIA). The QIA comprises a plurality of quantum systems and a plurality of devices operative to control quantum states of the quantum systems. The control system comprises a plurality of instruction queuing units (IQUs). Each of the IQUs comprises a data processor, a queue, and queue control logic. Each of the IQUs is associated with a corresponding one of the devices of the QIA, and each queue is configured to hold: a plurality of micro-instructions for control of the corresponding device; and a time point associated with each of the plurality of microinstructions. The data processor of each IQU is configured to process program execution instructions for the corresponding device and, in response to the program execution instructions, insert micro-instructions for controlling the corresponding device and the time point associated with each inserted micro-instruction into the queue of the IQU. The queue control logic is configured to release the microinstructions for controlling the corresponding device at times based on the time point associated with each of the micro-instructions.

[0017] In some embodiments, the queue control logic is configured to release each of the micro-instructions when the time point associated with the micro-instruction matches the current time.

[0018] In some embodiments, the IQU is configured to assign the time point to the micro- instruction such that the time point is before a desired execution time for the micro- instruction and the queue control logic is configured to apply a delay before releasing the micro-instruction. In some embodiments, the delay compensates for a latency between release of the micro-instruction and performance of an action corresponding to the micro-instruction by the corresponding one of the devices. In some embodiments, the latency for each of the IQUs is based on: a time for the control logic of the IQU to output a control signal for controlling the device after the micro- instruction is released; and calibration data that indicates a time for the associated one of the devices to perform the action after the control signal is output.

[0019] In some embodiments, the control logic comprises a state machine.

[0020] In some embodiments, the control logic is implemented by a combination of combinational and sequential logic.

[0021] In some embodiments, the plurality of devices includes devices of a plurality of different types, those of the IQUs associated with at least one of the types of thedevices each comprise a sequence generator, and in response to release of a microinstruction that specifies a sequence, the sequence generator is operative to generate a sequence of output pulses corresponding to the specified sequence. In some embodiments, the micro-instruction that specifies the sequence incorporates a binary number that defined the pulse sequence. In some embodiments, the binary number comprises a sequence of bit values and each of the bit values of the binary number specifies whether a pulse is present or not present during a time interval that corresponds to the bit value.

[0022] In some embodiments, at least some of the IQUs are provided in the form of application specific integrated circuits (ASICs). In some embodiments, one or more of the ASICs provides a plurality of the IQUs. In some embodiments, the one or more of the ASICs comprises one or more instruction memories for the plurality of IQUs on the one or more of the ASICs.

[0023] In some embodiments, at least some of the IQUs are implemented at least in part in configurable logic. In some embodiments, the devices comprise devices of a plurality of types; the control system comprises a plurality of configurable logic units; and each of the plurality of configurable logic units hosts a plurality of the IQUs. In some embodiments, the IQUs hosted on each of the plurality of configurable logic units are associated with devices of the same one of the plurality of types of devices. In some embodiments, the configurable logic comprises a field programmable gate array (FPGA).

[0024] In some embodiments, the control system comprises at least one result register bank accessible by the IQUs, the at least one result register bank storing results of measurements obtained by one or more measurement units. In some embodiments, the IQUs are configurable to release one or more micro-instructions conditionally based on one or more measurement results retrieved from the one or more result register bank.

[0025] In some embodiments, wherein the devices comprise at least one time tagger device, the at least one time tagger devices each being configured to receive measurement results from one of the one or more measurement units and associate a time point to each of the received measurement results.

[0026] In some embodiments, the control system is configured to store the measurement results and the time points associated with the measurement results by the one or more time tagger device in the one or more results register bank.

[0027] In some embodiments, the data processors for at least some of the IQUs comprise instruction sets that include custom instructions for one or more of: filling the queue, calibration, prefilling control, communication, synchronization and switching.

[0028] In some embodiments, the custom instructions include one or more custom instructions which cause the data processor to adjust the time points associated with micro-instructions by adding a predefined delay.

[0029] In some embodiments, the custom instructions include instructions that cause the data processor to place the queue of the IQU or a portion of the queue of the IQU in a locked mode such that any micro-instructions in the queue or portion of the queue are prevented from being released. In some embodiments, the control system is configurable to: prefill a first portion of the IQU with micro-instructions that correspond to a first condition being satisfied; prefill a second portion of the IQU with micro-instructions that correspond to a second condition being satisfied; and lock the first portion and the second portion of the IQU. In some embodiments, the control system is further configurable to: if the first condition is satisfied, unlock the first portion of the IQU and flush the second portion of the IQU; and if the second condition is satisfied, unlock the second portion of the IQU and flush the first portion of the IQU.

[0030] In some embodiments, the custom instructions include instructions which cause the data processor to perform one or more of: reading a current value of the time point corresponding to the latest scheduled micro-instruction; setting the time point for the next scheduled micro-instruction to have a specified value; and reading a current system time.

[0031] In some embodiments, the custom instructions include instructions which cause the data processor to issue control signals to control configuration of one or more switches that control routing of optical and / or electrical signals in the QIA.

[0032] In some embodiments, the IQUs include a latest time register (LTR) and are configured to store, in the LTR, a time point associated with an immediately preceding micro-instruction, and the IQU is configured to generate the time point for a next micro- instruction to be inserted into the queue based on the time point stored in the LTR.

[0033] In some embodiments, the control system is configurable to switch at least one of the IQUs from controlling one of the devices to controlling a different one of the devices during execution of a program.

[0034] In some embodiments, at least one of the devices comprises first and second control inputs, a first one of the IQUs is configured to generate control signals for a first one of the control inputs, and a second one of the IQUs is configured to generate control signals for a second one of the control inputs.

[0035] In some embodiments, the control system comprises a controller. In some embodiments, the controller is configured to distribute program execution instructions among a plurality of instruction memories that are each accessible by at least one of the IQUs. Each of the IQUs may be configured to retrieve those of the program execution instructions associated with the device corresponding to the IQU from one of the instruction memories. In some embodiments, each of the instruction memories is dedicated to a corresponding one of the IQUs. In some embodiments, each of the dedicated instruction memories is shared by the controller and the one of the IQUs to which the instruction memory is dedicated.

[0036] In some embodiments, the IQUs of the control system are coordinated such that when any two or more of the IQUs release micro-instructions associated with the same time point, the micro-instructions are released by each of the two or more IQUs such that the devices controlled by the two or more IQUs commence actions specified by the micro-instructions at times separated by no more than + / - 10 ns.

[0037] In some embodiments, the control system comprises one or more analog interfaces, each of the analog interfaces configured to generate and deliver to one of the devices analog signals in response to control signals from one of the IQUs.

[0038] In some embodiments, the control system is in combination with the QIA or with selected portions of or elements of the QIA.

[0039] In some embodiments, the QIA comprises one or more of: a quantum computer, a quantum repeater, a quantum data communication network, a quantum information storage device, and a quantum encryption device.

[0040] In some embodiments, the devices comprise devices of one or more of the following device types: devices that control magnetic fields, devices that control electric fields, devices that control substrate strains, devices that control optical sources, devices that control radiofrequency sources, devices that control switches, and devices that control measurement units.

[0041] Another aspect of the present technology provides a method for controlling a quantum information apparatus (QIA). The QIA comprises comprising a plurality of quantum systems and a plurality of devices operative to control quantum states of thequantum systems. The method comprises, for each of the devices, inserting microinstructions for controlling the device into a queue corresponding to the device together with a time point corresponding to each of the micro-instructions. From each of the queues the micro-instructions are released at times based on the time points associated with the micro-instructions.

[0042] In some embodiments, releasing the micro-instructions is performed by deterministic queue control logic. In some embodiments, the time point associated with the micro-instruction is before a desired execution time for the micro- instruction and the method comprises applying a delay before releasing the micro-instruction. In some embodiments, the delay compensates for a latency between release of the micro- instruction and performance of an action corresponding to the micro-instruction by the corresponding one of the devices

[0043] In some embodiments, for each of the devices, inserting micro-instructions for controlling the device into the queue is performed by a data processor associated with the queue, wherein each queue is associated with only one data processor.

[0044] In some embodiments, each of the data processors is associated with only one of the queues.

[0045] In some embodiments, the method comprises generating the microinstructions based on program execution instructions, wherein the method comprises distributing the program execution instructions to a plurality of instruction queuing units (IQUs), each of the IQUs associated with one of the devices, such that each IQU receives a set of the program execution instructions for controlling the device associated with the IQU.

[0046] Another aspect of the present technology provides a control system configured to perform the method described above. The control system may be comprised in the quantum informatics apparatus. Another aspect of the present technology provides a non-transitory medium which carries a set of computer-readable instructions which, when executed by a data processor, cause the data processor to execute the method described above.

[0047] Another aspect of the present technology provides any new and inventive feature, combination of features or sub-combination of features as described herein and / or depicted in the drawings.

[0048] Another aspect of the present technology provides methods that incorporate any new and inventive acts, steps, combination of acts and / or steps or sub-combination of acts and / or steps as described herein and / or depicted in the drawings.

[0049] Further aspects and example embodiments are illustrated in the accompanying drawings and / or described in the following description.

[0050] It is emphasized that the invention relates to all combinations of the above features, even if these are recited in different claims.Brief Description of the Drawings

[0051] The accompanying drawings illustrate non-limiting example embodiments of the invention.

[0052] Fig. 1 is a flowchart that illustrates a method according to an example embodiment of the present technology.

[0053] Fig. 2 is a schematic illustration of an example quantum informatics apparatus.

[0054] Fig. 3 is a schematic illustration showing an example quantum informatics apparatus that includes matter based quantum systems and various devices operable for controlling quantum states of the quantum systems.

[0055] Fig. 4 is a schematic illustration of a control system for a quantum informatics apparatus according to an example embodiment of the present technology.

[0056] Fig. 4A is a schematic illustration showing a portion of a control system for a quantum informatics apparatus with a switch to allow an instruction queueing unit to deliver instructions to different devices at different times according to an example embodiment of the present technology.

[0057] Fig. 5 is a schematic block diagram showing functional elements of an example instruction queuing unit according to an example embodiment of the present technology.

[0058] Fig. 6 is a perspective schematic view of a control system according to an example embodiment of the present technology.

[0059] Fig. 7 is a schematic block diagram showing an example quantum informatics apparatus according to an example embodiment of the present technology.

[0060] Fig. 8 is a flow chart for an example method for generating and executing a quantum informatics program according to an example embodiment of the present technology.Detailed Description

[0061] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention maybe practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive sense.

[0062] The present technology relates to quantum informatics apparatus (QIAs) and to systems and methods for control of QIAs. The term QIA encompasses quantum computers, quantum repeaters, quantum (data) communication networks, quantum data stores or quantum information storage devices, quantum cryptography apparatus such as a quantum encryption device, and other apparatuses that work with information in quantum states of quantum systems.

[0063] Fig. 1 is a flowchart that illustrates a method 10 that implements an example workflow for using a QIA to solve a problem. In block S11 the problem is defined. In block S12 a quantum program that implements an algorithm for solving the problem is defined. The quantum program may, for example, be defined by a quantum circuit. The quantum circuit may, for example, specify operations to be performed on a number of logical qubits.

[0064] Block S14 compiles the output of block S12 to yield a set of program commands for implementing the quantum circuit of block S12 on the particular quantum informatics apparatus on which the quantum circuit will be executed. Block S14 may be performed by a quantum compiler (e.g. a computer system that executes computer software that is configured to generate commands to implement a specified quantum circuit). The quantum compiler may have access to data that includes, for example, some or all of: details about the architecture of a QIA on which the quantum circuit will be executed; information regarding individual quantum systems of the QIA; information regarding devices included in the QIA; information regarding one or more quantum error correction protocols to be used when executing the quantum circuit; etc.

[0065] Block S14 may, for example, be configured to map logical qubits of a quantum circuit to specific quantum systems or sets of quantum systems of the quantum informatics apparatus and to map operations (e.g. generating entanglement of logical qubits, applying quantum gates to logical qubits, making measurements on logical qubits) to corresponding actions to be performed on quantum systems of the quantum informatics apparatus. These mappings may be in accordance with a selected quantum error correction scheme. The mapping may take into account a structure ofthe QIA, possibly taking into account factors such as: available interconnections between quantum systems, qualities of individual quantum systems, available mechanisms for manipulating quantum states of the available quantum systems, characteristics and interconnectivity of measurement devices of the QIA, etc.

[0066] The output of block S14 may, for example, be a set of program execution instructions which will cause coordinated operation of various devices incorporated into the QIA to execute the quantum circuit generated by block S12. As described below, the set of program execution instructions may be separated or separable into a separate set of program execution instructions for each device of a QIA that will be used in the course of executing a quantum circuit on the QIA.

[0067] Block S15 executes the program execution instructions from block S14 on the designated QIA.

[0068] Block S16 obtains the results output by the quantum circuit. These results may, for example comprise results of measurements on quantum systems of the QIA and / or on photon states emitted from quantum systems of the QIA.

[0069] Some aspects of the present technology relate particularly to block S15 of Fig. 1 . Executing a larger quantum circuit on a particular QIA typically requires the simultaneous coordinated control of a large number of individual devices at a high rate and with high precision under tight timing requirements. In some embodiments, timing must be coordinated such that operations performed by different devices in a QIA can be caused to occur simultaneously and / or at different times separated by a specified time difference, with a precision of + / - a few nanoseconds.

[0070] Fig. 2 is a schematic functional diagram for an example generalized QIA 20. QIA 20 includes N quantum systems 21-1 to 21-N (generally and collectively, quantum systems 21) that may be used to store and / or manipulate quantum information. In some embodiments, quantum systems 21 are used to provide qubits. N can be any suitable number. In some embodiments, N is more than 100 or more than 500 or more than 1000 or more than 10,000 or more than 50,000.

[0071] QIA 20 includes a control system 22 which provides functionality for performing quantum informatics. Control system 22 includes functionality 22A for modifying quantum states of qubits 21 . Functionality 22A may, for example be applied to initialize individual quantum systems 21 to desired quantum states and to modifyquantum states of quantum systems 21 , for example by applying selected quantum gates to selected ones of quantum systems 21 .

[0072] Control system 22 also includes functionality 22B for making measurements on quantum systems 21 .

[0073] In some embodiments, control system 22 also includes functionality 22C for directly and / or indirectly facilitating interactions between selected quantum systems 21.

[0074] Different QIAs can have different types of quantum systems, different types of devices for controlling quantum states of the quantum systems, different types of devices for making measurements on quantum systems and different arrangements of such devices. However, the basic scaling problem of how to precisely perform simultaneous coordinated control of a large number of such devices to perform desired quantum informatics processing is common across different possible architectures for QIAs which may incorporate different types of quantum systems.

[0075] Fig. 3 is a schematic diagram of an example QIA 30 of a type that is used herein as a non-limiting example to explain the present technology. QIA 30 incorporates quantum systems 21 that are located in or on a solid substrate 32. Quantum systems 21 may, for example comprise luminescence centres. The luminescence centres have the property that they can be caused to emit photon states that contain information about the quantum states of quantum systems 21 . For example, ground spin states of the luminescence centre may serve as qubit basis states. The luminescence centre may have a spin-dependent optical transition from the ground state to an excited state that can decay by emitting a photon.

[0076] In one example, quantum systems 21 comprise T centres, I centres or M centres and substrate 32 comprises one or more silicon substrates. QIA 30 may incorporate any suitable number of quantum systems 21 .

[0077] In example QIA 30, each quantum system 21 is optically coupled to an optical switching network 33. Optical switching network includes optical paths 33A that may, for example, be provided by optical waveguides. Coupling of photon states originating at quantum systems 21 may be facilitated by optical couplers 33B, which may, for example, comprise optical resonators. In some embodiments the optical resonators comprise photonic cavities. One or more switches in optical switching network 33C isselectively configurable to route a photon state from a specific one of quantum systems 21 to a specific measurement unit 34.

[0078] Optical switching network 33 allows each quantum system 21 to be optically coupled to at least one measurement unit 34. Measurement units 34 comprise single photon detectors 24A. In some embodiments measurement units 34 include or consist of Bell state analyzers. Each Bell state analyzer may include two or more single photon detectors. A measurement unit 34 may comprise or be associated with a device that associates time points to measurement results (e.g. photon detection events by a photon detector 24A). Such a device may be called a “time tagger”. QIAs as described herein may include time taggers. Such time taggers may be controlled as described herein.

[0079] Example QIA 30 includes devices of several types which can be operated to control quantum states of quantum systems 21 , interactions between quantum systems 21 and measurements of quantum systems 21 to execute a quantum informatics program. The illustrated QIA 30 includes: magnetic field generators 36A (which may generate static magnetic fields and / or magnetic fields that vary according to a waveform), electric field generators 36B (which may generate static electric fields and / or electric fields that vary according to a waveform), substrate strain actuators 36C, optical signal generators 36D, radiofrequency (e.g. microwave) signal generators 36E, optical coupler controllers 36F and switching controller 37.

[0080] In some embodiments, one or more of devices 37A to 37F is omitted and / or one or more additional devices are added (the additional devices may, for example have functions relating to controlling aspects of the environments of quantum systems 21 , controlling quantum states of quantum systems 21 , making measurements on quantum systems, time tagging events, directing optical or electronic signals etc.)

[0081] Fields controlled by magnetic field generators 36A, electric field generators 36B, and substrate strain actuators 36C can individually or collectively affect energy levels of a corresponding quantum system 21 . The energy levels, in turn, affect the wavelengths of photons emitted by the quantum system 21 as well as the wavelength(s) of light that, when applied to the quantum system 21 , can cause the quantum system 21 to transition to an excited state. Optical signal generators 36D may each be operated to illuminate one of more quantum systems 21 with light. The light may have a wavelength that matches an optical transition of one or more of theilluminated quantum systems 21 (i.e. the photon energy at the wavelength matches an energy difference of the optical transition). RF signal generators 36E can be controlled to emit RF signals that manipulate quantum states of individual quantum systems 21 .

[0082] In order to use a QIA (e.g. QIA 20 or QIA 30) to execute a quantum informatics process, devices of the QIA are controlled according to program execution instructions (e.g. as output from block S14 of Fig. 1).

[0083] In the present technology the program execution instructions may be prepared in advance. The program instructions may be executed to place appropriate microinstructions in a queue. The micro-instructions may have any suitable format which can be applied by apparatus downstream from queue 47 (e.g. by an interface 44 and / or by a controlled device 42) to control corresponding device 42. The microinstructions may for example comprise a series of binary values. Some of the binary values may encode a specified action (e.g. cause the device to emit a single pulse or cause the device to emit a pulse sequence). Some of the binary values may encode data (e.g. a definition of a pulse sequence or a waveform to be emitted by the device) etc.

[0084] Execution of the program execution instructions can occur in a non- deterministic time domain (i.e. a time domain in which it is not required that the microinstructions be placed in queues at precise times; it is sufficient if the microinstructions are in the appropriate queue early enough to be released from the queue at corresponding times). The queued micro-instructions may then be introduced into a deterministic time domain in which each micro-instruction is associated with a specific time point at which the micro-instruction will be executed.

[0085] A feature of the present technology is that the program execution instructions are directed to a plurality of device-dedicated instruction queuing units (IQUs). Each IQU receives program execution instructions for a particular device with which the IQU is associated. Each IQU is configured to, in response to the program execution instructions, insert micro-instructions for controlling the associated device into a respective device-specific queue that corresponds to the associated device.

[0086] Operation of the IQUs is coordinated such that actions caused by release of the micro-instructions are performed with a desired timing relationship. In some embodiments, when any two or more of the IQUs release micro-instructionsassociated with the same time point, the micro-instructions are released by each of the two or more IQUs such that the devices controlled by the two or more IQUs commence actions specified by the micro-instructions at times separated by an acceptable time difference, such as no more than + / - 10 ns.

[0087] In some embodiments, one or more type of controlled device has two or more distinct control inputs. For example, devices of a certain device may have a first control input for configuring the device and / or selecting an operational mode for the device and a second control input for triggering the device to perform an action. The performed action may be different depending on the configuration and / or mode of the device when the action is triggered. In some embodiments a separate IQU is provided for each of a plurality of control inputs for such devices.

[0088] An IQU may be implemented using any of a variety of technologies. For example, one or more IQUs may be implemented in an application specific integrated circuit (ASIC), or a circuit board that integrates plural discrete and / or integrated components or using configurable logic or combinations of these.

[0089] Once queued, the micro-instructions are in the deterministic time domain. The queue may be called a deterministic time queue (“DTQ”). In the device-specific queue, each micro-instruction is associated with a corresponding time point at which the micro-instruction will be executed to control the corresponding device.

[0090] Segregating the program execution instructions into sets according to the device that the program execution instructions are intended for (e.g. each set contains instructions for one device) and making each set of program execution instructions available to the IQU corresponding to the device facilitates independent and high-speed control of individual devices. This, in turn, can make scheduling faster and more reliable.

[0091] Making each IQU responsible for only one device, or, in some embodiments, only one control input for a device that includes plural control inputs (during any particular time period) and making each control input of each device be controlled by one IQU, avoids the possibility of conflicting control inputs being issued for the same device by different IQUs and avoids the possibility of an IQU receiving conflicting program execution instructions for different devices. Another benefit that may be achieved using the present technology is that scaling up to include more quantum systems (and therefore more devices) is simplified. As the number of devicesincreases, an additional IQU and a corresponding queue can be added for each new device.

[0092] In some embodiments each IQU comprises a data processor, for example a microprocessor. In some embodiments, each microprocessor is provided by a processor core implemented in configurable logic (e.g. in a FPGA, (Field Programmable Gate Array). In some embodiments the microprocessor has an instruction set that includes custom instructions. Some or all of the program execution instructions may correspond to custom instructions belonging to the instruction set. The custom instructions may, for example, include instructions for one or more of: filling a queue, calibration, prefilling control, communication, synchronization and switching.

[0093] Calibration custom instructions may, for example, comprise custom instructions which cause the microprocessor to adjust the time points associated with micro-instructions by adding a predefined delay. Calibration instructions may be used to set different delays for different DTQs. Such delays may compensate for differences in the time required for a device to respond to micro-instructions. For example, the time between delivering a micro-instruction to a pulser and delivery of a corresponding pulse to a corresponding quantum system may be different for different pulsers. These differences may be compensated for by adding selected delays (which may be done using custom instructions or in other ways).

[0094] Prefilling control custom instructions may comprise instructions that place a DTQ or portion of a DTQ in a locked mode. When the DTQ or portion thereof is in the locked mode, micro-instructions will not be released from the DTU or portion thereof. This functionality may, for example be used to prefill a DTQ or portion of the DTU with micro-instructions that will be executed only if a certain condition is satisfied (the condition may, for example, relate to results of one or more measurements that may be made during execution of a quantum informatics program). Upon the condition being satisfied, the DTQ or portion thereof may be unlocked so that the microinstructions can be released. Otherwise, the DTQ or portion thereof may be flushed.

[0095] In some embodiments, a first portion of a DTQ may be prefilled with instructions that correspond to a first possible branch of a quantum informatics program that corresponds to a first condition being satisfied and a second portion of the DTQ may be prefilled with micro-instructions corresponding to a second possible branch of the quantum informatics program that corresponds to a second conditionbeing satisfied. The first and second portions of the DTQ may be locked. The first and second conditions may be mutually exclusive. If the first condition is satisfied the first portion of the DTQ may be unlocked and the second portion of the DTQ may be flushed. If the second condition is satisfied then the second portion of the DTQ may be unlocked and the first portion of the DTQ may be flushed.

[0096] Communications custom instructions may cause a microprocessor to generate messages for other parts of a system. For example, a communication custom instruction may cause a microprocessor of an IQU to send information such as the results of one or more measurements to one or more other IQUs. This information may, for example, be used as a basis for evaluating conditions for controlling branching of a program as described above.

[0097] Synchronization custom instructions can be used to coordinate the operations of different IQUs. Synchronization custom instructions may, for example, include custom instructions for one or more of: reading the current value of the time point corresponding to the latest scheduled micro-instruction; setting the time point for the next scheduled micro-instruction to have a specified value; and reading the current system time (e.g. global counter value).

[0098] Switching custom instructions may include custom instructions that cause a microprocessor to set switches that control routing of optical and / or electrical signals in systems as described herein.

[0099] The microprocessor may include microcode that causes the custom instructions to cause the microprocessor to insert one or more specific microinstructions into the associated queue. In some embodiments the microprocessors comprise RISC (Reduced Instruction Set Computer) microprocessor cores.

[0100] In some embodiments, microprocessors of IQUs associated with devices of different types have different instruction sets that include custom instructions that are specific to the type of device with which the IQU is associated. For example, a microprocessor that feeds a queue for delivering micro-instructions for a measurement device may have an instruction set that includes custom instructions specific to controlling the measurement unit to make measurements and / or custom instructions specific for controlling capturing results of measurements. These custom instructions may not be needed or provided in microprocessors of IQUs that feed queues for delivering micro-instructions for a device of another type (e.g. a device for controlling a magnetic or electric field).

[0101] Fig. 4 is a schematic diagram that illustrates apparatus 40 according to an example embodiment of the present technology. Program execution instructions 41 for controlling individual devices 42A, 42B, 42C, 42D, 42E (generally and collectively devices 42) to perform a quantum informatics program are accessible to corresponding IQUs 43A, 43B, 43C, 43D and 43E (generally and collectively IQUs 43). Each IQU 43 is associated with a corresponding device 42. This correspondence can be a 1 :1 correspondence.

[0102] In some embodiments, including the embodiment of Fig. 4, program execution instructions 41 are divided into separate sets of program execution instructions, with one set of program execution instructions for each device 42 or, in some embodiments, for each control input of a device 42 that has plural control inputs. Fig. 4 shows program execution instruction sets 41 A, 41 B, 41 C, 41 D and 41 E which are respectively associated with devices 42A, 42B, 42C, 42D and 42E. In some embodiments, each program execution instruction set is present in a program memory that is associated with and dedicated to the IQU 43 that controls the device 42 for which the program execution instructions are intended. These program memories may be (but are not required to be) co-located with the corresponding IQUs 43. The number of program execution instruction sets may be as large as the number of devices 42 to be controlled, which may be tens, hundreds, thousands or more.

[0103] In Fig. 4, apparatus 40 includes devices 42 of five types (types A, B, C, D and E). Devices 42A are of type A, devices 42B are of type B, etc. Similarly, IQUs 43 that provide micro-instructions to devices 42A are labelled 43A, IQUs 43 that provide micro-instructions to devices 42B are labelled 43B and so on. Variants of apparatus 40 may include devices of more than or fewer than five types.

[0104] In Fig. 4, to avoid clutter in the drawing, only one device 42 of each type is shown. Apparatus 40 may include any suitable number of devices 42 of any type. In QIA according to some embodiments, the number of devices 42 of two or more types is not the same. For example, for some types of devices 42 a separate device 42 may be provided for every quantum system 21 (not shown in Fig. 4) whereas a single device 42 of another type may be provided for two or more quantum systems 21. For example, in a QIA 30, (see Fig. 3) an optical signal generator, which is one type of device, may be arranged to emit light (e.g. one or more optical pulses) that simultaneously illuminates two or more quantum systems 21 whereas an electric fieldcontrol, which is another type of device, may be provided for every quantum system 21 that will be used to execute a quantum informatics program. Consequently, this example of a QIA 30 may have more electric field controls than optical signal generators (and consequently there will be more IQUs that provide instructions to corresponding electric field controls than there are IQUs that provide instructions to corresponding optical signal generators).

[0105] In response to the program execution instructions, each IQU 43 inserts microinstructions into its queue 47. An IQU 43 may insert micro-instructions into its queues 47 before execution of a quantum circuit commences. The IQU may insert additional micro-instructions into its queue 47 as execution of the quantum circuit is underway.

[0106] The micro-instructions are delivered from each queue 47 to a corresponding interface 44 for execution at specific times. Interfaces 44 control the associated devices 42. Interfaces 44 may have different constructions depending on the nature of the device that they are designed to control and the inputs required to control that device. An interface 42 may output analog and / or digital signals (e.g. digital values and / or analog pulses) to control a device 42. In some embodiments, an IQU 43 is configured to send digital values based on micro-instructions to a corresponding interface 44 and the interface 44 is configured to receive the digital values and, based on the digital values, output one or more analog signals (e.g. an analog pulse or a series of two or more analog pulses) and / or output digital data (e.g. digital data that specifies a waveform, a device mode or configuration, etc). The analog and / or digital signals from an interface 44 cause the associated device 42 to perform a desired action.

[0107] Timing is coordinated across QIA 40 by one or more clock signals such that micro-instructions that must be executed with a specific timing relationship (e.g. simultaneously to within a tolerance, in sequence separated by a specific time difference within a tolerance) will be executed with the specified timing relationship.

[0108] In some quantum informatics processes, for at least some devices 42 of a particular type (e.g. type A) that are used in the process, there are portions of the process during which there are no micro-instructions pertaining to the device. In such cases it may be possible to execute the quantum informatics process with a reduced number of IQUs 43 by providing a system that allows an IQU 43 to deliver microinstructions to different devices 42 during different phases of a quantum informaticsprocess. For example, a system may incorporate one or more switches. The switches may be settable to control the destination device 42 for micro-instructions delivered by an IQU 43.

[0109] Switches for selecting the device 42 to which micro-instructions from a particular IQU 43 are delivered may, for example, include switches that are incorporated into the IQU 43 (e.g. to cause micro-instructions to be output from IQU 43 on selected output channels for routing to different devices 42 during different time periods) and / or switches incorporated into an interface 44 (e.g. to direct pulses from the interface 44 to different devices 42 at different times) and / or separate switches.

[0110] Fig. 4A shows an example implementation that includes a switch 48 that is configurable to direct signals (e.g. pulses, waveforms) output by an interface 44 to different devices 42 during respective periods..

[0111] In the example of Fig. 4A, the setting of switch 48 may be changed during execution of a quantum informatics program to direct micro-instructions from queue 47 to be delivered to control different ones of devices 42A-1 to 42A-M in different time periods while a quantum informatics program is being executed.

[0112] In using devices 42 to alter quantum states of quantum systems 21 to execute a quantum informatics process, timing is important. In general, where a device 42 is responsible for causing an action such as delivering a stimulus (e.g. an optical or radiofrequency pulse) or to change something about a physical environment of the quantum system 21 (e.g. a magnetic field, electric field, substrate strain, or coupling to an external waveguide, circuit or the like) it is the time that the stimulus begins to be delivered and / or the change is actually made that is important. The amount of time that elapses from the time that a micro-instruction is released from queue 47 to the time that a resulting stimulus or change is applied to a quantum system 21 (which may be called a “command result latency”) can be different for devices 42 of different types, different devices of the same type and / or for different micro-instructions for the same device.

[0113] In some embodiments IQUs are configured to release micro-instructions from queue 47 for delivery to interfaces 44 at times that are earlier than a specified time point for execution of the micro-instruction by a time period that compensates for the command result latency of the interfaces 44 and devices 42 that the IQU is controlling. In some embodiments the IQUs are configured to release micro-instructions from queue 47 for delivery to interfaces 44 early (e.g. a number of clock cycles prior to time points associated with the micro-instructions) and to delay delivering the micro-instructions to interfaces 44 by a delay time that is such that the combined effect of the early release and the delay time compensates for the command result latency. The delay time may be different for (e.g. specific to) devices 42 of different types, different individual devices and / or different micro-instructions.

[0114] As mentioned above, in some embodiments, IQUs are implemented in configurable logic units (e.g. in FPGAs). In some such embodiments the number and / or arrangement of IQUs may be determined based at least in part on the quantum informatics program (e.g. quantum circuit) to be executed. The resulting number and / or configuration of IQUs for providing micro-instructions to devices of each type may then be instantiated by configuring the configurable logic units.

[0115] Fig. 5 is a block diagram that illustrates an example IQU 50 that may be used, for example, for IQUs 43 of Figs. 4,4A. IQU 50 has a first part 50A that operates in a non-deterministic time control regime (a timing regime in which timing of operations is not necessarily coordinated with timing of operations of other IQUs) and a second part 50B that operates in a deterministic time control (DTC) regime (a timing regime in which timing is coordinated with the timing of parts 50B of other IQUs). First part 50A processes program execution instructions and inserts micro-instructions into queue 47 according to the program execution instructions. Second part 50B causes each micro- instruction in queue 47 to be executed at a specified time point.

[0116] Part 50A of IQU 50 comprises a data processor 51. Data processor 51 is configured to provide micro-instructions 47A for insertion into queue 47. Data processor 51 may, for example, have a RISC architecture. In some embodiments, data processor 51 is a RISC-V microprocessor.

[0117] Data processor 51 is configured to receive program execution instructions (in this example, from an instruction memory 52). The program execution instructions are executed by data processor 51 and cause data processor 51 to cause specific microinstructions to be provided for insertion into queue 47.

[0118] Data processors of different IQUs 50 which are associated with different ones of devices 42 may receive different program execution instructions and produce different sequences of micro-instructions. Micro-instructions for controlling devices of different types may have different formats. The micro-instructions can cause interfaces 44 to control devices 42 to perform corresponding actions at correspondingtime points.

[0119] Instruction memory 52 may be shared between data processor 51 and another data processor (not shown in Fig. 5 but see controller modules 62-1 of controller 60 of Fig. 6). The other data processor may be called a “controller”. The controller may store program execution instructions in instruction memory 52 that relate to one or more devices 42 for which IQU 50 is responsible for controlling. The program execution instructions in instruction memory 52 may, for example, have been generated by compiling a quantum informatics program.

[0120] IQU 50 also includes a data memory 53. Data memory 53 may be used to store and make available to data processor 51 run-time variables and measurement results. Data memory 53 may be used, for example, for disseminating information to IQUs 50. Data memory 53 may be shared between data processor 51 and a controller. For example, a set of program execution instructions for an IQU 50 may include program execution instructions for branches that are to be executed or not executed depending on results of a measurement or measurements that are to be made at certain points in the execution of a quantum circuit. Results of those measurements may be made available to an IQU 50 via data memory 53.

[0121] Data processor 51 may be configured to recognize custom instructions which, when executed, cause data processor 51 to output corresponding micro-instructions into queue 47 and / or to perform actions to manage queue 47 (e.g. to flush all or a portion of queue 47, lock micro-instructions in all or a portion of queue 47 from being released, etc.).

[0122] A custom instruction may facilitate creation and insertion of a particular microinstruction into queue 47 in one instruction cycle. Custom instructions are instructions that can be specific to inserting different micro-instructions into queue 47 and / or managing queue 47. Such custom instructions are not present in the instruction sets of general purpose data processors. Custom instructions can make data processors 51 more efficient. Creating and inserting a micro-instruction using instructions in a standard instruction set for a data processor comparable to data processor 51 could take significantly more time than creating and inserting the same mi era- instruction using a custom instruction of data processor 51 . Similarly, flushing a portion of queue 47 (deleting all micro-instructions from the portion of queue 47) may take significantly less time when performed using a custom instruction in data processor 51 than when using instructions in a standard instruction set of a data processor comparable to dataprocessor 51 .

[0123] Data processor 51 may retrieve program execution instructions from instruction memory 52 and generate micro-instructions which are passed to queue 47, as indicated by arrow 54, by way of a processor-DTQ interface 55.

[0124] Processor-DTQ interface 55 may provide functionality that includes determining time points to associate with micro-instructions. For example, the microinstructions provided to processor-DTQ interface 55 may each be associated with a timing value that indirectly identifies a time point for execution of the micro-instruction. For example, the timing value may indicate when that micro-instruction should be executed relative to the time point for execution of the immediately preceding microinstruction (e.g. the timing value may indicate a delay relative to the time for executing the previous micro-instruction - such a timing value may be called a “wait time”). This allows the micro-instructions to be generated without needing to concurrently specify the absolute time point at which each micro-instruction should be executed.

[0125] Processor-DTQ interface 55 may, for example, be implemented by combinational logic and / or sequential logic. Processor-DTQ interface 55 includes a latest time register (LTR) 55A which stores the time point associated with the immediately preceding micro-instruction. The combinational logic of processor-DTQ interface 55 may, for example, generate the time point for execution of the current micro- instruction by adding the time value for the current micro-instruction to a value stored in LTR 55A. The resulting time point may be written into LTR 55A and also into queue 47.

[0126] Queue 47 may comprise, for example, a first in first out (FIFO) that queues micro-instructions 47A together with corresponding time points 47B. DTQ logic 47C controls operation of queue 47, including when to release the next mi era- instruction for execution. In some embodiments, DTQ logic 47C is implemented by combinational logic and / or sequential logic.

[0127] A global counter 56 contains a value representing absolute time that is accessible to DTQ logic 47C. Global counter 56 may, for example, comprise a 32-bit counter that counts cycles of a timing signal (e.g. a timing signal having a suitable frequency such as 10 MHz -100 ns per cycle).

[0128] In some embodiments, DTQ logic 47C comprises a state machine. The state machine may switch among various states based on the status of queue 47. For example, in some embodiments, queue 47 may be in any of the following states:DTQ_empty; DTQ_not_empty; DTQ_pulse; DTQ_pulse_seq; DTQ_flush; and DTQ_error_time. DTQ logic 47C may operate differently depending on the current state of DTQ 47.

[0129] In the DTQ_empty state, there are no micro-instructions to be executed in queue 47. In this state, DTQ logic 47C is not performing time matches or causing any output to be directed to interface 44. In the DTQ_not-empty state, queue 47 contains some micro-instructions for execution but the time point for releasing those microinstructions is in the future. In this state, DTQ logic 47C is configured to detect a match between the current absolute time (e.g. the current value in global counter 56) and a time point associated with a micro-instruction in queue 47. If a time match is detected then the state of DTQ logic 47C depends on the micro-instruction for which the time match occurred. The DTQ_pulse state corresponds to the case where the micro- instruction calls for generation of a single pulse. In this state, DTQ logic 47C causes sequence generator 58 to output a single pulse. The DTQ_pulse_seq state corresponds to the case where the micro-instruction calls for generation of a pulse sequence. In this state, a time match has happened and DTQ logic 47C is causing sequence generator 58 to output the specified pulse sequence. The DTQ_flush state is initiated when data processor 51 instructs DTQ logic 47C (e.g. by delivering a micro- instruction via path 54A) to flush one or more micro-instructions from queue 47. In this state DTQ logic 47C causes a number of DTQ entries to be flushed as instructed by data processor 51 . The DTQ_error_time state is triggered if DTQ logic 47C determines that one or more micro-instructions in queue 47 is associated with a time point that has already passed. In this state DTQ logic 47C takes actions (e.g. removing such micro-instructions from queue 47) to handle this error.

[0130] In some embodiments, apparatus as described herein includes plural IQUs 50 with some IQUs 50 on each of a plurality of modules (e.g. cards). The timing signal may be distributed to each of the cards by a timing distribution network having a suitably low skew (e.g. sub-picosecond skew in some embodiments). A global counter 56 may be provided for each one of the modules. The global counter 56 may thus, for example, count cycles of the timing signal received from a timing distribution network.

[0131] For example, each module may include configurable logic (e.g. a FPGA) that instantiates plural IQUs. Each such programmable logic may be configured to provide a global counter 56. When such apparatus is initially powered up, the global countersin different ones of the FPGAs will, in general, not be synchronized to have the same counts. In some embodiments all of the global counters 56 are simultaneously reset periodically (e.g. on the order of once per second). Therefore, after the first such reset all of global counters 56 will be synchronized (i.e. will agree on an absolute time - e.g. by having the same counts).

[0132] Periodically resetting global counters 56 does not interfere with executing quantum informatics programs that have a duration longer than the period between resets since the scheduling of micro-instructions can take into account roll-over of global counters 56. For example, the difference of the global counter value and the time point associated with the next micro-instruction to be output from queue 47 may be computed. If the global counter value is less than the value of the time point then the reset has not happened (in the case where global counter 56 counts up). If the value of global counter 56 is more than the value of the time point then the difference between them may be compared to a limit value. The limit value may be chosen based on the size of the global counter (e.g. 32 bits) and an estimation of the magnitude of the delay expected between the time points of sequential microinstructions in queue 47. If the difference is greater than the threshold it can be concluded that a reset has happened and a time error has not occurred.

[0133] DTQ logic 47 may compare the absolute time value from global counter 56 to the time point associated with the next micro-instruction and may release the microinstruction for execution when these values satisfy a criterion (e.g. the values are the same, or there is a specific difference between the values etc.). For example, DTQ logic 47 may release a micro- instruction for execution a few counts (e.g. 2 counts) of global counter 56 prior to the time point associated with the micro-instruction.

[0134] Micro-instructions released from queue 47 are delayed by a delay unit 57. In some embodiments, delay unit 57 is integrated with and / or controlled by DTQ logic 47C. The amount of delay provided by delay unit 57 is selected so that, taking into account the time required for a device 42 to start generating an output specified by a micro- instruction (e.g. by starting to emit a pulse or pulse sequence) the output will commence at the time point associated with the micro-instruction. For example, if DTQ logic 47C is configured to release micro-instructions at a time that is before the time points associated with the micro-instructions by an amount t1 and the device 42 to be controlled by the micro-instruction takes a time t2 to start generating an output after the micro- instruction is released then delay unit 57 may be set to provide a delayof a duration t3 such that t1 =t2+t3.

[0135] In some embodiments, t2 included at least first and second components. The first component of t2 is how long it takes sequence generator 58 to generate a control output (e.g. a digital pulse) for interface 44. This first component can depend on the micro- instruction and / or the device being controlled. The first component introduces a delay that is known in advance and may be the same for all devices of the same type. The second component is how long it takes for the specific device to perform an action after the control output is generated by sequence generator 58. The second component may be different for every device. In some embodiments the second component is measured in a calibration procedure and calibration information (calibration data) based on this measurement is recorded. Delay t3 may be selected based on the recorded calibration information. In some embodiments, delay t3 is set so that the start of a pulse or series of pulses is synchronized with the rising edge of a timing signal of global counter 56.

[0136] For example, if DTQ logic 47C is configured to release micro-instructions 20 ns prior to the associated time points and the device 42 being controlled by the microinstructions takes 7 ns to begin generating an output then delay unit 57 may be set to delay communication of the micro-instructions to the device 42 by 20ns - 7 ns = 13 ns so that the device 42 will deliver the output at the desired time point.

[0137] In some embodiments, delay units 57 are operable to provide a settable calibration delay adjustment which is combined with delay t3. The calibration delay adjustment may be negative, zero or positive. The calibration delay adjustment may, for example, be used to compensate for variations in the time required for control signals to propagate from an IQU 50 to a controlled device 42.

[0138] In some embodiments a micro-instruction may specify a specific output to be delivered to drive a device 42. For example, the output might be selected from: a single pulse, a sequences of single pulses, an arbitrary waveform, any of these repeated a certain number of times, turning an output on and holding the output on, etc. In such embodiments, micro-instructions may be delivered to a sequence generator 58 that generates the specified output and delivers the output to an interface 44. In some embodiments, signal generator 58 is integrated with and / or controlled by DTQ logic 47C.

[0139] In some embodiments, DTQ logic 47C is configured to take certain actions conditionally depending upon results of measurements on quantum systems 21 . Tofacilitate this functionality, an IQU 50 may have access to a data store 59 that contains results of measurements made during execution of a quantum informatics process. The measurements may, for example, comprise detection of one or more photons (e.g. at measurement units 34). Data store 59 may be called a “result register bank”. Data store 59 may be included in or separate from data memory 53. In various embodiments, for one or more or all IQUs 50, the IQU 50 has a separate data store 59, data store 59 is shared by two or more IQUs 50 or data store 59 is common to all IQUs 50. The result register bank may, for example contain measurement results obtained by all IQUs that control measurement devices (e.g. measurement units 34 of Fig. 3). The result register bank may comprise a plurality of registers that are each associated with a channel. Each channel may contain results of measurements relating to a particular corresponding quantum system. Measurement results for each channel may be stored in one or a corresponding set of registers of the result register bank that is dedicated to that channel.

[0140] Data processor 51 (or another mechanism) may keep the result register bank up to date by delivering updates to data store 59. Since all current measurement results are stored in the result register bank any data processor 51 or DTQ logic 47C that has access to the register result bank can process the data in the result register bank to determine results of combined measurements on two quantum systems 21 (which can, for example, indicate whether an attempt to entangle two quantum systems succeeded or failed) without having to request measurement results from plural sources.

[0141] In some embodiments, a data processor 51 may process program execution instructions that indicate branches that are conditional on results available in data store 59. In response to such instructions, the data processor 51 may retrieve one or more results on which the branching is conditional from data store 59 and, based on the retrieved results, may alter the state of DTQ logic 47C (e.g. to cause microinstructions that should not be executed, because, for example, they belong to a branch for which a condition is not satisfied, to be flushed from queue 47.

[0142] Having measurement results immediately available in a data store 59 has example utility where repeated attempts are being made to entangle quantum states of two quantum systems 21 . If an entanglement attempt on the pair of quantum systems 21 is successful (as indicated by measurement results available in data store 59) then a further entanglement attempt on that pair of quantum systems 21 woulddestroy the entanglement. In some embodiments one or more IQUs 50 control devices that are capable of preventing further entanglement attempts on a particular pair of quantum systems 21 . Such devices may, for example control whether or not on-resonance optical pulses are delivered to the quantum systems of the pair or quantum systems. Examples of such devices are: devices that control electric field or substrate strain at locations of the quantum systems 21 (which can shift the wavelength of light required to excite an optical transition in the quantum system 21 and / or shift the resonant wavelength of an optical resonator associated with the quantum system 21), optical switches (which determine whether or not light will be routed to one or more of the quantum systems 21) and optical shutters (which may be provided to block light from reaching certain quantum systems 21). The ability to quickly disengage successfully entangled quantum systems from receiving optical pulses from an optical pulse chain (which may deliver optical pulses simultaneously to multiple quantum systems 21) can prevent entanglement from being destroyed.

[0143] Measurement results available in a result register bank may allow determining, without delay, information such as whether heralded entanglement of any two quantum systems 21 was successful or whether a quantum system 21 was successfully initialized in a particular quantum state. An IQU 50 may be configured to use this information to conditionally execute or conditionally not execute certain micro-instructions.

[0144] Interface 44 may, for example, comprise an analog interface that delivers analog signals which cause a device 42 to alter an environment of a quantum system 21 in a desired manner (e.g. by: varying a static magnetic field, a static electric field or a substrate strain at a location of the quantum system 21 , or applying an optical signal or a radiofrequency signal to the quantum system 21 , etc.). An interface 44 for a device that makes measurements may incorporate a time tagger that associates time points with measurement results, such as photon detections at the device.

[0145] As indicated schematically by arrow 54A in Fig. 5, data processor 51 may deliver micro-instructions relating to the operation of DTQ 47 to DTQ logic 47C. Such micro-instructions may, for example, cause some micro-instructions to be deleted (flushed) from queue 47 or cause queue 47 to pause outputting micro-instructions or otherwise managing queue 47.

[0146] In some embodiments the custom instructions include one or more custom instructions which result in generation of one or more micro-instruction(s) (“pulsemicro- instructions”) for causing an interface 44 to output a pulse or a sequence of pulses to an interface 44 of a controlled device 42. The pulse micro-instruction(s) may for example include one or more of:• A value that specifies a pulse mode. The pulse mode may, for example, be selected from: single pulse, pulse sequence, switch on and keep on until switched off, and switch off.• A binary number defining a pulse sequence. Each bit in the binary number may correspond to a level of the output channel of an interface 44 in a period. For example, the period may be a few ns (e.g. 10 ns). For example, the binary number may be a sequence of 5 or more bits (e.g. 10-bits). For example, the binary number 1010101010 may define a 10ns pulse that alternates between a 1 ns high signal (1 ) and 1 ns low signal (0).• A value that specifies a number of times to repeat a specified pulse or pulse sequence.• A value that specifies a “wait time” that indicates when the pulse sequence should start relative to a preceding micro-instruction.

[0147] In some embodiments an IQU 50 is configurable to alter control of a device 42 conditionally based on results of measurements. Control may be altered, for example, by deleting certain micro-instructions from queue 47 (e.g. where the results of measurements indicate that those micro-instructions are not required) and / or adding micro-instructions to queue 47. To support this functionality, in some embodiments, data processor 51 may comprise one or more custom instructions for one or more of: generate micro-instructions that specify a channel for reading detector results and a destination register for storing the detector results; determine whether or not a condition relating to detector results is satisfied (for example, the condition may check whether specified stored detector results do or do not match a specified pattern - e.g. a pattern that indicates whether or not entanglement of two quantum systems 21 has been heralded); remove or “flush” specified micro-instructions from queue 47 based on a condition.

[0148] It is generally required that the various devices controlled by different IQUs be operated in coordination with one another. In some embodiments data processor 51 is configured to receive and execute instructions for setting an absolute time reference. This feature may be used, for example, to synchronize time values for all IQUs in a system. A synchronization instruction may cause data processor 51 to loada specified value into a register to use as a new reference for absolute time point setting. In some embodiments the reference for absolute time point setting is loaded into latest time register 55A.

[0149] In some embodiments, IQUs 50 are hosted on plural modules (e.g. cards). Each module may host plural IQUs 50. Each module may host one or more configurable logic units (e.g. one or more FPGAs). In some embodiments, each module hosts plural IQUs that control devices of the same type (e.g. all IQUs of a module may be applied to control devices of the same type).

[0150] In an example embodiment, IQUs are implemented using AMC cards (i.e. cards that comply with the Advanced Mezzanine Card standard). Such cards may comply with a Telecommunications Computing Architecture (“TCA”) standard such as microTCA or Advanced TCA. In this example, each AMC card contains an FPGA. Each AMC card is assigned to a different type of device 42. For example, a type exemplified by one of devices 33C, 34 and 33A to 33F of apparatus 30 (Fig. 3). The apparatus may include control cards that host data processors (e.g. ARM data processors) that distribute instructions to instruction memories 52 as well as cards that host interfaces 44. Communication of timing and control signals and data among modules may be performed using TCA protocols.

[0151] Such a system may be scaled up by configuring more IQU’s in the FPGAs of individual cards and / or adding more cards to increase the number of IQUs that can be hosted (and the number of devices 42 that can be controlled as described herein).

[0152] Fig. 6 is a schematic illustration showing an example control apparatus 60. Apparatus 60 includes a plurality of modules 62 (which have the form factor of cards in some embodiments). Each module 62 connects to a backplane 64. Backplane 64 provides conductors for transmitting clock signals and data among cards 62.

[0153] Modules 62 include one or more controller modules 62-1 . Controller modules 62-1 each comprise one or more data processors 63 which are configured by software 64 to provide overall control of control apparatus 60. For example, the data processor(s) of controller module(s) 62-1 may perform functions such as: configuring IQUs in configurable logic as appropriate to execute a quantum informatics program and / or distributing instructions for execution by individual IQUs 50, initializing apparatus 60 etc.

[0154] Modules 62 also includes device control modules 62-2. Device control modules 62-2 are each dedicated to controlling a particular type of device 42. Fig. 6shows modules 62-2A through 62-2E which are dedicated to controlling devices of types A to E respectively. Other embodiments may have modules dedicated to controlling more or fewer types of device 42. Devices 42 may include, for example, one or more of measurement devices, light emitting devices, radiofrequency signal emitting devices, magnetic field controlling devices, electric field controlling devices, substrate strain controlling devices, and other devices that may be used to control quantum states of quantum systems of any type that are used for quantum informatics processing.

[0155] One or more of device control modules 62-2 is provided for each type of device 42 to be controlled. Depending upon the number of devices 42 of each type that are to be controlled, different numbers of device control modules 62-2 may be configured for controlling different types of device 42. Each module 62-2 hosts plural IQUs. In some embodiments, each module 62-2 includes configurable logic that can support a plurality of IQUs.

[0156] Apparatus 60 also includes one or more modules 63 that contain interfaces 44 for the devices 42 being controlled. Interfaces 44 may, for example, comprise or consist of analog interfaces. Interfaces 44 may be controlled to deliver analog voltage and / or current signals to controlled devices 42 by IQUs on device control modules 62- 2.

[0157] Fig. 7 is a block diagram that illustrates example apparatus 70 for quantum informatics processing which may integrate control apparatus as described herein. Apparatus 70 includes a quantum informatics program development environment 71 , a quantum informatics program compiler 72, a control system 73 as described herein and quantum system host hardware 74 that includes quantum systems having quantum states that may be manipulated to execute a quantum informatics program.

[0158] Development environment 71 may, for example, comprise a classical computer 71 A which executes software instructions 71 B which allow users to define quantum informatics programs 71 C, for example by specifying quantum circuits or in another manner. In some embodiments, programs 71 C are not specific to details of construction or arrangement of quantum system host hardware 74. In some embodiments, development environment 71 has no knowledge of the construction of quantum system host hardware 74 or of the nature of quantum systems used to store and / or manipulate information in quantum system host hardware 74.

[0159] Compiler 72 processes quantum programs 71C to generate instructions for executing quantum programs 71 C on quantum system host hardware 74. Compiler 72 may comprise a classical computer 72A which executes software instructions 72B for processing quantum informatics program 71C to yield instructions 72C. Compiler 72 may take input from a database 72D that includes relevant details about quantum system host hardware 74 (e.g. how many quantum systems 21 are available, how many measurement units (e.g. 34) are available, which pairs of quantum systems 21 can be directly entangled, what devices 42 are provided for controlling quantum states of quantum systems 21 , information about the rate of decoherence for different quantum systems 21 , and / or other information that can be used by compiler 72 for making a good or optimum mapping of quantum informatics program 71C to the available quantum systems 21 of quantum system host hardware 74).

[0160] Instructions 72C directly or indirectly specify actions to be taken by devices 42 in order to manipulate quantum states of quantum systems 21 hosted by quantum system host hardware 74 in order to execute a quantum informatics program 71 C.

[0161] In some embodiments, instructions 72C are separated or arranged to be separable into separate sets of instructions for different devices 42. For example, in some embodiments, instructions 72C comprise multiple binary executable instruction files. Each of these files may contain instructions for controlling a particular device 42. Execution of the instructions in all of the files in coordination with one another will execute quantum informatics program 71C on quantum system host hardware 74.

[0162] Control system 73 comprises a control system as described herein (one example being control system 60). Control system 73 takes instructions 72C and distributes program execution instructions into instruction memories 52 (see Fig. 5) for access by each IQU 50. The program execution Instructions may be the same as instructions 72C, modified versions of instructions 72C and / or instructions generated by processing instructions 72C at control system 73. Each IQU 50 has access to a corresponding subset of the program execution instructions that, when executed by the IQU 50, cause the IQU 50 to output control signals (e.g. pulses, waveforms, digital commands) for controlling a corresponding device 42 or a sequence of different devices 42. The coordinated control of devices 42 causes execution of a quantum informatics program 71 C using quantum system host hardware 74.

[0163] Quantum system host hardware 74 may include a controlled environment for quantum systems 21. For example, in the illustrated embodiment, quantum systems21 are located within a cryostat 74A which is cooled by a cryogenic refrigerator 74B to cryogenic temperatures. Electromagnetic shielding 74C may be provided to reduce electromagnetic interference from outside of cryostat 74A.

[0164] Quantum systems 21 are hosted inside cryostat 74A. Quantum systems 21 may be of any type that has quantum states which can be used for quantum informatics processing (e.g. trapped ions, neutral atoms, quantum dots, luminescence centres, superconducting circuits etc.). Devices 42 may be located inside and / or outside of cryostat 74A and arranged to interact with quantum systems 21 according to their functions.

[0165] Fig. 7 shows only two quantum systems 21 for clarity of illustration. Quantum system host hardware 74 may include any suitable number of quantum systems 21 that have quantum states that are usable for storing and / or manipulating quantum information. For example, quantum system host hardware 74 may include tens, hundreds, thousands or tens of thousands of quantum systems 21 . Each of quantum systems 21 can be controlled by control system 73 via a number of devices 42. In Fig. 7, devices 42A through 42E, respectively of different types A to E are provided for each quantum system 21. In some embodiments some devices 42 may be shared among a number of quantum systems 21 . For example, in some embodiments, a source of optical radiation (e.g. a laser) may simultaneously illuminate two or more quantum systems 21 when it is operated to emit optical radiation. In some embodiments more or fewer than five types of device 42 are provided.

[0166] In some embodiments, devices 42 of one or more types do not interact directly with quantum systems 21 . For example, some devices 42 may measure photon states emitted from a quantum systems 21 , some devices 42 may time tag events such as measurement results, some devices 42 may control other aspects of configuration of quantum system host hardware 74 (e.g. configuration of switches that control connections of quantum systems 21 to measurement devices and / or control connections that allow selected quantum systems 21 to interact with one another).

[0167] Advantageously, technology as describes herein can facilitate completely independent and high-speed control of individual devices 42 while keeping the operation of a potentially large number of devices 42 coordinated. Fast and reliable scheduling of operations to be performed is facilitated because there is no risk of conflicting operations being issued for the same device 42. Furthermore, the present technology facilitates scaling quantum informatics processing systems to includelarger numbers of quantum systems 21 since the number of IQUs 43 can be increased to support the devices 42 required to support any number of quantum systems 21 . Also, in some embodiments, micro-instructions are distributed among program memories that are local to IQUs and / or accessible to the IQUs via dedicated data paths prior to execution of a QI program. This can avoid bottlenecks that could interfere with timely handling of micro-instructions.

[0168] Fig. 8 is a flowchart that illustrates an example method 80 according to an aspect of the present technology. At block S81 a quantum informatics program 81 is created. Block S81 may, for example, comprise inputting a definition of a quantum circuit into a computer system programmed to generate instructions for executing the quantum information program. As another example block 81 may comprise inputting a definition of a protocol for operating a QIA of any type. The protocol may, for example, include steps of initializing quantum states of quantum systems, causing entanglement of quantum systems, manipulating quantum states of quantum systems, teleporting quantum states of quantum systems, making measurements on quantum systems etc.

[0169] At block S82 the quantum informatics program 81 output by block S81 is compiled to generate program execution instructions 82 for executing the quantum informatics program on a specific quantum informatics processing apparatus. The quantum informatics processing apparatus may, for example, comprise QIA 40 (see Fig. 4). Program execution instructions 82 specify actions to be performed by a plurality of devices 42 to cause the quantum informatics processing apparatus to execute quantum informatics program 81.

[0170] In some embodiments block S82 determines how many or both how many and which quantum systems 21 of the quantum informatics processing apparatus to use for executing quantum informatics program 81.

[0171] In some embodiments, program execution instructions 82 are arranged to provide distinct sets of instructions with each distinct set of instructions corresponding to a particular one of devices 42 (see e.g. program execution instruction sets 41A to 41 E in Fig. 4). In some embodiments, each set of program execution instructions 82 is provided in a separate file.

[0172] Block S83 configures the quantum informatics processing apparatus to execute quantum informatics program 81. Block S83 comprises block S83A which distributes those of program execution instructions 82 for controlling each device 42to be used for executing quantum informatics program 81 to a location (e.g. an instruction memory such as an instruction memory 52) from which those program execution instructions 82 can be accessed by an IQU (e.g. 43, 50) which will control the device 42 during execution of quantum informatics program 81.

[0173] In some embodiments block S83 also comprises block S83B which configures configurable logic of the quantum informatics processing apparatus to provide a sufficient number of IQUs 43, 50 for controlling those devices 42 that will be needed to execute quantum informatics program 81.

[0174] In some embodiments, block S83B configures the configurable logic to provide and / or allocate memory accessible by each of the IQUs 43, 50 to receive the program execution instructions to be delivered to the device 42 (or series of devices 42) which the IQU 43, 50 will control (e.g. by outputting micro-instructions according to the applicable program instructions 82).

[0175] In block S84 quantum informatics process 81 is executed. Block S84 may be performed by a QIA 40. Block S84 comprises making timing signals (e.g. global counters) available to each of IQUs 43, 50 and allowing IQUs 43, 50 to deliver microinstructions at associated time points, as required by program execution instructions 82. The coordinated and synchronized delivery of micro-instructions for control of devices 42 causes execution of quantum informatics program 81.

[0176] The present technology may be adapted to control QIAs that include quantum systems of any of a wide variety of types (e.g. superconducting qubits of various constructions, trapped ions, neutral atoms, etc.). Different selections of devices may be required to control quantum systems of different types. Such devices may be controlled using apparatus and methods as described herein. Those of ordinary skill in the art having read and understood this disclosure will further understand that the present technology is also applicable to controlling quantum systems in contexts that do not necessarily involve executing quantum circuits or performing quantum computing. For example, the technology as described herein may be used in quantum communications, for example to control quantum systems in quantum repeaters, quantum information storage devices, and the like.

[0177] Where a component (e.g. a software module, processor, assembly, device, circuit, etc.) is referred to herein, unless otherwise indicated, reference to that component (including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of thedescribed component (i.e. , that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0178] IQUs 43, 50 may be implemented using specifically designed hardware, configurable hardware, programmable data processors configured by the provision of software (which may optionally comprise “firmware”) capable of executing on the data processors, special purpose computers or data processors that are specifically programmed, configured, or constructed to perform one or more steps in a method as explained in detail herein and / or combinations of two or more of these. Examples of specifically designed hardware are: logic circuits, application-specific integrated circuits (“ASICs”), large scale integrated circuits (“ LSI s”), very large scale integrated circuits (“VLSIs”), and the like. Examples of configurable hardware are: one or more programmable logic devices such as programmable array logic (“PALs”), programmable logic arrays (“PLAs”), and field programmable gate arrays (“FPGAs”). Examples of programmable data processors are: microprocessors, digital signal processors (“DSPs”), embedded processors, graphics processors, math coprocessors, general purpose computers, server computers, cloud computers, mainframe computers, computer workstations, and the like. For example, one or more data processors in a control circuit for a device may implement methods as described herein by executing software instructions in a program memory accessible to the processors.

[0179] In some embodiments an IQU includes more than one queue 47 served by one or more data processor 51. In such embodiments the data processor(s) 51 should be fast enough to insert micro-instructions into each served queue 47 in time for the micro-instructions to cause the controlled devices to perform actions specified by the micro-instructions at the corresponding time points.

[0180] Advantageously, in embodiments for which there is a 1 :1 correspondence between data processors 51 and queues 47 (e.g. as in QIA 40) the likelihood of conflicts at processors 51 between conflicting program execution instructions for the same device or for different devices is reduced or altogether avoided.

[0181] Processing may be centralized or distributed. Where processing is distributed, information including software and / or data may be kept centrally or distributed. Such information may be exchanged between different functional units by way of a communications network, such as a serial data link, Local Area Network (LAN), WideArea Network (WAN), or the Internet, wired or wireless data links, electromagnetic signals, or other data communication channel.

[0182] Aspects of the invention may also be provided in the form of a program product. The program product may comprise any non-transitory medium which carries a set of computer-readable instructions which, when executed by a data processor, cause the data processor to execute a method of the invention and / or to configure hardware to provide apparatus as described herein. For example, a program product may configure a computer system to compile a quantum informatics program as described herein, cause configurable logic in a quantum informatics processing apparatus to be configured to provide IQUs 43 as descried herein, or perform other data processing as described herein.

[0183] A program products according to the invention may be in any of a wide variety of forms. The program product may comprise, for example, non-transitory media such as magnetic data storage media including floppy diskettes, hard disk drives, optical data storage media including CD ROMs, DVDs, electronic data storage media including ROMs, flash RAM, EPROMs, hardwired or preprogrammed chips (e.g., EEPROM semiconductor chips), nanotechnology memory, or the like. The computer- readable signals on the program product may optionally be compressed or encrypted.

[0184] In some embodiments, the invention may be implemented in software. For greater clarity, “software” includes any instructions executed on a processor, and may include (but is not limited to) firmware, resident software, microcode, code for configuring a configurable logic circuit, applications, apps, and the like. Both processing hardware and software may be centralized or distributed (or a combination thereof), in whole or in part, as known to those skilled in the art. For example, software and other modules may be accessible via local memory, via a network, via a browser or other application in a distributed computing context, or via other means suitable for the purposes described above.

[0185] Software and other modules may reside on servers, workstations, personal computers, tablet computers, and other devices suitable for the purposes described herein.Interpretation of Terms

[0186] Unless the context clearly requires otherwise, throughout the description and the claims:“comprise”, “comprising”, and the like are to be construed in an inclusive sense,as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”;• “connected”, “coupled”, or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof;• “herein”, “above”, “below”, and words of similar import, when used to describe this specification, shall refer to this specification as a whole, and not to any particular portions of this specification;• “or”, in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list;• the singular forms “a”, “an”, and “the” also include the meaning of any appropriate plural forms. These terms (“a”, “an”, and “the”) mean one or more unless stated otherwise;• “and / or” is used to indicate one or both stated cases may occur, for example A and / or B includes both (A and B) and (A or B);• “approximately” when applied to a numerical value means the numerical value ± 10%;• where a feature is described as being “optional” or “optionally” present or described as being present “in some embodiments” it is intended that the present disclosure encompasses embodiments where that feature is present and other embodiments where that feature is not necessarily present and other embodiments where that feature is excluded. Further, where any combination of features is described in this application this statement is intended to serve as antecedent basis for the use of exclusive terminology such as "solely," "only" and the like in relation to the combination of features as well as the use of "negative" limitation(s)” to exclude the presence of other features; and• “first” and “second” are used for descriptive purposes and cannot be understood as indicating or implying relative importance or indicating the number of indicated technical features.

[0187] Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “left”, “right”, “front”, “back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present), depend on the specific orientation ofthe apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.

[0188] Where a range for a value is stated, the stated range includes all sub-ranges of the range. It is intended that the statement of a range supports the value being at an endpoint of the range as well as at any intervening value to the tenth of the unit of the lower limit of the range, as well as any subrange or sets of sub ranges of the range unless the context clearly dictates otherwise or any portion(s) of the stated range is specifically excluded. Where the stated range includes one or both endpoints of the range, ranges excluding either or both of those included endpoints are also included in the invention.

[0189] Certain numerical values described herein are preceded by "about". In this context, "about" provides literal support for the exact numerical value that it precedes, the exact numerical value ±5%, as well as all other numerical values that are near to or approximately equal to that numerical value. Unless otherwise indicated a particular numerical value is included in “about” a specifically recited numerical value where the particular numerical value provides the substantial equivalent of the specifically recited numerical value in the context in which the specifically recited numerical value is presented. For example, a statement that something has the numerical value of “about 10” is to be interpreted as: the set of statements:• in some embodiments the numerical value is 10;• in some embodiments the numerical value is in the range of 9.5 to 10.5;• and if from the context the person of ordinary skill in the art would understand that values within a certain range are substantially equivalent to 10 because the values with the range would be understood to provide substantially the same result as the value 10 then “about 10” also includes:• in some embodiments the numerical value is in the range of C to D where C and D are respectively lower and upper endpoints of the range that encompasses all of those values that provide a substantial equivalent to the value 10.

[0190] Specific examples of systems, methods and apparatus have been described herein for purposes of illustration. These are only examples. The technology providedherein can be applied to systems other than the example systems described above. Many alterations, modifications, additions, omissions, and permutations are possible within the practice of this invention. This invention includes variations on described embodiments that would be apparent to the skilled addressee, including variations obtained by: replacing features, elements and / or acts with equivalent features, elements and / or acts; mixing and matching of features, elements and / or acts from different embodiments; combining features, elements and / or acts from embodiments as described herein with features, elements and / or acts of other technology; and / or omitting combining features, elements and / or acts from described embodiments.

[0191] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any other described embodiment(s) without departing from the scope of the present invention.

[0192] Any aspects described above in reference to apparatus may also apply to methods and vice versa.

[0193] Any recited method can be carried out in the order of events recited or in any other order which is logically possible. For example, while processes or blocks are presented in a given order, alternative examples may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, simultaneously or at different times.

[0194] Various features are described herein as being present in “some embodiments”. Such features are not mandatory and may not be present in all embodiments. Embodiments of the invention may include zero, any one or any combination of two or more of such features. All possible combinations of such features are contemplated by this disclosure even where such features are shown in different drawings and / or described in different sections or paragraphs. This is limited only to the extent that certain ones of such features are incompatible with other ones of such features in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment that combines such incompatiblefeatures. Consequently, the description that “some embodiments” possess feature A and “some embodiments” possess feature B should be interpreted as an express indication that the inventors also contemplate embodiments which combine features A and B (unless the description states otherwise or features A and B are fundamentally incompatible). This is the case even if features A and B are illustrated in different drawings and / or mentioned in different paragraphs, sections or sentences.

[0195] It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions, omissions, and sub-combinations as may reasonably be inferred. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.

Claims

WHAT IS CLAIMED IS:1 . A control system for a quantum informatics apparatus (QIA) that comprises a plurality of quantum systems and a plurality of devices operative to control quantum states of the quantum systems, the control system comprising: a plurality of instruction queuing units (IQUs) wherein each of the IQUs comprises a data processor, a queue, and queue control logic; wherein: each of the IQUs is associated with a corresponding one of the devices of the QIA, and each queue is configured to hold: a plurality of micro-instructions for control of the corresponding device, and a time point associated with each of the plurality of microinstructions; the data processor of each IQU is configured to process program execution instructions for the corresponding device and, in response to the program execution instructions, insert micro-instructions for controlling the corresponding device and the time point associated with each inserted micro-instruction into the queue of the IQU; and the queue control logic is configured to release the micro-instructions for controlling the corresponding device at times based on the time point associated with each of the micro-instructions.

2. The control system according to claim 1 wherein the queue control logic is configured to release each of the micro-instructions when the time point associated with the micro-instruction matches the current time.

3. The control system according to claim 1 wherein the IQU is configured to assign the time point to the micro-instruction such that the time point is before a desired execution time for the micro-instruction and the queue control logic is configured to apply a delay before releasing the micro-instruction.

4. The control system according to claim 3 wherein the delay compensates for a latency between release of the micro-instruction and performance of an actioncorresponding to the micro-instruction by the corresponding one of the devices.

5. The control system according to claim 4 wherein the latency for each of the IQUs is based on: a time for the control logic of the IQU to output a control signal for controlling the device after the micro-instruction is released; and calibration data that indicates a time for the associated one of the devices to perform the action after the control signal is output.

6. The control system according to any of the preceding claims wherein the control logic comprises a state machine.

7. The control system according to any of the preceding claims wherein the control logic is implemented by a combination of combinational and sequential logic.

8. The control system according to any of the preceding claims wherein: the plurality of devices includes devices of a plurality of different types, those of the IQUs associated with at least one of the types of the devices each comprise a sequence generator, and in response to release of a micro-instruction that specifies a sequence, the sequence generator is operative to generate a sequence of output pulses corresponding to the specified sequence.

9. The control system according to claim 8 wherein the micro-instruction that specifies the sequence incorporates a binary number that defined the pulse sequence.

10. The control system according to claim 9 wherein the binary number comprises a sequence of bit values and each of the bit values of the binary number specifies whether a pulse is present or not present during a time interval that corresponds to the bit value.11 . The control system according to any of the preceding claims wherein the IQUs are provided in the form of application specific integrated circuits (ASICs).

12. The control system according to claim 11 wherein one or more of the ASICs provides a plurality of the IQUs.

13. The control system according to claim 12 wherein the one or more of the ASICs comprises one or more instruction memories for the plurality of IQUs on the one or more of the ASICs.

14. The control system according to any of the preceding claims wherein at least some of the IQUs are implemented at least in part in configurable logic.

15. The control system according to claim 14 wherein: the devices comprise devices of a plurality of types; the control system comprises a plurality of configurable logic units; and each of the plurality of configurable logic units hosts a plurality of the IQUs.

16. The control system according to claim 15 wherein the IQUs hosted on each of the plurality of configurable logic units are associated with devices of the same one of the plurality of types of devices.

17. The control system according to any of claims 14 to 16 wherein the configurable logic comprises a field programmable gate array (FPGA).

18. The control system according to any of the preceding claims comprising at least one result register bank accessible by the IQUs, the at least one result register bank storing results of measurements obtained by one or more measurement units.

19. The control system according to claim 18 wherein the IQUs are configurable to release one or more micro-instructions conditionally based on one or more measurement results retrieved from the one or more result register bank.

20. The control system according to claim 18 or 19 wherein the devices comprise at least one time tagger device, the at least one time tagger devices each being configured to receive measurement results from one of the one or more measurement units and associate a time point to each of the received measurement results.21 . The control system according to claim 20 wherein the control system is configured to store the measurement results and the time points associated with the measurement results by the one or more time tagger device in the one or more results register bank.

22. The control system according to any of the preceding claims wherein the data processors for at least some of the IQUs comprise instruction sets that include custom instructions for one or more of: filling the queue, calibration, prefilling control, communication, synchronization and switching.

23. The control system according to claim 22 wherein the custom instructions include one or more custom instructions which cause the data processor to adjust the time points associated with micro-instructions by adding a predefined delay.

24. The control system according to claim 22 or 23 wherein the custom instructions include instructions that cause the data processor to place the queue of the IQU or a portion of the queue of the IQU in a locked mode such that any microinstructions in the queue or portion of the queue are prevented from being released.

25. The control system according to claim 24, wherein the control system is configurable to: prefill a first portion of the IQU with micro-instructions that correspond to a first condition being satisfied; prefill a second portion of the IQU with micro-instructions that correspond to a second condition being satisfied; and lock the first portion and the second portion of the IQU.

26. The control system according to claim 25, wherein the control system is further configurable to: if the first condition is satisfied, unlock the first portion of the IQU and flush the second portion of the IQU; and if the second condition is satisfied, unlock the second portion of the IQU and flush the first portion of the IQU.

27. The control system according to any of claims 22 to 26 wherein the custom instructions include instructions which cause the data processor to perform one or more of: reading a current value of the time point corresponding to the latest scheduled micro-instruction; setting the time point for the next scheduled microinstruction to have a specified value; and reading a current system time.

28. The control system according to any of claims 22 to 27 wherein the custom instructions include instructions which cause the data processor to issue control signals to control configuration of one or more switches that control routing of optical and / or electrical signals in the QIA.

29. The control system according to any of the preceding claims wherein the IQUs include a latest time register (LTR) and are configured to store, in the LTR, a time point associated with an immediately preceding micro-instruction, and the IQU is configured to generate the time point for a next micro-instruction to be inserted into the queue based on the time point stored in the LTR.

30. The control system according to any of the preceding claims wherein the control system is configurable to switch at least one of the IQUs from controlling one of the devices to controlling a different one of the devices during execution of a program.31 . The control system according to any of the preceding claims wherein at least one of the devices comprises first and second control inputs, a first one of the IQUs is configured to generate control signals for a first one of the control inputs, and a second one of the IQUs is configured to generate control signals for a second one of the control inputs.

32. The control system according to any of the preceding claims further comprising a controller.

33. The control system according to claim 32 wherein: the controller is configured to distribute program execution instructionsamong a plurality of instruction memories that are each accessible by at least one of the IQUs; and each of the IQUs is configured to retrieve those of the program execution instructions associated with the device corresponding to the IQU from one of the instruction memories.

34. The control system according to claim 32 or 33 wherein each of the instruction memories is dedicated to a corresponding one of the IQUs.

35. The control system according to claim 34 wherein each of the dedicated instruction memories is shared by the controller and the one of the IQUs to which the instruction memory is dedicated.

36. The control system according to any of the preceding claims wherein the IQUs of the control system are coordinated such that when any two or more of the IQUs release micro-instructions associated with the same time point, the micro-instructions are released by each of the two or more IQUs such that the devices controlled by the two or more IQUs commence actions specified by the micro-instructions at times separated by no more than + / - 10 ns.

37. The control system according to any of the preceding claims comprising one or more analog interfaces, each of the analog interfaces configured to generate and deliver to one of the devices analog signals in response to control signals from one of the IQUs.

38. The control system according to any of the preceding claims in combination with the QIA.

39. The control system according to claim 38 wherein the QIA comprises one or more of: a quantum computer, a quantum repeater, a quantum data communication network, a quantum information storage device, and a quantum encryption device.

40. The control system according to claim 38 or 39 wherein the devices comprise devices of one or more of the following device types: devices that control magneticfields, devices that control electric fields, devices that control substrate strains, devices that control optical sources, devices that control radiofrequency sources, devices that control switches, and devices that control measurement units.41 . A method for controlling a quantum information apparatus (QIA) comprising a plurality of quantum systems and a plurality of devices operative to control quantum states of the quantum systems, the method comprising: for each of the devices, inserting micro-instructions for controlling the device into a queue corresponding to the device together with a time point corresponding to each of the micro-instructions; and from each of the queues, releasing the micro-instructions at times based on the time points associated with the micro-instructions.

42. The method according to claim 41 wherein releasing the micro-instructions is performed by deterministic queue control logic.

43. The method according to claim 41 or claim 42 wherein, for at least one of the micro-instructions, the time point associated with the micro-instruction is before a desired execution time for the micro-instruction and the method comprises applying a delay before releasing the micro-instruction.

44. The method according to claim 43 wherein the delay compensates for a latency between release of the micro-instruction and performance of an action corresponding to the micro-instruction by the corresponding one of the devices.

45. The method according to any one of claims 41 to 44 wherein, for each of the devices, inserting micro-instructions for controlling the device into the queue is performed by a data processor associated with the queue, wherein each queue is associated with only one data processor.

46. The method according to claim 45 wherein each of the data processors is associated with only one of the queues.

47. The method according to any of claims 41 to 46 comprising generating themicro-instructions based on program execution instructions, wherein the method comprises distributing the program execution instructions to a plurality of instruction queuing units (IQUs), each of the IQUs associated with one of the devices, such that each IQU receives a set of the program execution instructions for controlling the device associated with the IQU.

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