Storage device

Abstract

Provided is a storage device that has a novel configuration. A first memory cell includes first to third transistors. A second memory cell includes fourth to sixth transistors. A switch circuit includes seventh and eighth transistors. One of the source and the drain of the seventh transistor is connected to one of the source and the drain of the first transistor and the gate of the second transistor. The other of the source and the drain of the seventh transistor is connected to one of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor. One of the source and the drain of the eighth transistor is connected to one of the source and the drain of the second transistor and one of the source and the drain of the third transistor. The other of the source and the drain of the eighth transistor is connected to one of the source and the drain of the fourth transistor and the gate of the fifth transistor.

Description

storage device

[0001] This specification describes storage devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] A dynamic random access memory (DRAM) having a three-transistor (3Tr) gain cell is known (see, for example, Japanese Patent Application Laid-Open No. 2003-222294).

[0004] U.S. Patent No. 9,922,696

[0005] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0006] 3Tr type gain cells have features such as high memory density and high rewrite endurance. Furthermore, SRAM (Static Random Access Memory) type memory cells have features such as superior operating speed compared to 3Tr type gain cells. For memory cells with different features, a circuit configuration that meets the required circuit specifications is desirable. However, when the circuit configurations differ, it is difficult to change the circuit configuration of the memory cell according to the application after manufacturing.

[0007] An object of one embodiment of the present invention is to provide a memory device in which the circuit configuration of a memory cell can be switched after manufacturing.Another object of one embodiment of the present invention is to provide a memory device including a memory cell that is less susceptible to variations in electrical characteristics of a transistor.Another object of one embodiment of the present invention is to provide a memory device that has excellent read and write speeds for memory cells.Another object of one embodiment of the present invention is to provide a memory device that is excellent in low power consumption.Another object is to provide a memory device with a novel structure.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0009] One embodiment of the present invention includes a first memory cell, a second memory cell, and a switch circuit, wherein the first memory cell includes a first transistor, a second transistor, and a third transistor, the second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor, and the switch circuit includes a seventh transistor and an eighth transistor, wherein one of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, one of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor is electrically connected to a gate of the fifth transistor, and one of the source or a drain of the fifth transistor is electrically connected to the source of the sixth transistor. or one of the drains of the seventh transistor is electrically connected to one of the source or drain of the first transistor and the gate of the second transistor, the other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor and one of the source or drain of the sixth transistor, the one of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the second transistor and one of the source or drain of the third transistor, and the other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the fourth transistor and the gate of the fifth transistor.

[0010] In one embodiment of the present invention, a memory device preferably includes first to fourth wirings, in which the other of the source and the drain of the first transistor is electrically connected to the first wiring, the other of the source and the drain of the third transistor is electrically connected to the second wiring, the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, and the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring.

[0011] In one embodiment of the present invention, the memory device preferably has a fifth wiring and a sixth wiring, the gate of the first transistor and the gate of the fourth transistor are electrically connected to the fifth wiring, and the gate of the third transistor and the gate of the sixth transistor are electrically connected to the sixth wiring.

[0012] In one embodiment of the present invention, the memory device preferably includes a seventh wiring, and a gate of the seventh transistor and a gate of the eighth transistor are electrically connected to the seventh wiring.

[0013] In one embodiment of the present invention, in the memory device, each of the seventh transistor and the eighth transistor preferably includes a semiconductor layer having a channel formation region, and the semiconductor layer preferably includes an oxide semiconductor.

[0014] In one embodiment of the present invention, the seventh transistor and the eighth transistor are preferably n-channel transistors, and a high-level potential that turns on the seventh transistor and the eighth transistor is preferably a potential higher than a potential that turns on or off the first memory cell and the second memory cell.

[0015] In one aspect of the present invention, the first memory cell and the second memory cell are preferably memory cells arranged adjacent to each other.

[0016] In one aspect of the present invention, the memory device preferably includes a third memory cell, the third memory cell being disposed between the first memory cell and the second memory cell.

[0017] In one aspect of the present invention, a preferred memory device is one in which the first memory cell has a first capacitor, the second memory cell has a second capacitor, a first electrode of the first capacitor is electrically connected to one of the source or drain of the first transistor, the gate of the second transistor, and one of the source or drain of the seventh transistor, and a first electrode of the second capacitor is electrically connected to one of the source or drain of the fourth transistor, the gate of the fifth transistor, and the other of the source or drain of the eighth transistor.

[0018] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0019] One embodiment of the present invention can provide a memory device in which the circuit configuration of a memory cell can be switched after manufacturing. Another embodiment of the present invention can provide a memory device having memory cells that are less susceptible to variations in electrical characteristics of transistors. Another embodiment of the present invention can provide a memory device with excellent read and write speeds for memory cells. Another embodiment of the present invention can provide a memory device with excellent low power consumption.

[0020] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0021] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of a memory device. FIG. 2 is a diagram illustrating an example of the configuration of a memory device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a memory device. FIGS. 4A and 4B are diagrams illustrating an example of the configuration of a memory device. FIGS. 5A, 5B, and 5C are diagrams illustrating an example of the configuration of a memory device. FIGS. 6A, 6B, and 6C are diagrams illustrating an example of the configuration of a memory device. FIGS. 7A, 7B, and 7C are diagrams illustrating an example of the configuration of a memory device. FIGS. 8A and 8B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 8C is a cross-sectional view illustrating an indium oxide film. FIG. 9 is a diagram illustrating various memory devices by layer. FIGS. 10A and 10B are diagrams illustrating an example of an electronic component. FIGS. 11A and 11B are diagrams illustrating an example of an electronic device. FIGS. 12A, 12B, and 12C are diagrams illustrating an example of an electronic device. FIG. 13 is a diagram illustrating an example of a mainframe computer.

[0022] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0024] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0025] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0026] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0027] Embodiment 1 A structure, operation, and the like of a storage device according to one embodiment of the present invention will be described.

[0028] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0029] 1A is a schematic diagram illustrating a memory device 100 according to one embodiment of the present invention. FIG. 1B is a circuit diagram illustrating a configuration example of a memory cell CEL and a switch circuit SEL included in the memory device 100.

[0030] The memory device 100 includes an element layer 10 and an element layer 30 provided to overlap the element layer 10. In the schematic diagram shown in Figure 1A, the element layer 10 and the element layer 30 provided to overlap the element layer 10 are shown separated from each other to make it easier to understand the arrangement of each element constituting the memory device 100. Note that the element layer is a layer in which a semiconductor element such as a transistor or a capacitor is provided.

[0031] 1B also illustrates a wiring relationship between two (a pair or a set) memory cells CEL (typically CEL_1 and CEL_2) included in the element layer 10 and a switch circuit SEL (typically SEL_1) included in the element layer 30. Note that in the following description, the transistors included in the memory cell CEL and the switch circuit SEL are n-channel transistors, for example. The memory device 100 of one embodiment of the present invention can also be a p-channel transistor by changing the potential of a signal applied to the transistors included in the memory cell CEL and the switch circuit SEL. Note that an n-channel transistor can be made conductive (on state) at a high-level potential (H level) and non-conductive (off state) at a low-level potential (L level).

[0032] 1A, in order to explain the arrangement of each component, the Z direction is defined as a direction perpendicular or approximately perpendicular to the surface of the element layer 10 (for example, a surface on which an interlayer insulating layer is provided). For ease of understanding, the Z direction may be referred to as a direction perpendicular to the surface of the element layer 10 in the specification. Note that "approximately perpendicular" refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0033] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in FIG. 1A, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the storage device 100. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.

[0034] The element layer 10 includes, for example, a memory cell array 11 in which a plurality of memory cells CEL are provided, a bit line side driver circuit 12, a word line side driver circuit 13, a switching driver circuit 14, and a control circuit 15. The element layer 30 includes a plurality of switch circuits SEL.

[0035] The memory cell CEL has a function of holding an amount of charge corresponding to a data value. The memory cell CEL is connected to a wiring that functions as a bit line or a word line, and data writing or reading is controlled. The memory cell CEL may also be called a memory circuit, a memory cell, a data holding circuit, etc.

[0036] The switch circuit SEL has a function of switching a signal path between two memory cells CEL. The switch circuit SEL has a transistor that functions as a switch. The switch circuit SEL is connected to wiring that controls the conductive state or non-conductive state of the transistor that functions as a switch. The switch circuit SEL may also be called a switching circuit, a path holding circuit, etc.

[0037] 1B illustrates memory cells CEL_1 and CEL_2 as an example of the memory cell CEL in FIG. 1A. In FIG. 1B, a switch circuit SEL_1 is illustrated as an example of the switch circuit SEL in FIG. 1A. The memory cell CEL_1 may be referred to as a first memory cell. The memory cell CEL_2 may be referred to as a second memory cell.

[0038] The memory cell CEL_1 includes transistors M11 to M13 and a capacitor C11. The memory cell CEL_1 is connected to wirings CLA_1 and CLB_1 arranged in the column direction and wirings RLA_1 and RLB_1 arranged in the row direction. The transistor M11 may be referred to as a first transistor. The transistor M12 may be referred to as a second transistor. The transistor M13 may be referred to as a third transistor. The capacitor C11 may be referred to as a first capacitor.

[0039] The transistors M11 to M13 and the capacitor C11 are connected to the wirings CLA_1, CLB_1 and RLA_1, RLB_1 as shown in FIG. 1B . Specifically, one of the source or the drain of the transistor M11 is connected to the gate of the transistor M12. The other of the source or the drain of the transistor M11 is connected to the wiring CLA_1. The gate of the transistor M11 is connected to the wiring RLA_1. One of the source or the drain of the transistor M12 is connected to one of the source or the drain of the transistor M13. The other of the source or the drain of the transistor M12 is connected to a constant potential line, for example, a ground line. The other of the source or the drain of the transistor M13 is connected to the wiring CLB_1. The gate of the transistor M13 is connected to the wiring RLB_1. A first electrode of the capacitor C11 is connected to one of the source or the drain of the transistor M11 and the gate of the transistor M12. The second electrode of the capacitor C11 is connected to a constant potential line, for example, a ground line.

[0040] The memory cell CEL_2 includes transistors M21 to M23 and a capacitor C21. The memory cell CEL_2 is connected to wirings CLA2 and CLB2 arranged in the column direction and wirings RLA_1 and RLB_1 arranged in the row direction. The transistor M21 may be referred to as a fourth transistor. The transistor M22 may be referred to as a fifth transistor. The transistor M23 may be referred to as a sixth transistor. The capacitor C21 may be referred to as a second capacitor.

[0041] The transistors M21 to M23 and the capacitor C21 are connected to the wirings CLA2, CLB2 and RLA_1, RLB_1 as shown in FIG. 1B . Specifically, one of the source or drain of the transistor M21 is connected to the gate of the transistor M22. The other of the source or drain of the transistor M21 is connected to the wiring CLA2. The gate of the transistor M21 is connected to the wiring RLA_1. One of the source or drain of the transistor M22 is connected to one of the source or drain of the transistor M23. The other of the source or drain of the transistor M22 is connected to a constant potential line, for example, a ground line. The other of the source or drain of the transistor M23 is connected to the wiring CLB2. The gate of the transistor M23 is connected to the wiring RLB_1. A first electrode of the capacitor C21 is connected to one of the source or drain of the transistor M21 and the gate of the transistor M22. The second electrode of the capacitor C21 is connected to a constant potential line, for example, a ground line.

[0042] The switch circuit SEL_1 has transistors M51 and M52. The switch circuit SEL_1 is connected to memory cells CEL_1 and CEL_2 arranged in the element layer 10. The switch circuit SEL_1 is connected to a wiring SEN_1 arranged to extend through the element layers 10 and 30. The transistor M51 may be referred to as a seventh transistor. The transistor M52 may be referred to as an eighth transistor.

[0043] The transistors M51 and M52 are connected to the wiring SEN_1 and the memory cells CEL_1 and CEL_2 as shown in FIG. 1B . Specifically, one of the source or drain of the transistor M51 is connected to one of the source or drain of the transistor M11, the first electrode of the capacitor C11, and the gate of the transistor M12. The other of the source or drain of the transistor M51 is connected to one of the source or drain of the transistor M22 and one of the source or drain of the transistor M23. The gate of the transistor M51 is connected to the wiring SEN_1. The one of the source or drain of the transistor M52 is connected to one of the source or drain of the transistor M21, the first electrode of the capacitor C21, and the gate of the transistor M22. The other of the source or drain of the transistor M52 is connected to one of the source or drain of the transistor M12 and one of the source or drain of the transistor M13. The gate of the transistor M52 is connected to the wiring SEN_1.

[0044] The switch circuit SEL_1 switches between two signal paths between the memory cells CEL_1 and CEL_2 using two transistors that function as switches. Specifically, by making the transistor between the memory cells CEL_1 and CEL_2 non-conductive, the circuit configuration can be switched to that of a 3Tr gain cell DRAM, and by making the transistor between the memory cells CEL_1 and CEL_2 conductive, the circuit configuration can be switched to that of a 4Tr SRAM.

[0045] The bit line side driver circuit 12 is a circuit that has the function of writing and reading data to the memory cells CEL via wiring that functions as bit lines (wirings CLA and CLB arranged in the column direction) connected to the memory cells CEL. The bit line side driver circuit 12 has the function of switching signals supplied to the wiring that functions as bit lines in accordance with the control of the control circuit 15. With this configuration, it is possible to write and read data in accordance with switching the circuit configuration of the memory cells CEL.

[0046] The word line side driver circuit 13 is a circuit that has a function of supplying a word signal or a constant potential to the memory cell CEL via wirings (wirings RLA and RLB arranged in the row direction) that function as word lines connected to the memory cell CEL. The word line side driver circuit 13 has a function of switching between the word signal and the constant potential under the control of the control circuit 15. With this configuration, it is possible to write and read data in accordance with switching the circuit configuration in the memory cell CEL.

[0047] The switching drive circuit 14 has a function of supplying a signal that controls the conductive or non-conductive state of the transistor in the switch circuit SEL, that is, the on or off state of the transistor that functions as a switch, via a wiring (wiring SEN) that extends to the upper element layer 30. The switching drive circuit 14 has a function of switching the on or off state of the switch in the switch circuit SEL in accordance with the control of the control circuit 15. With this configuration, it is possible to switch the circuit configuration in the memory cell CEL.

[0048] Note that the high-level potential of the signal supplied to the wiring SEN is preferably higher than the high-level potential of a signal that controls the conductive state or non-conductive state of the transistor included in the memory cell CEL, for example, the high-level potential of a signal supplied to the wiring RLA_1. With this configuration, the amount of current that flows when the transistor functioning as a switch is turned on can be made sufficiently large.

[0049] The control circuit 15 outputs signals to control the bit line side drive circuit 12, the word line side drive circuit 13, and the switching drive circuit 14 in accordance with switching of the circuit configuration of the memory cell CEL. The circuit configuration of the memory cell CEL can be switched at a timing according to a pre-set setting, such as when the storage device 100 is started up.

[0050] The element layer 10 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region. The element layer 10 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0051] Although the substrate provided in the element layer 10 is described as a silicon substrate, this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystal silicon substrate. The substrate is not limited to silicon, and may be made of materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide).

[0052] The Si transistors in the element layer 10 are made of highly crystalline silicon, such as single crystal silicon or polycrystalline silicon. The highly crystalline silicon in the element layer 10 allows for high field-effect mobility and faster operation. Therefore, the element layer 10 can be provided with a memory cell array 11, a bit line side driver circuit 12, a word line side driver circuit 13, a switching driver circuit 14, and a control circuit 15 integrated therein.

[0053] Note that the element layer 10 can also have a configuration including an arithmetic processing circuit that performs arithmetic processing using data stored in the memory cell array 11. In the memory device 100 of one embodiment of the present invention, the memory cells CEL included in the memory cell array 11 can be switched between a circuit configuration of an SRAM with excellent operating speed and a circuit configuration of a DRAM with excellent storage density. By using an SRAM memory cell or a DRAM memory cell as the circuit configuration of the memory cells CEL included in the memory cell array 11, it is possible to selectively increase or decrease the storage capacity of the main memory accessed by the arithmetic processing circuit or the storage capacity of the cache memory accessed by the arithmetic processing circuit. The storage capacity or access speed of the memory device that stores data used for arithmetic processing can be selectively switched.

[0054] The element layer 30 includes a transistor (OS transistor) having an oxide semiconductor (metal oxide) in a semiconductor layer having a channel formation region.

[0055] As the oxide semiconductor used in the OS transistor, for example, an In—Ga—Zn oxide or an indium oxide (In oxide or indium oxide) can be used. Examples of the atomic ratio of metal elements in In—Ga—Zn oxide include a composition in which In:Ga:Zn=1:1:1 or thereabouts, a composition in which In:Ga:Zn=1:1:1.2 or thereabouts, a composition in which In:Ga:Zn=2:1:3 or thereabouts, a composition in which In:Ga:Zn=3:1:2 or thereabouts, a composition in which In:Ga:Zn=4:2:3 or thereabouts, a composition in which In:Ga:Zn=4:2:4.1 or thereabouts, a composition in which In:Ga:Zn=5:1:3 or thereabouts, a composition in which In:Ga:Zn=5:1:6 or thereabouts, a composition in which In:Ga:Zn=5:1:7 or thereabouts, a composition in which In:Ga:Zn=5:1:8 or thereabouts, a composition in which In:Ga:Zn=6:1:6 or thereabouts, and a composition in which In:Ga:Zn=5:2:5 or thereabouts.

[0056] The element layer 30 including the OS transistor can be stacked over the element layer 10. By providing the element layer 30 over the element layer 10, the transistor density per unit area can be increased. Furthermore, the off-state current of an OS transistor is extremely low. Therefore, when the transistors M51 and M52 functioning as switches in the switch circuit SEL are turned off, the current flowing between the source and drain can be made extremely small. Therefore, the power consumption of the memory device 100 of one embodiment of the present invention can be reduced, and the reliability of data held in the memory cell CEL can be improved.

[0057] The element layer 30 including the OS transistor can be manufactured during the wiring process of the element layer 10. That is, the element layer 30 can be manufactured in the back end of line (BEOL). Therefore, the area overhead for providing the OS transistor can be eliminated or can be made extremely small. Furthermore, the current amount of the OS transistor provided in the element layer 30 can be increased by increasing the transistor size, such as the channel width.

[0058] FIG. 2 illustrates an example of the function of the memory device 100 described in FIGS. 1A and 1B. FIG. 2 illustrates a memory device having memory cells CEL_1, CEL_2, CEL_3, and CEL_4 arranged in two rows and two columns. The switch circuit SEL described in FIGS. 1A and 1B has the function of switching signal paths between a set of memory cells CEL, for example, the memory cells CEL_1 and CEL_2 described in FIG. 1B. FIG. 2 illustrates a switch circuit SEL_1 that switches the connection state of two paths provided between the memory cells CEL_1 and CEL_2, and a switch circuit SEL_2 that switches the connection state of two paths provided between the memory cells CEL_3 and CEL_4.

[0059] The switch circuit SEL_1 provided between the memory cells CEL_1 and CEL_2 includes transistors that function as switches. In Fig. 2, switches SW51 and SW52 are illustrated as switches corresponding to the transistors M51 and M52 shown in Fig. 1B. Also in Fig. 2, switches S33 and S34 are illustrated as the switch circuit SEL_2 provided between the memory cells CEL_3 and CEL_4.

[0060] 1B, memory cell CEL_1 has transistors M11 to M13 and a capacitor C11. Memory cell CEL_2 has transistors M21 to M23 and a capacitor C21. Memory cell CEL_3 has transistors M31 to M33 and a capacitor C31. Memory cell CEL_4 has transistors M41 to M43 and a capacitor C41. In memory cells CEL_1 to CEL_4 shown in FIG. 2, the transistors and capacitors are connected in the same manner as in FIG. 1B.

[0061] 2 illustrates wirings RLA_1, RLB_1, RLA_2, and RLB_2 as wirings that function as word lines. Also, FIG. 2 illustrates wirings CLA_1, CLB_1, CLA_2, and CLB_2 as wirings that function as bit lines. As shown in FIG. 2, wirings RLA_1 and RLB_1 are connected to transistors included in memory cells CEL_1 and CEL_2. Also, as shown in FIG. 2, wirings RLA_2 and RLB_2 are connected to transistors included in memory cells CEL_3 and CEL_4. Also, as shown in FIG. 2, wirings CLA_1 and CLB_1 are connected to transistors included in memory cells CEL_1 and CEL_3. Also, as shown in FIG. 2, wirings CLA_2 and CLB_2 are connected to transistors included in memory cells CEL_2 and CEL_4.

[0062] 3A is a diagram illustrating a case where the switches (switches SW51 to SW54) of the switch circuits SEL_1 and SEL_2 are turned off and memory cells CEL_1 to CEL_4 are used as a 3Tr-type gain cell circuit configuration in the 2-row, 2-column memory device 100 shown in FIG. 2. In FIG. 3A, "OFF" is added to the reference symbols of the switches SW51 to SW54 to indicate that the switches SW51 to SW54 are off. The switching of each switch circuit is performed by the switching drive circuit 14, as described above.

[0063] With this configuration, the memory cells CEL_1 and CEL_2, whose circuit configurations are controlled by the switch circuit SEL_1, can be electrically separated by the switches SW51 and SW52 being turned off. Similarly, the memory cells CEL_3 and CEL_4, whose circuit configurations are controlled by the switch circuit SEL_2, can be electrically separated by the switches SW53 and SW54 being turned off.

[0064] In this case, the wiring RLA_1 shown in FIG. 2 functions as a write word line WWL_1 for writing data, as shown in FIG. 3A. The wiring RLB_1 shown in FIG. 2 functions as a read word line RWL_1 for reading data, as shown in FIG. 3A. The wiring CLA_1 shown in FIG. 2 functions as a write bit line WBL_1 for writing data, as shown in FIG. 3A. The wiring CLB_1 shown in FIG. 2 functions as a read bit line RBL_1 for reading data, as shown in FIG. 3A. The wiring RLA_2 shown in FIG. 2 functions as a write word line WWL_2 for writing data, as shown in FIG. 3A. The wiring RLB_2 shown in FIG. 2 functions as a read word line RWL_2 for reading data, as shown in FIG. 3A. The wiring CLA_2 shown in FIG. 2 functions as a write bit line WBL_2 for writing data, as shown in FIG. 3A. 2 functions as a read bit line RBL_2 for reading data, as shown in Fig. 3A. Signals on each line can be switched by a bit line side driver circuit 12 and a word line side driver circuit 13.

[0065] By switching the switch circuit SEL_1 shown in Figure 3A and switching the signals of each wiring, memory cell CEL_1, which has transistors M11 to M13 and capacitor C11, can be configured as a 3Tr gain cell DRAM circuit as shown in Figure 3B. Figure 3B illustrates memory cell CEL, which has transistors M1 to M3 and capacitor C1 and is connected to write word line WWL, read word line RWL, write bit line WBL, and read bit line RBL. Similarly, memory cell CEL_2, which has transistors M21 to M23 and capacitor C21, can be configured in a similar manner.

[0066] 3A, by switching the switch circuit SEL_2 and the signals of the respective wirings, the memory cell CEL_3 having the transistors M31 to M33 and the capacitor C31 can be similarly configured as a 3Tr gain cell DRAM circuit as shown in FIG. 3B. Similarly, the memory cell CEL_4 having the transistors M41 to M43 and the capacitor C41 can be configured as a similar circuit.

[0067] 3A and 3B , the memory device 100 of one embodiment of the present invention can be used as a DRAM with a 3Tr gain cell by switching the switch circuit SEL and switching signals of each wiring. The DRAM with a 3Tr gain cell can be used as a memory cell that has a higher memory density, requires less energy for rewriting, and has a higher rewriting endurance than an SRAM.

[0068] 4A is a diagram illustrating a case where the switches (switches SW51 to SW54) of the switch circuits SEL_1 and SEL_2 are turned on and memory cells CEL_1 to CEL_4 are used as a 4Tr SRAM circuit configuration in the 2-row, 2-column memory device 100 shown in FIG. 4A. In FIG. 4A, "ON" is added to the reference numerals of the switches SW51 to SW54 to indicate that the switches SW51 to SW54 are on. The switching of each switch circuit can be controlled by the switching drive circuit 14.

[0069] In addition, in the case of a 4Tr SRAM circuit configuration, the wirings RLB_1 and RLB_2 shown in FIG. 2 are set to the L level (in the figure, RLB_1 = L, RLB_2 = L), turning off the transistors M13, M23, M33, and M43. In the schematic diagram of the memory cells CEL_1 to CEL_4 in FIG. 4A, the circuit symbols of the transistors that are turned off are indicated by a cross. The wirings CLB_1 and CLB_2 shown in FIG. 2, which are connected to the transistors that are turned off, are also set to the L level (in the figure, CLB_1 = L, CLB_2 = L). Note that the wirings CLB_1 and CLB_2 are not limited to the L level and can also be set to the H level. The potentials of the wirings can be switched by the bit line side driver circuit 12 and the word line side driver circuit 13.

[0070] With this configuration, the memory cells CEL_1 and CEL_2, whose circuit configurations are controlled by the switch circuit SEL_1, can be connected by the switches SW51 and SW52 that are on. Similarly, the memory cells CEL_3 and CEL_4, whose circuit configurations are controlled by the switch circuit SEL_2, can be connected by the switches SW53 and SW54 that are on.

[0071] At this time, the wiring RLA_1 shown in Fig. 2 is made to function as a word line WL_1 as shown in Fig. 4A. The wiring CLA_1 shown in Fig. 2 is made to function as a bit line BL_1 as shown in Fig. 4A. The wiring RLA_2 shown in Fig. 2 is made to function as a word line WL_2 as shown in Fig. 4A. The wiring CLA_2 shown in Fig. 2 is made to function as an inverted bit line BLB_1 as shown in Fig. 4A. The signals of each wiring can be switched by the bit line side driver circuit 12 and the word line side driver circuit 13.

[0072] By switching the switch circuit SEL_1 shown in Fig. 4A and switching the potentials of the wirings, the memory cells CEL_1 and CEL_2, each including the transistors M11 to M13, the transistors M21 to M23, and the capacitors C11 and C21, can be configured as a 4Tr SRAM circuit as shown in Fig. 4B. Fig. 4B illustrates the memory cell CEL_12, which includes the transistors M11, M12, M21, and M22, and the capacitors C1 and C2, and is connected to the word line WL, the bit line BL, and the inverted bit line BLB.

[0073] Similarly, by switching the switch circuit SEL_2 shown in Figure 4A and switching the potential of the wiring, memory cells CEL_3 and CEL_4 having transistors M31 to M33, M41 to M43 and capacitors C31 and C41 can also be configured as memory cell CEL_34, which has a circuit configuration of a 4Tr type SRAM shown in Figure 4B.

[0074] 4A and 4B , the memory device 100 of one embodiment of the present invention can be used as a 4Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. The 4Tr SRAM can be used as a memory cell with a higher operating speed than a DRAM.

[0075] As described above, the memory device 100 of one embodiment of the present invention can be used as either a 3Tr gain cell DRAM or a 4Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. Therefore, the memory device 100 can be flexibly switched between a 3Tr gain cell DRAM, which has high memory density, low rewrite energy, and high rewrite endurance, and a 4Tr SRAM, which has excellent operating speed, after the memory device 100 is manufactured, depending on the application. Therefore, the memory device 100 can be provided with excellent convenience.

[0076] 2 illustrates and explains a configuration in which each memory cell has a capacitor for retaining charge, but it is also possible to omit the capacitor, as in the memory device 100A of FIG. 5A. In this case, the circuit configuration can be switched between the 3Tr gain cell of FIG. 5B and the 4Tr SRAM of FIG. 5C by turning on or off the switch circuits SEL_1 and SEL_2 and switching the signal or potential of each wiring. This configuration is preferable because it eliminates the need for a separate capacitor.

[0077] Furthermore, a back gate may be provided in each memory cell, and a potential may be applied from the back gate to control the electrical characteristics of the transistor included in the memory cell. With this configuration, the electrical characteristics of the transistor can be improved.

[0078] 6A to 6C are cross-sectional schematic diagrams illustrating the arrangement of the switch circuit SEL included in the element layer 10 and the memory cell CEL included in the element layer 30 illustrated in Fig. 1A etc. In Fig. 6A to 6C, in order to facilitate understanding of how the element layer 10 and the element layer 30 illustrated in Fig. 1A are stacked, the cross-sectional schematic diagrams are illustrated with the Z direction, as well as the X direction and the Y direction.

[0079] 6A is a diagram showing a configuration example in which an element layer 30 is provided on the element layer 10 shown in FIG. 1A. As described above, the element layer 10 is provided with memory cells CEL, and the element layer 30 is provided with switch circuits SEL connected to two memory cells CEL. The element layer 30 includes a transistor 51 having an oxide semiconductor in a semiconductor layer 52 having a channel formation region. The element layer 10 also includes a transistor 53 having silicon in a semiconductor layer 54 having a channel formation region.

[0080] The switch circuit SEL is configured to be disposed in a different element layer from the memory cells CEL. This configuration allows for a larger memory capacity, i.e., a larger number of memory cells CEL, compared to when the memory cells CEL and the switch circuit SEL are disposed on the same element layer. The switch circuit SEL can be fabricated in the back-end of the line (BEOL). Therefore, there is no area overhead for providing OS transistors. Furthermore, by using OS transistors as the switch circuits SEL connected to two memory cells CEL, the off-state current flowing when the switch circuits SEL are off can be significantly reduced. This configuration allows for a memory device with a smaller circuit area and lower power consumption.

[0081] 6B is a modified example of the cross-sectional schematic diagram shown in FIG. 6A. In FIG. 6B, the bit line side driver circuit 12, word line side driver circuit 13, switching driver circuit 14, and control circuit 15 shown in FIG. 1A, each having a transistor 53 that is a Si transistor, are provided in an element layer 10. In FIG. 6B, a memory cell CEL having a transistor 51 that is an OS transistor is provided in an element layer 20 above the element layer 10. In FIG. 6B, a switch circuit SEL having a transistor 51 that is an OS transistor is provided in an element layer 30 above the element layer 20.

[0082] By arranging the memory cells CEL and the drive circuits that drive the memory cells CEL and the switch circuits SEL on different element layers, the memory capacity, i.e., the number of memory cells CEL, can be increased compared to when the memory cells CEL and the drive circuits are arranged on the same element layer. Additionally, by arranging the memory cells CEL and the switch circuits SEL on different element layers, the memory capacity, i.e., the number of memory cells CEL, can be increased compared to when the memory cells CEL and the switch circuits SEL are arranged on the same element layer. The increase in circuit area associated with adding switch circuits SEL can be suppressed. Furthermore, the transistor structures or semiconductor materials of the semiconductor layers can be different between the element layers 20 and 30. This allows for a memory device that achieves reduced circuit area, lower power consumption, and higher speeds.

[0083] 6B, each transistor included in the memory cell CEL provided in the element layer 20 can be an OS transistor. A storage device including a memory cell having an OS transistor may be referred to as an "OS memory."

[0084] As described above, the off-state current of an OS transistor is extremely low. Therefore, charge corresponding to data written to the memory cell CEL can be held for a long time. That is, data once written to the memory cell CEL can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the memory device 100 of one embodiment of the present invention can be reduced.

[0085] The memory cells having OS transistors described with reference to FIGS. 3A and 3B can be nonvolatile oxide semiconductor random access memories (NOSRAMs). NOSRAMs rewrite data by charging and discharging a capacitor, so in principle, there is no limit to the number of rewrites and they require low energy. Therefore, NOSRAMs are capable of high-speed operation, low power consumption, and high rewrite endurance. Furthermore, NOSRAMs are suitable for long-term data retention because they can read written data nondestructively.

[0086] Fig. 6C is a modified example of the cross-sectional schematic diagram shown in Fig. 6B. In Fig. 6C, an arithmetic processing circuit 16 for performing arithmetic processing and having a transistor 53 that is a Si transistor is provided in the element layer 10. As in Fig. 6B, element layers 20 and 30 are provided above the element layer 10.

[0087] A storage device with a computing function can be realized by arranging the element layer 20 having the memory cell CEL on the element layer 10 provided with the arithmetic processing circuit 16. In the storage device with a computing function, the signal propagation distance between the memory cell CEL functioning as a main memory or cache memory and the arithmetic processing circuit 16 that performs arithmetic processing using the data stored in the memory cell CEL can be shortened. This allows for faster data writing and reading between a memory circuit such as a register in the arithmetic processing circuit 16 and the storage device functioning as a cache memory or main memory. Furthermore, the number of wirings between each circuit can be increased, thereby improving the bandwidth (also referred to as memory bandwidth) of the storage device. Therefore, in the storage device with a computing function, the memory cell CEL can be used for applications such as a high bandwidth memory (HBM).

[0088] 7A to 7C are schematic diagrams illustrating an example of the arrangement of switch circuits SEL connected to two memory cells CEL. In order to facilitate understanding of the arrangement of an element layer 30 having switch circuits SEL superimposed on the element layer 10 having memory cells CEL illustrated in FIG. 1A, the schematic diagrams are indicated by X, Y, and Z directions. The schematic diagrams of FIGS. 7A to 7C correspond to top views viewed from the Z direction. Furthermore, the memory cells CEL arranged in the rows and columns of the X and Y directions are indicated by column numbers such as the first column, the second column, and the first row, the second row.

[0089] 7A, a switch circuit SEL is provided that is connected to the memory cells CEL in the first and second columns of the first row. Similarly, a switch circuit SEL is provided that is connected to the memory cells CEL in the third and fourth columns. The same applies to the second row and beyond. In other words, the illustration shows a switch circuit SEL that is connected to adjacent memory cells CEL, such as a memory cell CEL in an odd-numbered column and a memory cell CEL in an even-numbered column.

[0090] 7A, by turning off the switches of the switch circuit SEL, eight memory cells CEL arranged in two rows and four columns can be used as a circuit configuration of a 3Tr gain cell DRAM. Also, by turning on the switches of the switch circuit SEL, a combination of four adjacent pairs of memory cells CEL can be used as a circuit configuration of a 4Tr SRAM.

[0091] 7B, a switch circuit SEL is provided that is connected to the memory cells CEL in the first row and the first and third columns. Similarly, a switch circuit SEL is provided that is connected to the memory cells CEL in the second and fourth columns. The same applies to the second row and beyond. In other words, the two memory cells CEL (first memory cell and second memory cell) connected to the switch circuit SEL are arranged with another memory cell (a third memory cell arranged between the first memory cell and the second memory cell) sandwiched between them.

[0092] In Fig. 7B, as in Fig. 7A, by turning off the switches of the switch circuit SEL, eight memory cells CEL arranged in two rows and four columns can be used as a circuit configuration of a 3Tr-type gain cell DRAM. Also, in Fig. 7B, as in Fig. 7A, by turning on the switches of the switch circuit SEL, a combination of four pairs of memory cells CEL arranged adjacently can be used as a circuit configuration of a 4Tr-type SRAM.

[0093] 7B, the circuit configuration of the 4Tr SRAM allows the four transistors to be arranged in a common centroid configuration. In other words, the pass transistors (transistors M11 and M21 in FIG. 4B) and the pull-down transistors (transistors M12 and M22 in FIG. 4B) of the 4Tr SRAM can be arranged at separate locations, reducing the variation (mismatch) in the characteristics of paired transistors. This allows for a highly reliable memory device.

[0094] 7C, a switch circuit SEL is provided that is connected to the memory cell CEL in the first column of the first row and the first column of the second row. Similarly, a switch circuit SEL is provided that is connected to the memory cells CEL in the second to fourth columns of the first and second rows. In other words, the switch circuit SEL is shown that is connected to adjacent memory cells CEL, such as a memory cell CEL in an odd-numbered row and a memory cell CEL in an even-numbered row.

[0095] Furthermore, as explained in FIG. 7B, the configuration of FIG. 7C can be combined with a configuration in which two memory cells CEL (first memory cell, second memory cell) connected to a switch circuit SEL are arranged with another memory cell (a third memory cell arranged between the first memory cell and the second memory cell) sandwiched between them, thereby reducing the variation (mismatch) in the characteristics of the paired transistors, resulting in a highly reliable memory device.

[0096] As described above, the memory device 100 of one embodiment of the present invention can be used as either a 3Tr gain cell DRAM or a 4Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. Therefore, the memory device 100 can be flexibly changed between a 3Tr gain cell DRAM, which has high memory density, low rewrite energy, and high rewrite endurance, and a 4Tr SRAM, which has excellent operating speed, after manufacturing the memory device 100, depending on the application. Therefore, the memory device 100 can be provided with excellent convenience.

[0097] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0098] Embodiment 2 In this embodiment, a semiconductor layer 52 included in a transistor 51 that can be used in a memory device or the like will be described.

[0099] Crystalline indium oxide is preferably used for the semiconductor layer 52 of the transistor 51 included in the element layers 20 and 30. By using indium oxide for the semiconductor layer, the transistor can have a large on-state current and high frequency characteristics.

[0100] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0101] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0102] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 8A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 8B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0103] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 8B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 8A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 8A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 8A.

[0104] 8A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0105] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0106] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0107] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0108] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 8A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0109] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0110] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 8B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 8A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0111] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0112] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0113] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0114] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0115] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0116] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0117] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0118] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0119] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0120] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0121] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0122] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0123]

[0124] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0125] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0126] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0127] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0128] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0129] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 8C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0130] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0131] Furthermore, as shown in FIG. 8C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0132] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0133] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0134]

[0135] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0136] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0137] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0138] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0139] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0140] The semiconductor material that can be used for the semiconductor layer 52 of the transistor 51 included in the element layers 20 and 30 is not limited to indium oxide. A metal oxide (oxide semiconductor) having semiconductor properties can be used as the semiconductor layer. The oxide semiconductor preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.

[0141] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0142] Alternatively, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0143] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0144] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0145] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0146] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0147] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a memory device with a large on-current can be provided.

[0148] According to one embodiment of the present invention, a novel transistor and a novel memory device can be provided. Alternatively, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory device with favorable frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with favorable reliability can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a memory device including a transistor with large on-state current can be provided. Alternatively, a memory device with little variation in transistor characteristics can be provided. Alternatively, a memory device with favorable electrical characteristics can be provided.

[0149] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0150] Embodiment 3 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0151] <Memory Hierarchy of Memory Devices> Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 9 shows various memory devices by memory hierarchy. The higher the memory device, the faster the access speed is required, while the lower the memory device, the larger the memory capacity and recording density are required. Figure 9 shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0152] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0153] SRAM is used, for example, as a cache. A cache has the function of storing a copy of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0154] DRAM is used, for example, as a main memory. The main memory has the function of storing programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm ２ is.

[0155] 3D NAND memory is used, for example, for storage. Storage has the function of storing data that requires long-term storage or various programs used in processing units. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm ２ is.

[0156] A storage device according to one embodiment of the present invention is advantageous in that it can switch between a memory cell circuit configuration that can be used as an SRAM with excellent operating speed and a 3Tr-type gain cell circuit configuration that can be used as a DRAM with excellent memory density. The storage device according to one embodiment of the present invention can switch between a memory hierarchy 901 in which a cache memory is located and a memory hierarchy 902 in which a main memory is located. Therefore, the circuit configuration can be switched depending on the memory capacity required for each memory hierarchy.

[0157] Next, electronic components, electronic devices, and large scale computers that can use the memory device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the memory device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0158] [Electronic Component] FIG. 10A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 709 is mounted. Electronic component 709 shown in FIG. 10A has memory device 100 inside mold 711. FIG. 10A omits some parts in order to show the interior of electronic component 709. Electronic component 709 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 100 via wires 714. Electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0159] The memory device 100 includes, as an example, an element layer 10 having an operation core, an element layer 20 having memory cells, and an element layer 30 having a switch circuit SEL. The element layer 20 having memory cells includes a plurality of memory cells (not shown). The stacked structure of the element layer 10 having the operation core, the element layer 20 having memory cells, and the element layer 30 having the switch circuit SEL can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By forming the element layer 10 having the operation core, the element layer 20 having memory cells, and the element layer 30 having the switch circuit SEL in a monolithic stacked structure, for example, a so-called on-chip memory structure can be achieved, in which memory is formed directly on a processor. The on-chip memory structure enables the operation of the interface between the processor and memory to be faster.

[0160] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0161] Furthermore, it is preferable that the transistors constituting the plurality of memory cells included in the element layer 20 and the plurality of switches included in the element layer 30 are OS transistors. This configuration allows the plurality of memory cells and switch circuits to be monolithically stacked on the element layer 10 having the processor core. By configuring the plurality of memory cell arrays as monolithic stacks, it is possible to improve either or both of the memory bandwidth and the memory access latency. The bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange.

[0162] The storage device 100 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0163] 10B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a memory device 735 and a plurality of memory devices 100 provided on the interposer 731.

[0164] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0165] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0166] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0167] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0168] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0169] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 100 and the memory device 735.

[0170] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 10B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0171] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0172] [Electronic Device] Fig. 11A is an external view showing an example of a portable electronic device. Fig. 11B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0173] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by the speaker 597, the camera 598, the microphone 599, etc. using the electronic component 709. The portable electronic device 595 can also be used in systems that perform voice guidance, image search, etc.

[0174] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0175] 12A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0176] 12B shows a stick-shaped electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0177] 12C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0178] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 13 shows an example of the configuration of the system 3000.

[0179] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be carried out via an internet line 3003.

[0180] The mainframe 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided on the racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in the mainframe 3002. The mainframe 3002 can then perform neural network calculations using data input from the electronic device 3001 via the Internet line 3003. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0181] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0182] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0183] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0184] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0185] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0186] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0187] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0188] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0189] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0190] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0191] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0192] In this specification and the like, terms such as "film" and "layer" may be interchangeable in some cases. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0193] In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows, or a device that has the function of selecting and switching a path for a current to flow.

[0194] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0195] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0196] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0197] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0198] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0199] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0200] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0201] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0202] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0203] C11: capacitor, C21: capacitor, CEL: memory cell, CEL_1: memory cell, CEL_2: memory cell, CLA: wiring, CLB: wiring, M11: transistor, M12: transistor, M13: transistor, M21: transistor, M22: transistor, M23: transistor, M51: transistor, M52: transistor, RLA: wiring, RLB: wiring, SEL: switch circuit, SEN: wiring, 10: element layer, 11: memory cell array, 12: bit line side drive circuit, 13: word line side drive circuit, 14: switching drive circuit, 15: control circuit, 16: arithmetic processing circuit, 20: element layer, 30: element layer, 51: transistor, 52: semiconductor layer, 53: transistor, 54: semiconductor layer, 100: memory device

Claims

a first memory cell, a second memory cell, and a switch circuit; the first memory cell includes a first transistor, a second transistor, and a third transistor; the second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor; the switch circuit includes a seventh transistor and an eighth transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; one of the source and the drain of a seventh transistor is electrically connected to one of the source and the drain of the first transistor and the gate of the second transistor; the other of the source or the drain of the seventh transistor is electrically connected to one of the source or the drain of the fifth transistor and one of the source or the drain of the sixth transistor; one of the source or the drain of an eighth transistor is electrically connected to one of the source or the drain of the second transistor and one of the source or the drain of the third transistor; the other of the source or the drain of the eighth transistor is electrically connected to the one of the source or the drain of the fourth transistor and the gate of the fifth transistor; storage device. 　 In claim 1, The first wiring to the fourth wiring are included, the other of the source and the drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the third transistor is electrically connected to the second wiring; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is electrically connected to the fourth wiring; storage device. 　 In claim 1, a fifth wiring and a sixth wiring, a gate of the first transistor and a gate of the fourth transistor are electrically connected to the fifth wiring; a gate of the third transistor and a gate of the sixth transistor are electrically connected to the sixth wiring; storage device. 　 In claim 1, A seventh wiring is provided, a gate of the seventh transistor and a gate of the eighth transistor are electrically connected to the seventh wiring; storage device. 　 In claim 1, the seventh transistor and the eighth transistor each have a semiconductor layer having a channel formation region; the semiconductor layer includes an oxide semiconductor; storage device. 　 In claim 5, the seventh transistor and the eighth transistor are each an n-channel transistor, the high-level potential that turns on the seventh transistor and the eighth transistor is a potential higher than a potential that turns on or off the first memory cell and the second memory cell; storage device. 　 In claim 1, the first memory cell and the second memory cell are memory cells arranged adjacent to each other; storage device. 　 In claim 1, a third memory cell; the third memory cell is disposed between the first memory cell and the second memory cell; storage device. 　 In claim 1, the first memory cell has a first capacitor; the second memory cell has a second capacitor; a first electrode of the first capacitor is electrically connected to one of the source or the drain of the first transistor, the gate of the second transistor, and one of the source or the drain of the seventh transistor; a first electrode of the second capacitor is electrically connected to one of the source and the drain of the fourth transistor, the gate of the fifth transistor, and the other of the source and the drain of the eighth transistor; storage device.

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