Semiconductor device and storage device

Abstract

Provided is a semiconductor device which allows for miniaturization and a high level of integration. This semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor is a p-channel transistor. The second transistor is an n-channel transistor positioned to overlap on top of the first transistor. The third transistor is an n-channel transistor positioned to overlap on top of the second transistor. The gate of the first transistor and one of either the source or the drain of the second transistor are electrically connected at a first node. One of either the source or the drain of the first transistor, the gate of the second transistor, and one of either the source or the drain of the third transistor are electrically connected at a second node. Each of the first transistor, the second transistor, and the third transistor is a vertical transistor.

Description

Semiconductor device and storage device

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a semiconductor device, a memory device, a transistor, and an electronic device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, development of semiconductor devices has progressed, and for example, large scale integrated circuits (LSIs) are used in semiconductor devices. For example, central processing units (CPUs), memories, etc. are used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits such as CPUs and memories are mounted on circuit boards, for example, printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has been attracting attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also been attracting attention as other materials.

[0007] It is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby providing a plurality of memory cells in a superimposed manner.

[0009] Furthermore, if a transistor can be made vertical, it is possible to increase the density of an integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulating layer.

[0010] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0011] M. Oota et. al., "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with a Gate Length of 72 nm," IEDM Tech. Dig., 2019, pp. 50-53. Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0012] SRAM (Static Random Access Memory) does not require refresh operations and is known as a memory device that consumes less power than DRAM (Dynamic Random Access Memory). Furthermore, because it can operate faster than DRAM, it is widely used, for example, in CPU caches. Meanwhile, while DRAM has an extremely simple configuration consisting of only one transistor and one capacitive element, SRAM requires at least six transistors. Therefore, the area occupied by each SRAM memory device is larger than that of DRAM.

[0013] One way to reduce the area occupied by an SRAM is to miniaturize the transistors that constitute the SRAM. However, when a transistor using silicon in a semiconductor layer (hereinafter also referred to as a Si transistor) is used, the further miniaturization proceeds, the more likely a defect called a short channel effect (SCE) becomes apparent. For example, the shorter the channel length of a Si transistor, the more likely its off-state current increases, so it is not preferable to apply such a transistor to a memory device.

[0014] An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or memory device with high operating speed. Another object of one embodiment of the present invention is to provide a novel semiconductor device, memory device, or transistor.

[0015] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0016] In a memory device having a large number of transistors, such as an SRAM, it is preferable to use transistors using an oxide semiconductor material (hereinafter also referred to as OS transistors) that are less susceptible to short-channel effects as at least some of the transistors. It is also preferable to use vertical transistors, which can be miniaturized more easily than planar transistors, as at least some of the transistors. Furthermore, it is preferable to stack the transistors constituting the memory device on each other.

[0017] As described above, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor, in which the first transistor is a p-channel transistor, the second transistor is an n-channel transistor overlapping the first transistor, and the third transistor is an n-channel transistor overlapping the second transistor, a gate of the first transistor and one of a source and a drain of the second transistor are electrically connected at a first node, and the source or the drain of the first transistor, the gate of the second transistor, and one of a source or a drain of the third transistor are electrically connected at a second node.

[0018] In the above, the second transistor and the third transistor are preferably vertical transistors.

[0019] In the above, the second transistor and the third transistor preferably contain indium and oxygen in a semiconductor layer having a channel formation region.

[0020] In the above, the first transistor preferably includes silicon in a semiconductor layer having a channel formation region.

[0021] Another embodiment of the present invention includes a first semiconductor device that is the above-described semiconductor device and a second semiconductor device that is different from the first semiconductor device. The second semiconductor device includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor is a p-channel transistor, the fifth transistor is an n-channel transistor overlapping the fourth transistor, and the sixth transistor is an n-channel transistor overlapping the fifth transistor. A gate of the fourth transistor and a source or drain of the fifth transistor are connected to each other. one of the gates of the first transistor and the second transistor is electrically connected at a third node; one of the source or drain of the fourth transistor, the gate of the fifth transistor, and one of the source or drain of the sixth transistor are electrically connected at the fourth node; the first transistor and the fourth transistor are located on the same layer; the second transistor and the fifth transistor are located on the same layer; the third transistor and the sixth transistor are located on the same layer; the second node and the third node are electrically connected; and the first node and the fourth node are electrically connected.

[0022] In the above, the fifth transistor and the sixth transistor are preferably vertical transistors.

[0023] In the above, the fifth transistor and the sixth transistor preferably contain indium and oxygen in a semiconductor layer having a channel formation region.

[0024] In the above, the fourth transistor preferably includes silicon in a semiconductor layer having a channel formation region.

[0025] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor, in which the first transistor is a p-channel transistor, the second transistor is an n-channel transistor overlapping the first transistor, and the third transistor is an n-channel transistor overlapping the second transistor. A gate of the first transistor and one of a source and a drain of the second transistor are electrically connected to a first node, and the one of the source and the drain of the first transistor, the gate of the second transistor, and one of the source and the drain of the third transistor are electrically connected to a second node. The first transistor, the second transistor, and the third transistor are each vertical transistors.

[0026] In the above, the second transistor and the third transistor preferably contain indium and oxygen in a semiconductor layer having a channel formation region.

[0027] In the above, the first transistor preferably includes silicon in a semiconductor layer having a channel formation region.

[0028] In the above, the first transistor preferably contains tin and oxygen in a semiconductor layer having a channel formation region.

[0029] Another embodiment of the present invention includes a first semiconductor device that is the above-described semiconductor device and a second semiconductor device that is different from the first semiconductor device. The second semiconductor device includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor is a p-channel transistor, the fifth transistor is an n-channel transistor overlapping the fourth transistor, and the sixth transistor is an n-channel transistor overlapping the fifth transistor. A gate of the fourth transistor and one of a source and a drain of the fifth transistor are electrically connected to a third node. a gate of the fifth transistor and one of the source and drain of the sixth transistor are electrically connected at a fourth node, the fourth transistor, the fifth transistor, and the sixth transistor are each vertical transistor, the first transistor and the fourth transistor are located on the same layer, the second transistor and the fifth transistor are located on the same layer, the third transistor and the sixth transistor are located on the same layer, the second node and the third node are electrically connected, and the first node and the fourth node are electrically connected.

[0030] In the above, the fifth transistor and the sixth transistor preferably contain indium and oxygen in a semiconductor layer having a channel formation region.

[0031] In the above, the fourth transistor preferably includes silicon in a semiconductor layer having a channel formation region.

[0032] In the above, the fourth transistor preferably contains tin and oxygen in a semiconductor layer having a channel formation region.

[0033] According to one embodiment of the present invention, a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a transistor with high on-state current can be provided. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with high operating speed can be provided. According to one embodiment of the present invention, a novel semiconductor device, memory device, or transistor can be provided.

[0034] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0035] FIGS. 1A and 1B are circuit diagrams illustrating a configuration example of a semiconductor device. FIG. 1C is a circuit diagram illustrating a configuration example of a memory cell. FIGS. 1D and 1E are block diagrams illustrating a configuration example of a semiconductor device. FIGS. 2A, 2B, and 2C are plan views illustrating a configuration example of a semiconductor device. FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 4 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 5A, 5B, and 5C are plan views illustrating a configuration example of a semiconductor device. FIG. 6 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 7 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views illustrating a configuration example of a transistor. FIGS. 9A and 9B are cross-sectional views illustrating a configuration example of a transistor. FIGS. 10A and 10B are cross-sectional views illustrating a configuration example of a transistor. FIGS. 11A and 11B are cross-sectional views illustrating a configuration example of a transistor. FIG. 12A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 12B and 12C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 13A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 13B and 13C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 14A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 15A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 15B and 15C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 16A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 17A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 18A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIG. 19A is a plan view illustrating an example of a method for manufacturing a transistor. FIGS. 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a transistor. 20A and 20B are diagrams illustrating the carrier concentration dependence of Hall mobility, Fig. 20C is a cross-sectional view illustrating an indium oxide film, and Fig. 21 is a block diagram illustrating a configuration example of a semiconductor device.FIG. 22 is a circuit diagram showing an example of the configuration of a memory cell. FIGS. 23A and 23B are perspective views showing an example of the configuration of a semiconductor device. FIG. 24 is a block diagram explaining a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. FIGS. 27A and 27B are views showing various memory devices by hierarchy. FIGS. 28A and 28B are views showing an example of an electronic component. FIGS. 29A and 29B are views showing an example of an electronic device. FIGS. 29C, 29D, and 29E are views showing an example of a mainframe computer. FIG. 30 is a view showing an example of space equipment. FIG. 31 is a view showing an example of a storage system applicable to a data center.

[0036] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0037] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0038] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in an actual manufacturing process, a layer or resist mask may be unintentionally thinned by a process such as etching, but this may not be reflected in the drawings for ease of understanding.

[0039] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0040] A transistor is a type of semiconductor element and can realize functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0041] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0042] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0043] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the defect state density of the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. Furthermore, for example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also referred to as "(semi-transitional)") may be formed.

[0044] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0045] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0046] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film", and the term "conductive film" can be changed to the term "conductive layer". Furthermore, for example, the term "insulating film" can be changed to the term "insulating layer", and the term "insulating layer" can be changed to the term "insulating film". Furthermore, for example, the term "semiconductor film" can be changed to the term "semiconductor layer", and the term "semiconductor layer" can be changed to the term "semiconductor film".

[0047] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0049] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0050] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0051] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0052] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. When a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0053] For example, in this specification, a transistor having a multi-gate structure with two or more gates can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0054] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is shown on a circuit diagram, this includes two or more resistors electrically connected in series. For example, when a single capacitor is shown on a circuit diagram, this includes two or more capacitors electrically connected in parallel. For example, when a single transistor is shown on a circuit diagram, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is shown on a circuit diagram, this includes two or more transistors, with the switch including two or more transistors electrically connected in series or parallel, and the gates of the respective transistors electrically connected to each other.

[0055] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. Also, a terminal, a wiring, etc. can be referred to as a node.

[0056] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0057] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0058] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0059] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0060] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0061] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0062] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0063] In this specification and the like, when it is stated that A is located on B, it means that at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0064] In this specification and the like, when it is stated that A covers B, it means that at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has a region that covers B.

[0065] In this specification and the like, when it is stated that A overlaps with B, it means that at least a part of A overlaps with B. Therefore, for example, it can be rephrased as saying that A has an overlapping region with B.

[0066] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0067] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxide nitrides.

[0068] Embodiment 1 A semiconductor device of one embodiment of the present invention includes a first transistor, a second transistor, and a third transistor, which are stacked in this order.

[0069] The first transistor is a p-channel transistor. The second transistor and the third transistor are each an n-channel transistor. A channel formation region of the first transistor (a p-channel transistor) can be formed using silicon or an oxide semiconductor. Furthermore, an oxide semiconductor can be used for the channel formation regions of the second transistor and the third transistor (an n-channel transistor).

[0070] Of the first to third transistors, at least the second and third transistors have a vertical transistor structure (a transistor structure in which the source and drain are located at different heights relative to the substrate surface and the drain current flows in the height direction (vertical direction)).

[0071] The gate of the first transistor and one of the source or drain of the second transistor are connected to a first node, and the gate of the second transistor, one of the source or drain of the first transistor, and one of the source or drain of the third transistor are connected to a second node.

[0072] A memory device can be configured by combining two semiconductor devices according to one embodiment of the present invention. For example, a first node of one semiconductor device is connected to a second node of the other semiconductor device, and the second node of one semiconductor device is connected to a first node of the other semiconductor device, whereby a circuit configuration similar to that of an SRAM can be realized.

[0073] The SRAM having the above-described structure can drastically reduce the area occupied by the SRAM compared to a case where the SRAM is configured with six transistors provided on the same plane. Furthermore, since at least some of the transistors constituting the SRAM are vertical transistors, the area occupied by the SRAM can be reduced compared to a case where all the transistors are planar transistors. Furthermore, since an oxide semiconductor can be used for the channel formation region of each transistor, even when miniaturization of the transistors is attempted, the short channel effect, which occurs when silicon is used, is less likely to become apparent. Therefore, a miniaturized and highly integrated memory device can be realized. Furthermore, a memory device with low power consumption can be realized. Furthermore, a memory device with high operating speed can be realized.

[0074] A semiconductor device according to one embodiment of the present invention will be described below with reference to drawings.

[0075] 1A is a circuit diagram illustrating a configuration of a semiconductor device 30A of one embodiment of the present invention. The semiconductor device 30A includes a transistor M1A, a transistor M2A, and a transistor M3A. The transistor M1A is a p-channel transistor, and the transistors M2A and M3A are n-channel transistors.

[0076] The gate of the transistor M1A is connected to one of the source and drain of the transistor M2A (the connection point (also referred to as a node) is shown as a node NNA in FIG. 1A). The source or drain of the transistor M1A is connected to one of the source and drain of the transistor M3A (the connection point is shown as a node NPA in FIG. 1A).

[0077] 1B is a circuit diagram of a semiconductor device 30B having the same configuration as the semiconductor device 30A shown in FIG. 1A. The description of the semiconductor device 30B can be applied by replacing the transistors M1A, M2A, M3A, the node NNA, and the node NPA in the description of the semiconductor device 30A with the transistors M1B, M2B, M3B, the node NNB, and the node NPB, respectively.

[0078] The semiconductor device 30A and the semiconductor device 30B can each constitute a part of a memory device. For example, by connecting the node NPA in the semiconductor device 30A to the node NNB in ​​the semiconductor device 30B and connecting the node NPB in the semiconductor device 30B to the node NNA in the semiconductor device 30A, the memory cell 30 shown in FIG. 1C can be formed. The memory cell 30 has a circuit configuration similar to that of an SRAM.

[0079] In the memory cell 30 shown in FIG. 1C , a first terminal (either the source or the drain) of a transistor M3A is connected to a wiring BL, and a second terminal (the other of the source or the drain) of the transistor M3A is connected to a first terminal (either the source or the drain) of a transistor M1A, a first terminal (either the source or the drain) of a transistor M2B, the gate of the transistor M1B, and the gate of the transistor M2A. The gate of the transistor M3A is connected to a wiring WL. A first terminal (either the source or the drain) of the transistor M3B is connected to a wiring BLB, and a second terminal (the other of the source or the drain) of the transistor M3B is connected to a first terminal (either the source or the drain) of the transistor M1B, the first terminal (either the source or the drain) of the transistor M2A, the gate of the transistor M1A, and the gate of the transistor M2B. The gate of the transistor M3B is connected to a wiring WL.

[0080] A second terminal (the other of the source and drain) of the transistor M1A is connected to the wiring VDD. A second terminal (the other of the source and drain) of the transistor M1B is connected to the wiring VDD. A second terminal (the other of the source and drain) of the transistor M2B is connected to the wiring VSS. A second terminal (the other of the source and drain) of the transistor M2A is connected to the wiring VSS.

[0081] The wirings BL and BLB function as bit lines, and the wiring WL functions as a word line.

[0082] The wiring VDD is a wiring that applies a high-level potential, and the wiring VSS is a wiring that applies a low-level potential.

[0083] When the semiconductor device of one embodiment of the present invention (semiconductor device 30A and semiconductor device 30B), the wiring BL, the wiring BLB, the wiring WL, the wiring VDD, and the wiring VSS are connected in the above-described manner, the memory cell 30 can function as an SRAM.

[0084] Note that in this specification and the like, an SRAM at least partly including an OS transistor may be referred to as an OS-SRAM.

[0085] An example of operation when the memory cell 30 is made to function as an SRAM will be described below.

[0086] Data is written by applying a high-level potential to the wiring WL. At this time, a potential corresponding to information to be recorded is applied to the wiring BL, and the potential is written to the gates of the transistors M1B and M2A.

[0087] When a potential corresponding to information to be recorded is applied to the wiring BLB, the potential is written to the gates of the transistors M1A and M2B. Below, a method for storing and reading data when a potential is written to the gates of the transistors M1B and M2A will be described.

[0088] The memory cell 30 includes an inverter loop formed by transistors M1A, M1B, M2A, and M2B. Therefore, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M3B. Since transistor M3B is on at this time, the potential applied to wiring BL, i.e., the inverted signal of the signal input to wiring BL, is output to wiring BLB. Then, a low-level potential is applied to wiring WL to turn off transistors M3A and M3B, thereby maintaining the potentials written to the gates of transistors M1B and M2A.

[0089] Data is read by precharging the wiring BL to a predetermined potential and then applying a high-level potential to the wiring WL. At this time, because the transistor M3A is in a conductive state, the potential written to the gates of the transistors M1B and M2A is output to the wiring BL. As a result, the potential of the wiring BL changes from the precharged potential to the potential written to the gates of the transistors M1B and M2A. This allows the potential held in the memory cell 30 to be read.

[0090] In the memory cell 30, the transistors M1A and M1B, which are p-channel transistors, can each be a Si transistor. The transistors M2B and M2A, which are n-channel transistors and form inverters with the transistors M1A and M1B, can each be an OS transistor. The transistors M3A and M3B, which function as data write and read transistors, can each be an OS transistor.

[0091] In particular, as described in Embodiment 2, by using a crystalline indium oxide film for the semiconductor layer of an OS transistor, a transistor with high field-effect mobility close to that of a Si transistor can be realized. Therefore, a memory cell 30 with high operating speed can be realized. On the other hand, by using an indium oxide film containing gallium, such as indium gallium zinc oxide, for the semiconductor layer of an OS transistor, a transistor with an off-state current much smaller than that of a Si transistor can be realized. Therefore, a memory cell 30 with excellent retention characteristics can be realized.

[0092] As described above, two semiconductor devices according to one embodiment of the present invention can be combined to function as an SRAM. Furthermore, as described above, three transistors constituting the semiconductor device can be stacked. For example, in the case of semiconductor device 30A, transistors M1A, M2A, and M3A can be stacked in this order. Furthermore, in the case of semiconductor device 30B, transistors M1B, M2B, and M3B can be stacked in this order. Therefore, forming a memory cell 30 by stacking two adjacent semiconductor devices, each with three stacked transistors, as shown in FIG. 1E can significantly reduce the area occupied by the memory cell 30 on the substrate surface, compared to forming a memory cell 30 by arranging the six transistors described above on the same plane as shown in FIG. 1D. In particular, since an SRAM has a larger number of elements than a DRAM or the like, applying the configuration shown in FIG. 1E is particularly effective.

[0093] 3 and other figures, vertical transistors can be used for at least some of the transistors constituting the memory cells 30. This allows the area occupied by the memory cells 30 within the substrate to be further reduced compared to when planar transistors are used, thereby realizing a highly integrated memory device.

[0094] As described above, OS transistors can be used for at least some of the transistors constituting the memory cell 30. Therefore, even when a transistor with an extremely short channel length such as a vertical transistor is used, it is less susceptible to adverse effects due to the short channel effect of a Si transistor (for example, a shift in threshold voltage toward normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to a gate electrode, and a current flows through the transistor) and an increase in off-state current), and favorable electrical characteristics can be maintained.

[0095] <Structural Example 1 of Semiconductor Device> Below, structural examples of a semiconductor device of one embodiment of the present invention and a memory cell formed using the semiconductor device will be described with reference to FIGS. 2A to 4 . FIG.

[0096] 2A to 2C are plan views (also referred to as top views) of a memory cell 30 formed using a semiconductor device (semiconductor device 30A and semiconductor device 30B) of one embodiment of the present invention. FIG. 2A is a plan view of a first layer of the memory cell 30 (a layer in which the transistors M1A and M1B in FIG. 1E are provided). FIG. 2B is a plan view of a second layer of the memory cell 30 (a layer in which the transistors M2A and M2B in FIG. 1E are provided). FIG. 2C is a plan view of a third layer of the memory cell 30 (a layer in which the transistors M3A and M3B in FIG. 1E are provided). Some elements, such as insulating layers, are omitted in FIGS. 2A to 2C for clarity. Some elements may also be omitted in the plan views shown below.

[0097] 3 is a cross-sectional view taken along the dashed dotted line A1-A2 shown in FIGS. 2A to 2C, and FIG. 4 is a cross-sectional view taken along the dashed dotted line A3-A4 shown in FIGS. 2A to 2C.

[0098] 2A , in a memory cell of one embodiment of the present invention, transistors 300A and 300B are provided in a first layer. As shown in FIG. 2B , transistors 200A and 200B are provided in a second layer. As shown in FIG. 2C , transistors 100A and 100B are provided in a third layer. Here, the transistors 300A, 300B, 200A, 200B, 100A, and 100B shown in FIGS. 2A to 2C correspond to the transistors M1A, M1B, M2A, M2B, M3A, and M3B shown in FIGS. 1A to 1E, respectively.

[0099] 3 and 4 show cross-sectional views of a portion including three of the six transistors constituting the memory cell (transistor 300A, transistor 200A, and transistor 100A). For cross-sectional views of a portion including the other three transistors (transistor 300B, transistor 200B, and transistor 100B), the same configuration as in FIGS. 3 and 4 can be applied by replacing transistor 300A, transistor 200A, and transistor 100A with transistor 300B, transistor 200B, and transistor 100B, respectively.

[0100] A memory cell of one embodiment of the present invention includes a semiconductor device including three transistors. As shown in the cross-sectional views of FIGS. 3 and 4 , the semiconductor device includes a transistor 300A, a transistor 200A, and a transistor 100A stacked in this order.

[0101] 4, the transistor 300A includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including a part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. As described above, the transistor 300A is a p-channel transistor. The substrate 311 may be, for example, a single-crystal silicon substrate.

[0102] Here, in the transistor 300A, a semiconductor region 313 (part of the substrate 311) where a channel is formed has a convex shape. An insulating layer 312 is provided on a region of the substrate 311 that does not overlap with the semiconductor region 313. As shown in FIG. 3 , a conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 and the top surface of the insulating layer 312 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 can be formed using a material having a work function that can adjust the threshold voltage of the transistor 300A (for example, shift it toward normally-off characteristics (characteristics in which no current flows between the source and drain of the transistor when no voltage is applied to the gate or when a ground potential is applied to the gate)). Such a transistor 300A is also referred to as a FIN-type transistor because of its shape using the convex portions of the semiconductor substrate. Note that an insulator that is in contact with the top of the convex portions and functions as a mask for forming the convex portions can also be provided. Moreover, although the case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, it is also possible to process an SOI (Silicon On Insulator) substrate to form a semiconductor film having a convex shape.

[0103] In this specification, a FIN transistor refers to a transistor having a structure in which a gate electrode is arranged to surround at least two or more sides (specifically, two, three, or four sides, etc.) of a channel formation region.

[0104] FIG. 3 corresponds to a cross-sectional view of the transistor 300A in the channel width direction, and FIG. 4 corresponds to a cross-sectional view of the transistor 300A in the channel length direction. As shown in FIG. 3 , the transistor 300A is a fin-type transistor. Therefore, in the cross-sectional view in the channel width direction, a conductive layer 316 functioning as a gate electrode is provided to surround a semiconductor region 313 in which a channel is formed. Therefore, the channel formation region can be electrically surrounded by an electric field from the gate electrode, and the effect of the gate electric field on carriers in the channel formation region can be strengthened. Therefore, the on-state current of the transistor 300A can be increased. Furthermore, by using the transistor 300A as a fin-type transistor, the resistance to the short-channel effect can be improved. In other words, even if the channel length of the transistor 300A is shortened, the transistor 300A can be made less susceptible to the short-channel effect.

[0105] Note that the transistor 300A shown in FIGS. 3 and 4 is an example, and the structure is not limited thereto. It is preferable to use an appropriate transistor depending on the circuit configuration or driving method.

[0106] A wiring layer including an interlayer insulating layer, wiring, plugs, etc. may be provided between the structures. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as both the wiring and the plug.

[0107] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order over the transistor 300A as an interlayer insulating layer. The height of the top surface of the insulating layer 320 is approximately the same as the height of the top surface of the conductive layer 316. The top surfaces of the insulating layer 320 and the conductive layer 316 are planarized, and the insulating layer 322 is provided in contact with the planar top surfaces of the insulating layer 320 and the conductive layer 316. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322. The conductive layer 328 has a region in contact with the top surface of the conductive layer 316. A conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 330 has a region in contact with the top surface of the conductive layer 328 and the top surface of the insulating layer 322. The upper surface of the conductive layer 330 is planarized and is approximately flush with the upper surface of the insulating layer 326. The conductive layers 328 and 330 function as plugs or wiring.

[0108] Among the interlayer insulating layers, the insulating layer 324 has a function of suppressing diffusion of impurities such as water and hydrogen from the transistor 300A toward the transistor 200A. For example, the semiconductor region 313 of the transistor 300A, which is a Si transistor, can contain hydrogen to terminate silicon dangling bonds at the interface with the gate insulating layer (insulating layer 315), thereby improving the electrical characteristics and reliability of the transistor 300A. Therefore, the transistor 300A preferably contains as much hydrogen as possible. On the other hand, the transistor 200A, which is located above the transistor 300A, is an OS transistor. Therefore, if hydrogen diffuses into the semiconductor layer (oxide semiconductor) of the transistor 200A, oxygen vacancies may be formed in the semiconductor layer. Therefore, the transistor 200A preferably contains as little hydrogen as possible. Therefore, it is preferable to provide an insulating layer, such as the insulating layer 324, between the transistor 300A (Si transistor) and the transistor 200A (OS transistor) to suppress diffusion of impurities such as water and hydrogen.

[0109] 3 and 4, conductive layer 328 and conductive layer 330 connected to conductive layer 316 function as part of a plug connecting the gate of transistor M1A shown in FIG. 1C to each of the first terminal of transistor M1B, the first terminal of transistor M2A, the gate of transistor M2B, and the second terminal of transistor M3B.

[0110] 4, the conductive layer 328 and the conductive layer 330 connected to the low-resistance region 314a function as part of a plug that connects the second terminal of the transistor M1A shown in FIG. 1C with the wiring VDD. The conductive layer 328 and the conductive layer 330 connected to the low-resistance region 314b function as part of a plug that connects the first terminal of the transistor M1A shown in FIG. 1C with the gate of the transistor M1B, the first terminal of the transistor M2B, the gate of the transistor M2A, and the second terminal of the transistor M3A.

[0111] The insulating layer functioning as an interlayer insulating layer can also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 can be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0112] A wiring layer can also be provided over the insulating layer 326 and the conductive layer 330. For example, in FIGS. 3 and 4 , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is embedded in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 has a region in contact with the top surface of the conductive layer 330. The conductive layer 356 functions as a plug or a wiring.

[0113] Of the wiring layers, the insulating layer 350, like the insulating layer 324, has the function of preventing impurities such as water and hydrogen from diffusing from the transistor 300A to the transistor 200A.

[0114] 3 and 4, conductive layer 356 connected to conductive layer 316 via conductive layer 328 and conductive layer 330 functions as part of a plug connecting the gate of transistor M1A and the first terminal of transistor M2A shown in FIG. 1C.

[0115] Also, in FIG. 4, the conductive layer 356 connected to the low resistance region 314b via the conductive layer 328 and the conductive layer 330 functions as part of a plug connecting the first terminal of the transistor M1A and the first terminal of the transistor M2B shown in FIG. 1C.

[0116] The transistor 200A overlaps with and is provided over the transistor 300A. The transistor 200A includes a conductive layer 111b functioning as one of a source electrode and a drain electrode, a conductive layer 112b functioning as the other of the source electrode and the drain electrode, a semiconductor layer 113b functioning as a semiconductor layer having a channel formation region, an insulating layer 105b functioning as a gate insulating layer, and a conductive layer 115b functioning as a gate electrode.

[0117] The conductive layer 111b is provided over the insulating layer 354 and the conductive layer 356. The conductive layer 111b has a region in contact with the top surface of the insulating layer 354 and the top surface of the conductive layer 356.

[0118] An insulating layer 103b is provided over the conductive layer 111b and the insulating layer 354. The top surface of the insulating layer 103b is planarized. Note that it is not necessary to planarize the top surface of the insulating layer 103b as long as it does not interfere with the formation of a structure over the insulating layer 103b. This allows the number of manufacturing steps of a semiconductor device and a memory cell to be reduced.

[0119] A conductive layer 112b is provided over the insulating layer 103b. The conductive layer 112b is provided in contact with the top surface of the insulating layer 103b so as to have a region overlapping with the conductive layer 111b.

[0120] An opening (first opening) reaching the conductive layer 111b is provided in the conductive layer 112b and the insulating layer 103b. The first opening is preferably provided in a region overlapping with the transistor 300A. This allows the transistor 200A to overlap with the transistor 300A, thereby reducing the area occupied by the semiconductor device.

[0121] 2B shows an example in which the shape of the first opening (corresponding to the dashed line shown in the region where the semiconductor layer 113b and the conductive layer 115b overlap) is circular in plan view. By making the top surface shape of the first opening circular, processing accuracy when forming the first opening can be improved, and the first opening can be formed with a minute size. Note that the top surface shape of the first opening may be, for example, an ellipse, a rectangle, or another polygon.

[0122] A semiconductor layer 113b is provided in contact with the top surface of the conductive layer 111b in the first opening, the side surface of the insulating layer 103b in the first opening, the side surface of the conductive layer 112b in the first opening, and the top surface of the conductive layer 112b.

[0123] The insulating layer 105b is provided in contact with the top surface and side surfaces of the semiconductor layer 113b, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 103b.

[0124] A conductive layer 115b is provided on the insulating layer 105b so as to fill the first opening. The conductive layer 115b has a region located inside the first opening and a region located outside the first opening.

[0125] The insulating layer 107b is provided in contact with part of the top surface and side surfaces of the conductive layer 115b and the top surface of the insulating layer 105b. The insulating layer 107b has a function of suppressing diffusion of impurities such as water and hydrogen from layers above the transistor 200A into the transistor 200A.

[0126] An insulating layer 131 is provided on the insulating layer 107b. The insulating layer 131 functions as the interlayer insulating layer described above.

[0127] The upper surface of the conductive layer 115b is flattened, and the upper surface of the conductive layer 115b and the upper surface of the insulating layer 131 are approximately flush with each other.

[0128] As shown in FIG. 4 , openings different from the first opening are provided in the insulating layer 103b and the insulating layer 105b. The openings are provided to reach another conductive layer 111b (conductive layer 111b_2, not shown, corresponding to one of the source electrode and drain electrode of the transistor 200B) provided in a region different from the conductive layer 111b of the transistor 200A. A conductive layer 258 is provided to fill the openings. The conductive layer 115b extends in the Y direction (A4 side) to have a region overlapping with the conductive layer 111b_2, and the top surface of the conductive layer 258 is in contact with the conductive layer 115. The conductive layer 258 functions as a plug that connects the gate of the transistor M2A shown in FIG. 1C to the first terminal of the transistor M2B.

[0129] The transistor 200A is a vertical transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside an opening formed in an interlayer insulating layer. In other words, the transistor 200A is a transistor in which the semiconductor layer is provided to surround the gate electrode via the gate insulating layer in a plan view. This allows the channel length direction of the transistor 200A to be aligned along the side surface of the insulating layer 103b in the first opening in a cross-sectional view. Therefore, the fabrication accuracy in the channel length direction is not affected by the performance of an exposure tool used to fabricate the transistor 200A, and the channel length can be made smaller than the resolution limit of the exposure tool. Therefore, an extremely fine transistor 200A can be fabricated.

[0130] As described above, the transistor 200A is an OS transistor. That is, an oxide semiconductor material can be used for the semiconductor layer 113b. Even though an OS transistor has a transistor structure with an extremely short channel length like a vertical transistor, adverse effects due to short-channel effects (e.g., a shift in threshold voltage toward normally-on characteristics, an increase in off-state current, etc.) that are common in Si transistors are less likely to become apparent. Therefore, the transistor 200A can be miniaturized and have favorable electrical characteristics.

[0131] The transistor 100A overlaps with and is provided over the transistor 200A. The transistor 100A includes a conductive layer 111a functioning as one of a source electrode and a drain electrode, a conductive layer 112a functioning as the other of the source electrode and the drain electrode, a semiconductor layer 113a functioning as a semiconductor layer having a channel formation region, an insulating layer 105a functioning as a gate insulating layer, and a conductive layer 115a functioning as a gate electrode.

[0132] The conductive layer 111a is provided over the conductive layer 115b. The conductive layer 111a has a region in contact with the top surface of the conductive layer 115b.

[0133] An insulating layer 103a is provided over the conductive layer 111a and the insulating layer 131. The top surface of the insulating layer 103a is planarized. Note that it is not necessary to planarize the top surface of the insulating layer 103a as long as it does not interfere with the formation of a structure on the insulating layer 103a. This allows the number of manufacturing steps of a semiconductor device and a memory cell to be reduced.

[0134] A conductive layer 112a is provided over the insulating layer 103a. The conductive layer 112a is provided in contact with the top surface of the insulating layer 103a so as to have a region overlapping with the conductive layer 111a.

[0135] 2C and 4, the conductive layer 112a is provided to extend in the Y direction (A3 side and A4 side). The conductive layer 112a also functions as a wiring BL connected to a first terminal of the wiring M3A shown in FIG. 1C. Note that the conductive layer 112a included in the transistor 100B shown in FIG. 2C also functions as a wiring BLB connected to a first terminal of the wiring M3B shown in FIG. 1C.

[0136] An opening (second opening) reaching the conductive layer 111a is provided in the conductive layer 112a and the insulating layer 103a. The second opening is preferably provided in a region overlapping with the transistor 200A. This allows the transistor 100A to overlap with the transistor 200A (and the transistor 300A), thereby reducing the area occupied by the semiconductor device.

[0137] 2C shows an example in which the shape of the second opening (corresponding to the dashed line showing the region where the semiconductor layer 113a and the conductive layer 115a overlap) is circular in a plan view. By making the top surface shape of the second opening circular, the processing accuracy when forming the second opening can be improved, and the second opening can be formed with a minute size. Note that the top surface shape of the second opening may also be, for example, an ellipse, a rectangle, or another polygon.

[0138] A semiconductor layer 113a is provided in contact with the top surface of the conductive layer 111a in the second opening, the side surface of the insulating layer 103a in the second opening, the side surface of the conductive layer 112a in the second opening, and the top surface of the conductive layer 112a.

[0139] The insulating layer 105a is provided in contact with the top surface and side surfaces of the semiconductor layer 113a, the top surface and side surfaces of the conductive layer 112a, and the top surface of the insulating layer 103a.

[0140] A conductive layer 115a is provided on the insulating layer 105a to fill the second opening. The conductive layer 115a has a region located within the second opening and a region located above the second opening. As shown in FIG. 2C , the conductive layer 115a is shared as a gate electrode of both the transistor 100A and the transistor 100B and is provided extending in the X direction (A1 side and A2 side). The conductive layer 115a also functions as a wiring WL connected to each of the gates of the transistors M3A and M3B shown in FIG. 1C .

[0141] The insulating layer 107a is provided in contact with part of the top surface and side surfaces of the conductive layer 115a and the top surface of the insulating layer 105a. The insulating layer 107a has a function of suppressing diffusion of impurities such as water and hydrogen from layers above the transistor 100A into the transistor 100A.

[0142] An insulating layer 139 is provided on the insulating layer 107a. The insulating layer 139 functions as the interlayer insulating layer described above.

[0143] The transistor 100A is also a vertical transistor, similar to the above-described transistor 200A, and therefore, an extremely miniaturized transistor 100A can be manufactured.

[0144] The transistor 100A is an OS transistor like the transistor 200A. That is, an oxide semiconductor material can be used for the semiconductor layer 113a. Therefore, the transistor 100A can be miniaturized and have favorable electrical characteristics.

[0145] As shown in FIG. 3 , a conductive layer 211 is provided on the insulating layer 131 in a region adjacent to the conductive layer 111a of the transistor 100A. The conductive layer 211 is provided to have a region overlapping with the conductive layer 112b of the transistor 200A. A conductive layer 257 is embedded in the insulating layers 105b, 107b, and 131 in a region sandwiched between the conductive layer 211 and the conductive layer 112b. As shown in FIG. 2B , the conductive layer 211 is provided extending in the Y direction (toward A3 and A4). The conductive layer 211 functions as a wiring VSS connecting the second terminal of the transistor M2A and the second terminal of the transistor M2B shown in FIG. 1C . The conductive layer 257 functions as a plug connecting the second terminal of the transistor M2A shown in FIG. 1C to the wiring VSS.

[0146] 3, another conductive layer 111a (conductive layer 111a_2, which corresponds to one of the source electrode and drain electrode of the transistor 100B, although not shown) is provided over the insulating layer 131 in a region opposite the conductive layer 111a of the transistor 100A across the conductive layer 211. The conductive layer 111a_2 is provided to have a region overlapping with the conductive layer 111b. A conductive layer 256 is embedded in the insulating layer 103b, the insulating layer 105b, the insulating layer 107b, and the insulating layer 131 in a region sandwiched between the conductive layer 111a_2 and the conductive layer 111b. The conductive layer 256 functions as a plug that connects the first terminal of the transistor M2A and the second terminal of the transistor M3B shown in FIG. 1C.

[0147] 3 and 4 show a structure in which the transistor 100A is stacked over the transistor 200A, but this is not limiting. The transistors 200A and 100A are both vertical transistors and OS transistors. Therefore, for example, the transistor 100A can be provided adjacent to the transistor 200A. In this case, the transistors 200A and 100A can be simultaneously fabricated in the same process. As a result, the semiconductor device has a two-layer stacked structure in which the transistor 300A is provided in the first layer and the transistors 200A and 100A are provided in the second layer. Therefore, the number of steps required for fabricating the semiconductor device can be significantly reduced compared to the structure shown in FIGS. 3 and 4 (a three-layer stacked structure). For example, if the occupied areas of the transistors 200A and 100A are sufficiently small (e.g., half or less) relative to the occupied area of ​​the transistor 300A, the two-layer stacked structure is preferable because it does not increase the occupied area of ​​the entire semiconductor device compared to a three-layer stacked structure.

[0148] <Structure Example 2 of Semiconductor Device> Below, with reference to FIGS. 5A to 7 , a semiconductor device of one embodiment of the present invention, which is different from the one described in <Structure Example 1 of Semiconductor Device> with reference to FIGS. 2A to 4 , and a structure example of a memory cell formed using the semiconductor device will be described.

[0149] 5A to 5C are plan views of a memory cell 30 different from that shown in FIGS. 2A to 2C. Of these, FIG. 5A is a plan view of the first layer of the memory cell 30, FIG. 5B is a plan view of the second layer of the memory cell 30, and FIG. 5C is a plan view of the third layer of the memory cell 30. In FIGS. 5A to 5C, some elements such as insulating layers are omitted for clarity.

[0150] 6 is a cross-sectional view taken along dashed dotted line A1-A2 shown in FIGS. 5A to 5C, and FIG. 7 is a cross-sectional view taken along dashed dotted line A3-A4 shown in FIGS. 5A to 5C.

[0151] Note that the configurations of the second layer (the layer in which the transistors 200A and 200B are formed) and the third layer (the layer in which the transistors 100A and 100B are formed) in the memory cells shown in FIGS. 5A to 7 are the same as the configurations of the second layer and the third layer in the memory cells shown in FIGS. 2A to 4, respectively. Therefore, the following description will mainly focus on the configuration of the first layer of the memory cells shown in FIGS. 5A to 7. For the configurations of the other layers (the second and third layers), the description of the memory cells shown in FIGS. 2A to 4 can be referred to.

[0152] The memory cells shown in FIGS. 5A to 7 differ from the memory cells shown in FIGS. 2A to 4 in the configuration of the first layer (the layer in which the transistors 300A and 300B are formed). Specifically, the memory cells shown in FIGS. 2A to 4 differ in that the transistor 300A is a FIN transistor, whereas the memory cells shown in FIGS. 5A to 7 differ in that the transistor 300A is a vertical transistor, similar to the transistors 200A and 100A. The vertical transistor structure of the transistor 300A allows for smaller transistor size than a FIN transistor structure. Therefore, the overall area occupied by the semiconductor device 30A, including the transistors 200A and 100A stacked on the transistor 300A, can be reduced, and the overall area occupied by the memory cell 30, including the semiconductor device 30B, can be reduced.

[0153] The transistor 300A is provided over a substrate 101. The transistor 300A includes a conductive layer 111c functioning as one of a source electrode and a drain electrode, a conductive layer 112c functioning as the other of the source electrode and the drain electrode, a semiconductor layer 113c functioning as a semiconductor layer having a channel formation region, an insulating layer 105c functioning as a gate insulating layer, and a conductive layer 115c functioning as a gate electrode.

[0154] The conductive layer 111c, which functions as one of the source electrode and the drain electrode of the transistor 300A, is provided to extend in the X direction (toward the A1 side and the A2 side) as shown in Figures 5A and 6. The conductive layer 111c also functions as part of a plug that connects the second terminal of the transistor M1A shown in Figure 1C to the wiring VDD.

[0155] An insulating layer 103c is provided over the conductive layer 111c and the substrate 101. The top surface of the insulating layer 103c is planarized. Note that it is not necessary to planarize the top surface of the insulating layer 103c as long as it does not interfere with the formation of a structure on the insulating layer 103c. This allows the number of manufacturing steps for a semiconductor device and a memory cell to be reduced.

[0156] A conductive layer 112c is provided over the insulating layer 103c. The conductive layer 112c is provided in contact with the top surface of the insulating layer 103c so as to have a region overlapping with the conductive layer 111c.

[0157] An opening (third opening) reaching the conductive layer 111c is provided in the conductive layer 112c and the insulating layer 103c. Figure 5C shows an example in which the shape of the third opening is circular in a plan view. By making the top surface shape of the third opening circular, processing accuracy when forming the third opening can be improved, and the third opening can be formed with a fine size. Note that the top surface shape of the third opening may be, for example, an ellipse or a polygon such as a rectangle.

[0158] A semiconductor layer 113c is provided in contact with the top surface of the conductive layer 111c in the third opening, the side surface of the insulating layer 103c in the third opening, the side surface of the conductive layer 112c in the third opening, and the top surface of the conductive layer 112c.

[0159] Here, since the transistor 300A is a p-channel transistor, a p-type semiconductor material can be used for the semiconductor layer 113c. For example, a p-type silicon material can be used for the semiconductor layer 113c, as in the transistor 300A described in <Configuration Example 1 of Semiconductor Device>.

[0160] As mentioned above, a Si transistor has a problem in that the shorter the channel length, the more likely the short-channel effect becomes apparent. However, since the channel length direction of a vertical transistor corresponds to a direction perpendicular or approximately perpendicular to the substrate surface, even if the channel length is increased to suppress the occurrence of the short-channel effect, the occupied area does not increase as in a planar transistor. Therefore, even if a silicon material is used for the semiconductor layer 113c, a vertical transistor 300A with good electrical characteristics can be realized without increasing the occupied area. The channel length of the vertical transistor will be described in detail with reference to FIG. 8A.

[0161] For example, a p-type oxide semiconductor material can be used for the semiconductor layer 113c. Examples of p-type oxide semiconductor materials include tin oxide (also referred to as SnO). This allows the transistor 300A to be an OS transistor, which can have a smaller off-state current than a Si transistor. Furthermore, since the transistors 100A, 200A, and 300A can all be OS transistors, the memory cell 30 can have better retention characteristics than a Si transistor.

[0162] An insulating layer 105c is provided in contact with the top surface and side surfaces of the semiconductor layer 113c, the top surface and side surfaces of the conductive layer 112c, and the top surface of the insulating layer 103c.

[0163] A conductive layer 115c is provided on the insulating layer 105c so as to fill the third opening. The conductive layer 115c has a region located inside the third opening and a region located outside the third opening.

[0164] The insulating layer 107c is provided in contact with part of the top surface and side surfaces of the conductive layer 115c and the top surface of the insulating layer 105c. The insulating layer 107c has a function of suppressing diffusion of impurities such as water and hydrogen from layers above the transistor 300A into the transistor 300A.

[0165] An insulating layer 231 is provided over the insulating layer 107c. The insulating layer 231 functions as the interlayer insulating layer described above.

[0166] The upper surface of the conductive layer 115c is flattened, and the upper surface of the conductive layer 115c and the upper surface of the insulating layer 231 are approximately flush with each other.

[0167] An insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order between the transistor 300A and the transistor 200A. A conductive layer 356 is embedded in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 has a region in contact with the top surface of the conductive layer 115c.

[0168] 6, another conductive layer 112c (conductive layer 112c_2) is provided over the insulating layer 103c in addition to the conductive layer 112c of the transistor 300A. The conductive layer 112c_2 corresponds to the other of the source electrode and the drain electrode of the transistor 300B. The conductive layer 115c extends in the X direction (A2 side) and is in contact with the top surface of the conductive layer 112c_2. The conductive layer 115c also functions as a plug that connects the gate of the transistor M1A shown in FIG. 1C to the first terminal of the transistor M1B.

[0169] 7 , the conductive layer 112c extends in the Y direction (A4 side) to have a region overlapping with the conductive layer 111b (corresponding to the conductive layer 111b_2 shown in FIG. 7 ) that functions as one of the source and drain electrodes of the transistor 200B. In this region (where the conductive layer 112c overlaps with the conductive layer 111b_2), openings reaching the conductive layer 112c are provided in the insulating layers 105c, 107c, 231, 350, 352, and 354, and a conductive layer 259 is provided to fill the openings. The top surface of the conductive layer 259 is in contact with the conductive layer 111b_2. The conductive layer 259 functions as a plug that connects the first terminal of the transistor M1A shown in FIG. 1C to the first terminal of the transistor M2B.

[0170] Regarding the semiconductor device and the memory cell illustrated in FIGS. 5A to 7 , the contents described in <Configuration Example 1 of Semiconductor Device> regarding the semiconductor device and the memory cell illustrated in FIGS. 2A to 4 can be referred to for other details.

[0171] In this specification and the like, the insulating layers 103a, 103b, and 103c may be collectively referred to as the insulating layer 103. The insulating layers 105a, 105b, and 105c may be collectively referred to as the insulating layer 105. The insulating layers 107a, 107b, and 107c may be collectively referred to as the insulating layer 107. The conductive layers 111a, 111b, and 111c may be collectively referred to as the conductive layer 111. The conductive layers 112a, 112b, and 112c may be collectively referred to as the conductive layer 112. The semiconductor layers 113a, 113b, and 113c may be collectively referred to as the semiconductor layer 113. The conductive layers 115a, 115b, and 115c may be collectively referred to as the conductive layer 115.

[0172] As described above, in a semiconductor device according to one embodiment of the present invention, a p-channel transistor 300A, an n-channel transistor 200A, and an n-channel transistor 100A are stacked in this order. In addition, a semiconductor device according to one embodiment of the present invention includes a p-channel transistor 300B, an n-channel transistor 200B, and an n-channel transistor 100B, stacked in this order. Among these, the transistors 200A and 100A, and the transistors 200B and 100B each have a vertical transistor structure in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided in an opening formed in an interlayer insulating layer, and one of a source electrode and a drain electrode is provided under the opening and the other of the source electrode and drain electrode is provided on the interlayer insulating layer. This reduces the area occupied by the semiconductor device in a plan view. Furthermore, the transistors 200A and 100A, and the transistors 200B and 100B can each be an OS transistor. Therefore, even a minute vertical transistor with an extremely short channel length is less susceptible to the short channel effect that is a problem with Si transistors, and a minute semiconductor device with good electrical characteristics can be realized.

[0173] Furthermore, by combining two semiconductor devices according to one embodiment of the present invention, a configuration similar to that of a memory cell (specifically, an SRAM) can be realized. Therefore, even in the case of a memory cell having a configuration with a large number of elements like an SRAM, a very high-performance memory device that is miniaturized, highly integrated, and has excellent operating speed and retention characteristics can be realized.

[0174] <Structure Example 1 of Transistor> A structure, a material, and the like of a vertical transistor included in a semiconductor device of one embodiment of the present invention will be described in detail below.

[0175] 8A is an enlarged view of the transistor 100A and its vicinity shown in FIGS. 3 and 4, and FIGS. 5 and 6. FIG. 8B shows a cross-sectional view of the transistor shown in FIG. 8A taken along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112. The structures shown in FIGS. 8A and 8B can be applied not only to the transistor 100A but also to the transistor 200A. In FIG. 8A and other drawings, an opening corresponding to the first opening in the transistor 200A or the second opening in the transistor 100A is shown as an opening 121.

[0176] As shown in FIG. 8A, the semiconductor layer 113 has a region 113i, and regions 113na and 113nb that are provided so as to sandwich the region 113i.

[0177] The region 113na is a region in contact with the conductive layer 111 of the semiconductor layer 113. At least a portion of the region 113na functions as one of the source region and the drain region of the transistor. The region 113nb is a region in contact with the conductive layer 112 of the semiconductor layer 113. At least a portion of the region 113nb functions as the other of the source region and the drain region of the transistor. As shown in FIG. 8B , the conductive layer 112 is in contact with the entire periphery of the semiconductor layer 113. Therefore, the other of the source region and the drain region of the transistor can be formed on the entire periphery of a portion of the semiconductor layer 113 formed in the same layer as the conductive layer 112.

[0178] The region 113i is a region between the region 113na and the region 113nb in the semiconductor layer 113. At least a part of the region 113i functions as a channel formation region of the transistor. That is, the channel formation region of the transistor is located in a region of the semiconductor layer 113 between the conductive layer 111 and the conductive layer 112. It can also be said that the channel formation region of the transistor is located in a region of the semiconductor layer 113 that is in contact with the insulating layer 103 or in a region in the vicinity of the region.

[0179] The channel length of a transistor is the distance between the source region and the drain region. In other words, it can be said that the channel length of a transistor is determined by the thickness of the insulating layer 103 on the conductive layer 111. In Figure 8A, the channel length L of the transistor is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the edge of the region where the semiconductor layer 113 and the conductive layer 112 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 103 on the opening 121 side in a cross-sectional view.

[0180] Note that the sum of the length of the side surface of insulating layer 103 on the opening 121 side in the above-described cross-sectional view and the thickness of conductive layer 112 (i.e., the depth of opening 121) may be defined as channel length L. For example, in a configuration in which semiconductor layer 113 is in contact only with the top surface of conductive layer 112 and is not in contact with the side surface of conductive layer 112 within opening 121, it is preferable to define the depth of opening 121 as channel length L.

[0181] In a planar transistor, the channel length is set by the exposure limit of photolithography. However, in a transistor included in a semiconductor device of one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 103. Therefore, the channel length of the transistor can be made into an extremely fine structure (e.g., 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 5 nm to 10 nm) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor, thereby improving frequency characteristics. Therefore, the read speed and write speed of the memory cell can be improved, and thus a memory device with high operating speed can be realized.

[0182] 8A and 8B , when a vertical transistor having a shorter channel length than a planar transistor is used in the semiconductor device of one embodiment of the present invention, a metal oxide is preferably used for the semiconductor layer 113.

[0183] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 121. This allows the area occupied by the transistor to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for a high integration of the semiconductor device, and therefore allows for a larger storage capacity per unit area of ​​a storage device configured using the semiconductor device.

[0184] As shown in FIG. 8B , in the XY plane including the channel formation region of the semiconductor layer 113, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged concentrically. Therefore, the side surface of the central conductive layer 115 faces the side surface of the semiconductor layer 113 via the insulating layer 105. In other words, in a planar view, the entire inner periphery of the semiconductor layer 113 forms the channel formation region. In this case, the channel width of the transistor can be determined by the length of the inner periphery of the semiconductor layer 113. Alternatively, for example, the channel width of the transistor may be determined by the outer periphery of the semiconductor layer 113 (which may also be referred to as the periphery of the opening 121). In this case, the channel width of the transistor can be determined by the maximum width of the opening 121 (or the diameter, if the opening 121 is circular in planar view). In FIGS. 8A and 8B , the maximum width D of the opening 121 is indicated by a double-headed, dashed arrow. In FIG. 8B , the channel width W of the transistor is indicated by a double-headed, dashed arrow. By increasing the size of the maximum width D of the opening 121, the ratio of the channel width to the channel length (channel width / channel length) increases, and therefore the on-current can be increased.

[0185] The maximum width D of the opening 121 is preferably, for example, 5 nm to 100 nm, 10 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm. When the opening 121 is circular in plan view, the maximum width D of the opening 121 corresponds to the diameter of the opening 121, and the channel width W can be calculated as "D × π".

[0186] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor is preferably smaller than at least the channel width W of the transistor. The channel length L of the transistor of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0187] Note that by providing the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 concentrically, the distance between the conductive layer 115 and the semiconductor layer 113 becomes approximately uniform. Therefore, a gate electric field can be applied to the semiconductor layer 113 approximately uniformly.

[0188] 8B and other figures, the top surface shape of the opening 121 is shown as a circle, but is not limited to this. For example, the top surface shape of the opening 121 may be formed to be an ellipse or a polygon such as a rectangle. Even in this case, the distance between the conductive layer 115 and the semiconductor layer 113 remains approximately uniform, and therefore, a gate electric field can be applied to the semiconductor layer 113 approximately uniformly.

[0189] The sidewall of the opening 121 is preferably perpendicular to the top surface of the conductive layer 111, for example. This structure allows miniaturization or high integration of the semiconductor device. The sidewall of the opening 121 may be tapered. This can improve coverage of a film (e.g., the semiconductor layer 113) that forms the sidewall of the opening 121 as a surface to be formed.

[0190] Components of a transistor (here, a vertical transistor) included in a semiconductor device will be described below.

[0191] [Transistor Components] A metal oxide described in the section [Metal Oxide] below can be used as a single layer or a stacked layer for the semiconductor layer 113. Furthermore, a material such as silicon described in the section [Other Semiconductor Materials] below can be used as a single layer or a stacked layer for the semiconductor layer 113.

[0192] When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:3:4 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:2 [atomic ratio] or a composition thereabout, or In:M:Zn = 4:2:3 [atomic ratio] or a composition thereabout can be used as the semiconductor layer 113. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0193] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0194] For example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the metal oxide used in the semiconductor layer 113. Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0195] The metal oxide can be preferably formed by atomic layer deposition (ALD).

[0196] Alternatively, the metal oxide can be formed by sputtering or chemical vapor deposition (CVD).

[0197] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0198] The metal oxide used for the semiconductor layer 113 preferably has crystallinity. Examples of crystalline oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductor, single-crystalline oxide semiconductor, and the like. For the semiconductor layer 113, it is preferable to use a CAAC-OS or an nc-OS, and it is particularly preferable to use a CAAC-OS.

[0199] The CAAC-OS preferably has multiple layered crystalline regions with c-axes oriented in the normal direction to the surface where it is formed. For example, the semiconductor layer 113 preferably has layered crystals that are substantially parallel to the sidewall of the opening 121, particularly to the side surface of the insulating layer 103. With this structure, the layered crystals of the semiconductor layer 113 are formed substantially parallel to the channel length direction of the transistor, which enables the on-state current of the transistor to be increased.

[0200] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0201] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that the CAAC-OS has a crystal structure in which a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0202] Furthermore, by using a crystalline metal oxide such as CAAC-OS for the semiconductor layer 113, it is possible to suppress extraction of oxygen from the semiconductor layer 113 by the source electrode or the drain electrode. Thus, even when heat treatment is performed, oxygen can be suppressed from being extracted from the semiconductor layer 113, and the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0203] The crystallinity of the semiconductor layer 113 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0204] The thickness of the semiconductor layer 113 is preferably, for example, 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 12 nm, or 5 nm to 10 nm.

[0205] 3, 4, 6, 7, and 8A, the semiconductor layer 113 is shown as a single layer, but the present invention is not limited to this. The semiconductor layer 113 may also have a stacked structure of multiple metal oxide layers with different chemical compositions. For example, a structure in which multiple types of metal oxides selected from the above metal oxides are appropriately stacked may also be used.

[0206] The insulating layer 105 functioning as a gate insulating layer can be formed using a single layer or a stacked layer of any of the insulators described in the section [Insulators] below. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 105. Silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0207] Furthermore, a material with a high relative dielectric constant, so-called high-k material, which will be described later in the section [Insulator], may be used as the insulating layer 105. For example, hafnium oxide or aluminum oxide may be used.

[0208] The thickness of the insulating layer 105 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. The insulating layer 105 preferably has a region with the above thickness in at least a part thereof.

[0209] The concentration of impurities such as water and hydrogen in the insulating layer 105 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the semiconductor layer 113.

[0210] 3, 4, 6, 7, and 8A, the insulating layer 105 is shown as a single layer, but the present invention is not limited to this. The insulating layer 105 may also have a laminated structure.

[0211] The conductive layer 115 functioning as a gate electrode can be a single layer or a stacked layer of any of the conductors described in the section [Conductor] below. For example, the conductive layer 115 can be made of a conductive material with high conductivity, such as tungsten, aluminum, or copper.

[0212] Furthermore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that has a function of suppressing oxygen diffusion, or the like, for the conductive layer 115. Examples of such a conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride), a conductive material containing oxygen (for example, ruthenium oxide), and the like. This can suppress a decrease in the conductivity of the conductive layer 115. Furthermore, for the conductive layer 115, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide can also be used.

[0213] 3, 4, 6, 7, and 8A, the conductive layer 115 is shown as a single layer, but the present invention is not limited to this. The conductive layer 115 may have a stacked structure.

[0214] The conductive layer 111 can be formed using a single layer or a stacked layer of any of the conductors described in the section [Conductor] below. It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 111. For example, titanium nitride, tantalum nitride, or the like can be used. Alternatively, for example, a structure in which tantalum nitride is stacked on titanium nitride can be used. In this case, titanium nitride is in contact with the insulating layer 354, the insulating layer 131, the insulating layer 103, or the like, and tantalum nitride is in contact with the semiconductor layer 113. With such a structure, excessive oxidation of the conductive layer 111 by the semiconductor layer 113 can be suppressed. Furthermore, when an oxide insulator is used for the insulating layer 354, the insulating layer 131, the insulating layer 103, or the like, the insulating layer can suppress excessive oxidation of the conductive layer 111. Alternatively, for example, a structure in which tungsten is stacked on titanium nitride can be used for the conductive layer 111.

[0215] Furthermore, since the conductive layer 111 has a region in contact with the semiconductor layer 113, it is preferable to use a conductive material containing oxygen described in the section of [Conductor] described later. By using a conductive material containing oxygen for the conductive layer 111, the conductive layer 111 can maintain conductivity even when it absorbs oxygen. For example, indium tin oxide (also referred to as ITO), indium tin oxide doped with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used as a single layer or a stacked layer.

[0216] 3, 4, 6, 7, and 8A show a configuration in which the upper surface of the conductive layer 111 is flat, but the present invention is not limited to this. For example, a configuration in which a recess overlapping the opening 121 is formed on the upper surface of the conductive layer 111 may be used. By forming at least a portion of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 so as to fill the recess, it is possible to easily apply the gate electric field of the conductive layer 115 up to the vicinity of the conductive layer 111 of the semiconductor layer 113.

[0217] A single layer or a stack of conductors described in the section [Conductor] below can be used as the conductive layer 112. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, can be used as the conductive layer 112.

[0218] Like the conductive layer 111 and the conductive layer 115, the conductive layer 112 is preferably formed using a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, tantalum nitride, or the like can be used. With such a structure, excessive oxidation of the conductive layer 112 by the semiconductor layer 113 can be suppressed. Similarly to the conductive layer 115, the conductive layer 112 can be formed using a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

[0219] Alternatively, for example, a structure in which tungsten is stacked over titanium nitride may be used. By stacking tungsten over titanium nitride in this manner, the conductivity of the conductive layer 112 can be improved.

[0220] Furthermore, when the conductive layer 112 has a structure in which a first conductive layer and a second conductive layer are stacked in this order, for example, the first conductive layer can be formed using a conductive material with high conductivity, and the second conductive layer can be formed using a conductive material containing oxygen. By using a conductive material containing oxygen for the second conductive layer whose area in contact with the insulating layer 105 is larger than that of the first conductive layer, it is possible to prevent oxygen in the insulating layer 105 from diffusing into the first conductive layer of the conductive layer 112. For example, tungsten can be used for the first conductive layer of the conductive layer 112, and indium tin oxide to which silicon is added can be used for the second conductive layer of the conductive layer 112.

[0221] When the semiconductor layer 113 and the conductive layer 111 come into contact with each other, a metal compound or oxygen vacancy is formed in the semiconductor layer 113, and the resistance of a region 113na of the semiconductor layer 113 is reduced. When the semiconductor layer 113 comes into contact with the conductive layer 111, the resistance of the semiconductor layer 113 and the conductive layer 111 is reduced, thereby reducing the contact resistance between the semiconductor layer 113 and the conductive layer 111. Similarly, when the semiconductor layer 113 and the conductive layer 112 come into contact with each other, the resistance of a region 113nb of the semiconductor layer 113 is reduced. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

[0222] The insulating layer 103, insulating layer 131, etc., which function as an interlayer insulating layer, preferably have a low dielectric constant. By using a material with a low dielectric constant as an interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 103, insulating layer 131, etc., an insulator containing a material with a low dielectric constant, as described in the section [Insulator] below, can be used in a single layer or a stacked layer. In particular, silicon oxide and silicon oxynitride are preferred because of their thermal stability.

[0223] The concentrations of impurities such as water and hydrogen in the insulating layer 103, the insulating layer 131, and the like are preferably reduced, thereby preventing impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0224] The insulating layer 103 disposed in the vicinity of the channel formation region of the semiconductor layer 113 preferably contains oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). By performing heat treatment on the insulating layer 103 containing excess oxygen, oxygen is supplied from the insulating layer 103 to the channel formation region of the semiconductor layer 113, and oxygen vacancies in the semiconductor layer 113 and defects in which hydrogen has entered the oxygen vacancies (hereinafter, referred to as V Ｏ This can stabilize the electrical characteristics of the transistor and improve its reliability.

[0225] Alternatively, an insulator having a function of capturing or fixing hydrogen, which will be described later in the section [Insulator], can be used as the insulating layer 103. With such a structure, hydrogen can be captured or fixed in the semiconductor layer 113, thereby reducing the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, or the like can be used as the insulating layer 103.

[0226] 3, 4, 6, 7, and 8A, the insulating layer 103 is shown as a single layer, but the present invention is not limited to this. The insulating layer 103 may also have a laminated structure.

[0227] For the insulating layer 107, an insulator having a barrier property against hydrogen, as described in the section [Insulator] below, can be preferably used. This can suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 113 through the insulating layer 105. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 107.

[0228] Furthermore, it is preferable to use an insulator having a function of capturing hydrogen or fixing hydrogen, as described in the section [Insulator] below, for the insulating layer 107. With such a structure, diffusion of hydrogen from above the insulating layer 107 to the semiconductor layer 113 can be suppressed, and further hydrogen in the semiconductor layer 113 can be captured or fixed to reduce the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used for the insulating layer 107. Alternatively, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used for the insulating layer 107.

[0229] 3, 4, 6, 7, and 8A illustrate the structure in which the insulating layer 107 is formed on the top surface of the transistor, but the present invention is not limited to this. For example, the insulating layer 107 or an insulating layer having a similar function or material to the insulating layer 107 may be formed on the side and bottom surfaces of the transistor, and the transistor may be surrounded by the insulating layer. Alternatively, the insulating layer 107 may be formed on the top, side, and bottom surfaces of the transistor 200A and the transistor 100A, and the transistor 200A and the transistor 100A may be surrounded by the insulating layer 107. This structure can prevent impurities (e.g., water, hydrogen, etc.) from entering the transistor 200A and the transistor 100A.

[0230] 8A and 8B , a transistor configuration example different from the transistor configuration example 1 will be described. Note that the following mainly describes differences from the transistor configuration example 1.

[0231] Fig. 9A is a cross-sectional view of a transistor having a different structure from that shown in Fig. 8A , and Fig. 9B is a cross-sectional view of the transistor shown in Fig. 9A cut along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112.

[0232] The transistors illustrated in FIGS. 9A and 9B are different from the transistors illustrated in FIGS. 8A and 8B in that they include a second gate electrode (also referred to as a back gate electrode) and a second gate insulating layer (also referred to as a back gate insulating layer) and in that the insulating layer 103 has a two-layer structure.

[0233] 9A and 9B, the insulating layer 103 has a two-layer structure of an insulating layer 103_1 and an insulating layer 103_2 over the insulating layer 103_1. The insulating layer 103_1 and the insulating layer 103_2 can each be made of the material that can be used for the insulating layer 103.

[0234] A conductive layer 117 is provided over the insulating layer 103_1, and an insulating layer 103_2 is provided over the conductive layer 117. The conductive layer 117 is provided to have a region overlapping with the conductive layer 111. A conductive layer 112 is provided over the insulating layer 103_2.

[0235] An opening 121 reaching the conductive layer 111 is provided in the insulating layer 103_1, the conductive layer 117, the insulating layer 103_2, and the conductive layer 112. An insulating layer 116 is provided in the opening 121 so as to be in contact with a part of the upper surface of the conductive layer 111, the side surfaces of the insulating layer 103_1, the side surfaces of the conductive layer 117, and the side surfaces of the insulating layer 103_2. The upper end of the insulating layer 116 has a curved shape.

[0236] A semiconductor layer 113 is provided in contact with another part of the upper surface of the conductive layer 111 in the opening 121 , the upper surface of the insulating layer 116 in the opening 121 , the curved portion of the insulating layer 116 , and the upper surface of the conductive layer 112 .

[0237] 9A and 9B , the conductive layer 117 functions as a back gate electrode. In addition, a region of the insulating layer 116 that is sandwiched between the semiconductor layer 113 and the conductive layer 117 in the opening 121 functions as a back gate insulating layer.

[0238] That is, the transistor shown in FIGS. 9A and 9B has a structure in which two gate electrodes (conductive layers 115 and 117) sandwich the semiconductor layer 113 in the opening 121. This allows an electric field to be applied to the semiconductor layer 113 (mainly the channel formation region) from the two gate electrodes, thereby making it possible to strengthen the effect of the gate electric field on carriers in the channel formation region compared to the transistor shown in FIGS. 8A and 8B. Therefore, the on-state current can be increased compared to the transistor shown in FIGS. 8A and 8B. The off-state current can also be reduced. Furthermore, the threshold voltage can be shifted further toward the normally-off characteristic side. A potential can be applied to each of the two gate electrodes independently. Alternatively, the two gate electrodes can be connected to each other so that the same potential is applied to them. Alternatively, the back gate electrode and the source electrode can be connected to each other.

[0239] For example, the transistors shown in FIGS. 9A and 9B can be applied to the transistors M3A and M3B in the memory cell 30 shown in FIG. 1C . As described above, the transistors M3A and M3B function as transistors for writing and reading data to and from the memory cell 30, respectively. Therefore, by applying the transistors shown in FIGS. 9A and 9B to the transistors M3A and M3B, respectively, a memory cell 30 with high operating speed can be realized. Furthermore, when data is retained in the memory cell 30, the transistors M3A and M3B are both turned off, thereby realizing a memory cell 30 with excellent retention characteristics. Note that the transistors shown in FIGS. 9A and 9B can also be applied to the transistors M2A and M2B in the memory cell 30, respectively.

[0240] 9A and 9B , the channel length is the length along the interface between the insulating layer 116 and the semiconductor layer 113 between the contact point between the source electrode and the semiconductor layer 113 and the contact point between the drain electrode and the semiconductor layer 113. In Fig. 9A , the channel length L is indicated by a dashed double-headed arrow.

[0241] The insulating layer 116 can be formed using the same material as that used for the insulating layer 105. Alternatively, the insulating layer 116 can be formed using the same material as that used for the insulating layer 103.

[0242] The conductive layer 117 can be formed using the above-described material that can be used for the conductive layer 111. Alternatively, the conductive layer 112 can be formed using the above-described material that can be used for the conductive layer 115.

[0243] Regarding the transistors illustrated in FIGS. 9A and 9B , the description of <Structure example 1 of transistor> illustrated in FIGS. 8A and 8B can be referred to for details other than those described above.

[0244] 9A and 9B , a transistor configuration example different from the transistor configuration example 2 will be described. Note that the following mainly describes differences from the transistor configuration example 2.

[0245] Fig. 10A is a cross-sectional view of a transistor having a different structure from that shown in Fig. 9A , and Fig. 10B is a cross-sectional view of the transistor shown in Fig. 10A cut along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112.

[0246] 10A and 10B is a transistor having a structure in which the conductive layer 115 functioning as a first gate electrode (also referred to as a top gate electrode) is not included, among the two gate electrodes (conductive layer 115 and conductive layer 117) included in the transistor shown in FIG. 9A and 9B. That is, the transistor shown in FIG. 10A and 10B is a transistor having only one gate electrode (conductive layer 117).

[0247] 8A and 8B also have a structure including only one gate electrode (conductive layer 115), but the transistor has a structure in which the gate electrode (conductive layer 115) is surrounded by a semiconductor layer (semiconductor layer 113) having a channel formation region in a plan view (also referred to as a channel all around (CAA) structure). In contrast, the transistor shown in FIGS. 10A and 10B has a structure in which the gate electrode (conductive layer 117) is surrounded by a semiconductor layer 113 in a plan view (also referred to as a gate all around (GAA) structure), which is different from the transistor shown in FIGS. 8A and 8B.

[0248] As described above, a vertical transistor that can be applied to the semiconductor device of one embodiment of the present invention can have either a CAA structure or a GAA structure. For example, when a conductive layer that functions as a gate electrode is routed above a conductive layer (conductive layer 112) that functions as the other of the source and drain electrodes and used as a wiring, the CAA structure is preferably used. On the other hand, when the conductive layer 112 is routed above a conductive layer that functions as a gate electrode and used as a wiring, the GAA structure is preferably used. For example, although the cross-sectional views of the memory cell 30 in FIGS. 3 and 4 show an example in which both the transistor 200A and the transistor 100A have the CAA structure, the transistor 200A may have the CAA structure and the transistor 100A may have the GAA structure. Furthermore, for example, the cross-sectional views of the memory cell 30 shown in Figures 6 and 7 show examples in which the transistors 300A, 200A, and 100A all have the CAA structure, but it is also possible to apply the CAA structure to one or both of the transistors 300A and 200A, and the GAA structure to the transistor 100A.

[0249] 10A , the insulating layer 107 has a shape that conforms to the opening 121, and a recess is formed on the insulating layer 107 that overlaps with the opening 121. The recess can also be filled with an insulating material that functions as a planarization layer, such as an organic insulating material. This can improve the coverage of the film formed on the transistor shown in FIGS. 10A and 10B . Note that if the coverage is not impaired, it may be unnecessary to fill the recess with the insulating material. This can reduce the number of manufacturing steps for a semiconductor device.

[0250] 10A and 10B, the description of <Structure example 2 of transistor> in FIGS. 9A and 9B can be referred to for other details.

[0251] 8A and 8B , a transistor configuration example different from the transistor configuration example 1 will be described. Note that the following mainly describes differences from the transistor configuration example 1.

[0252] Fig. 11A is a cross-sectional view of a transistor having a different structure from that shown in Fig. 8A , and Fig. 11B is a cross-sectional view of the transistor shown in Fig. 11A cut along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112.

[0253] 11A and 11B , the insulating layer 103 and the conductive layer 112 do not have openings 121, and the insulating layer 103 and the conductive layer 112 are provided in an island shape to have a region overlapping with an end portion of the conductive layer 111. A semiconductor layer 113 is provided to cover the side surfaces of the island-shaped insulating layer 103 and the conductive layer 112. The semiconductor layer 113 has regions in contact with the side surfaces, the top surface of the conductive layer 111, and the top surface of the conductive layer 112. The insulating layer 105 has regions in contact with the top surface and side surfaces of the semiconductor layer 113, the top surface of the conductive layer 111, and the top surface of the conductive layer 112. The conductive layer 115 is provided over the insulating layer 105 to have a region overlapping with the semiconductor layer 113.

[0254] 11A and 11B , the distance between the source electrode and the drain electrode along the interface between the semiconductor layer 113 and the insulating layer 103 is the channel length L (see FIG. 11A ). Also, in a plan view, the distance along the interface between the semiconductor layer 113 and the conductive layer 112 is the channel width W (see FIG. 11B ). Note that, in a plan view, the distance along the interface between the semiconductor layer 113 and the conductive layer 111 can also be defined as the channel width W. Also, in a plan view, the intermediate value between the distance along the interface between the semiconductor layer 113 and the conductive layer 112 and the distance along the interface between the semiconductor layer 113 and the conductive layer 111 can also be defined as the channel width W.

[0255] 11A has a shape obtained by dividing the transistor shown in Fig. 8A symmetrically with respect to the conductive layer 115 in a cross-sectional view in the YZ plane. Therefore, the transistors shown in Fig. 11A and 11B may occupy a smaller area in a plan view than the transistors shown in Fig. 8A and 8B.

[0256] Regarding the transistors illustrated in FIGS. 11A and 11B , the description of <Structure example 1 of transistor> illustrated in FIGS. 8A and 8B can be referred to for details other than those described above.

[0257] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for a transistor, an insulating layer, and the like that form a semiconductor device of one embodiment of the present invention will be described below.

[0258] [Substrate] For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used for each of the substrate 311 and the substrate 101. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements.

[0259] [Insulator] Examples of insulators that can be used for each of the insulating layer 103, the insulating layer 105, the insulating layer 107, the insulating layer 116, the insulating layer 131, the insulating layer 139, the insulating layer 231, the insulating layer 312, the insulating layer 315, the insulating layer 320, the insulating layer 322, the insulating layer 324, the insulating layer 326, the insulating layer 350, the insulating layer 352, and the insulating layer 354 include insulating oxides (including metal oxides), nitrides, oxynitrides (including metal oxynitrides), and nitride oxides (including metal nitride oxides).

[0260] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the insulator that functions as the gate insulating layer enables lower voltage during transistor operation while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer insulating layer can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select a material depending on the function of the insulator. Note that a material with a low dielectric constant also has high dielectric strength.

[0261] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0262] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other examples of inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may also contain nitrogen. Silicon oxide may also be formed using an organic silane such as tetraethoxysilane (TEOS).

[0263] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0264] Furthermore, an insulator such as a gate insulating layer that is in contact with a semiconductor layer or that is provided near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, by providing an insulator having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0265] Examples of insulators having a barrier property against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0266] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0267] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0268] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0269] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, the term "barrier property against oxygen" refers to the property of making it difficult for at least one of oxygen atoms, oxygen molecules, etc. to diffuse.

[0270] [Conductor] The conductor that can be used for each of the conductive layers 111, 112, 115, 117, 211, 256, 257, 258, 259, 316, 328, 330, and 356 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or the like, or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy can also be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide can be used.

[0271] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, conductive materials containing oxygen are sometimes referred to as oxide conductors.

[0272] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0273] Furthermore, a plurality of conductors formed from the above materials can be stacked. For example, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure can also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure can also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0274] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0275] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, can also be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon can also be used. Furthermore, indium gallium zinc oxide containing nitrogen can also be used. Using such a material may enable the capture of hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may enable the capture of hydrogen introduced from an external insulator or the like.

[0276] [Metal Oxide] Metal oxides that can be used for the semiconductor layer 113 may have lattice defects. Examples of lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that cause the generation of lattice defects include a deviation in the ratio of the number of atoms of constituent elements (an excess or deficiency of constituent atoms), impurities, etc.

[0277] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0278] In a transistor using a metal oxide for a semiconductor layer, oxygen vacancies (V Ｏ ) and impurities, the electrical characteristics may be easily changed and the reliability may be deteriorated. ＯH may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the metal oxide in the channel formation region, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the metal oxide in the channel formation region. In other words, it is preferable that the carrier concentration in the metal oxide in the channel formation region is reduced and the metal oxide is made i-type (intrinsic) or substantially i-type.

[0279] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide, the method for forming the metal oxide film, and the like.

[0280] The structure of metal oxides can be divided into single crystal structures and other structures (non-single crystal structures). Examples of non-single crystal structures include CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures. The a-like structure has a structure between the nc structure and the amorphous structure.

[0281] Furthermore, metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Furthermore, metal oxides having an a-like structure have a higher hydrogen concentration than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0282] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for the semiconductor layer of a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0283] Furthermore, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0284] Here, it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, the crystal preferably has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having such crystals include single-crystal oxide semiconductors and CAAC-OS.

[0285] Furthermore, the c-axis of the crystal is preferably oriented in the normal direction to the surface on which the metal oxide is formed or the film surface, so that the layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface, i.e., the layers extend in the channel length direction.

[0286] For example, the above-described three-layered crystal structure may have the following structure: The first layer has an octahedral oxygen atomic coordination structure with the metal contained in the first layer at the center; The second layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the second layer at the center; The third layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the third layer at the center.

[0287] The crystal structure of the above crystal is, for example, YbFe ２ O ４ Type structure, Yb２ Fe ３ O ７ There are various types of structures, including modified structures.

[0288] Furthermore, each of the first to third layers is preferably composed of one metal element or multiple metal elements having the same valence and oxygen. The valence of the one or more metal elements constituting the first layer is preferably the same as the valence of the one or more metal elements constituting the second layer. The first layer and the second layer may contain the same metal element. The valence of the one or more metal elements constituting the first layer is preferably different from the valence of the one or more metal elements constituting the third layer.

[0289] The above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases and the electrical characteristics of the transistor can be improved.

[0290] Examples of metal oxides of one embodiment of the present invention include indium oxide (also referred to as indium oxide), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0291] Examples of metal oxides of one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable materials include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0292] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0293] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0294] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0295] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0296] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0297] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0298] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0299] Note that a metal oxide (indium oxide) other than In—Ga—Zn oxide that can be used for the semiconductor device of one embodiment of the present invention will be described in Embodiment 2.

[0300] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms one layer at a time. The ALD method makes it easy to form the metal oxide having the layered crystal structure.

[0301] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0302] The ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS.

[0303] When the ALD method is used as a method for forming a metal oxide film, by adopting a condition in which the substrate temperature is high during film formation and / or by performing an impurity removal process, the amount of carbon and chlorine contained in the film can be reduced compared to when the ALD method is used without applying these conditions.

[0304] For example, it is preferable to perform an impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of a metal oxide film. Furthermore, it is preferable to perform an impurity removal treatment in an oxygen-containing atmosphere after the formation of a metal oxide film. By performing an impurity removal treatment either during or after the formation of a metal oxide film, impurities in the film can be removed. This can prevent impurities (e.g., hydrogen, carbon, nitrogen) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. Furthermore, the crystallinity of the metal oxide can be improved.

[0305] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0306] When performing plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher and 500° C. or lower, 100° C. or higher and 500° C. or lower, 200° C. or higher and 500° C. or lower, 300° C. or higher and 500° C. or lower, 400° C. or higher and 500° C. or lower, or 400° C. or higher and 450° C. or lower. The heat treatment temperature is preferably set to 100° C. or higher and 450° C. or lower, 200° C. or higher and 450° C. or lower, 300° C. or higher and 450° C. or lower, or 400° C. or higher and 450° C. or lower.

[0307] The temperature for the impurity removal treatment is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or a semiconductor device, because the amount of impurities in the metal oxide can be reduced without reducing productivity. For example, the productivity of the semiconductor device can be increased by setting the maximum temperature in the manufacturing process of the semiconductor device of one embodiment of the present invention to 500° C. or lower, preferably 450° C. or lower.

[0308] Here, the microwave treatment refers to, for example, a treatment using a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0309] In the microwave treatment, it is preferable to use, for example, a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0310] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0311] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0312] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less.

[0313] The heat treatment is also carried out in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment can also be carried out in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less).

[0314] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２ The metal atoms and oxygen atoms can be released as O. Furthermore, simultaneously with the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be performed, improving crystallinity. Therefore, it is possible to form a metal oxide with a highly crystalline layered crystal structure, particularly a metal oxide with the above-mentioned CAAC structure.

[0315] Unlike film formation methods in which particles emitted from a target are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as a sputtering method or a CVD method, which have a faster film formation rate. For example, a method can be used in which a first metal oxide film is formed by sputtering, and a second metal oxide film is formed on the first metal oxide by ALD. For example, if the first metal oxide has crystalline portions, the second metal oxide may grow crystals using the crystalline portions as nuclei.

[0316] The ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, for example, the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0317] [Transistor Having Metal Oxide] Next, a case where a metal oxide (oxide semiconductor) is used in a transistor will be described.

[0318] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. Furthermore, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.

[0319] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ or less, more preferably 1 × 10 １５ cm −３ or less, more preferably 1 × 10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that when the carrier concentration of an oxide semiconductor film is reduced, it is preferable to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0320] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0321] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0322] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0323] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2.0 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current of the transistor can be reduced.

[0324] Furthermore, in Si transistors, a short-channel effect occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the reasons for the short-channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short-channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short-channel effect or has an extremely small short-channel effect.

[0325] The short-channel effect is a deterioration in electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0326] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0327] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0328] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ accumulation type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0329] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 10 nm, 5 nm to 7 nm, or 5 nm to 6 nm. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be preferably used as a transistor with a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0330] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0331] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0332] [Impurities in Metal Oxide] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0333] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0334] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen in a semiconductor layer tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm３ The following applies.

[0335] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Less than.

[0336] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0337] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0338] [Other Semiconductor Materials] The semiconductor layer 113 can be rephrased as a semiconductor layer including a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0339] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0340] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0341] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0342] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0343] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a semiconductor device with a large on-current can be provided.

[0344] <Example of Method for Manufacturing Transistor> An example of a method for manufacturing a transistor included in a semiconductor device of one embodiment of the present invention (here, the vertical transistor illustrated in FIGS. 8A and 8B) will be described below with reference to the drawings.

[0345] (A) in each figure shows a plan view. Also, (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure. Also, (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure. Note that in the plan view of (A) of each figure, some elements have been omitted for clarity.

[0346] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0347] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0348] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0349] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method does not use plasma, and therefore is a film formation method capable of forming films without causing plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, and therefore produces films with fewer defects.

[0350] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0351] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0352] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0353] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0354] First, a substrate (not shown) or a structure such as a transistor (not shown) is prepared, and then a conductive layer 111 is formed on the substrate or the structure ( FIGS. 12A to 12C ). For example, the conductive layer 111 can be formed by forming a conductive film that will become the conductive layer 111 and processing the conductive film. For the conductive film that will become the conductive layer 111, any of the above-described conductive materials that can be used for the conductive layer 111 can be used as appropriate.

[0355] The conductive film to be the conductive layer 111 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a stacked film in which tungsten and titanium nitride are deposited in this order can be formed as the conductive film to be the conductive layer 111 by a CVD method. After the conductive film to be the conductive layer 111 is formed, for example, a pattern is formed by lithography, and the conductive film is processed by a dry etching method, a wet etching method, or the like based on the pattern, thereby forming the conductive layer 111. Here, processing the conductive film by a dry etching method is preferable because fine processing can be performed.

[0356] In the lithography method, first, the resist is exposed to light through a mask, and then the exposed area is removed or left behind using a developer to form a resist mask, thereby forming a pattern.

[0357] For example, a resist mask is formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Also, a liquid immersion technique may be used, in which exposure is performed by filling a liquid (e.g., water) between the substrate and the projection lens. Also, an electron beam or an ion beam may be used instead of the light described above. Note that, when an electron beam or an ion beam is used, a mask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0358] Next, etching is performed through the resist mask, whereby the conductive layer, the semiconductor layer, the insulating layer, or the like can be processed into a desired shape.

[0359] When dry etching is performed as the etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, NF ３ Gas, CHF ３ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, CCl ４ Gas, or BBr ３ A gas such as a silicon dioxide gas can be used alone or in combination of two or more gases. Furthermore, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the etching gas as appropriate. The etching conditions can be appropriately set depending on the target to be etched.

[0360] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0361] Next, an insulating layer 103 functioning as an interlayer insulating layer is formed over the substrate (or structure) and the conductive layer 111 ( FIGS. 12A to 12C ). The insulating layer 103 can be formed using any of the above-described insulating materials as appropriate. The insulating layer 103 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. For example, a silicon oxide film is formed as the insulating layer 103 by a sputtering method. Note that the insulating layer 103 is preferably planarized by performing CMP treatment after the formation thereof. By performing the planarization treatment on the insulating layer 103, the conductive layer 112 functioning as a wiring can be suitably formed in a later step. Alternatively, aluminum oxide may be formed on the insulating layer 103 by, for example, a sputtering method, and then CMP treatment may be performed until the insulating layer 103 is reached. The CMP treatment can planarize and smooth the surface of the insulating layer 103. By disposing the aluminum oxide on the insulating layer 103 and performing the CMP process, it becomes easy to detect the end point of the CMP process.

[0362] Note that there are cases where CMP treatment is not necessary. In this case, the upper surface of the insulating layer 103 has a convex curved shape. By not performing planarization treatment, manufacturing costs can be reduced and production yields can be increased.

[0363] Here, since the film thickness of the insulating layer 103 on the conductive layer 111 corresponds to the channel length of the vertical transistor, the film thickness of the insulating layer 103 can be appropriately set in accordance with the design value of the channel length of the vertical transistor.

[0364] Furthermore, the insulating layer 103 can be formed to contain excess oxygen by being deposited by a sputtering method in an oxygen-containing atmosphere. Furthermore, the use of a sputtering method, which does not require the use of hydrogen-containing molecules in a deposition gas, can reduce the hydrogen concentration in the insulating layer 103. By depositing the insulating layer 103 in this manner, oxygen can be supplied from the insulating layer 103 to a channel formation region of the semiconductor layer 113 to be formed in a later step, thereby reducing oxygen vacancies and VoH.

[0365] Next, a conductive film 112A, which will later become the conductive layer 112, is formed over the insulating layer 103 (FIGS. 12A to 12C). The conductive film 112A can be formed using any of the above-described conductive materials that can be used for the conductive layer 112. The conductive film 112A can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0366] Next, part of the conductive film 112A and part of the insulating layer 103 are processed to form an opening 121 reaching the conductive layer 111 (FIGS. 13A to 13C). The opening 121 can be formed by, for example, lithography and etching.

[0367] Here, the sidewalls of the opening 121 are preferably perpendicular to the upper surface of the conductive layer 111. Such a configuration allows miniaturization or high integration of the semiconductor device. The sidewalls of the opening 121 may also be tapered. By tapering the sidewalls of the opening 121, for example, coverage by a metal oxide film or the like that will become the semiconductor layer 113 (described later) can be improved, and defects such as voids can be reduced.

[0368] The maximum width of the opening 121 (or the diameter when the opening 121 is circular in plan view) is preferably very small. For example, the maximum width of the opening 121 is preferably 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 5 nm to 20 nm.

[0369] Because the opening 121 has a large aspect ratio, it is preferable to process a part of the conductive film 112A and a part of the insulating layer 103 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Different processing conditions may be used depending on the layer. Note that, depending on the conditions for processing the conductive film 112A and a part of the insulating layer 103, the inclination of the side surface of the conductive layer 112 in the opening 121 may differ from the inclination of the side surface of the insulating layer 103 in the opening 121.

[0370] Subsequently, heat treatment can be performed. The heat treatment is performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in, for example, a nitrogen gas or inert gas atmosphere. The heat treatment can also be performed under reduced pressure. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 103 and the like can be reduced before the formation of a metal oxide film that becomes the semiconductor layer 113, which will be described later.

[0371] The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, for example, moisture can be prevented from being absorbed into the insulating layer 103 as much as possible.

[0372] Next, a metal oxide film to be the semiconductor layer 113 is formed in contact with the bottom of the opening 121 (i.e., the top surface of the conductive layer 111 in the opening 121) and the sidewalls (i.e., the side surfaces of the insulating layer 103 in the opening 121 and the side surfaces of the conductive film 112A in the opening 121), and at least a part of the top surface of the conductive film 112A. The metal oxide film can be formed by appropriately using any of the above-described metal oxides applicable to the semiconductor layer 113. The metal oxide film can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the metal oxide film is preferably formed in contact with the side surfaces of the insulating layer 103, the side surfaces of the conductive film 112A, and the top surface of the conductive layer 111 in the opening 121 having a large aspect ratio. Therefore, the metal oxide film is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like. For example, the metal oxide film may be formed by an ALD method using In—Ga—Zn oxide, In—Al—Zn oxide, or indium oxide, as described in Embodiment 2.

[0373] When the sidewall of the opening 121 has a tapered shape, the method for forming the metal oxide film is not limited to the CVD method or the ALD method, and for example, sputtering can also be used.

[0374] Furthermore, when the semiconductor layer 113 has a stacked structure, the deposition methods for the layers included in the semiconductor layer 113 can be the same or different. For example, when the semiconductor layer 113 has a two-layer stacked structure, the first layer of the metal oxide film that becomes the semiconductor layer 113 can be deposited by sputtering, and the second layer can be deposited by ALD. Metal oxide films deposited by sputtering tend to have crystallinity. Therefore, by providing a crystalline metal oxide film as the first layer, the crystallinity of the second layer can be improved. Furthermore, even if pinholes or discontinuities are formed in the first layer of a metal oxide film deposited by sputtering, the overlapping portions can be filled with the second layer of a metal oxide film deposited by ALD, which has good coverage.

[0375] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not become polycrystallized, for example, at a temperature of 250° C. to 650° C., preferably 400° C. to 600° C. For details of the heat treatment, refer to the above description.

[0376] Here, the heat treatment is preferably performed in a state where the insulating layer 103 containing excess oxygen is provided in contact with the metal oxide film. By performing the heat treatment in this manner, oxygen can be supplied from the insulating layer 103 to the metal oxide film, and oxygen vacancies and VoH in the semiconductor layer 113 to be formed later can be reduced.

[0377] Although the above example shows a case where heat treatment is performed after the metal oxide film is formed, the present invention is not limited to this example, and heat treatment may be performed in a later step.

[0378] Next, a pattern is formed on the metal oxide film that will become the semiconductor layer 113 by, for example, lithography, and then the pattern is processed by etching. As a result, the semiconductor layer 113 is formed so as to have a region that overlaps with the opening 121 ( FIGS. 14A to 14C ). As a result, a portion of the semiconductor layer 113 is formed in the opening 121. The semiconductor layer 113 also comes into contact with a portion of the top surface of the conductive film 112A. As a result, the semiconductor layer 113 is formed to have a region that contacts the top surface of the conductive layer 111 in the opening 121, a region that contacts the side surface of the insulating layer 103 in the opening 121, a region that contacts the side surface of the conductive film 112A in the opening 121, and a region that contacts the top surface of the conductive film 112A.

[0379] Next, part of the conductive film 112A is processed to form the conductive layer 112 so as to have a region overlapping with the conductive layer 111 (FIGS. 15A to 15C). The conductive layer 112 can be formed, for example, by forming a pattern by lithography and then processing the conductive film 112A by etching based on the pattern. For example, dry etching or wet etching can be used for this processing, but dry etching is preferable because it is suitable for fine processing.

[0380] Although the example in which the semiconductor layer 113 and the conductive layer 112 are formed after the opening 121 is formed has been described above, this is not limiting. Below, an example of a manufacturing method in which the opening 121, the semiconductor layer 113, and the conductive layer 112 are formed in a procedure different from that described above will be described.

[0381] The method is the same as that described above until the conductive film 112A shown in FIGS. 12A to 12C is formed.

[0382] Next, part of the conductive film 112A is processed to form the conductive layer 112. For example, the method for forming the conductive layer 112 can refer to the above description.

[0383] Next, a part of the conductive layer 112 and a part of the insulating layer 103 are processed to form an opening 121 that reaches the conductive layer 111. For example, the above description can be referred to for the method of forming the opening 121.

[0384] Subsequently, a heat treatment may be carried out. For example, the conditions for the heat treatment can be as described above.

[0385] Next, a metal oxide film to be the semiconductor layer 113 is formed in contact with the bottom and sidewall of the opening 121 and at least a part of the top surface of the conductive layer 112. At this time, the metal oxide film has a region outside the opening 121 that is in contact with the top surface of the insulating layer 103. For example, the above-described description can be referred to for the method of forming the metal oxide film.

[0386] Next, it is preferable to perform a heat treatment. For example, the conditions for the heat treatment can be as described above.

[0387] Next, the metal oxide film that will become the semiconductor layer 113 is processed by lithography to form the semiconductor layer 113 (FIGS. 15A to 15C).

[0388] From this point on, the same procedure can be followed regardless of which of the above-mentioned production methods is applied.

[0389] Next, the insulating layer 105 is formed over the semiconductor layer 113, the conductive layer 112, and the insulating layer 103 ( FIGS. 16A to 16C ). The insulating layer 105 can be formed using any of the above-described insulating materials as appropriate. The insulating layer 105 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. Here, the insulating layer 105 is preferably formed in contact with the semiconductor layer 113 provided in the opening 121 having a large aspect ratio. Therefore, the insulating layer 105 is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like. For example, the insulating layer 105 is formed using silicon oxide by an ALD method.

[0390] Note that when the sidewall of the opening 121 has a tapered shape, the method for forming the insulating layer 105 is not limited to the CVD method or the ALD method, and for example, a sputtering method can also be used.

[0391] By forming the insulating layer 105 after forming the semiconductor layer 113, the side edges of the semiconductor layer 113 are covered with the insulating layer 105. This makes it possible to prevent a short circuit between the semiconductor layer 113 and the conductive layer 115 formed in a later step. Furthermore, by using the above-described structure, the side edges of the conductive layer 112 are covered with the insulating layer 105. This makes it possible to prevent a short circuit between the conductive layer 112 and the conductive layer 115.

[0392] Next, a conductive film 115A is formed over the insulating layer 105 so as to fill the recesses of the insulating layer 105 ( FIGS. 16A to 16C ). The conductive film 115A can be formed using any of the above-described conductive materials applicable to the conductive layer 115 as appropriate. The conductive film 115A can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate. Here, the conductive film 115A is preferably formed in contact with the insulating layer 105 provided in the opening 121 having a large aspect ratio. Therefore, a film formation method with good coverage or filling properties is preferably used for forming the conductive film 115A, and more preferably a CVD method, an ALD method, or the like.

[0393] Note that when the conductive film 115A is formed by a CVD method, the average surface roughness of the top surface of the conductive film 115A may become large. In this case, it is preferable to planarize the top surface of the conductive film 115A by a CMP method. Before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film 115A, and the CMP treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0394] In the above description, the conductive film 115A is provided so as to fill the opening 121, but the present invention is not limited to this. For example, a recess that reflects the shape of the opening 121 may be formed in the center of the conductive film 115A. Alternatively, the recess may be filled with, for example, an inorganic insulating material.

[0395] Next, a part of the conductive film 115A is processed to form the conductive layer 115 (FIGS. 17A to 17C). The conductive layer 115 can be formed, for example, by forming a pattern by lithography and then processing the conductive film 115A by etching based on the pattern. For example, dry etching or wet etching can be used for this processing, but dry etching is preferable because it is suitable for fine processing. The conductive layer 115 is formed on the insulating layer 105 so as to have a region overlapping with the semiconductor layer 113.

[0396] In this manner, the vertical transistor shown in FIGS. 8A and 8B can be formed, which includes the conductive layer 111, the conductive layer 112, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115. As described above, the conductive layer 111 functions as one of the source electrode and the drain electrode of the vertical transistor. The conductive layer 112 functions as the other of the source electrode and the drain electrode of the vertical transistor. The semiconductor layer 113 functions as a semiconductor layer having a channel formation region of the vertical transistor. The insulating layer 105 functions as a gate insulating layer of the vertical transistor. The conductive layer 115 functions as a gate electrode of the vertical transistor.

[0397] Next, an insulating layer 107 is formed to cover the conductive layer 115 and the insulating layer 105. After that, an insulating layer 131 is formed over the insulating layer 107 (FIGS. 18A to 18C). The insulating layer 107 and the insulating layer 131 can be formed using any of the above-described insulating materials as appropriate. The insulating layer 107 and the insulating layer 131 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate.

[0398] When further structures such as transistors are to be fabricated on the vertical transistor, it is preferable to polish the top surfaces of the insulating layer 131, the insulating layer 107, and the conductive layer 115 by CMP treatment. By this treatment, the insulating layer 131, the insulating layer 107, and the conductive layer 115 are formed to have approximately the same height relative to the substrate surface ( FIGS. 19A to 19C ).

[0399] Next, a structure such as a transistor is formed over the conductive layer 115, the insulating layer 107, and the insulating layer 131. For example, when a vertical transistor is formed, the steps described with reference to FIGS. 12A to 18C are repeated. This allows a plurality of stacked vertical transistors to be formed, such as the transistor 200A and the transistor 100A shown in FIGS. 3 and 4 or the transistor 300A, the transistor 200A, and the transistor 100A shown in FIGS. 6 and 7.

[0400] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0401] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0402] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0403] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0404] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0405] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0406] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0407] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0408] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0409] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0410] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0411] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0412] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also referred to as microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0413] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0414] The crystallinity of indium oxide can be analyzed by, for example, XRD, TEM, or ED. Alternatively, the analysis may be performed by a combination of these methods.

[0415] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0416] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0417] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0418] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0419] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0420] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0421] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0422] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0423] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0424] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0425]

[0426] A seed layer is preferably provided so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals that has a small difference in lattice constant with indium oxide (also referred to as lattice mismatch). This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0427] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0428] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0429] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0430] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0431] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0432] Embodiment 3 In this embodiment, a memory device 900 to which the semiconductor device of one embodiment of the present invention described in Embodiment 1 can be applied will be described.

[0433] Fig. 21 is a block diagram showing a configuration example of a memory device 900. The memory device 900 shown in Fig. 21 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 21 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0434] The semiconductor device of one embodiment of the present invention described in Embodiment 1 can be applied to the memory cell 950. By using the semiconductor device, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacity per area of ​​the memory device can be increased.

[0435] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0436] In the storage device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0437] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0438] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the memory device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0439] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0440] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0441] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0442] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the memory device 900. The data output from the output circuit 926 is a signal RDA.

[0443] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the memory device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 21, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, it is preferable to provide a power switch for each power domain.

[0444] The OS-SRAM (for example, the memory cell 30 in FIG. 1C ) formed using the semiconductor device of one embodiment of the present invention, which is described in Embodiment 1, can be used as the memory cell 950 .

[0445] 22 shows a configuration example of a memory cell 31, which is an OS-SRAM different from the memory cell 30 and can be applied to the memory cell 950. While the memory cell 30 is composed of six transistors, the memory cell 31 is composed of eight transistors and two capacitive elements. The memory cell 31 is a backup-capable SRAM memory cell.

[0446] The memory cell 31 includes a transistor M1A, a transistor M2A, a transistor M3A, a transistor M1B, a transistor M2B, a transistor M3B, a transistor M4, a transistor M5, a capacitor C1, and a capacitor C2. Note that the transistors M1A and M1B are p-channel transistors, and the transistors M2A, M3A, M2B, M3B, M4, and M5 are n-channel transistors.

[0447] For transistors M1A, M2A, M3A, M1B, M2B, and M3B, refer to the description of the memory cell 30. Therefore, it can be said that the memory cell 31 has a configuration in which transistors M4, M5, capacitive elements C1, and C2 are added to the configuration of the memory cell 30.

[0448] The first terminal (either the source or the drain) of the transistor M3A is connected to the wiring BL, and the second terminal (the other of the source or the drain) of the transistor M3A is connected to the first terminal (either the source or the drain) of the transistor M1A, the first terminal (either the source or the drain) of the transistor M2B, the gate of the transistor M1B, the gate of the transistor M2A, and the first terminal (either the source or the drain) of the transistor M5. The gate of the transistor M3A is connected to the wiring WL. The first terminal (either the source or the drain) of the transistor M3B is connected to the wiring BLB, and the second terminal (the other of the source or the drain) of the transistor M3B is connected to the first terminal (either the source or the drain) of the transistor M1B, the first terminal (either the source or the drain) of the transistor M2A, the gate of the transistor M1A, the gate of the transistor M2B, and the first terminal (either the source or the drain) of the transistor M4. The gate of the transistor M3B is connected to the wiring WL.

[0449] A second terminal (the other of the source and drain) of the transistor M1A is connected to the wiring VDD. A second terminal (the other of the source and drain) of the transistor M1B is connected to the wiring VDD. A second terminal (the other of the source and drain) of the transistor M2B is connected to the wiring GND. A second terminal (the other of the source and drain) of the transistor M2A is connected to the wiring GND.

[0450] The second terminal (the other of the source and drain) of the transistor M4 is connected to the first terminal (one of the electrodes) of the capacitor C1, and the gate of the transistor M4 is connected to the wiring BRL. The second terminal (the other of the source and drain) of the transistor M5 is connected to the first terminal (one of the electrodes) of the capacitor C2, and the gate of the transistor M5 is connected to the wiring BRL.

[0451] The second terminal (the other electrode) of the capacitance element C1 is connected to the wiring GND, and the second terminal (the other electrode) of the capacitance element C2 is connected to the wiring GND.

[0452] The wirings BL and BLB function as bit lines, the wiring WL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M4 and M5.

[0453] The wiring VDD is a wiring that applies a high-level potential, and the wiring GND is a wiring that applies a low-level potential.

[0454] Data is written by applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. Specifically, when the transistor M5 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BL, and the potential is written to the second terminal of the transistor M5.

[0455] Since the memory cell 31 includes an inverter loop formed by transistors M1A, M1B, M2A, and M2B, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M3B. Because transistor M3B is conductive, the potential applied to wiring BL, i.e., the inverted signal of the signal input to wiring BL, is output to wiring BLB. Because transistors M4 and M5 are conductive, the potentials of the second terminals of transistors M3A and M3B are held in the first terminals of capacitors C2 and C1, respectively. Subsequently, a low-level potential is applied to wiring WL and a low-level potential is applied to wiring BRL, thereby turning off transistors M3A, M3B, M4, and M5, thereby holding the potentials of the first terminals of capacitors C1 and C2.

[0456] Data is read by precharging the wirings BL and BLB to a predetermined potential in advance, and then applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor C1 is refreshed by the inverter loop of the memory cell 31 and output to the wiring BLB. The potential of the first terminal of the capacitor C2 is refreshed by the inverter loop of the memory cell 31 and output to the wiring BL. The potentials of the wirings BL and BLB change from the precharged potentials to the potentials of the first terminal of the capacitor C2 and the first terminal of the capacitor C1, respectively. Therefore, the potential held in the memory cell 31 can be read from the potential of the wiring BL or the wiring BLB.

[0457] Note that OS transistors are preferably used as the transistors M3A, M3B, M4, and M5. This allows written data to be held by the transistors M3A, M3B, M4, and M5 for a long time, thereby reducing the frequency of refreshing the memory cell 31. Alternatively, the refresh operation of the memory cell 31 can be eliminated. Furthermore, by using the OS transistors described in Embodiment 1 as the transistors M3A, M3B, M4, and M5, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0458] Note that Si transistors may be used as the transistors M1A, M1B, M2A, M2B, M4, and M5.

[0459] In the memory cell 31 shown in FIG. 22, the semiconductor device of one embodiment of the present invention described in Embodiment 1 can be applied to each of the transistors M1A, M2A, and M3A, and the transistors M1B, M2B, and M3B.

[0460] 22, the transistors M4 and M5 can be provided in the first layer (the layer in which the transistors M1A and M1B are provided) of the memory cell 30 shown in FIG. 1E. Alternatively, a new layer (e.g., a layer having transistors) can be formed between the first layer and the second layer (the layer in which the transistors M2A and M2B are provided), and the transistors M4 and M5 can be provided in that layer. In this case, the memory cell 31 has a four-layer stacked structure.

[0461] In this manner, by applying the semiconductor device of one embodiment of the present invention to the memory cell 31, a very high-performance memory cell 31 that is small and has excellent retention characteristics and high operating speed can be realized.

[0462] The drive circuit 910 and the memory array 920 of the memory device 900 shown in FIG. 21 can be provided on the same plane.

[0463] 23A, the drive circuit 910 and the memory array 920 can be provided overlapping each other. By providing the drive circuit 910 and the memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 23B, the memory array 920 can be provided in multiple layers on the drive circuit 910. This allows the storage capacity of the storage device 900 to be increased without increasing the area occupied by the storage device 900.

[0464] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0465] 24 shows a block diagram of the arithmetic device 970. The arithmetic device 970 shown in FIG. 24 can be applied to, for example, a CPU. The arithmetic device 970 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0466] The arithmetic device 970 shown in FIG. 24 has an ALU 991 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0467] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0468] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 970. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0469] The arithmetic device 970 shown in FIG. 24 is merely an example of a simplified configuration, and actual arithmetic devices 970 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 970 shown in FIG. 24 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 970 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0470] An instruction input to the arithmetic unit 970 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0471] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 970 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the arithmetic unit 970.

[0472] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0473] 24, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitance elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitance elements is selected, the data is rewritten to the capacitance elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0474] The memory array 920 and the arithmetic unit 970 can be provided overlapping each other. Perspective views of a semiconductor device 975A are shown in Figures 25A and 25B. The semiconductor device 975A has a layer 930 on which memory arrays are provided above the arithmetic unit 970. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 970 and each memory array have overlapping regions. To make the configuration of the semiconductor device 975A easier to understand, the arithmetic unit 970 and the layer 930 are shown separately in Figure 25B.

[0475] By stacking the layer 930 having the memory array and the arithmetic unit 970, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance can reduce power consumption.

[0476] As a method for stacking the layer 930 having a memory array and the arithmetic device 970, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 970 may be used, or a method in which the arithmetic device 970 and the layer 930 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0477] Here, the arithmetic unit 970 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0478] The above-described OS-SRAM (e.g., memory cell 30 or memory cell 31) can be applied to each of the memory array 920L1, the memory array 920L2, and the memory array 920L3. That is, the semiconductor device of one embodiment of the present invention can be applied to each of the memory array 920L1, the memory array 920L2, and the memory array 920L3. In particular, it is preferable to apply an OS-SRAM to the memory array 920L1, which has the smallest capacity and the highest access frequency.

[0479] When the cache 999 provided in the arithmetic unit 970 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0480] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0481] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0482] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0483] Whether the memory array 920 functions as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the storage device 900 to function as RAM based on a signal supplied from the arithmetic device 970.

[0484] The memory device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the memory device 900 can function as both a cache and a main memory. The memory device 900 of one embodiment of the present invention can function as, for example, a universal memory.

[0485] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 970. Figure 26A shows a perspective view of a semiconductor device 975B.

[0486] In the semiconductor device 975B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0487] Furthermore, in the semiconductor device 975B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0488] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 975C.

[0489] The semiconductor device 975C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 970, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0490] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0491] In this embodiment, an application example of the memory device of one embodiment of the present invention will be described. As described in Embodiment 3, the semiconductor device of one embodiment of the present invention described in Embodiment 1 can be applied to the memory device of one embodiment of the present invention.

[0492] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 27A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 27A , from the top layer, there are memories embedded as registers in a processing unit such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches may also be included.

[0493] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0494] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0495] The main memory has a function of holding programs, data, etc. read from storage.

[0496] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0497] A storage device (OS memory) using an oxide semiconductor of one embodiment of the present invention has high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 27A , the storage device of one embodiment of the present invention can be suitably used in both the tier where a cache is located and the tier where a main memory is located. The storage device of one embodiment of the present invention can also be applied to the tier where a storage is located.

[0498] FIG. 27B also shows an example in which an SRAM is used as part of a cache and an OS memory of one embodiment of the present invention is used as the other part of the cache.

[0499] The lowest level cache can be called a Last Level Cache (LLC). While an LLC does not require faster operation speed than higher-level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operation speed and can retain data for a long period of time, and therefore can be suitably used for an LLC. The OS memory of one embodiment of the present invention can also be applied to a Final Level Cache (FLC).

[0500] For example, as shown in Fig. 27B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 27B, not only the OS memory but also DRAM can be applied to the main memory.

[0501] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0502] Embodiment 5 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described with reference to drawings. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0503] [Electronic Component] FIG. 28A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 28A has semiconductor device 710 inside mold 711. FIG. 28A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0504] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0505] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0506] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0507] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained during the semiconductor chip manufacturing process, for example, by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0508] 28B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0509] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0510] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0511] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, TSVs can also be used as through electrodes.

[0512] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0513] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0514] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space corresponding to the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0515] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0516] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 28B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0517] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0518] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 29A . The electronic device 6500 shown in FIG. 29A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0519] 29B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0520] [Mainframe] Next, Fig. 29C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 29C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0521] The computer 5620 can have the configuration shown in the perspective view in Fig. 29D, for example. In Fig. 29D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0522] A PC card 5621 shown in Figure 29E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although Figure 29E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, the following descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for information about these semiconductor devices.

[0523] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0524] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0525] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0526] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0527] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0528] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, learning and inference in artificial intelligence.

[0529] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0530] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0531] Fig. 30 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 30, a planet 6804 is shown in space as an example.

[0532] 30 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0533] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0534] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may also be called a solar cell module.

[0535] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0536] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0537] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0538] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0539] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0540] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0541] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0542] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0543] Fig. 31 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 31 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0544] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0545] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0546] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0547] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0548] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0549] This embodiment mode can be combined with other embodiment modes as appropriate.

[0550] 30: memory cell, 30A: semiconductor device, 30B: semiconductor device, 31: memory cell, 100A: transistor, 100B: transistor, 101: substrate, 103: insulating layer, 103_1: insulating layer, 103_2: insulating layer, 103a: insulating layer, 103b: insulating layer, 103c: insulating layer, 105: insulating layer, 105a: insulating layer, 105b: insulating layer, 105c: insulating layer, 107: insulating layer, 107a: insulating layer, 107b: insulating layer, 107c: insulating layer, 111: conductive layer, 111a: conductive layer, 111a_2: conductive layer, 111b: conductive layer, 111b_2: conductive layer, 111c: conductive layer layer, 112: conductive layer, 112a: conductive layer, 112A: conductive film, 112b: conductive layer, 112c: conductive layer, 112c_2: conductive layer, 113: semiconductor layer, 113a: semiconductor layer, 113b: semiconductor layer, 113c: semiconductor layer, 113i: region, 113na: region, 113nb: region, 115: conductive layer, 115a: conductive layer, 115A: conductive film, 115b: conductive layer, 115c: conductive layer, 116: insulating layer, 117: conductive layer, 121: opening, 131: insulating layer, 139: insulating layer, 200A: transistor, 200B: transistor, 211: conductive layer, 231: insulating layer, 256: Conductive layer, 257: conductive layer, 258: conductive layer, 259: conductive layer, 300A: transistor, 300B: transistor, 311: substrate, 312: insulating layer, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: run 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: memory device, 910: drive circuit, 910L1: drive circuit, 910L2: drive circuit, 910L3: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 920L1: memory array, 920L2: memory array, 920L3: memory array, 923: row driver, 924: column driver, 925: input circuit,926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 940L1: connection electrode, 940L2: connection electrode, 940L3: connection electrode, 941: row decoder, 942: column decoder, 950: memory cell, 970: arithmetic unit, 975A: semiconductor device, 975B: semiconductor device, 975C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor body device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device sb: server, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network,

Claims

a first transistor, a second transistor, and a third transistor; the first transistor is a p-channel transistor, the second transistor is an n-channel transistor overlapping the first transistor, the third transistor is an n-channel transistor located overlying the second transistor, a gate of the first transistor and one of a source and a drain of the second transistor are electrically connected at a first node; one of the source and the drain of the first transistor, the gate of the second transistor, and one of the source and the drain of the third transistor are electrically connected at a second node; Semiconductor device. 　 In claim 1, the second transistor and the third transistor are each a vertical transistor. Semiconductor device. 　 In claim 1 or claim 2, the second transistor and the third transistor each contain indium and oxygen in a semiconductor layer having a channel formation region; Semiconductor device. 　 In claim 1, the first transistor has silicon in a semiconductor layer having a channel formation region; Semiconductor device. 　 A semiconductor device comprising: a first semiconductor device that is the semiconductor device according to claim 1; and a second semiconductor device that is different from the first semiconductor device; the second semiconductor device includes a fourth transistor, a fifth transistor, and a sixth transistor; the fourth transistor is a p-channel transistor, the fifth transistor is an n-channel transistor located overlying the fourth transistor, the sixth transistor is an n-channel transistor located overlying the fifth transistor, the gate of the fourth transistor and one of the source and the drain of the fifth transistor are electrically connected to a third node; one of the source and the drain of the fourth transistor, the gate of the fifth transistor, and one of the source and the drain of the sixth transistor are electrically connected to a fourth node; the first transistor and the fourth transistor are located on the same layer; the second transistor and the fifth transistor are located on the same layer; the third transistor and the sixth transistor are located on the same layer; the second node and the third node are electrically connected; the first node and the fourth node are electrically connected; storage device. 　 In claim 5, the fifth transistor and the sixth transistor are each a vertical transistor. storage device. 　 In claim 5, the fifth transistor and the sixth transistor each contain indium and oxygen in a semiconductor layer having a channel formation region; storage device. 　 In claim 5, the fourth transistor has silicon in a semiconductor layer having a channel formation region; storage device. a first transistor, a second transistor, and a third transistor; the first transistor is a p-channel transistor, the second transistor is an n-channel transistor overlapping the first transistor, the third transistor is an n-channel transistor located overlying the second transistor, a gate of the first transistor and one of a source and a drain of the second transistor are electrically connected at a first node; one of the source and the drain of the first transistor, the gate of the second transistor, and one of the source and the drain of the third transistor are electrically connected at a second node; the first transistor, the second transistor, and the third transistor are each a vertical transistor. Semiconductor device. 　 In claim 9, the second transistor and the third transistor each contain indium and oxygen in a semiconductor layer having a channel formation region; Semiconductor device. 　 In claim 9 or claim 10, the first transistor has silicon in a semiconductor layer having a channel formation region; Semiconductor device. 　 In claim 9 or claim 10, the first transistor includes tin and oxygen in a semiconductor layer having a channel formation region; Semiconductor device. 　 A semiconductor device comprising: a first semiconductor device that is the semiconductor device according to claim 9; and a second semiconductor device that is different from the first semiconductor device; the second semiconductor device includes a fourth transistor, a fifth transistor, and a sixth transistor; the fourth transistor is a p-channel transistor, the fifth transistor is an n-channel transistor located overlying the fourth transistor, the sixth transistor is an n-channel transistor located overlying the fifth transistor, the gate of the fourth transistor and one of the source and the drain of the fifth transistor are electrically connected to a third node; one of the source and the drain of the fourth transistor, the gate of the fifth transistor, and one of the source and the drain of the sixth transistor are electrically connected to a fourth node; the fourth transistor, the fifth transistor, and the sixth transistor are each vertical transistors; the first transistor and the fourth transistor are located on the same layer; the second transistor and the fifth transistor are located on the same layer; the third transistor and the sixth transistor are located on the same layer; the second node and the third node are electrically connected; the first node and the fourth node are electrically connected; storage device. 　 In claim 13, the fifth transistor and the sixth transistor each contain indium and oxygen in a semiconductor layer having a channel formation region; storage device. 　 In claim 13, the fourth transistor has silicon in a semiconductor layer having a channel formation region; storage device. 　 In claim 13, the fourth transistor includes tin and oxygen in a semiconductor layer having a channel formation region; storage device.

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