Method for producing semiconductor device

Abstract

Provided is a transistor that has a small footprint, or a method for producing the same. This method for producing a semiconductor device that has a crystalline semiconductor layer has: a first step for forming a semiconductor layer on an insulating layer in which a groove section is provided; a second step for forming a mask on the semiconductor layer; a third step for etching the semiconductor layer on the insulating layer, where the mask is not formed; and a fourth step for etching the semiconductor layer in the groove section, where the mask is not formed. The surface of the semiconductor layer on the insulating layer is formed so as to have a first crystal plane, and the surface of the semiconductor layer on a side surface of the groove section is formed so as to have a second crystal plane.

Description

Method for manufacturing a semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, and a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include large-scale integration (LSI) chips, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), AI chips, memories (storage devices), input devices, input / output devices, sensors, imaging devices, display devices, light-emitting devices, power storage devices, electronic devices, and driving methods thereof or manufacturing methods thereof. Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and includes a circuit including a transistor, a device having the same circuit, and the like. Furthermore, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object or a method. Alternatively, it relates to a method (process), a machine, a manufacture, or a composition of matter.

[0004] A technology for constructing transistors using semiconductor thin films formed on insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, metal oxides (oxide semiconductors) that exhibit semiconducting properties have also attracted attention.

[0005] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0006] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device in which transistors can be arranged at high density. Another object is to provide a semiconductor device with low power consumption.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, and to overcome at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a method for manufacturing a semiconductor device having a crystalline semiconductor layer, the method including: a first step of forming a semiconductor layer over an insulating layer provided with a groove; a second step of forming a mask over the semiconductor layer; a third step of etching the semiconductor layer over the insulating layer where the mask is not formed; and a fourth step of etching the semiconductor layer in the groove where the mask is not formed, in which a surface of the semiconductor layer over the insulating layer has a first crystal plane and a surface of the semiconductor layer on a side surface of the groove has a second crystal plane.

[0013] One embodiment of the present invention is a method for manufacturing a semiconductor device having a crystalline semiconductor layer, the method including: a first step of forming a semiconductor layer over an insulating layer provided with a groove; a second step of forming a mask over the semiconductor layer; a third step of etching the semiconductor layer over the insulating layer where the mask is not formed; and a fourth step of etching the semiconductor layer in the groove where the mask is not formed, in which the third step is anisotropic dry etching and the fourth step is isotropic dry etching, in which a surface of the semiconductor layer over the insulating layer has a first crystal plane and a surface of the semiconductor layer on a side surface of the groove has a second crystal plane.

[0014] In the above-described method for manufacturing a semiconductor device, the third step and the fourth step are preferably performed using the same apparatus.

[0015] In the method for manufacturing a semiconductor device described above, the bias power of the dry etching used in the third and fourth steps is preferably smaller in the fourth step than in the third step.

[0016] One embodiment of the present invention is a method for manufacturing a semiconductor device having a crystalline semiconductor layer, the method including: a first step of forming a semiconductor layer over an insulating layer provided with a groove; a second step of forming a mask over the semiconductor layer; a third step of etching the semiconductor layer over the insulating layer where the mask is not formed; and a fourth step of etching the semiconductor layer in the groove where the mask is not formed, in which the third step is anisotropic dry etching and the fourth step is wet etching, in which a surface of the semiconductor layer over the insulating layer has a first crystal plane and a surface of the semiconductor layer on a side surface of the groove has a second crystal plane.

[0017] In the above-described method for manufacturing a semiconductor device, the semiconductor layer preferably has a cubic crystal structure, the first crystal plane is a {111} crystal plane, and the second crystal plane is a crystal plane other than the {111} crystal plane.

[0018] In the above-described method for manufacturing a semiconductor device, the semiconductor layer preferably contains indium and oxygen.

[0019] In the above-described method for manufacturing a semiconductor device, it is preferable that a seed layer is formed before the first step, a semiconductor layer is formed in contact with the seed layer in the first step, the semiconductor layer has a cubic crystal, the semiconductor layer has a portion in contact with the seed layer, and the surface of the semiconductor layer in contact with the seed layer has a {111} crystal plane.

[0020] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor with high reliability can be provided. One embodiment of the present invention can provide a semiconductor device in which transistors can be arranged at high density. Furthermore, a semiconductor device with low power consumption can be provided.

[0021] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel configuration, and to improve at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A, 1B, 1C, and 1D are structural examples of semiconductor devices. FIGS. 2A, 2B, and 2C are structural examples of semiconductor devices. FIGS. 3A, 3B, 3C, 3D, and 3E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 4A, 4B, 4C, 4D, and 4E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 5A, 5B, 5C, 5D, and 5E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 6A, 6B, 6C, 6D, and 6E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 7A, 7B, 7C, 7D, and 7E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 8A, 8B, 8C, 8D, and 8E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 9A, 9B, 9C, 9D, and 9E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 10A, 10B, 10C, 10D, and 10E are diagrams illustrating the crystal structure of a metal oxide. FIGS. 11A and 11B are cross-sectional schematic diagrams illustrating an example of a semiconductor device. FIGS. 12A, 12B, 12C, 12D, and 12E are configuration examples of semiconductor devices. FIGS. 13A, 13B, 13C, 13D, and 13E are configuration examples of semiconductor devices. FIGS. 14A, 14B, 14C, and 14D are configuration examples of semiconductor devices. FIGS. 15A and 15B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 15C is a cross-sectional view illustrating an indium oxide film. FIGS. 16A, 16B, and 16C are configuration examples of memory devices. FIG. 17 is a configuration example of a memory device. FIG. 18 is a block diagram illustrating a configuration example of a semiconductor device. 19A, 19B, 19C, 19D, 19E, 19F, and 19G are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 20A and 20B are perspective views of a semiconductor device. FIGS. 21A and 21B are diagrams illustrating an example of an electronic component. FIGS. 22A, 22B, and 22C are diagrams illustrating an example of a mainframe computer. FIG. 22D is a diagram illustrating an example of space equipment. FIG. 22E is a diagram illustrating an example of a storage system applicable to a data center. FIG. 23A is an AFM image of an indium oxide film, and FIGS. 23B, 23C, and 23D are EBSD images.

[0024] The following description of the preferred embodiments will be made with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of layers, the positional relationship, or the area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor for a semiconductor layer and a transistor having an oxide semiconductor for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and drain through the channel formation region. In this specification and the like, the channel formation region refers to a region of a semiconductor layer that overlaps (or faces) a gate electrode via a gate insulating film and is located between a region in contact with the source electrode and a region in contact with the drain electrode.

[0031] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage Vgs between the gate and the source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor). Note that when "Vgs" is used to refer to a voltage, it refers to the potential difference between the source and the gate when the source is used as the reference.

[0034] In this specification and the like, unless otherwise specified, the on-state current refers to the drain current when a transistor is in an on state (also referred to as a "conducting state"). Unless otherwise specified, the on state refers to a state in which Vg is equal to or higher than Vth for an n-channel transistor, and a state in which Vg is equal to or lower than the threshold voltage for a p-channel transistor.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0036] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0038] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0039] In this specification and the like, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (for example, a substrate) on which the component is formed.

[0040] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0041] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0042] In this specification, "equal height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces to be processed in the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ due to differences in the processing equipment, processing method, and material of the processed surface during the CMP process, or differences in polishing rate and etching rate. In this specification, this case is also treated as "equal height."

[0043] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0044] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0045] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0046] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0047] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described.

[0048] In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1 to 11B. Note that in the plan views and perspective views shown below, some components (such as an insulating layer) may be omitted.

[0049] [Configuration Example of Semiconductor Device] FIGS. 1A to 1D are diagrams illustrating an example of a semiconductor device. FIG. 1A is a plan view of the semiconductor device, and the semiconductor device has a transistor 100A. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 1A. FIG. 1D is a horizontal cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 1B. FIGS. 2A to 2C are schematic perspective views of the semiconductor device illustrated in FIGS. 1A to 1D. FIG. 2A does not illustrate an interlayer insulating film to make the structure easier to understand. FIG. 2B is a schematic perspective view in which a portion of FIG. 2A is cut away. FIG. 2C is a schematic perspective view including the horizontal cross-sectional view of FIG. 1D. Note that FIG. 2C illustrates insulating layers 12 and 13.

[0050] The transistor 100A includes at least a conductive layer 11, a conductive layer 15 (conductive layers 15a and 15b), a semiconductor layer 17, an insulating layer 19, and a conductive layer 20. A part of the conductive layer 11 functions as a source electrode or a drain electrode. A part of the conductive layer 15 functions as a source electrode or a drain electrode. A part of the insulating layer 19 functions as a gate insulating film. A part of the conductive layer 20 functions as a gate electrode.

[0051] In this specification, when describing matters common to components distinguished by alphabets attached to symbols (conductive layer 15a, conductive layer 15b, etc.) and components distinguished by numbers attached to symbols (conductive layer 11_1, conductive layer 11_2, etc.), the description may be made using symbols with the alphabets or numbers omitted (conductive layer 15, conductive layer 11, etc.).

[0052] The insulating layer 10 is provided on a substrate (not shown). The conductive layers 11 (conductive layer 11_1, conductive layer 11_2) are provided on the insulating layer 10. The conductive layer 11 may extend in the X direction, the Y direction, or both the X and Y directions. The conductive layer 11 preferably has a two-layer structure of the conductive layer 11_1 and the conductive layer 11_2, but may also be formed as a single layer or a laminate of three or more layers.

[0053] The insulating layer 12 is provided on the conductive layer 11. It is also desirable that the insulating layer 12 has a flat upper surface. The insulating layer 12 can be formed as a single layer or a laminate of two or more layers. For example, in the case of two layers, it is preferable to use different film formation methods. Specifically, the first layer may be formed of silicon nitride or silicon nitride oxide by ALD (Atomic Layer Deposition), and the second layer may be formed of silicon nitride or silicon nitride oxide by sputtering or CVD (Chemical Vapor Deposition). The insulating layer 13 is provided on the insulating layer 12. The insulating layer 14 is provided on the insulating layer 13.

[0054] The conductive layer 15a and the conductive layer 15b are provided separately over the insulating layer 14. The conductive layer 15a (conductive layer 15b) preferably has a two-layer structure in which the conductive layer 15a_2 (conductive layer 15b_2) is provided over the conductive layer 15a_1 (conductive layer 15b_1), but may also have a single-layer structure or a stacked structure of three or more layers.

[0055] The seed layer 16 is provided on the conductive layer 15. More specifically, the seed layer 16a is provided on the conductive layer 15a, and the seed layer 16b is provided on the conductive layer 15b.

[0056] Groove portion 200 is located between conductive layer 15a and conductive layer 15b, which are spaced apart from each other, in a plan view. Groove portion 200 is provided in insulating layer 14, insulating layer 13, and insulating layer 12, and reaches conductive layer 11. The portion of conductive layer 11 that overlaps with groove portion 200 has a recess.

[0057] The semiconductor layer 17 is provided so as to cover the inner walls and part of the bottom surface of the groove 200, and is provided inside the groove 200 in contact with the side surfaces of the insulating layer 14, the side surfaces of the insulating layer 13, the side surfaces of the insulating layer 12, and the recess surface of the conductive layer 11. The semiconductor layer 17 is also provided on the conductive layer 15 and the seed layer 16. The semiconductor layer 17 has a portion in contact with the seed layer 16. The semiconductor layer 17 also has a portion in contact with the side surface of the conductive layer 15. Since the semiconductor layer 17 has a portion in contact with the conductive layer 15 without the seed layer 16 therebetween, better contact can be obtained between the semiconductor layer 17 and the conductive layer 15.

[0058] The insulating layer 19 has a portion in contact with the semiconductor layer 17 and is provided to cover the semiconductor layer 17. The insulating layer 19 is also provided so that at least a portion thereof is located within the groove portion 200. The conductive layer 20 is provided on the insulating layer 19 and has a portion which is provided within the groove portion 200. The conductive layer 20 has a portion which overlaps with the semiconductor layer 17 with the insulating layer 19 interposed therebetween.

[0059] The insulating layer 21 is provided on the insulating layer 19 and the conductive layer 20. The insulating layer 21 is provided so that at least a portion thereof contacts the insulating layer 19 and the conductive layer 20 and covers the semiconductor layer 17, the conductive layer 15, and the conductive layer 20. The insulating layer 22 is provided on the insulating layer 21. It is also desirable that the upper surface of the insulating layer 22 is flat.

[0060] The conductive layers 23 a and 23 b are provided so as to be embedded in openings provided in the insulating layers 21 and 22 .

[0061] The conductive layer 24 is provided on the insulating layer 22. The conductive layer 24 is connected to the conductive layer 15a via the conductive layer 23a. The conductive layer 24 is also connected to the conductive layer 15b via the conductive layer 23b.

[0062] As shown in FIG. 1B , the transistor 100A has a structure in which one of the source electrode and the drain electrode (the conductive layer 11 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 15a and the conductive layer 15b here) is located above, and thus current flows vertically. That is, a channel is formed along the side surface of the groove 200. As a result, the transistor 100A can occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. Note that the channel length direction of the transistor 100A can be said to have a component in the height direction (vertical direction); therefore, the transistor 100A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0063] 1B and 2B , the portion of the conductive layer 11 that overlaps with the groove portion 200 has a recess. By having this recess, the contact area between the conductive layer 11 and the semiconductor layer 17 can be made larger than in a case where the recess is not provided. Therefore, the contact resistance between the conductive layer 11 and the semiconductor layer 17 can be made smaller.

[0064] 1B shows an example in which the height of the lower surface of the conductive layer 20 in the groove 200 is the same as the height of the upper surface of the conductive layer 11 other than the recess. It is also preferable that the height of the lower surface of the conductive layer 20 in the groove 200 is the same as or lower than the height of the upper surface of the conductive layer 11 other than the recess. For example, it is preferable that the depth of the recess is the same as, approximately the same as, or deeper than the film thickness of the insulating layer 19. By doing so, it is possible to improve the controllability of the electron density of the semiconductor layer 17 near one of the source electrode and the drain electrode (here, the conductive layer 11) by the gate electric field from the gate electrode (conductive layer 20) compared to a case in which the recess is not provided.

[0065] The recess in the conductive layer 11 may have a curved portion, as shown in FIGS. 1B and 2B . When the recess has a curved portion, the portions of the semiconductor layer 17, insulating layer 19, and conductive layer 20 provided on the recess near the recess may also have a curved portion. In other words, the portion may have a curved or concave surface in cross-sectional view. Furthermore, the portion may not have a corner (right angle or acute angle) in cross-sectional view. This reduces electric field concentration on the insulating layer 19 near the recess, improves the dielectric strength of the transistor 100A, and suppresses electrostatic breakdown of the transistor 100A. Therefore, the reliability of the semiconductor device can be improved.

[0066] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to FIGS. 3A to 9E . In the drawings illustrating an example of a manufacturing method of a semiconductor device, A in each drawing is a plan view. B in each drawing is a cross-sectional view taken along dashed dotted line A1-A2 in A of each drawing. C in each drawing is a cross-sectional view taken along dashed dotted line A3-A4 in A of each drawing. D in each drawing is a cross-sectional view taken along dashed dotted line B1-B2 in A of each drawing. E in each drawing is a cross-sectional view taken along dashed dotted line B3-B4 in A of each drawing.

[0067] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. Examples of CVD methods include plasma enhanced chemical vapor deposition (PECVD), thermal CVD, and photo CVD. Thermal CVD methods include metal organic chemical vapor deposition (MOCVD) and metal chemical vapor deposition (metal CVD).

[0068] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, etc.

[0069] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0070] For the etching, a dry etching method, a wet etching method, or the like can be used.

[0071] First, the insulating layer 10 is formed on a substrate (not shown). For example, an inorganic insulating film such as silicon oxide, silicon nitride, or silicon oxynitride can be used as the insulating layer 10. For example, sputtering, CVD, or ALD can be used to form the insulating layer 10. If the surface on which the insulating layer 10 is to be formed is not flat, a planarization process may be performed after the insulating layer 10 is formed so that the upper surface of the insulating layer 10 is flat.

[0072] Subsequently, films to become the conductive layers 11 (conductive layers 11_1 and 11_2) are deposited on the insulating layer 10. The films to become the conductive layers 11 are processed to form the conductive layers 11. The conductive layers 11 can be deposited by, for example, a metal CVD method, an MOCVD method, a sputtering method, an ALD method, or the like. The conductive layers 11 can be formed using, for example, metals such as tungsten and molybdenum, nitrides such as titanium nitride and tantalum nitride, or conductive oxides such as In—Sn oxide. The conductive layers 11 preferably have a stacked structure. For example, it is preferable to use tungsten for the conductive layer 11_1 and In—Sn oxide for the conductive layer 11_2 deposited on the conductive layer 11_1. Anisotropic dry etching is preferably used to process the films to become the conductive layers 11. 3B and 3D show an example in which the side surface of the conductive layer 11 is perpendicular to the surface on which the conductive layer 11 is formed, but depending on the etching conditions, the side surface of the conductive layer 11 may have a tapered shape inclined relative to the surface on which the conductive layer 11 is formed.

[0073] Subsequently, the insulating layer 12 is formed on the conductive layer 11. The insulating layer 12 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, silicon nitride can be used for the insulating layer 12. For the insulating layer 12, it is preferable to use an insulating film having the function of capturing or fixing hydrogen, which will be described later. It is also preferable to use an insulating film having a barrier property against hydrogen, which will be described later.

[0074] 3B to 3E, it is preferable to perform a planarization process on the insulating layer 12. For example, a chemical mechanical polishing (CMP) method can be used as the planarization process.

[0075] Subsequently, insulating layers 13 and 14 are sequentially formed on the insulating layer 12. The insulating layers 13 and 14 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used for the insulating layer 13. For the insulating layer 13, a film formed by a sputtering method in which the film formation gas does not contain hydrogen is preferably used. Furthermore, it is preferable to perform a heat treatment after the formation of the insulating layer 13 to reduce hydrogen in the insulating layer 13. For example, silicon nitride can be used for the insulating layer 14. For the insulating layer 14, it is preferable to use an insulating film having a function of capturing or fixing hydrogen, as described below. For the insulating layer 14, it is preferable to use an insulating film having a barrier property against hydrogen.

[0076] The apparatus used for the heat treatment is not particularly limited, and may be an apparatus that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas.

[0077] Subsequently, films to be the conductive layers 15 (conductive layers 15_1 and 15_2) are deposited on the insulating layer 14. The film to be the conductive layer 15 can be deposited using the same film deposition method and material as those for the conductive layer 11. The film to be the conductive layer 15 preferably has a stacked structure. For example, it is preferable to use tungsten for the film to be the conductive layer 15_1 and to use In—Sn oxide for the film to be the conductive layer 15_2 deposited on the film to be the conductive layer 15_1.

[0078] A film that will become the seed layer 16 is provided on the film that will become the conductive layer 15. The film that will become the seed layer 16 can be a film that contains crystals that will serve as nuclei for crystallizing the semiconductor layer 17f that will be formed later. Therefore, the seed layer 16 can be called a seed crystal layer. There are no particular limitations on the method for forming the seed layer 16. For example, the seed layer 16 can be formed using a sputtering method, an ALD method, or the like. It is preferable to use a metal oxide or an oxide semiconductor for the seed layer 16. More preferably, it is preferable to use an In-Ga-Zn oxide for the seed layer 16.

[0079] The seed layer 16 preferably has a thin film thickness. For example, the film thickness of the seed layer 16 is preferably thinner than the film thickness of the semiconductor layer 17. Specifically, the seed layer 16 preferably has a region with a film thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a film thickness of 0.5 nm or more and less than 2 nm. The seed layer 16 may be in the form of a film or particles.

[0080] The conductive layer 15 and the seed layer 16 are formed by processing the film that will become the conductive layer 15 and the film that will become the seed layer 16 ( FIGS. 3A to 3E ). Anisotropic dry etching is preferably used to process the film that will become the conductive layer 15. Although FIGS. 3B , 3D , and 3E show examples in which the side surfaces of the conductive layer 15 and the seed layer 16 are perpendicular to the surface on which they are formed, depending on the etching conditions, the side surfaces of the conductive layer 15 and the seed layer 16 may have a tapered shape that is inclined relative to the surface on which they are formed.

[0081] Next, the groove 200 is formed. A resist mask is formed in areas other than the area that will become the groove 200, and the seed layer 16, the conductive layer 15, the insulating layer 14, the insulating layer 13, part of the insulating layer 12, and part of the conductive layer 11 in the areas where the resist mask is not formed are removed by etching ( FIGS. 4A to 4E ). Anisotropic dry etching is preferably used for this etching process. After the etching process, the resist mask is removed. Along with the formation of the groove 200, the seed layer 16a, the seed layer 16b, the conductive layer 15a (conductive layer 15a_1 and conductive layer 15a_2), and the conductive layer 15b (conductive layer 15b_1 and conductive layer 15b_2) are formed. It is preferable that the area of ​​the conductive layer 11 that overlaps with the groove 200 be recessed. It is also preferable that the insulating layer 12 that overlaps with the groove 200 in the area where the conductive layer 11 is not present be recessed.

[0082] Next, the semiconductor layer 17f is formed (FIGS. 5A to 5E). The semiconductor layer 17f is formed so as to cover at least a portion of the conductive layer 15, the seed layer 16, and the groove 200. Within the groove 200, the semiconductor layer 17f has a region in contact with the side surface of the insulating layer 14, a region in contact with the side surface of the insulating layer 13, a region in contact with the side surface of the insulating layer 12, and a region in contact with the recess of the conductive layer 11. The semiconductor layer 17f can be formed by a film formation method such as an ALD method or a sputtering method. The semiconductor layer 17f is preferably made of, for example, indium oxide. The semiconductor layer 17f may also have a stacked structure. For example, when the semiconductor layer 17f has a two-layer stacked structure, the first layer may be made of indium oxide on the side in contact with the seed layer 16, and the second layer may be made of In—Ga—Zn oxide on top of the first layer.

[0083] The thickness of the semiconductor layer 17 is preferably 1 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. It is sufficient that at least a portion of the semiconductor layer 17 has a region with the above-described thickness. For example, it is sufficient that the channel formation region of the semiconductor layer 17 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 17 within the above range, the crystallinity of the semiconductor layer 17 can be improved. By improving the crystallinity of the semiconductor layer 17, the semiconductor layer 17 can have crystal grains.

[0084] After the semiconductor layer 17f is formed, it is preferable to perform heat treatment. The temperature of the heat treatment is preferably 100° C. or higher and 950° C. or lower, more preferably 250° C. or higher and 650° C. or lower, and even more preferably 350° C. or higher and 450° C. or lower. For details of the heat treatment, see the above description.

[0085] Furthermore, it is preferable that the gas used in the heat treatment is highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 17f as much as possible. Alternatively, it is possible to reduce impurities such as carbon and hydrogen from the semiconductor layer 17f and to achieve high purity.

[0086] After the semiconductor layer 17f is formed, microwave-excited plasma treatment (also simply referred to as microwave plasma treatment) may be performed. By performing the microwave-excited plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 17f can be reduced.

[0087] The microwave-excited plasma treatment refers to a treatment using a device having a power source that generates high-density plasma using microwaves, and can also be called a microwave-excited high-density plasma treatment.

[0088] In the microwave-excited plasma treatment, it is preferable to use, for example, a plasma treatment apparatus having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave-excited plasma treatment apparatus is preferably 1000 W to 10,000 W, and preferably 2000 W to 5,000 W. Furthermore, the microwave-excited plasma treatment apparatus may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the film.

[0089] The microwave-excited plasma treatment can be performed using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is greater than 0% and less than 100%. Preferably, it is greater than 0% and less than 50%. More preferably, it is greater than 10% and less than 40%. Even more preferably, it is greater than 10% and less than 30%. Typically, it is 25%. When performing processing using oxygen (O) radicals, it is preferable to increase the oxygen flow rate ratio. On the other hand, if the oxygen flow rate ratio is large, there is a possibility that the risk of particle generation or the risk of damage to the processing chamber increases, or both. Therefore, the oxygen flow rate needs to be set within an appropriate range.

[0090] The seed layer 16 has crystals. The seed layer 16 functions as a seed or nucleus when a process for increasing the crystallinity of the semiconductor layer 17f is performed. In other words, the seed layer 16 functions as a seed or nucleus when the semiconductor layer 17f grows crystals. In this specification and the like, the seed layer 16 or the crystals contained in the seed layer 16 can be referred to as a seed, a seed crystal, or a crystal nucleus.

[0091] The seed layer 16 may be made of a conductive oxide or an oxide semiconductor. Specifically, it is preferable to use an In—Ga—Zn oxide as the seed layer 16. In this case, the seed layer 16 contains indium, gallium, zinc, and oxygen. More specifically, it is preferable to use a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto. Metal oxides of these compositions are suitable for the seed layer 16 because they easily form a layered structure. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0092] In—Ga—Zn oxide, In—Sn—Zn oxide, etc., tend to have a c-axis aligned crystal (CAAC) structure. When an oxide having a CAAC structure is used for the seed layer 16, the c-axis of the crystal nuclei is perpendicular or approximately perpendicular to the surface of the seed layer 16 or the surface on which it is formed. By using a metal oxide that tends to have a CAAC structure for the seed layer 16, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

[0093] Indium oxide crystals tend to have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 17f, the seed layer 16 preferably has, for example, a hexagonal or trigonal crystal structure. In this case, the seed layer 16 has crystals with a <001> crystal orientation relative to the surface or surface on which the seed layer 16 is to be formed, so that the <111> crystal orientation of the semiconductor layer 17f in contact with the surface of the seed layer 16 can be parallel or approximately parallel to the <001> crystal orientation relative to the surface or surface on which the seed layer 16 is to be formed. When the crystals of the seed layer 16 have a <001> crystal orientation relative to the surface or surface on which the seed layer 16 is to be formed, the c-axis of the crystals is perpendicular or approximately perpendicular to the surface or surface on which the seed layer 16 is to be formed. When the crystals of the hexagonal or trigonal crystal structure are layered crystals, the structure can be interpreted as a semiconductor layer 17f having a cubic crystal structure formed on the seed layer 16 having a layered crystal structure. As such, it can also be considered as a layered structure fabricated using heteroepitaxial growth techniques or heteroepitaxial-like techniques.

[0094] The indium oxide used in the semiconductor layer 17 may be mixed with Ga, Zn, Sn, W, Ge, Ti, Mg, Cd, Ca, or the like to such an extent that the indium oxide crystals can maintain a cubic crystal structure.

[0095] Here, the crystal structures of metal oxides are shown in Figures 10A to 10E. Figure 10A is a diagram of the crystal structure of In-Ga-Zn oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] viewed from a direction perpendicular to the c-axis. Figure 10B is a diagram of the plane indicated by the dashed line in Figure 10A viewed from the c-axis direction. Figure 10C is a diagram of the plane indicated by the dashed line in Figure 10A viewed from the c-axis direction. Figure 10D is a diagram of the plane indicated by the dashed line in Figure 10A viewed from the c-axis direction. Mx in Figures 10A, 10C, and 10D represents Ga atoms or Zn atoms. Note that in Figure 10A, the plane indicated by the dashed line, the plane indicated by the dashed line, and the plane indicated by the dashed line can be collectively referred to as the c-plane. Figure 10E is a diagram of the crystal structure of indium oxide viewed from a direction perpendicular to the (111) plane.

[0096] The distance between metal atoms on the c-plane (arrows shown in each of FIGS. 10B to 10D) is said to be 0.330 nm. The In-In distances on the (111) plane (arrows shown in FIG. 10E) are said to be 0.334 nm, 0.335 nm, and 0.385 nm. This shows that the arrangement of metal atoms on the c-plane of the CAAC structure and the (111) plane of indium oxide are similar. Therefore, a metal oxide that easily has a CAAC structure can be suitably used as the seed layer 16.

[0097] 11A shows a cross-sectional view of the upper end of the groove 200 in FIG. 5B and its vicinity, including the insulating layer 13, the insulating layer 14, the conductive layer 15a_1, the conductive layer 15a_2, the seed layer 16a, and the semiconductor layer 17f. The semiconductor layer 17f has a portion in contact with the side surface of the conductive layer 15a_1. The semiconductor layer 17f also has a portion in contact with the side surface of the conductive layer 15a_2. When a metal oxide that easily has a CAAC structure is used for the seed layer 16, the crystal orientation <111> in the semiconductor layer 17f is perpendicular or approximately perpendicular to the surface of the seed layer 16 or the surface on which it is formed. Furthermore, the crystal orientation <111> in the portion of the semiconductor layer 17f along the side surface of the groove 200 is parallel or approximately parallel to the side surface of the groove 200. In other words, the crystal orientation <001> of the seed layer 16 having a hexagonal or trigonal structure and the crystal orientation <111> of the semiconductor layer 17f located on the side surface of the groove 200 can be said to be parallel or approximately parallel. Alternatively, when a metal oxide that easily has a CAAC structure is used for the seed layer 16, the C-axis of the metal oxide that easily has a CAAC structure and the crystal orientation <111> of the semiconductor layer 17f located on the side surface of the groove 200 can be said to be parallel or approximately parallel. Therefore, crystal planes other than the {111} plane are likely to appear on the surface of the semiconductor layer 17f in the portion along the side surface of the groove 200.

[0098] 11B shows a cross-sectional view including the insulating layer 13, the insulating layer 14, and the semiconductor layer 17f at and near the upper end of the groove 200 in FIG. 5C. The semiconductor layer 17f has a crystal orientation <111> that is perpendicular or approximately perpendicular to the surface of the insulating layer 14 or the surface on which it is formed. At least the semiconductor layer 17f along the side surface of the groove 200 has a crystal orientation <111> that is parallel or approximately parallel to the side surface of the groove 200. In other words, the crystal orientation <001> of the seed layer 16 shown in FIG. 11A and the crystal orientation <111> of the semiconductor layer 17f located on the side surface of the groove 200 are parallel or approximately parallel to each other. 11A is parallel or substantially parallel to the crystal orientation <111> of the semiconductor layer 17f located on the side surface of the groove 200. Therefore, crystal planes other than the {111} plane tend to appear on the surface of the semiconductor layer 17f in the portion along the side surface of the groove 200.

[0099] 11A, the upper corners of the seed layer 16a on the groove 200 side may be curved. As shown in FIG. 11B, the upper corners of the insulating layer 14 on the groove 200 side may be curved.

[0100] A metal oxide having a cubic crystal structure can also be used for the seed layer 16. If the crystals of the seed layer 16 and the crystals of the semiconductor layer 17f both have a cubic crystal structure and have a low lattice mismatch, the semiconductor layer 17f can grow epitaxially using the seed layer 16 as a nucleus, thereby improving the crystallinity of the semiconductor layer 17f.

[0101] For indium oxide used for the semiconductor layer 17f, the description in Embodiment 2 can be referred to.

[0102] The semiconductor layer 17f is preferably made of indium oxide. In this case, the higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in indium oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 17, the transistor can have a large on-state current and high frequency characteristics.

[0103] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films and polycrystalline films. In polycrystalline films, crystal grain boundaries are observed.

[0104] The crystallinity of the semiconductor layer 17 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0105] The crystal grains can be confirmed, for example, in a high-resolution transmission electron microscope (TEM) image. Furthermore, the crystal grain boundaries can sometimes be confirmed, for example, in a high-resolution TEM image. That is, the crystal grains and the crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring the TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0106] The indium oxide film is preferably a single-crystal film. A single-crystal film does not have grain boundaries, so that carrier scattering at the grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility and high reliability.

[0107] The indium oxide film may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, a structure in which no crystal grain boundaries are observed in the channel formation region can be achieved. Even in such a structure, the same effects as in a structure in which the indium oxide film is a single crystal film can be achieved.

[0108] Two or more crystal grains may also be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first crystal grain and the second crystal grain. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first crystal grain and the second crystal grain can be suppressed. Therefore, even in this configuration, the same effect as in the configuration in which the indium oxide film is a single crystal film can be achieved. Note that the coincidence or substantially coincidence of the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain may be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, it can be confirmed that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains.

[0109] In this specification, the term "grain boundary" refers to, for example, a grain boundary formed at the boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a grain boundary formed at the boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0110] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0111] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered a single-crystal film. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0112] The extension length of the grain boundaries in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less. By having the indium oxide film with the extension length of the grain boundaries in the above range in the semiconductor layer 17, a configuration in which no crystal grain boundaries are observed or the grain boundary components are small can be realized. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundaries is 90 nm square.

[0113] Subsequently, a mask 18 is formed on the semiconductor layer 17f in the region where the semiconductor layer 17 is to be formed (FIGS. 5A to 5E).

[0114] Subsequently, the semiconductor layer 17f is processed to form the semiconductor layer 17. The region of the semiconductor layer 17f that does not overlap with the mask 18 is removed by etching to form the semiconductor layer 17 (FIGS. 6A to 7E).

[0115] The etching process for the semiconductor layer 17f preferably includes at least a first step and a second step. The first step is preferably anisotropic etching, and the second step is preferably isotropic etching. The order of the first and second steps may be reversed.

[0116] 6A to 6E, in the first step, the semiconductor layer 17f on the insulating layer 14 is etched by anisotropic etching. As a result, for example, the semiconductor layer 17f remains on the side surface of the groove 200 even in the region not overlapping with the mask 18 (FIG. 6C).

[0117] Next, in the second step, the semiconductor layer 17f on the side surfaces of the grooves 200 in the regions not overlapping with the mask 18 is removed by isotropic etching (FIG. 7C).

[0118] For anisotropic etching, dry etching is preferably used. In dry etching, anisotropy can be enhanced by increasing the bias power, for example. The bias voltage is preferably 10 W or more and 1000 W or less, and more preferably 50 W or more and 500 W or less.

[0119] As the etching gas for the dry etching process, the following gases can be used alone or in combination of two or more gases.

[0120] The gas used for dry etching may be, for example, a gas containing halogen. For example, an etching gas containing at least one of chlorine and bromine may be used as the gas containing halogen. For example, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or Br ３ The gases may be used alone or in combination of two or more.

[0121] The etching gas for the dry etching process may contain a gas containing fluorine, such as a fluorocarbon gas, a hydrofluorocarbon gas, or SF ６ Fluorocarbon gases include C ｘ F ｙ A gas represented by (y≦2x+2) can be used. An example of a fluorocarbon gas that satisfies y=2x+2 is CF. ４ , C ２ F ６ , C ３ F ８ , C ４ F １０ , C ５ F １２ Examples of fluorocarbon gases that satisfy the condition y<2x+2 include saturated fluorocarbon compounds such as C ２ F ４ , C ２ F２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ Examples of hydrofluorocarbon gases include unsaturated fluorocarbon compounds such as CHF ３ Gas, CH ２ F ２ In addition, the gas containing fluorine may include noble gases, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ At least one of a fluorine-containing gas, a fluorine-containing gas, a hydrogen gas, etc. may be added.

[0122] Furthermore, a gas containing carbon, such as a hydrocarbon, can be used as the etching gas. For example, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ ) can be used.

[0123] For example, a noble gas can be added to the etching gas. Examples of noble gases include helium, neon, argon, krypton, xenon, and radon. In addition, one or both of nitrogen gas and hydrogen gas may be added to the etching gas. Furthermore, when a gas containing halogen is used as the etching gas, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ At least one of a nitrogen gas, a hydrogen gas, a hydrocarbon gas, etc. may be added as appropriate.

[0124] Furthermore, as the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0125] In the dry etching process of isotropic etching, the isotropy can be increased, for example, by reducing the bias power. In the dry etching process of isotropic etching, the isotropy can be increased, for example, by increasing the pressure of the etching gas. By reducing the bias power, ions generated from the plasma are less likely to be attracted in a direction perpendicular to the substrate, thereby increasing the isotropy. Increasing the pressure of the etching gas shortens the mean free path of molecules in the atmosphere. Therefore, collisions between molecules are more likely to occur, thereby increasing the isotropy. The bias power during isotropic etching is preferably less than 10 W, and more preferably 0 W.

[0126] Here, if the isotropy is increased in the dry etching process, the ions contained in the etching gas may not be sufficiently accelerated. As a result, the etching process may take a long time. If the etching process takes a long time, for example, the mask 18 may shrink, resulting in a shrinkage of the semiconductor layer 17. Therefore, it is preferable to keep the etching process time short.

[0127] When anisotropic etching and isotropic etching are performed in dry etching, it is preferable to perform them using the same equipment or in the same chamber. By performing the processes in the same equipment or chamber, transportation time can be reduced and productivity can be improved.

[0128] For the indium oxide used in the semiconductor layer 17, the description of the examples can be referred to. As shown in the examples, the etching rate of crystalline indium oxide varies depending on the crystal orientation. Specifically, when crystalline indium oxide is etched using oxalic acid, the etching rate of the {111} plane is slower than the etching rate of other crystal planes. It is preferable to etch the semiconductor layer 17f by utilizing this crystal anisotropy.

[0129] Therefore, by making the crystal orientation <111> of the semiconductor layer 17 formed on the side surface of the groove 200 parallel or approximately parallel to the side surface of the groove 200, the surface to be treated by isotropic etching of the semiconductor layer 17 formed on the side surface of the groove 200 can be made to be a plane other than the {111} plane. Therefore, the surface can be treated by etching for a shorter time than when the surface is the {111} plane.

[0130] Although an example in which dry etching is used for both anisotropic etching and isotropic etching in the etching process of the semiconductor layer 17f has been shown here, wet etching may also be used for the isotropic etching. For example, oxalic acid or a ferric chloride solution can be used as a wet etching chemical. Alternatively, a hydrohalic acid such as HCl, HBr, or HI can be used. Alternatively, hydrochloric acid containing 1H ions can be used. ２ or FeCl ３Alternatively, a mixed solution of nitric acid and hydrochloric acid can be used. Also, an aqueous solution obtained by diluting the above solution with pure water or the like can be used.

[0131] Next, the mask 18 is removed. The mask 18 may be removed by, for example, dry etching or wet etching (FIGS. 8A to 8E).

[0132] Subsequently, an insulating layer 19 is formed so as to cover the semiconductor layer 17 (FIGS. 9A to 9E). The insulating layer 19 is preferably formed using an ALD method, which has better step coverage than other film formation methods.

[0133] Next, a film that will become the conductive layer 20 is formed on the insulating layer 19. The film that will become the conductive layer 20 is preferably formed using, for example, a metal CVD method, an MOCVD method, an ALD method, a sputtering method, or the like. The conductive layer 20 can be formed in the groove portion 200, for example, by processing the entire surface of the film that will become the conductive layer 20 by anisotropic etching without forming a mask. The conductive layer 20 is formed to extend, for example, in the Y direction, similar to the groove portion 200.

[0134] Subsequently, the insulating layer 21 is formed over the insulating layer 19 and the conductive layer 20. The insulating layer 21 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For the insulating layer 21, it is preferable to use an insulating film having a function of capturing or fixing hydrogen, which will be described later. It is also preferable to use an insulating film having a barrier property against hydrogen, which will be described later.

[0135] Subsequently, the insulating layer 22 is formed on the insulating layer 21. The insulating layer 22 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. After the insulating layer 22 is formed, the insulating layer 22 is planarized by a planarization process. For example, a CMP method can be used as the planarization process.

[0136] Next, the conductive layer 23a and the conductive layer 23b are formed. First, openings are formed in the insulating layer 22, the insulating layer 21, and the insulating layer 19. After the openings are formed, a conductive material is filled by a metal CVD method or the like, and CMP is performed to form the conductive layer 23a and the conductive layer 23b. Note that openings may also be formed in the semiconductor layer 17, the seed layer 16, the conductive layer 15a_2, and the conductive layer 15b_2. For example, when a conductive oxide is used for the conductive layer 15a_2 (conductive layer 15b_2) and a material having a lower resistance than that is used for the conductive layer 15a_1 (conductive layer 15b_1), it is preferable to form openings in the conductive layer 15a_2 (conductive layer 15b_2) so that the conductive layer 23a (conductive layer 23b) is in contact with the conductive layer 15a_1 (conductive layer 15b_1). With such a structure, the conductive layers 23a and 23b can form good contact with the conductive layers 15a_1 and 15b_1.

[0137] Next, a film that will become the conductive layer 24 is formed and processed using photolithography to form the conductive layer 24.

[0138] 1A to 1D can be manufactured by the above steps. By using such a manufacturing method, a transistor that can be miniaturized or a transistor that occupies a small area can be provided.

[0139] 1A to 1D show transistors manufactured using a method in which the entire surface of a film that becomes the conductive layer 20 is processed by anisotropic etching without forming a mask, thereby forming the conductive layer 20 in the groove 200, but the structures shown in FIGS. 12A to 12E may also be used. The transistor 100B shown in FIG. 12 can be manufactured using a method in which, after forming the film that becomes the conductive layer 20, a mask is formed and the film that becomes the conductive layer 20 is etched to form the conductive layer 20.

[0140] In the semiconductor device variation 1, the conductive layer 20 is formed using a mask separate from the layout pattern of the groove 200, so that the degree of freedom in the layout design of the conductive layer 20 can be increased.

[0141] [Variation 2 of Semiconductor Device] In the example of the manufacturing method of this embodiment, as shown in FIGS. 3A to 4E , a film that becomes the seed layer 16 is deposited on a film that becomes the conductive layer 15, etched using the same mask as the conductive layer 15, and then a groove 200 is formed to form the seed layer 16a and the seed layer 16b. However, the seed layer 16 may be formed by another method. For example, as shown in FIGS. 13A to 13E , a transistor 100C may be formed by etching the film that becomes the conductive layer 15 without depositing a film that becomes the seed layer 16 on the film that becomes the conductive layer 15, and then forming the groove 200. After forming the groove 200, the seed layer 16 may be formed by a sputtering method. Because film formation by sputtering is highly anisotropic, the seed layer 16 is not deposited on the side surfaces of the groove 200, as shown in FIGS. 13A to 13E , and the seed layer 16 can be formed. The film that becomes the seed layer 16 is etched simultaneously with the semiconductor layer 17 to become the seed layer 16a, the seed layer 16b, and the seed layer 16c. Note that the seed layer 16c may not be formed if the width of the groove portion 200 is narrow.

[0142] In the semiconductor device variation 2, after the film that will become the seed layer 16 is formed, the semiconductor layer 17f can be formed without being exposed to the mask 18 and the process of removing the mask 18. Therefore, the semiconductor layer 17f can be formed while the surface of the film that will become the seed layer 16 remains in a better state. Therefore, the crystallization of the semiconductor layer 17 can be further promoted.

[0143] The seed layer 16 and the semiconductor layer 17 can be processed by the method described in the above-mentioned [Example of manufacturing method].

[0144] [Variation 3 of Semiconductor Device] Figures 14A to 14D are diagrams showing an example of a semiconductor device. The semiconductor device shown in Figure 14A has a transistor 100D. Figure 14B is a cross-sectional view taken along dash-dotted line A1-A2 in Figure 14A. Figure 14C is a cross-sectional view taken along dash-dotted line A3-A4 in Figure 14A. Figure 14D is a horizontal cross-sectional view taken along dash-dotted line B1-B2 in Figure 14A. The configurations shown in Figures 14A to 14D show an example in which a transistor is provided using one of a pair of opposing side surfaces of groove portion 200.

[0145] The transistor 100D includes at least a conductive layer 11a (conductive layer 11a_1, conductive layer 11a_2), a conductive layer 15a (conductive layer 15a_1, conductive layer 15a_2), a semiconductor layer 17, an insulating layer 19, and a conductive layer 20. A part of the conductive layer 11 functions as a source electrode or a drain electrode. A part of the conductive layer 15 functions as a source electrode or a drain electrode. A part of the insulating layer 19 functions as a gate insulating film. A part of the conductive layer 20 functions as a gate electrode.

[0146] The insulating layer 10 is provided on a substrate (not shown). The conductive layers 11 (conductive layer 11a_1, conductive layer 11a_2, conductive layer 11b_1, conductive layer 11b_2) are provided on the insulating layer 10. The conductive layers 11 may extend in the X direction, the Y direction, or both the X and Y directions. The conductive layers 11 preferably have a two-layer structure of conductive layers 11_1 and 11_2, but may also be formed as a single layer or a stack of three or more layers.

[0147] The insulating layer 12 is provided on the conductive layer 11. It is also desirable that the upper surface of the insulating layer 12 is flat. The insulating layer 12 can be formed as a single layer or a laminate of two or more layers. For example, in the case of two layers, it is preferable to use different film formation methods. Specifically, the first layer may be formed of silicon nitride or silicon nitride oxide by the ALD method, and the second layer may be formed of silicon nitride or silicon nitride oxide by the sputtering method or the CVD method. The insulating layer 13 is provided on the insulating layer 12. The insulating layer 14 is provided on the insulating layer 13.

[0148] The conductive layers 15 (conductive layer 15a_1, conductive layer 15a_2, conductive layer 15b_1, and conductive layer 15b_2) are provided over the insulating layer 14. The conductive layer 15 preferably has a two-layer structure of the conductive layer 15_1 and the conductive layer 15_2, but can also be formed as a single layer or a stack of three or more layers.

[0149] The insulating layer 401 is provided on the insulating layer 14. The upper surface of the insulating layer 401 is provided so as to be flush or approximately flush with the upper surface of the conductive layer 15. For example, the insulating layer 401 may be formed by forming the conductive layer 15, followed by processing by the CMP method until the upper surface of the conductive layer 15 is exposed.

[0150] Groove portion 200 is located between conductive layer 15a and conductive layer 15b, which are spaced apart from each other, in a plan view. Groove portion 200 is provided in at least insulating layer 14, insulating layer 13, and insulating layer 12, and reaches conductive layer 11. The portion of conductive layer 11 that overlaps with groove portion 200 has a recess.

[0151] After the groove portion 200 is formed, a film that will become the seed layer 16 and a film that will become the semiconductor layer 17 are deposited. Then, the film that will become the seed layer 16 and the film that will become the semiconductor layer 17 are etched using the same mask, thereby providing the seed layer 16 and the semiconductor layer 17. The seed layer 16 is preferably deposited using a sputtering method. Because film deposition using the sputtering method has high anisotropy, as shown in FIGS. 14A to 14D , the seed layer 16 can be formed without being deposited on the side surfaces of the groove portion 200. Note that the seed layer 16c (seed layer 16c_1, seed layer 16c_2) may not be deposited if the width of the groove portion 200 is narrow.

[0152] The seed layer 16 and the semiconductor layer 17f can be processed using the methods described in the above-mentioned [Example of Manufacturing Method] and [Modification Example 2 of Semiconductor Device].

[0153] The semiconductor layer 17 has a portion provided on the side surface of the groove portion 200. The insulating layer 19 is provided so as to cover the semiconductor layer 17. The conductive layer 20 has a portion overlapping the semiconductor layer 17 with the insulating layer 19 interposed therebetween. The conductive layer 20 has a portion extending in the Y direction along the side surface of the groove portion 200.

[0154] The insulating layer 402 is provided along the side surface of the conductive layer 20 within the groove 200. It is preferable that the insulating layer 402 covers at least a part of the side surface of the conductive layer 20.

[0155] Insulating layer 403 is provided on insulating layer 19 and conductive layer 20. Insulating layers 404 and 405 have portions located within groove portion 200. Furthermore, the upper surfaces of insulating layer 404 and insulating layer 405 are provided so as to be flush or approximately flush with each other.

[0156] The conductive layer 24 is provided on the insulating layer 404 and is connected to the conductive layer 15 via the conductive layer 23. The conductive layer 24 has a portion that extends in the X direction.

[0157] In the third variation of the semiconductor device, one of the pair of opposing side surfaces of the groove 200 can be used to form a transistor, and the other can be used to provide another transistor, thereby enabling the manufacture of a semiconductor device with a high degree of transistor integration.

[0158] Materials that can be used in the semiconductor device of the present application will be described below. Each layer constituting the semiconductor device of the present application may have a single layer structure or a multilayer structure.

[0159] [Conductive Layer] The conductive layers 11, 15, 20, 23, and 24 can be formed using the following conductors as appropriate. It is preferable to use a low-resistance conductor (a conductor with high conductivity) as a conductor in a semiconductor device. For these conductors, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the metal element. Alternatively, a nitride of the metal element or an alloy containing the metal element as a main component, or an oxide of the metal element or an alloy containing the metal element as a main component, may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferable because they are conductors that are difficult to oxidize or conductors that maintain conductivity even when oxidized. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used. Tantalum, tantalum nitride, etc., are also preferable as conductors because they have barrier properties against hydrogen.

[0160] The conductive layer 11 and the conductive layer 15 are in contact with the seed layer 16 or the semiconductor layer 17. When an oxide semiconductor is used as the semiconductor layer 17, if an easily oxidized metal such as aluminum is used in the portions of the conductive layer 11 and the conductive layer 15 in contact with the seed layer 16 or the semiconductor layer 17, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 15 and the seed layer 16 or the semiconductor layer 17, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material in at least the portions of the conductive layer 11 and the conductive layer 15 in contact with the seed layer 16 or the semiconductor layer 17.

[0161] For the conductive layer 11 and the conductive layer 15 in contact with the semiconductor layer 17, it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0162] Alternatively, conductive oxides such as indium oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, and In—Sn—Si oxide can be used for the conductive layers 11 and 15 in contact with the semiconductor layer 17. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide semiconductors applicable to the semiconductor layer 17 can also be used as conductive layers by increasing the carrier concentration.

[0163] For example, the conductive layer 11 and the conductive layer 15 can each have a single-layer structure of the above-mentioned conductive oxide film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film, or a two-layer structure in which a conductive oxide film is stacked on a tungsten film.

[0164] For example, the conductive layer 20 and the conductive layer 23 can have a two-layer structure in which a tungsten film is stacked on a titanium nitride film.

[0165] For example, the conductive layer 24 may have a single-layer structure of a tungsten film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, or a structure in which a titanium film, a titanium nitride film, and an aluminum film are stacked.

[0166] [Gate insulating film] As transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer.

[0167] The insulating layer 19 functions as a gate insulating film of a transistor. When an oxide semiconductor is used for the semiconductor layer 17, it is preferable to use an oxide insulating film for at least a film of the insulating layer 19 that is in contact with the semiconductor layer 17. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 19. The insulating layer 19 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0168] The insulating layer 19 is preferably formed by stacking insulating films with a high dielectric constant (high-k), and is preferably formed by stacking an insulating film with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material. For example, hafnium oxide, zirconium oxide, and aluminum oxide can be used as the insulating layer 19. Alternatively, an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) can be stacked in this order. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown can be suppressed. Examples of insulating films with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. The above-mentioned ZAZ and ZAZA are also examples of insulating films with a high dielectric constant. Silicon oxide or silicon oxynitride can be used as an insulating film with high dielectric strength. Silicon oxide or silicon oxynitride can also be said to be insulating films that suppress leakage current.

[0169] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 19. Examples of the material exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0170] When the insulating layer 19 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film located on the semiconductor layer 17 side, and an insulating film having a barrier property against hydrogen as the film located on the conductive layer 20 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 20 side to the semiconductor layer 17, thereby realizing a highly reliable transistor.

[0171] When the insulating layer 19 has a three-layer structure, it is preferable to use an insulating film with high dielectric strength or an insulating film that suppresses leakage current as the film located on the semiconductor layer 17 side, an insulating film with barrier properties against hydrogen, an insulating film with barrier properties against oxygen, or an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the film located on the conductive layer 20 side, and an insulating film that has the function of capturing or fixing hydrogen as the film located between them. The film located on the conductive layer 20 side prevents oxygen from diffusing toward the conductive layer 20 side, and suppresses oxidation of the conductive layer 20.

[0172] When the insulating layer 19 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film located closest to the semiconductor layer 17, an insulating film having high dielectric strength or an insulating film that suppresses leakage current as the film next closest to the semiconductor layer 17, an insulating film having the function of capturing or fixing hydrogen as the film closest to the semiconductor layer 17, and an insulating film having a barrier property against hydrogen, an insulating film having a barrier property against oxygen, or an insulating film having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the film located closest to the conductive layer 20. That is, in addition to the above-described three-layer structure, a configuration can be adopted in which an additional film is located on the semiconductor layer 17 side. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 17, oxygen desorption from the semiconductor layer 17 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 17. Aluminum oxide not only has barrier properties against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 17.

[0173] When the insulating layer 19 has a stacked structure, each insulating film is preferably a thin film. For example, the total thickness of the insulating layer 19 is 1 nm to 20 nm, preferably 2 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0174] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 17 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 17 side.

[0175] As another specific example, it is preferable to use a four-layer structure in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 17 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 17 side.

[0176] As another specific example, it is preferable to use a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in this order from the semiconductor layer 17 side, and to set the thicknesses of these films to 1 nm and 1.5 nm from the semiconductor layer 17 side.

[0177] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that makes the permeability of the corresponding substance low, or a function that suppresses the permeation of the corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0178] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.

[0179] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide). Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0180] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0181] Examples of materials for the insulating film having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, hafnium zirconium oxide, silicon nitride, silicon nitride oxide, and gallium oxide films.

[0182] Examples of materials for insulating films having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0183] [Insulating Layer] The insulating layer 13, the insulating layer 22, the insulating layer 401, the insulating layer 403, and the insulating layer 405 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 17 can be suppressed, and the electrical characteristics of the semiconductor device can be stabilized.

[0184] The insulating layer 13, the insulating layer 22, the insulating layer 401, the insulating layer 403, and the insulating layer 405 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. As the material with a low dielectric constant, for example, one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies are preferable. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0185] Since the insulating layer 13, the insulating layer 22, the insulating layer 401, the insulating layer 403, and the insulating layer 405 function as interlayer insulating layers, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 13 and the insulating layer 22 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0186] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For the insulating layers 10, 12, 14, 21, 402, and 404 included in the semiconductor device, an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has a function of capturing or fixing hydrogen, an insulating film that has a barrier property against hydrogen, or an insulating film that also has a barrier property against oxygen is preferably used. The use of these insulating films can suppress the diffusion of hydrogen into the semiconductor layer 17. Furthermore, oxidation of the conductive layer 15 can be suppressed.

[0187] The insulating layer 10, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 10 can be made of any of the insulating materials that can be used for the insulating layer 10, the insulating layer 12, the insulating layer 14, the insulating layer 21, the insulating layer 402, and the insulating layer 404.

[0188] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0189] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0190] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0191] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0192] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 15A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 15B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0193] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 15B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 15A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 15A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 15A.

[0194] 15A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0195] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0196] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0197] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0198] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 15A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0199] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0200] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 15B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 15A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0201] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0202] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0203] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0204] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0205] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0206] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0207] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0208] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0209] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0210] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0211] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0212] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0213]

[0214] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0215] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0216] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0217] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0218] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0219] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 15C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0220] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0221] Furthermore, as shown in FIG. 15C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the membrane and is released as water molecules.

[0222] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0223] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0224]

[0225] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0226] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0227] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0228] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0229] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0230] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0231] 16A to 17 . The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor. The transistor described in Embodiment 1 can be used as the transistor.

[0232] The configuration of a semiconductor device having a memory cell 600 will be described with reference to Figures 16A to 16C. Figure 16A is a plan view of a recording device having a memory cell 600. Figure 16B is a cross-sectional view taken along dashed line A1-A2 in Figure 16A. Figure 16C is a cross-sectional view taken along dashed line B1-B2 in Figure 16A.

[0233] 16A to 16C includes a memory cell 600 on a substrate (not shown). The memory cell 600 includes at least a capacitor 300 and a transistor 100A.

[0234] 16A to 16C includes an insulating layer 601, an insulating layer 602, an insulating layer 603, a conductive layer 604_1, and a conductive layer 604_2 over a substrate (not shown), and a capacitor 300 over the conductive layer 604. The capacitor 300 includes a conductive layer 608, an insulating layer 609, and a conductive layer 610 (conductive layer 610_1 and conductive layer 610_2). The insulating layer 609 is provided between the conductive layer 608 and the conductive layer 610. At least a part of the conductive layer 608 functions as one of a pair of electrodes of the capacitor. At least a part of the conductive layer 610 functions as the other of the pair of electrodes of the capacitor. At least a part of the insulating layer 609 functions as a dielectric of the capacitor.

[0235] The insulating layer 605, the insulating layer 606, and the insulating layer 607 are provided over the insulating layer 603. An opening 690 is provided in the insulating layer 605, the insulating layer 606, and the insulating layer 607 so as to reach the conductive layer 604. The conductive layer 608 has a portion provided along the inside of the opening 690 and a portion in contact with the conductive layer 604 at the bottom of the opening. Parts of the conductive layer 608, the insulating layer 609, and the conductive layer 610 are provided so as to be located inside the opening 690. The conductive layer 610_1 is preferably provided so as to fill the opening 690.

[0236] At least a portion of the capacitor 300 can be provided inside the opening 690, so that the capacitance per unit area in plan view can be increased.

[0237] By providing the capacitor 300 and the transistor 100A stacked one above the other, the area occupied by the memory cell 600 in a plan view can be reduced, and the degree of integration of the memory cell can be improved.

[0238] Furthermore, by configuring the capacitor 300 and the transistor 100A to be stacked vertically, one conductive layer of a pair of electrodes of the capacitor can also serve as one conductive layer of the source electrode or drain electrode of the transistor, thereby simplifying the manufacturing process and improving productivity and yield.

[0239] The insulating layers 601, 602, 603, 605, 606, and 607 can be formed using the materials described in the [Gate insulating film] and [Insulating layer] sections of Embodiment 1. In particular, the insulating layers 602, 605, and 607 are preferably formed using an insulating film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film having a function of capturing or fixing hydrogen, an insulating film having a barrier property against hydrogen, or an insulating layer having a barrier property against oxygen. Use of these insulating layers can suppress diffusion of hydrogen into the semiconductor layer 17 of the transistor 100A disposed over the capacitor 300. Furthermore, the transistor 100A disposed over the capacitor 300 can have high reliability.

[0240] The conductive layers 604, 608, and 610 can be formed as a single layer or a stacked layer using the materials described in [Conductive Layer] in Embodiment 1. For example, the conductive layer 604 can have a two-layer structure in which titanium nitride is used for the conductive layer 604_1 and tungsten is used for the conductive layer 604_2. Since a conductive material with high conductivity, such as tungsten, can be used, the wiring resistance of the conductive layer 604 can be reduced. Furthermore, the conductive layer 608 is preferably formed using a conductive material that is not easily oxidized. For example, the conductive layer 608 is preferably formed using a conductive oxide, such as titanium nitride or In—Sn oxide.

[0241] The insulating layer 609 can be formed as a single layer or a stacked layer using any of the materials described in the [Gate insulating film] section of Embodiment 1. A high-k material having a high relative dielectric constant is preferably used for the insulating layer 609. For example, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. By using a high-k material for the insulating layer 609, the thickness of the insulating layer 609 can be increased to a degree that can suppress leakage current and the capacitance of the capacitor 300 can be sufficiently ensured.

[0242] A ferroelectric material may be used for the insulating layer 609. For example, a metal oxide containing one or both of hafnium and zirconium can be used as the ferroelectric material. By using a ferroelectric material for the dielectric of the capacitor 300, the memory device described in this embodiment can function as a ferroelectric memory.

[0243] FIG. 17 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0244] 17, a memory cell 600 (a transistor 100A and a capacitor 300) is provided above a Si transistor 1100. The Si transistor 1100 is one of the transistors included in a driver circuit including a sense amplifier.

[0245] The Si transistor 1100 will be described. The Si transistor 1100 is a Fin-type transistor. Fig. 17 shows a schematic cross-sectional view in the channel length direction.

[0246] The Si transistor 1100 is provided on a substrate 1011 and has a conductive layer 1018a that functions as a gate electrode, an insulating layer 1017 that functions as a gate insulating film, a semiconductor region 1013 that functions as a channel formation region, and a low-resistance region 1014 that functions as a source region or a drain region.

[0247] The substrate 1011 may be, for example, a silicon substrate or an SOI (Silicon On Insulator) substrate.

[0248] Next, the semiconductor device shown in FIG. 17 will be described. An element isolation layer 1012, an insulating layer 1015, a dummy gate electrode 1018b, and a dummy gate electrode 1018c are provided on a substrate 1011. The insulating layer 1015 functions as a sidewall. Furthermore, insulating layers 1016, 1019, 1020, 1021, 1023, 1025, 1026, 1027, 1029, and 1030 are provided, and these insulating layers function as interlayer insulating films. Furthermore, the insulating layers 1019, 1021, 1025, 1027, and 1030 function as barrier films. The conductive layers 1022, 1024, and 1028 function as plugs, electrodes, or wirings.

[0249] As shown in FIG. 17, one of the source or drain of the Si transistor 1100 (here, the low resistance region 1014) is connected to the memory cell 600 via a conductive layer (conductive layer 501, conductive layer 502, conductive layer 503, conductive layer 24, conductive layer 23b, etc.).

[0250] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0251] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0252] Fig. 18 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 18 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 18 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0253] For example, the memory device described in Embodiment 3 (such as the memory cell 600) can be applied to the memory cell 950.

[0254] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0255] In the semiconductor device, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0256] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0257] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0258] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0259] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0260] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0261] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0262] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 18, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0263] 19A to 19G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0264] 19A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0265] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0266] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0267] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0268] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0269] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 951 does not need to include the capacitor CA and the wiring CAL, and the first terminal of the transistor M1 may be in an electrically floating state.

[0270] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951.

[0271] Furthermore, like a memory cell 952 shown in FIG. 19B, one wiring BIL can be provided in common for two or more DRAM memory cells.

[0272] 19C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0273] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0274] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0275] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0276] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0277] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 19D . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BIL.

[0278] 19E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 19F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0279] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0280] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0281] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0282] 19G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0283] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0284] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0285] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0286] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0287] Note that at least the transistor M4 is preferably an OS transistor.

[0288] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0289] The transistors described in Embodiment 1 can be used as the transistors M1, M2, and M4 in this embodiment.

[0290] 20A and 20B show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which a memory array is provided, on an arithmetic device 960. The layer 930 is provided with a memory array 920L1, a memory array 920L2, and a memory array 920L3. The arithmetic device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 20B. The arithmetic device 960 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or the like.

[0291] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0292] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0293] Here, the arithmetic unit 960 does not have a cache, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0294] When the cache provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0295] 20B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0296] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0297] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface or may be configured to be connected to the cache interface. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface or may be configured to be connected to it.

[0298] 20A and 20B show an example in which one layer 930 provided with a memory array is provided on the arithmetic device 960, but two or more layers 930 provided with memory arrays may be provided.

[0299] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0300] In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention is suitable for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers because it can provide a transistor with high on-state current and a small area.

[0301] [Electronic Component] FIG. 21A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 21A has a semiconductor device 981 inside a mold 984. FIG. 21A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0302] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0303] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0304] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0305] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0306] 21B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0307] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0308] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0309] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0310] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0311] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0312] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0313] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0314] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 21B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0315] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0316] 22A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 22A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0317] The computer 5620 can have the configuration shown in the perspective view of Fig. 22B, for example. In Fig. 22B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0318] PC card 5621 shown in Figure 22C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that although Figure 22C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced for information on these semiconductor devices.

[0319] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630 , and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630 .

[0320] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0321] Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. The semiconductor device 5627 may be, for example, the electronic component 990.

[0322] The semiconductor device 5628 can be, for example, a memory device. The semiconductor device 5628 can be, for example, the electronic component 990.

[0323] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0324] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0325] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Note that outer space refers to an altitude of 100 km or higher, for example. However, the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0326] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0327] Fig. 22D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 22D shows a planet 6804 in space as an example.

[0328] 22D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0329] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0330] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0331] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0332] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0333] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0334] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0335] Fig. 22E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 22E has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0336] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0337] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0338] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0339] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0340] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0341] In this example, an investigation into the difference in wet etching amount depending on the crystal orientation of a crystalline indium oxide film will be described.

[0342] First, the prepared sample will be described.

[0343] A quartz substrate was prepared, and an indium oxide film was formed on the quartz substrate by sputtering. ２ O ３ The substrate temperature was set to room temperature, and the gas flow rate was Ar=49 sccm, O ２ =0.5sccm, H ２ The film was formed at a flow rate of 2.6 sccm.

[0344] Subsequently, a heat treatment (CDA: Clean Dry Air atmosphere) was carried out at 350° C. for 1 hour, thereby obtaining a polycrystalline indium oxide film.

[0345] As a result of the above, a sample A was obtained in which an indium oxide film having a thickness of 50 nm was formed on a quartz substrate.

[0346] Next, wet etching using oxalic acid was performed using Sample A. Here, the oxalic acid solution temperature was set to 60°C and a dipping process was performed. Sample A, which had been wet etched using oxalic acid, was evaluated using an atomic force microscope (AFM), and it was confirmed that the height difference was approximately 20 nm ( FIG. 23A ). The AFM measurement conditions were as follows: using a Bruker AXS NanoScope V / Dimension Icon, measurement mode: tapping mode, measurement area: 15 μm × 15 μm, number of measurement points: 512 × 512, and probe tip curvature radius: Si: approximately 10 nm.

[0347] Next, the region evaluated by AFM was evaluated by electron backscatter diffraction (EBSD or EBSP: Electron Backscatter Diffraction Pattern) ( FIG. 23B ). EBSD was performed using a JEOL JSM-700F microscope with an accelerating voltage of 15 kV, a sample tilt of 70°, a measurement area of ​​12 μm × 12 μm, and a step of 0.05 μm. Analysis was performed using TSL OIM software version 7.3.

[0348] Regions with less film loss were extracted from the AFM evaluation results and compared with the EBSD evaluation results. This suggests that the crystal grains with less film loss have many crystal faces near the {111} plane (FIG. 23C). Furthermore, regions with more film loss were extracted from the AFM evaluation results and compared with the EBSD evaluation results. This suggests that the crystal grains with more film loss have many crystal faces between the {001} and {101} planes, such as the {310} and {210} planes (FIG. 23D). The cubes shown in FIGS. 23C and 23D are schematic representations of the orientation of cubic crystals.

[0349] This suggests that the etching rate (film loss) of crystalline indium oxide varies depending on the crystal orientation of the surface. Specifically, it suggests that the film surface is more susceptible to etching when the crystal plane of the film surface is between the {001} and {101} planes, such as the {310} and {210} planes, than when the film surface has a crystal plane close to the {111} plane.

[0350] The configuration, structure, or method described in this example can be used in appropriate combination with the configuration, structure, or method described in other embodiments, etc. [Explanation of Symbols] 10: insulating layer, 11: conductive layer, 11_1: conductive layer, 11_2: conductive layer, 11a: conductive layer, 11a_1: conductive layer, 11a_2: conductive layer, 11b_1: conductive layer, 11b_2: conductive layer, 12: insulating layer, 13: insulating layer, 14: insulating layer, 15: conductive layer, 15_1: conductive layer, 15_2: conductive layer, 15a: conductive layer, 15a_1: conductive layer, 15a_2: conductive layer, 15b: conductive layer, 15b_1: conductive layer, 15b_2: conductive layer, 16: seed layer, 16a: seed layer, 16b: seed layer, 16c: seed layer, 16c_1: seed layer, 16 c_2: seed layer, 17: semiconductor layer, 17f: semiconductor layer, 18: mask, 19: insulating layer, 20: conductive layer, 21: insulating layer, 22: insulating layer, 23: conductive layer, 23a: conductive layer, 23b: conductive layer, 24: conductive layer, 100A: transistor, 100B: transistor, 100C: transistor, 100D: transistor, 200: groove, 300: capacitor, 401: insulating layer, 402: insulating layer, 403: insulating layer, 404: insulating layer, 405: insulating layer, 501: conductive layer, 502: conductive layer, 503: conductive layer, 600: memory cell, 60 1: insulating layer, 602: insulating layer, 603: insulating layer, 604: conductive layer, 604_1: conductive layer, 604_2: conductive layer, 605: insulating layer, 606: insulating layer, 607: insulating layer, 608: conductive layer, 609: insulating layer, 610: conductive layer, 610_1: conductive layer, 610_2: conductive layer, 690: opening, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generating circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 960: arithmetic unit, 970A: semiconductor device, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire,988: printed circuit board, 989: mounting substrate, 990: electronic component, 991: interposer, 992: package substrate, 993: electrode, 994: semiconductor device, 1011: substrate, 1012: element isolation layer, 1013: semiconductor region, 1014: low resistance region, 1015: insulating layer, 1016: insulating layer, 1017: insulating layer, 1018a: conductive layer, 1018b: dummy gate electrode, 1018c: dummy gate electrode, 1019: insulating layer, 1020: insulating layer, 1021: insulating layer, 1022: conductive layer, 1023: insulating layer, 1024: conductive layer, 1025: insulating layer, 1026: insulating layer, 1027: insulating layer, 1028: conductive layer, 1029: insulating layer, 1030: insulating layer, 1100: Si Transistor, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

A method for manufacturing a semiconductor device having a crystalline semiconductor layer, comprising: a first step of forming the semiconductor layer on an insulating layer having a groove; a second step of forming a mask on the semiconductor layer; a third step of etching the semiconductor layer on the insulating layer where the mask is not formed; a fourth step of etching the semiconductor layer in the groove portion where the mask is not formed; and a surface of the semiconductor layer on the insulating layer is formed to have a first crystal plane; a surface of the semiconductor layer at the side surface of the trench portion is formed to have a second crystal plane; A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device having a crystalline semiconductor layer, comprising: a first step of forming the semiconductor layer on an insulating layer having a groove; a second step of forming a mask on the semiconductor layer; a third step of etching the semiconductor layer on the insulating layer where the mask is not formed; a fourth step of etching the semiconductor layer in the groove portion where the mask is not formed; and the third step is anisotropic dry etching, and the fourth step is isotropic dry etching; a surface of the semiconductor layer on the insulating layer is formed to have a first crystal plane; a surface of the semiconductor layer at the side surface of the trench portion is formed to have a second crystal plane; A method for manufacturing a semiconductor device.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the third step and the fourth step are performed in the same apparatus.

3. The method for manufacturing a semiconductor device according to claim 2, wherein bias power for the dry etching used in the third step and the fourth step is smaller in the fourth step than in the third step. A method for manufacturing a semiconductor device having a crystalline semiconductor layer, comprising: a first step of forming the semiconductor layer on an insulating layer having a groove; a second step of forming a mask on the semiconductor layer; a third step of etching the semiconductor layer on the insulating layer where the mask is not formed; a fourth step of etching the semiconductor layer in the groove portion where the mask is not formed; and the third step is anisotropic dry etching, and the fourth step is wet etching; a surface of the semiconductor layer on the insulating layer is formed to have a first crystal plane; a surface of the semiconductor layer at the side surface of the trench portion is formed to have a second crystal plane; A method for manufacturing a semiconductor device. 　 In any one of claims 1, 2 and 3, the semiconductor layer has a cubic crystal; the first crystal face is a {111} face, The second crystal plane is other than a {111} crystal plane. A method for manufacturing a semiconductor device.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer contains indium and oxygen. 　 In any one of claims 1, 2 and 3, forming a seed layer prior to the first step; In the first step, the semiconductor layer is formed so as to be in contact with the seed layer; the semiconductor layer has a cubic crystal; the semiconductor layer has a portion in contact with the seed layer, the surface of the semiconductor layer in contact with the seed layer has a {111} crystal plane; A method for manufacturing a semiconductor device.

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