Display device and display system

Abstract

[Problem] To provide a display device and display system having a small circuit scale and low power consumption. [Solution] A display device according to the present disclosure comprises: a pixel array unit in which a plurality of pixels are arranged in a two-dimensional array; a plurality of drive circuits for applying a write voltage corresponding to a gradation value to a plurality of the pixels arranged in the same row; a plurality of load circuits for generating a current corresponding to the gradation value and providing feedback to corresponding drive circuits; a plurality of first switches for connecting corresponding pixels among the plurality of pixels arranged in the same row to corresponding drive circuits; and a plurality of second switches for connecting corresponding pixels among the plurality of pixels arranged in the same row to corresponding load circuits.

Description

Display device and display system

[0001] The present disclosure relates to a display device and a display system.

[0002] In recent years, there has been a demand for smaller circuit scales and lower power consumption in display devices that include a display unit such as an OLED (Organic Light Emitting Diode).

[0003] US Patent Application Publication No. 2021 / 0201735

[0004] In the display device described above, a desired VGS is written to the pixel without Vth correction by performing two-stage amplification using the drive stage, pixel, and load current source.

[0005] However, this display device has one driver circuit for each pixel, which can lead to a large circuit size. Also, this display device has a large number of driver circuits, which can lead to high power consumption.

[0006] In view of these problems, the present disclosure provides a display device and a display system with a small circuit scale and low power consumption.

[0007] A display device according to a first aspect of the present disclosure includes a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, a plurality of drive circuits that apply write voltages corresponding to gradation values ​​to the plurality of pixels arranged in the same row, a plurality of load circuits that generate currents corresponding to the gradation values ​​and feed them back to the corresponding drive circuits, a plurality of first switches that connect corresponding pixels among the plurality of pixels arranged in the same row to corresponding drive circuits, and a plurality of second switches that connect corresponding pixels among the plurality of pixels arranged in the same row to corresponding load circuits. This allows, for example, the display device to reduce the number of drive circuits and the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduced number of drive circuits.

[0008] In addition, in this first aspect, the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing within one horizontal period, and the plurality of pixels arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits. This allows, for example, the display device to reduce the number of drive circuits and the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduction in the number of drive circuits.

[0009] In addition, in this first aspect, the first to nth pixels (n is an integer satisfying 1<n<=9) arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits by time-division driving. As a result, for example, in the display device, by limiting the number of pixels connected to the drive circuits and load circuits to a predetermined number in time-division driving, a sufficient writing time can be ensured.

[0010] In this first aspect, each of the pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on the write voltage, thereby enabling the display device to apply the write voltage to the pixel with high accuracy without Vth correction, for example.

[0011] In this first aspect, the plurality of drive circuits receive a negative reference voltage and output a positive write voltage, thereby enabling the display device to apply a write voltage to the pixel with high accuracy without Vth correction, for example.

[0012] In addition, in this first aspect, each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light emitting element to emit light based on the write voltage, thereby enabling the display device to apply the write voltage to the pixel with high accuracy without Vth correction, for example.

[0013] In the display device according to the first aspect, the plurality of drive circuits receive a reference voltage of positive polarity and output a write voltage of negative polarity. This allows the display device to apply a write voltage to the pixel with high accuracy without Vth correction, for example.

[0014] In the first aspect, the drive circuit is a differential amplifier circuit, which allows the display device to apply a write voltage to the pixel with high precision without Vth correction, for example.

[0015] In this first aspect, the load circuit is a current DAC, which allows the display device to apply a write voltage to the pixel with high precision without Vth correction, for example.

[0016] In this first aspect, each pixel includes a drive transistor that causes a light-emitting element to emit light, the first switch is connected to the gate of the drive transistor, and the second switch is connected to the source or drain of the drive transistor. This allows, for example, the display device to reduce the number of drive circuits and thereby reduce the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduction in the number of drive circuits.

[0017] A display system according to a second aspect of the present disclosure is a display system including a display device, the display device including a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, a plurality of drive circuits that apply write voltages corresponding to gradation values ​​to the plurality of pixels arranged in the same row, a plurality of load circuits that generate currents corresponding to the gradation values ​​and feed them back to the corresponding drive circuits, a plurality of first switches that connect corresponding pixels among the plurality of pixels arranged in the same row to corresponding drive circuits, and a plurality of second switches that connect corresponding pixels among the plurality of pixels arranged in the same row to corresponding load circuits. This allows, for example, the display system to reduce the number of drive circuits and the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduced number of drive circuits.

[0018] In this second aspect, the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing within one horizontal period, and sequentially switch and connect the plurality of pixels arranged in the same row to the corresponding drive circuits and load circuits. This allows, for example, a display system to reduce the number of drive circuits and the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduction in the number of drive circuits.

[0019] In addition, in this second aspect, the first to nth pixels (n is an integer satisfying 1<n<=9) arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits by time-division driving. As a result, for example, in a display system, by limiting the number of pixels connected to drive circuits and load circuits to a predetermined number in time-division driving, sufficient writing time can be ensured.

[0020] In this second aspect, each of the pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on the write voltage, thereby enabling, for example, a display system to apply a write voltage to the pixel with high accuracy without Vth correction.

[0021] In this second aspect, the plurality of drive circuits receive a negative reference voltage and output a positive write voltage, thereby enabling, for example, a display system to apply a write voltage to a pixel with high accuracy without Vth correction.

[0022] In addition, in this second aspect, each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light-emitting element to emit light based on the write voltage, thereby enabling, for example, a display system to apply a write voltage to the pixel with high accuracy without Vth correction.

[0023] In this second aspect, the plurality of drive circuits receive a reference voltage of positive polarity and output a write voltage of negative polarity, thereby enabling, for example, a display system to apply a write voltage to a pixel with high accuracy without Vth correction.

[0024] In the second aspect, the drive circuit is a differential amplifier circuit, which allows the display system to apply a write voltage to the pixel with high precision without Vth correction, for example.

[0025] In the second aspect, the load circuit is a current DAC, which allows, for example, a display system to apply a write voltage to a pixel with high precision without Vth correction.

[0026] In this second aspect, each pixel includes a drive transistor that drives a light-emitting element, the first switch is connected to the gate of the drive transistor, and the second switch is connected to the source or drain of the drive transistor. This allows, for example, the display device to reduce the number of drive circuits and thereby reduce the circuit scale. Furthermore, the display device can reduce the power consumption of the entire circuit due to the reduction in the number of drive circuits.

[0027] 1 is a configuration example of a display device according to the present embodiment; FIG. 2 is a schematic configuration diagram of pixels and horizontal analog circuits according to the present embodiment; FIG. 3 is an example of a circuit diagram of pixels and horizontal analog circuits according to the present embodiment; FIG. 4 is an example of a timing chart of pixels according to the present embodiment; FIG. 5 is an example of a circuit diagram of pixels and horizontal analog circuits according to a first modified example of the present embodiment; FIG. 6 is an example of a circuit diagram of pixels according to a second modified example of the present embodiment; FIG. 7 is an example of a circuit diagram of pixels according to a third modified example of the present embodiment; FIG. 8 is an example of a circuit diagram of pixels according to a fourth modified example of the present embodiment; FIG. 9 is an example of a circuit diagram of pixels according to a fifth modified example of the present embodiment; and FIG. 10 is an example of a circuit diagram of pixels according to a sixth modified example of the present embodiment.

[0028] Hereinafter, an embodiment of a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] Fig. 1 is a block diagram showing a schematic configuration of a display device 1 according to an embodiment of the present disclosure. The display device 1 in Fig. 1 is, for example, an active matrix microdisplay. The display device 1 in Fig. 1 includes a pixel array unit 2, a scanning line driver 3, a signal line driver 4, a video signal generator 5, and a timing generator 6. Control within the display device 1 is performed by, for example, a controller such as a processor (not shown).

[0030] The pixel array unit 2 has pixels 8 arranged in a two-dimensional array, i.e., a plurality of pixels 8 arranged in the row and column directions. Each pixel 8 has a plurality of sub-pixels 8a. The plurality of sub-pixels 8a includes, for example, three sub-pixels 8a of red, blue, and green. The plurality of sub-pixels 8a may also include sub-pixels 8a of colors other than red, blue, and green (for example, white). In this specification, the sub-pixels 8a may also be collectively referred to as pixels 8.

[0031] Each sub-pixel 8a in the pixel 8 has a light-emitting element EL. The light-emitting element EL is, for example, an OLED. The light-emitting element EL may be a liquid crystal element or a self-emitting element other than an OLED. The configuration of the pixel 8 will be described later.

[0032] The pixel array section 2 has a plurality of scanning lines WSL arranged for each pixel group in the row direction, and a plurality of signal lines SIG1 and SIG2 arranged for each pixel group in the column direction. Pixels 8 are provided near each intersection of these scanning lines WSL and the signal lines SIG1 and SIG2. In this specification, the row direction may be referred to as the horizontal line direction, and the column direction may be referred to as the vertical line direction.

[0033] The scanning line driver 3 drives the plurality of scanning lines WSL in turn. The signal line driver 4 includes a horizontal analog circuit 4 a, and drives the plurality of signal lines SIG1 and SIG2 in the horizontal line direction at the same timing in synchronization with the timing at which the scanning lines WSL drive each horizontal line.

[0034] The video signal generator 5 performs predetermined signal processing on the video signal supplied from an external device (e.g., a processor) to generate a gradation signal corresponding to the gradation value. The predetermined signal processing is, for example, gamma correction or overdrive correction.

[0035] The timing generation unit 6 supplies timing control signals to the scanning line drive unit 3 and the signal line drive unit 4 based on a synchronization signal supplied from the outside, causing the scanning line drive unit 3 and the signal line drive unit 4 to operate in synchronization.

[0036] There is no particular limit to the number of pixels in the pixel array unit 2 in Fig. 1. In a high-definition display device 1 with a large number of pixels, the scanning line driving unit 3 may be disposed on both ends of the horizontal line direction. Also, in order to drive a plurality of signal lines SIG in the horizontal line direction by dividing them into several groups, a plurality of signal line driving units 4 may be provided.

[0037] FIG. 2 is a schematic diagram of the pixel 8 and the horizontal analog circuit 4a in this embodiment.

[0038] In this embodiment, the horizontal analog circuit 4a includes a drive circuit 40 and a load circuit 50, and one horizontal analog circuit 4a is connected to multiple sub-pixels 8a. As will be described in detail later, a changeover switch arranged in each sub-pixel 8a switches the connection of the horizontal analog circuit 4a. Because each sub-pixel 8a has the same circuit configuration, in the following description of operation, one sub-pixel 8a will be collectively referred to as a pixel 8. In addition, in the following description, the write voltage applied to the gate of the drive transistor relative to the source will also be referred to as VGS.

[0039] In this embodiment, the horizontal analog circuit 4a includes a plurality of drive circuits 40 and a plurality of load circuits 50. The drive circuits 40 supply currents corresponding to a reference voltage VREF input to their inverting input terminals, and apply the voltages to the pixels 8. The drive circuits 40 also receive currents corresponding to gradation values ​​output from the corresponding load circuits 50 as inputs at their non-inverting input terminals. The drive circuits 40 compare the voltage value of the received input current with the reference voltage, amplify it, and supply it to the pixels 8 as a write voltage VGS.

[0040] FIG. 3 is an example of a circuit diagram of the pixel 8 and the horizontal analog circuit 4a in this embodiment.

[0041] This diagram shows 1st to nth pixels 8 arranged in a certain row, and these pixels 8 are connected to one drive circuit 40 and one load circuit 50 by time-division driving. Sets of selection switches and feedback-side selection switches that selectively connect the 1st to nth pixels 8 to these circuits are shown as selection switches SEL1_A to SELn_A and feedback-side selection switches FBSEL1_A to FBSELn_A, respectively. The pixels 8 to which the drive circuit 40 and the load circuit 50 are connected are also called the output stage.

[0042] In this embodiment, the drive circuit 40 is, for example, a differential amplifier circuit, and the load circuit 50 is, for example, a current DAC (IDAC). The horizontal analog circuit 4a generates a current corresponding to the gradation value using the current DAC, and inputs the current to the corresponding differential amplifier circuit through feedback (negative feedback in this case). Furthermore, the differential amplifier circuit compares the voltage value of the input current with a reference voltage VREF, amplifies the voltage, and supplies it to the pixel 8 as a write voltage VGS, thereby generating a highly accurate write voltage VGS without Vth correction. A bias current may be supplied to the differential amplifier circuit from a bias circuit (not shown).

[0043] In this embodiment, the input voltage to the non-inverting input terminal, i.e., the voltage input by the feedback operation, is designated as VFB_A. In this example, the load circuit 50 may be connected to, for example, a gamma circuit (not shown). A voltage corresponding to the gradation value is set in the load circuit 50 from among VG0 to VG255, and the amount of current flowing through the drive transistor of the pixel 8 and the amount of current flowing through the feedback circuit are controlled based on this setting.

[0044] In this embodiment, multiple pixels 8 arranged in the same row are sequentially switched within one horizontal period by time-division driving to be connected to a corresponding one of the drive circuits 40 and a corresponding one of the load circuits 50. That is, each pixel 8 is connected to the drive circuit 40 and the load circuit 50 at a different predetermined timing. Because the write voltage VGS is applied to each pixel 8 using feedback operation by the drive circuit 40 and the load circuit 50, it is desirable to ensure sufficient write time for each pixel 8 when connected to the circuit by time-division driving. Therefore, in this embodiment, the number of pixels 8 connected to one drive circuit 40 and one load circuit 50 is nine, and these first to ninth pixels 8 are sequentially connected to the drive circuit 40 and the load circuit 50 within one horizontal period. Because every nth pixel 8 is connected to one drive circuit 40 and one load circuit 50 by time-division driving, the overall circuit area can be reduced compared to when these circuits are provided for each pixel 8.

[0045] In this embodiment, the pixel 8 includes a light-emitting element EL, a write switch WS, a drive transistor Tr, a drive switch DS, and a feedback-side switch FB. Under the control of the control unit, the pixel 8 is connected to the drive circuit 40 via a selection switch SELn_A, and is connected to the load circuit 50 via a feedback-side selection switch FBSELn_A. The selection switch SELn_A is an example of a first switch, and the feedback-side selection switch FBSELn_A is an example of a second switch.

[0046] One end of the write switch WS is connected to a signal line SGL1, and the other end is connected to the gate of the drive transistor Dr. A current corresponding to a reference voltage VREF or a write voltage VSIG is supplied to the write switch WS via the signal line SGL1. Various other signals or signals for voltage precharge driving may also be supplied to the write switch WS via the signal line SGL1. The on / off operation of the write switch WS is controlled by a control unit. The write switch WS is an example of a third switch. The write switch WS does not need to be included in the configuration of the pixel 8.

[0047] The drive transistor Tr causes the light-emitting element EL to emit light at a luminance corresponding to the write voltage VGS. One of the drain or source of the drive transistor Tr is connected to the power supply line VCCP. The other of the drain or source of the drive transistor Tr is connected to one side of the drive switch DS and one side of the feedback switch FB. In this embodiment, the drive transistor Tr is a P-type transistor, and the potential of the source voltage is output in opposite phase to the input voltage of the gate.

[0048] One end of the drive switch DS is connected to the source terminal of the drive transistor Tr, and the other end is connected to the anode electrode of the light-emitting element EL. The on / off operation of the drive switch DS is controlled by the control unit.

[0049] One side of the feedback switch FB is connected to the drive switch DS and the source terminal of the drive transistor Tr, and the other side is connected to the signal line SGL2 and the feedback side selection switch FBSELn_A. Various signals may be supplied to the pixel 8 from the signal line SGL2 via the feedback side switch FB. The feedback side switch FB is an example of a fourth switch. The feedback side switch FB does not need to be included in the configuration of the pixel 8.

[0050] The selection switch SELn_A connects the pixel 8 to the drive circuit 40. More specifically, the selection switch SELn_A connects a corresponding one of the multiple pixels 8 arranged in the same row and connected to one drive circuit 40 to the drive circuit 40 at a predetermined timing by time-division driving. One side of the selection switch SELn_A is connected to the gate of the drive transistor Tr via the write switch WS, and the other side is connected to the drive circuit 40.

[0051] The feedback-side selection switch FBSELn_A connects the pixel 8 to the load circuit 50. More specifically, one corresponding pixel 8 among a plurality of pixels 8 arranged in the same row and connected to one load circuit 50 is connected to the load circuit 50 at a predetermined timing by time-division driving. One side of the feedback-side selection switch FBSELn_A is connected to one of the drain or source of the drive transistor Tr and the drive switch DS via the feedback-side switch FB, and the other side is connected to the load circuit 50. During time-division driving, the pair of the feedback-side selection switch FBSELn_A and the selection switch SELn_A is connected to the pixel 8 at the same timing.

[0052] Furthermore, the terminal voltage SIGn_A indicates the terminal voltage between the selection switch SELn_A and the write switch WS, and the terminal voltage FB1_A indicates the terminal voltage between the feedback-side selection switch FBSELn_A and the feedback-side switch FB.

[0053] FIG. 4 is an example of a timing chart for the pixel 8 in this embodiment.

[0054] In this figure, the operation of the first to n-th pixels 8 connected to one drive circuit 40 and one load circuit 50 for one horizontal period is shown as a timing chart.

[0055] The IDAC output in the timing chart indicates the value of the output current of the load circuit 50. In this example, under the control of the control unit, the load circuit 50 outputs values ​​ISIG1 to ISIGn that are changed according to the gradation value of each pixel 8 connected thereto.

[0056] The selection switches SEL1_A to SELn_A are driven in a time-division manner under the control of the control unit, and are turned on at predetermined timings, connecting the corresponding pixels 8 to the drive circuit 40. In this timing chart, the selection switches SEL1_A to SELn_A are turned on in this order, and the reference voltage VREF is input from the drive circuit 40.

[0057] Furthermore, at the timing when the selection switches SEL1_A to SELn_A are turned on, the feedback-side selection switches FBSEL1_A to FBSELn_A are also turned on, the corresponding pixels 8 are connected to the load circuit 50, and a feedback operation is performed on the non-inverting input terminal of the drive circuit 40. By the feedback operation, gate voltages VSIG1 to VSIGn are applied to the gates of the drive transistors Tr of the pixels 8. This causes the light-emitting elements EL to emit light with a brightness according to the gradation value.

[0058] When VSIG1 to VSIGn are input as write voltages VGS to the corresponding pixels 8, the terminal voltages SIG1_A to SIGn_A exhibit the same voltage value during the horizontal period.

[0059] FIG. 5 is an example of a circuit diagram of the pixel 8 and the horizontal analog circuit 4a in a first modified example of this embodiment.

[0060] In the example of Fig. 3, the pixel 8 includes a common-source circuit using a P-type drive transistor Tr. Therefore, in the example of Fig. 3, the pixel 8 has a fast switching operation and a large voltage gain on the output side. On the other hand, in this modification, the pixel 8 uses an N-type transistor as the drive transistor Tr and includes a common-source follower circuit. In this case, the impedance on the output side of the drive transistor Tr is low, and the phase of the voltage on the output side is output approximately in phase with the input voltage to the gate.

[0061] Furthermore, in this modification, the polarities of the input and output of the drive circuit 40 are different from those in Fig. 3. In the example of Fig. 3, the polarity of the reference voltage VREF in the drive circuit 40 is negative and the output is positive, but in the drive circuit 40 of this modification, the polarities are reversed, with the reference voltage VREF being positive and the output being negative. That is, in the drive circuit 40, a current corresponding to the reference voltage VREF is input to the non-inverting input terminal, and a current associated with the feedback operation is input to the inverting input terminal.

[0062] In the following modified examples, descriptions of the drive circuit 40 and the load circuit 50 are omitted, but the pixel PIX is connected to the drive circuit 40 via the terminal VOUT, as in the above example, and is connected to the load circuit 50 via the terminal VIN. In the following modified examples, one of the multiple pixels 8 connected to the drive circuit 40 and the load circuit 50 will be taken as the pixel PIX for explanation. In addition, the pixel PIX is connected to the drive circuit 40 and the load circuit 50 by time-division driving, as in the above-described pixel 8.

[0063] FIG. 6 is an example of a circuit diagram of a pixel PIX in a second modified example of this embodiment.

[0064] 6 shows another example of the configuration of pixel PIX. Pixel PIX has a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to scan line WSL2, one of its source and drain connected to signal line SGL1, and the other of its source and drain connected to signal line SGL2 and transistor MP42.

[0065] Furthermore, the pixel PIX is connected to the selection switch SELn_A via a signal line SIG1 and to the feedback-side selection switch FBSELn_A via a signal line SIG2. The display device 1 may be configured without the selection switch SELn_A and the feedback-side selection switch FBSELn_A. In this case, the transistor MP49 is treated as the selection switch SELn_A, and the transistor MP44 is treated as the feedback-side selection switch FBSELn_A.

[0066] Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to the scan line WSL1, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to the power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of the source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of transistors MP44 and MP45. The gate of transistor MP44 is connected to the control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to the control line DSL, one of the source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, the other of the source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of the source and drain is connected to the power supply line VSS.

[0067] The signal line SGL1 is connected to the VOUT terminal, which is the output side of the drive circuit 40, via a selection switch SELn_A, and the signal line SGL2 is connected to the load circuit 50 via a feedback-side selection switch FBSELn_A.

[0068] With this configuration, in pixel PIX, when the selection switch SELn_A, the feedback side selection switch FBSELn_A, the transistor MP49, the transistor MP42, and the transistor MP44 are turned on, the voltage across the capacitor C41 is set based on the write voltage VGS set by the feedback operation.

[0069] Furthermore, transistor MP45 is turned on and off based on a signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to write voltage VGS.

[0070] During the period in which the transistor MP46 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0071] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0072] FIG. 7 is an example of a circuit diagram of a pixel PIX in a third modified example of this embodiment.

[0073] In the second modification, the feedback-side selection switch FBSELn_A is connected to the signal line SGL2, but in this modification, the feedback-side selection switch FBSELn_A is connected to the power supply line VSS. In this modification, one of the source and drain of the transistor MP45 is connected to the other of the source and drain of the transistor MP43 and one of the source and drain of the transistor MP44. In addition, the other of the source and drain of the transistor MP45 is connected to one of the source and drain of the transistor MP46, the anode of the light-emitting element EL, and the feedback-side selection switch FBSELn_A.

[0074] In this modification, the transistor MP45 is turned on and off based on a signal on the control line DSL, and during a period in which the transistor MP45 is in an on state, the feedback-side selection switch FBSELn_A of the transistor MP43 is also in an on state, and the transistor MP45 is connected to the load circuit 50. The pixel PIX uses the feedback operation to pass a current corresponding to the voltage across the capacitor C41 to the light-emitting element EL.

[0075] As an example different from the connection to the feedback circuit described in this modification, the pixel PIX may include a feedback-side selection switch FBSELn_A on the power supply line VSS that enables connection to the load circuit 50. In this case, the pixel 8 may be connected by a changeover switch to the load circuit 50 via the feedback-side selection switch FBSELn_A during the light-emitting period, and may be connected to the power supply line VSS during the initialization period.

[0076] FIG. 8 is an example of a circuit diagram of a pixel PIX in a fourth modified example of this embodiment.

[0077] The signal on the control line WSNL and the signal on the control line WSPL are inverted signals to each other.

[0078] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element EL. The pixel PIX is connected to a selection switch SELn_A via a signal line SGL, and the power supply line VSS side is connected to a feedback side selection switch FBSELn_A.

[0079] The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to the control line WSNL, the other of its source and drain is connected to the signal line SGL and one of the source and drain of the transistor MP64, one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to the control line WSPL, one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may also be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may also be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to a control line AZL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of the source and drain is connected to the feedback-side selection switch FBSELn_A. The gate of transistor MN67 is connected to a control line DSL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of the source and drain is connected to the anode of the light-emitting element EL. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0080] The signal line SGL is connected via the selection switch SELn_A to the VOUT terminal, which is the output side of the drive circuit 40. As described above, one of the source and drain of the transistor MN66 is connected to the feedback-side selection switch FBSELn_A and is connected to the load circuit 50.

[0081] With this configuration, in pixel PIX, when the selection switch SELn_A and at least one of the transistors MN63 and MP64 are turned on, and further when the transistor MN66 and the feedback side selection switch FBSELn_A are turned on, the voltage across the capacitors C61 and C62 is set based on the write voltage VGS set by the feedback operation.

[0082] The transistor MN67 is turned on and off based on the signal on the control line DSL. While the transistor MN67 is on, the transistor MN65 passes a current corresponding to the voltage across the capacitors C61 and C62 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MP65. In this way, the pixel PIX emits light at a brightness corresponding to the write voltage VGS. The transistor MN66 is turned on and off based on the signal on the control line AZL.

[0083] Furthermore, by connecting the transistor MN66 to the pixel PIX, the transistor MN66 functions as a resistive element having a resistance value according to the signal on the control line AZL. In this case, the transistors MN65 and MN66 form a source follower circuit.

[0084] The transistors MN63, MP64, and MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0085] FIG. 9 is an example of a circuit diagram of a pixel PIX in a fifth modified example of this embodiment.

[0086] The pixel PIX includes transistors T7 to T10, a capacitor C81, and a light-emitting element EL. The pixel PIX is connected to a selection switch SELn_A via a signal line SGL1, and to a feedback-side selection switch FBSELn_A via a signal line SGL2. The display device 1 may be configured without the selection switch SELn_A and the feedback-side selection switch FBSELn_A. In this case, the transistor T7 is treated as the selection switch SELn_A, and the transistor T9 is treated as the feedback-side selection switch FBSELn_A.

[0087] The gate of the transistor T7 is connected to the control line WS, one of the source and drain is connected to the signal line SGL1, and the other of the source and drain is connected to one side of the capacitor C81 and the gate of the transistor T8.

[0088] One of the source and drain of the transistor T8 is connected to the power supply line VCCP, and the other of the source and drain is connected to the other side of the transistor T9 and one side of the transistor T10.

[0089] The gate of the transistor T9 is connected to the control line WS, one of the source and drain is connected to the signal line SGL2, and the other of the source and drain is connected to the other side of the transistor T8 and one side of the transistor T10.

[0090] The gate of the transistor T10 is connected to the control line DSL, one of the source and drain is connected to the other side of the transistor T8 and the other side of the transistor T9, and the other of the source and drain is connected to the anode of the light-emitting element EL.

[0091] The signal line SGL1 is connected via a selection switch SELn_A to the VOUT terminal which is the output side of the drive circuit 40. The signal line SGL2 is connected to the load circuit 50 via a feedback-side selection switch FBSELn_A.

[0092] With this configuration, in pixel PIX, when the selection switch SELn_A, the feedback side selection switch FBSELn_A, and the transistors T7, T8, and T9 are turned on, the voltage across the capacitor C81 is set based on the write voltage VGS and voltage RL set by the feedback operation.

[0093] The transistor T10 is turned on and off based on a signal on the control line DSL. During the period when the transistor T10 is in the on state, the transistor T8 passes a current corresponding to the voltage across the capacitor C81 through the light-emitting element EL.

[0094] FIG. 10 is an example of a circuit diagram of a pixel PIX in a sixth modified example of this embodiment.

[0095] The pixel PIX includes a transistor T21 and a light emitting element, and is connected to the selection switch SELn_A via a signal line SGL1 and to the feedback side selection switch FBSELn_A via a signal line SGL2.

[0096] The transistor T21 has a gate connected to the signal line SGL1, a source and a drain connected to the power supply VDD, and a back gate connected to the other of the source and drain of the transistor T21.

[0097] The signal line SGL1 is connected via the selection switch SELn_A to the VOUT terminal, which is the output side of the drive circuit 40. As described above, the other of the source and drain of the transistor T21 is connected via the signal line SGL2 to the feedback-side selection switch FBSELn_A and to the load circuit 50.

[0098] With this configuration, in the pixel PIX, the selection switch SELn_A and the feedback-side selection switch FBSELn_A are turned on, and thus the transistor T21 is turned on based on the reference gamma voltage Vgamma supplied to the signal line SGL1. During the period in which the transistor T21 is turned on, a current corresponding to the power supply VDD flows to the light-emitting element EL. During this period, a current corresponding to the voltage Vout flows to the load circuit 50 via the feedback-side selection switch FBSELn_A.

[0099] According to this embodiment, the display device 1 performs two-stage amplification using a feedback operation by the drive circuit 40, the pixels 8, and the load circuit 50. This allows the display device 1 to apply a write voltage to the pixels 8 with high precision without Vth correction.

[0100] Furthermore, according to this embodiment, the display device 1 includes a selection switch SELn_A and a feedback-side selection switch FBSELn_A in each pixel 8, and controls the drive circuit 40 based on control by the control unit to perform time-division driving of the plurality of pixels 8. This allows the display device 1 to reduce the number of drive circuits and downsize the circuit scale. Furthermore, the display device 1 can reduce the power consumption of the entire circuit due to the reduction in the number of drive circuits.

[0101] Furthermore, according to this embodiment, the display device 1 can ensure sufficient writing time by limiting the number of pixels 8 connected to the drive circuit 40 and the load circuit 50 to a predetermined number when performing time-division driving.

[0102] 2. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0103] 11 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0104] (Application Example 2) FIG. 12 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0105] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0106] (Application Example 3) Figures 13A and 13B show an example of the appearance of a digital still camera 130, with Figure 13A showing a front view and Figure 13B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually recognize the optical image of the subject guided by the photographing lens unit 132 and determine the composition of the shot. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0107] 14 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0108] 15 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0109] (Application Example 6) Figures 16A and 16B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 16A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 16B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0110] The vehicle in Figures 16A and 175 has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0111] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 16A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0112] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0113] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0114] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0115] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0116] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0117] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0118] The techniques according to the above-described embodiments can be applied to the center display 201, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0119] The present disclosure has been described above by giving embodiments and their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0120] Furthermore, for example, the present disclosure can be configured as follows.

[0121] (1) A display device comprising: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; a plurality of drive circuits that apply write voltages corresponding to gradation values ​​to a plurality of the pixels arranged in the same row; a plurality of load circuits that generate currents corresponding to the gradation values ​​and feed them back to the corresponding drive circuits; a plurality of first switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding drive circuits; and a plurality of second switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding load circuits.

[0122] (2) The display device according to (1), wherein the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing in one horizontal period, and sequentially switch and connect the plurality of pixels arranged in the same row to the corresponding drive circuits and load circuits.

[0123] (3) The display device according to (2), wherein the 1st to nth (n is an integer satisfying 1<n<=9) pixels arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits by time-division driving.

[0124] (4) The display device according to (1), wherein each of the pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

[0125] (5) The display device according to (4), wherein the plurality of drive circuits receive an input of a reference voltage of negative polarity and output a write voltage of positive polarity.

[0126] (6) The display device according to (1), wherein each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light emitting element to emit light based on the write voltage.

[0127] (7) The display device according to (6), wherein the plurality of drive circuits receive an input of a reference voltage of positive polarity and output a write voltage of negative polarity.

[0128] (8) The display device according to (1), wherein the drive circuit is a differential amplifier circuit.

[0129] (9) The display device according to (1), wherein the load circuit is a current DAC.

[0130] (10) The display device according to (1), wherein each of the pixels includes a drive transistor that causes a light-emitting element to emit light, the first switch is connected to a gate of the drive transistor, and the second switch is connected to a source or a drain of the drive transistor.

[0131] (11) A display system including a display device, the display device including: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; a plurality of drive circuits that apply write voltages according to gradation values ​​to a plurality of the pixels arranged in the same row; a plurality of load circuits that generate currents according to the gradation values ​​and feed them back to the corresponding drive circuits; a plurality of first switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding drive circuits; and a plurality of second switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding load circuits.

[0132] (12) The display system according to (11), wherein the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing in one horizontal period, and sequentially switch and connect the plurality of pixels arranged in the same row to the corresponding drive circuits and load circuits.

[0133] (13) The display system according to (12), wherein the 1st to nth (n is an integer satisfying 1<n<=9) pixels arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits by time-division driving.

[0134] (14) The display system according to (11), wherein each of the pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

[0135] (15) The display system according to (14), wherein the plurality of drive circuits receive an input of a reference voltage of negative polarity and output a write voltage of positive polarity.

[0136] (16) The display system according to (11), wherein each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

[0137] (17) The display system according to (16), wherein the plurality of drive circuits receive an input of a reference voltage of positive polarity and output a write voltage of negative polarity.

[0138] (18) The display system according to (11), wherein the drive circuit is a differential amplifier circuit.

[0139] (19) The display system according to (11), wherein the load circuit is a current DAC.

[0140] (20) The display system according to (11), wherein each of the pixels includes a drive transistor that causes a light-emitting element to emit light, the first switch is connected to a gate of the drive transistor, and the second switch is connected to a source or a drain of the drive transistor.

[0141] 1: display device, 2: pixel array section, 3: scanning line driving section, 4: signal line driving section, 4a: horizontal analog circuit, 5: video signal generating section, 6: timing generating section, 8: pixel, 8a: sub-pixel, 40: driving circuit, 50: load circuit, 110: head mounted display, 111: display section, 112: ear hook section, 120: head mounted display, 121: main body section, 122: arm section, 123: lens barrel section, 128: glasses, 129: lens, 130: digital still camera, 131: camera main body section, 132: photographing lens unit, 133: grip section, 134: monitor, 135: electronic viewfinder, 140: television device, 141: video display screen section, 142: front panel, 143: filter glass, 150: smartphone, 151: display section, 152: Operation unit, 200: Vehicle, 201: Center display, 202: Console display, 203: Head-up display, 204: Digital rearview mirror, 205: Steering wheel display, 206: Rear entertainment display, 261: Dashboard, 262: Driver's seat, 263: Passenger seat, 264: Center console, 265: Shift lever, 266: Windshield, 267: Steering wheel

Claims

1. A display device comprising: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; a plurality of drive circuits that apply write voltages corresponding to gradation values ​​to a plurality of the pixels arranged in the same row; a plurality of load circuits that generate currents corresponding to the gradation values ​​and feed them back to the corresponding drive circuits; a plurality of first switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding drive circuits; and a plurality of second switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding load circuits.

2. The display device according to claim 1, wherein the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing within one horizontal period, and sequentially switch and connect the plurality of pixels arranged in the same row to the corresponding drive circuits and load circuits.

3. The display device according to claim 2, wherein the 1st to nth (n is an integer satisfying 1<n<=9) pixels arranged in the same row are sequentially switched and connected to the corresponding drive circuits and load circuits by time-division driving.

4. The display device according to claim 1, wherein each of said pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on said write voltage.

5. The display device according to claim 4, wherein the plurality of drive circuits receive an input of a reference voltage of negative polarity and output a write voltage of positive polarity.

6. The display device according to claim 1, wherein each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

7. The display device according to claim 6, wherein the plurality of drive circuits receive an input of a reference voltage of positive polarity and output a write voltage of negative polarity.

8. The display device according to claim 1, wherein the drive circuit is a differential amplifier circuit.

9. The display device according to claim 1, wherein the load circuit is a current DAC.

10. The display device according to claim 1, wherein each of the pixels includes a drive transistor that causes a light-emitting element to emit light, the first switch is connected to a gate of the drive transistor, and the second switch is connected to a source or drain of the drive transistor.

11. A display system including a display device, the display device comprising: a pixel array section in which a plurality of pixels are arranged in a two-dimensional array; a plurality of drive circuits that apply write voltages corresponding to gradation values ​​to a plurality of the pixels arranged in the same row; a plurality of load circuits that generate currents corresponding to the gradation values ​​and feed them back to the corresponding drive circuits; a plurality of first switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding drive circuits; and a plurality of second switches that connect corresponding pixels of the plurality of pixels arranged in the same row to corresponding load circuits.

12. A display system as described in claim 11, wherein the plurality of first switches and the plurality of second switches are driven in a time-division manner at a predetermined timing within one horizontal period, and sequentially switch and connect the plurality of pixels arranged in the same row to the corresponding drive circuits and load circuits.

13. A display system according to claim 12, wherein the 1st to nth (n is an integer satisfying 1<n<=9) pixels arranged in the same row are connected to the corresponding drive circuits and load circuits in a sequentially switched manner by time-division driving.

14. The display system according to claim 11, wherein each of the pixels includes a common-source circuit using a P-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

15. The display system according to claim 14, wherein the plurality of drive circuits receive an input of a reference voltage of negative polarity and output a write voltage of positive polarity.

16. The display system according to claim 11, wherein each of the pixels includes a source follower circuit using an N-type drive transistor that causes a light-emitting element to emit light based on the write voltage.

17. The display system according to claim 16, wherein the plurality of drive circuits receive an input of a reference voltage of positive polarity and output a write voltage of negative polarity.

18. The display system according to claim 11, wherein the drive circuit is a differential amplifier circuit.

19. The display system of claim 11, wherein the load circuit is a current DAC.

20. The display system of claim 11, wherein each of the pixels includes a drive transistor that causes a light-emitting element to emit light, the first switch is connected to a gate of the drive transistor, and the second switch is connected to a source or drain of the drive transistor.

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