Semiconductor device

Abstract

This semiconductor device comprises: a MIS transistor structure including a first impurity region of a first conductivity type in a surface layer portion of a main surface of a chip, a second impurity region of a second conductivity type, a third impurity region of the first conductivity type, and a gate structure facing a channel region in the second impurity region; a gate electrode film on an insulating layer on the main surface, the gate electrode film including a pad portion and a finger portion extending linearly from the pad portion and surrounding an active region; a main surface electrode film on the insulating layer in the active region and electrically connected to the third impurity region; and a main surface contact region of the second conductivity type, which is located on a portion of the surface layer portion of the second impurity region along the finger portion at the outer peripheral edge of the active region, electrically connected to the main surface electrode film, and has a higher impurity concentration than the second impurity region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-113606 filed with the Japan Patent Office on July 16, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a SiC semiconductor device including a SiC semiconductor layer including an active region and an outer region, and a gate principal surface electrode layer and a source principal surface electrode layer disposed on the principal surface of the SiC semiconductor layer. The gate principal surface electrode layer includes a gate pad and gate fingers extending from the gate pad in a strip shape along the periphery of the active region. The source principal surface electrode layer includes a source pad and a source lead-out wiring extending from the source pad and formed endlessly to surround the active region and the gate fingers in a plan view. The source lead-out wiring is electrically connected to the SiC semiconductor layer in the outer region.

[0004] Japanese Patent Application Laid-Open No. 2023-179690

[0005] an insulating layer on the main surface; a gate electrode film on the insulating layer and electrically connected to the gate structure, the gate electrode film including a pad portion and finger portions extending in a line from the pad portion and surrounding the active region; a main surface electrode film on the insulating layer in the active region and electrically connected to the third impurity region; and a main surface contact region of a second conductivity type on a part of the surface portion of the second impurity region along the outer periphery of the active region, the main surface contact region being electrically connected to the main surface electrode film and having an impurity concentration higher than that of the second impurity region.

[0006] FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a plan view showing a layout of a principal surface electrode film. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a plan view showing a layout of an underlying wiring layer. FIG. 5 is a perspective view showing a layout of a well region. FIG. 6 is a plan view showing a layout of a well region. FIG. 7 is an enlarged view of a portion surrounded by a two-dot chain line VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX in FIG. 7. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 7. FIG. 12 is a cross-sectional view showing a boundary between an active region and a peripheral region. FIG. 13 is an enlarged cross-sectional view showing a main portion of the active region. FIG. 14 is an enlarged cross-sectional view showing a main portion of the active region. FIG. 15 is a cross-sectional perspective view showing a main portion of the active region. FIG. 16 is a cross-sectional perspective view showing a main portion of the active region. FIG. 17 is a cross-sectional perspective view showing a main portion of the boundary between the active region and the peripheral region. FIG. 18 is an enlarged view of a portion surrounded by two-dot chain line XVIII shown in FIG. 4. FIG. 19 is a cross-sectional view taken along line IXX-IXX shown in FIG. 18. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 18. FIG. 21 is an enlarged view of a portion surrounded by two-dot chain line XXI shown in FIG. 4. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 21. FIG. 23 is a diagram showing a first modified example of the layout of the gate electrode film. FIG. 24 is a diagram showing a second modified example of the layout of the gate electrode film. FIG. 25 is a diagram showing a third modified example of the layout of the gate electrode film. FIG. 26 is a diagram showing a fourth modified example of the layout of the gate electrode film. FIG. 27 is a diagram showing a fifth modified example of the layout of the gate electrode film. FIG. 28 is a diagram showing a first modified example of the layout of the main surface contact region. FIG. 29 is a diagram showing a second modified example of the layout of the main surface contact region. FIG. 30 is a cross-sectional perspective view showing a first modified example of various insulating films. Fig. 31 is a cross-sectional view showing a second modified example of various insulating films. Fig. 32 is a cross-sectional view showing a third modified example of various insulating films. Fig. 33 is a cross-sectional view showing a fourth modified example of various insulating films. Fig. 34 is a cross-sectional view showing a fifth modified example of various insulating films. Fig. 35 is a cross-sectional view showing a main part of a planar gate structure.FIG. 36 is a cross-sectional view showing a main part of a planar gate structure.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) Basic Structure of Semiconductor Device 1 Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a plan view showing the layout of a main surface electrode film 31. Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2. Fig. 4 is a plan view showing the layout of an underlying wiring layer 20.

[0012] The semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0013] 1 to 4, semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. Semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. The semiconductor device 1 is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 (not shown in FIGS. 1 to 3 ) on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not more than 10°. The off-angle is preferably not more than 5°.

[0018] The first side surface 5A and the second side surface 5B each extend in a first direction X along the first main surface 3 and face opposite each other in a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D each extend in the second direction Y and face opposite each other in the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may have a value that belongs to any one of the ranges of 0.5 mm or more and 1 mm or less, 1.5 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D may be 5 mm or more.

[0022] 2 to 4, semiconductor device 1 includes an active region 6 and a peripheral region 8 defined on first main surface 3 of chip 2. As shown in FIG.

[0023] The active region 6 includes a device structure (transistor structure Tr) and is a region (element region) where an output current (drain current) is generated. The active region 6 is set in the interior of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) in a plan view. The active region 6 is formed in a polygonal shape with sides parallel to the periphery of the chip 2 in a plan view. In this embodiment, the active region 6 is formed in a polygonal shape with a recessed portion recessed along a gate pad electrode 36 (described later) in a plan view. The active region 6 may also be formed in a quadrangular shape in a plan view. The planar area of ​​the active region 6 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0024] The active region 6 may include a plurality of active regions 6 that are separated from one another. In this embodiment, the active region 6 includes a first active region 61 and a second active region 62 that are separated from one another. The first active region 61 and the second active region 62 may be disposed on one side and the other side of the center of the chip 2 in the first direction X, respectively. The first active region 61 and the second active region 62 may have planar shapes that are axisymmetric to each other with respect to the finger wirings 39 that extend in the second direction Y.

[0025] The peripheral region 8 is a region that does not include a device structure (transistor structure Tr). In plan view, the peripheral region 8 is provided in a region between the periphery of the chip 2 and the active region 6. In plan view, the peripheral region 8 extends in a strip shape along the active region 6 and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 6.

[0026] The semiconductor device 1 includes an n-type first semiconductor layer 9 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 9 as a first potential (high potential). The first semiconductor layer 9 may also be referred to as a "semiconductor region (layer)", a "base region (layer)", a "drain region (layer)", or the like.

[0027] The first semiconductor layer 9 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 9 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 9 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 9 is made of a substrate (SiC substrate) made of SiC single crystal. The first semiconductor layer 9 has the off direction and off angle described above.

[0028] The first semiconductor layer 9 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The first semiconductor layer 9 may have the following n-type impurity concentration as a peak value. The first semiconductor layer 9 preferably has an n-type impurity concentration that is approximately constant in the thickness direction. The n-type impurity concentration of the first semiconductor layer 9 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the first semiconductor layer 9 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the first semiconductor layer 9 is adjusted by nitrogen.

[0029] The first semiconductor layer 9 may have a first thickness T1 of 10 μm to 500 μm inclusive. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm inclusive, 50 μm to 100 μm inclusive, 100 μm to 150 μm inclusive, 150 μm to 200 μm inclusive, 200 μm to 300 μm inclusive, 300 μm to 400 μm inclusive, and 400 μm to 500 μm inclusive.

[0030] The semiconductor device 1 includes an n-type second semiconductor layer 10 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 10 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 10 extends in a layered form along the first main surface 3, and forms the first main surface 3 and first to fourth side surfaces 5A to 5D.

[0031] In this embodiment, the second semiconductor layer 10 is an n-type semiconductor layer. Specifically, the second semiconductor layer 10 is an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 10 (epitaxial layer) has the off direction and off angle described above. The second semiconductor layer 10 is an epitaxial layer (SiC epitaxial layer) grown from the first semiconductor layer 9.

[0032] The second semiconductor layer 10 has a lower end and an upper end. The lower end of the second semiconductor layer 10 is the starting point of crystal growth, and the upper end of the second semiconductor layer 10 is the ending point of crystal growth. The lower end of the second semiconductor layer 10 is also the bottom of the second semiconductor layer 10. Because the second semiconductor layer 10 is grown continuously from the first semiconductor layer 9, the lower end of the second semiconductor layer 10 coincides with the upper end of the first semiconductor layer 9.

[0033] The second semiconductor layer 10 includes an n-type drift region 11. In this embodiment, the drift region 11 is formed by a part (n-type portion) of the second semiconductor layer 10.

[0034] The boundary between the first semiconductor layer 9 and the second semiconductor layer 10 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 10 has an off direction and an off angle that are approximately the same as those of the first semiconductor layer 9.

[0035] The second semiconductor layer 10 may have a lower n-type impurity concentration than the first semiconductor layer 9. The second semiconductor layer 10 has a n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １７ cm －３ The second semiconductor layer 10 may have the following peak n-type impurity concentration: It is preferable that the second semiconductor layer 10 has a substantially constant n-type impurity concentration in the thickness direction.

[0036] The second semiconductor layer 10 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0037] The semiconductor device 1 includes a plurality of trench electrode type gate structures 12 formed on the first main surface 3 in the active region 6. The gate structures 12 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 12 as a control potential.

[0038] In this embodiment, the multiple gate structures 12 are arranged at intervals in the second direction Y, and are each formed in a band shape extending in the first direction X. In this embodiment, the multiple gate structures 12 are arranged in a stripe shape extending in the first direction X. The multiple gate structures 12 are formed at intervals from the lower end (first semiconductor layer 9) of the second semiconductor layer 10 toward the first main surface 3, and face the first semiconductor layer 9 with a part of the second semiconductor layer 10 sandwiched between them. In this embodiment, the multiple gate structures 12 are arranged in a stripe shape extending in the first direction X.

[0039] The semiconductor device 1 includes a p-type well region 13 in the second semiconductor layer 10. The well region 13 is formed in a surface layer portion of the second semiconductor layer 10. The well region 13 includes an active well region 14 in the active region 6 and an outer well region 15 in the peripheral region 8.

[0040] The semiconductor device 1 includes a plurality of p-type bottom well regions 16 formed at intervals in the horizontal direction in the second semiconductor layer 10 of the active region 6. Specifically, the plurality of bottom well regions 16 are formed at the bottom of the gate structure 12, respectively.

[0041] The semiconductor device 1 includes a p-type field region 17 formed in the surface layer portion of the first main surface 3 in the peripheral region 8 (the peripheral portion of the first main surface 3).

[0042] The semiconductor device 1 includes a surface insulating film 18 that selectively covers the first main surface 3. The surface insulating film 18 may also be referred to as an "outer surface insulating film." The surface insulating film 18 covers the first main surface 3 in the peripheral region 8 in a film-like manner.

[0043] Specifically, the surface insulating film 18 covers the outer well region 15 and the plurality of field regions 17 in the peripheral region 8. The surface insulating film 18 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 18 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0044] 4 , the semiconductor device 1 includes an underlying wiring layer 20 as an example of a wiring layer formed on the first main surface 3 in the peripheral region 8. The underlying wiring layer 20 supplies current from a gate pad electrode 36 (described later) to a plurality of gate structures 12. The underlying wiring layer 20 is an underlying layer for a metallic main surface electrode film 31 (described later) on an interlayer insulating film 29 (described later), and is laid out directly below the main surface electrode film 31. For clarity in FIG. 4 , the formation regions of the underlying wiring layer 20 and the gate structures 12 are indicated by hatching, and the outline of the main surface electrode film 31 above the underlying wiring layer 20 is indicated by a dashed line.

[0045] In this embodiment, the underlying wiring layer 20 is made of the same material as the gate structure 12 and is formed integrally with the gate structure 12. The underlying wiring layer 20 and the gate structure 12 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0046] The underlying wiring layer 20 includes a base portion 21 and an extension portion 22. The base portion 21 is disposed directly below a gate pad electrode 36 (described later). The base portion 21 is formed in a ring shape surrounding the periphery of the gate pad electrode 36 in a plan view. The base portion 21 is disposed near one of the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the base portion 21 is disposed close to the first side surface 5A at the center of the first side surface 5A in the first direction X.

[0047] The extension portion 22 extends outward in a strip shape from the outer edge of the annular base portion 21. The semiconductor device 1 includes a plurality of extension portions 23 to 25 that extend in strip shapes in different directions from the outer edge of the base portion 21. The plurality of extension portions 23 to 25 are arranged in a non-parallel positional relationship with each other. The plurality of extension portions 23 to 25 may include a first extension portion 23, a second extension portion 24, and a third extension portion 25.

[0048] The first extension portion 23 and the second extension portion 24 extend from the base portion 21 in opposite directions along the periphery of the chip 2, and as a whole surround the active region 6. In this embodiment, the first extension portion 23 extends from the base portion 21 in the first direction X along the first side surface 5A and then the third side surface 5C, and has a first tip portion 26 at a corner C of the chip 2 where the third side surface 5C and the second side surface 5B intersect. The second extension portion 24 extends from the base portion 21 in the first direction X along the first side surface 5A and then the fourth side surface 5D, and has a second tip portion 27 at a corner C of the chip 2 where the fourth side surface 5D and the second side surface 5B intersect.

[0049] The first extension 23 and the second extension 24 are each formed in a substantially L-shape in a plan view and have a corner C2 at a position corresponding to a corner C of the chip 2. The first extension 23 may be referred to as, for example, a "first peripheral underlay wiring," a "first peripheral underlay electrode," a "first peripheral underlay finger wiring," a "first peripheral underlay finger electrode," or the like. The second extension 24 may be referred to as, for example, a "second peripheral underlay wiring," a "second peripheral underlay electrode," a "second peripheral underlay finger wiring," a "second peripheral underlay finger electrode," or the like. The first extension 23 and the second extension 24 may be collectively referred to as a "peripheral underlay wiring," a "peripheral underlay electrode," a "peripheral underlay finger wiring," a "peripheral underlay finger electrode," or the like that surround the active region 6.

[0050] The third extension portion 25 extends from the base portion 21 toward the center of the chip 2 and crosses the active region 6. The third extension portion 25 may extend from the base portion 21 toward the second side surface 5B and divide the active region 6 into left and right sides (both sides of the third side surface 5C and the fourth side surface 5D). The third extension portion 25 has a third tip portion 28 located inside the area surrounded by the first extension portion 23 and the second extension portion 24. The third tip portion 28 is arranged closer to the active region 6 than the first tip portion 26 and the second tip portion 27. The third extension portion 25 may be referred to as, for example, a "central underlying wiring," a "central underlying electrode," a "central underlying finger wiring," a "central underlying finger electrode," or the like.

[0051] The plurality of gate structures 12 may be arranged across two different locations on the underlying wiring layer 20. One end and the other end of each strip-shaped gate structure 12 are connected to two different locations on the underlying wiring layer 20. In this embodiment, the plurality of gate structures 12 electrically connect between the base portion 21 and the first extension portion 23, between the base portion 21 and the second extension portion 24, between the first extension portion 23 and the third extension portion 25, and between the second extension portion 24 and the third extension portion 25.

[0052] The semiconductor device 1 includes an insulating interlayer insulating film 29 that covers the surface insulating film 18. The interlayer insulating film 29 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer insulating film 29 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0053] 2 and 3, a contact opening 30 exposing the active region 6 is formed in the interlayer insulating film 29. The active well region 14 and the gate structure 12 are exposed from the contact opening 30.

[0054] 2 and 3, the semiconductor device 1 includes a main surface electrode film 31 and a gate electrode film 32 disposed on an interlayer insulating film 29. In Fig. 2, the interlayer insulating film 29 is shown as a white region, and the main surface electrode film 31 and the gate electrode film 32 are shown as hatched regions. Also in Fig. 2, a contact opening 30 is shown by a dashed line.

[0055] The principal surface electrode film 31 may also be referred to as a source electrode film. The principal surface electrode film 31 is a film that is physically and electrically separated from the gate electrode film 32. The principal surface electrode film 31 is disposed on the interlayer insulating film 29 at a distance from the gate electrode film 32. The principal surface electrode film 31 is an electrode to which a source potential is applied from the outside. The principal surface electrode film 31 may also be referred to as a "first principal surface electrode," a "source electrode film," a "source pad electrode," a "source metal," a "first pad electrode," etc.

[0056] The principal surface electrode film 31 is formed of a metal material containing Al (aluminum). The principal surface electrode film 31 includes an Al-based metal film. The principal surface electrode film 31 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The principal surface electrode film 31 may also be a metal film other than an Al-based metal film. The principal surface electrode film 31 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0057] In this embodiment, the principal surface electrode film 31 is disposed on the active region 6 in a plan view. The principal surface electrode film 31 is formed in a polygonal shape in a plan view. The principal surface electrode film 31 includes a first electrode region 33 and a second electrode region 34 that are separated from each other. In this embodiment, the principal surface electrode film 31 includes the first electrode region 33 disposed in a region closer to the third side surface 5C than a central position in the first direction X of the active region 6 (first principal surface 3), and the second electrode region 34 disposed in a region closer to the fourth side surface 5D than the central position. The first electrode region 33 and the second electrode region 34 may be connected to each other by a connection region 35 at their ends on the second side surface 5B side.

[0058] The gate electrode film 32 is an electrode to which a gate potential is applied from the outside. The gate electrode film 32 may also be called a "second principal surface electrode," a "gate metal," a "second pad electrode," or the like.

[0059] The gate electrode film 32 is formed of a metal material containing Al (aluminum). The gate electrode film 32 includes an Al-based metal film. The gate electrode film 32 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate electrode film 32 may also be a metal film other than an Al-based metal film. The gate electrode film 32 may include at least one of a Ti film, a TiN film, a W film, a Cu film, a Cu alloy film, and a conductive polysilicon film.

[0060] The gate electrode film 32 includes a gate pad electrode 36 as an example of a pad portion and a gate wiring 37 as an example of a finger portion. In this embodiment, the gate pad electrode 36 is disposed on the peripheral region 8. Specifically, the gate pad electrode 36 is disposed in a region close to the center of one side of the first main surface 3 (the first side surface 5A in this embodiment) in a plan view. The gate pad electrode 36 is disposed in a recess formed in the main surface electrode film 31. The gate pad electrode 36 may be disposed in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 36 may be disposed at any corner C of the chip 2 on the first main surface 3 in a plan view. The gate pad electrode 36 may be disposed in the center of the first main surface 3 in a plan view. The gate pad electrode 36 may be disposed on the active region 6. In this embodiment, the gate pad electrode 36 is formed in a quadrangular shape in a plan view.

[0061] The gate wiring 37 is routed from the gate pad electrode 36 around the periphery of the active region 6, surrounding the active region 6. The gate wiring 37 transmits the gate potential applied to the gate pad electrode 36 to the plurality of gate structures 12.

[0062] The gate wiring 37 includes a base wiring 38 and finger wiring 39. The base wiring 38 is disposed directly above the base portion 21 of the underlying wiring layer 20. The base wiring 38 is formed in a ring shape that overlaps the base portion 21, and surrounds the periphery of the gate pad electrode 36 in a plan view.

[0063] The finger wirings 39 extend outward in a strip shape from the outer edge of the annular base wiring 38. The semiconductor device 1 includes a plurality of finger wirings 40 to 42 extending in strip shapes in different directions from the outer edge of the base wiring 38. The plurality of finger wirings 40 to 42 are arranged in a non-parallel positional relationship with each other. The plurality of finger wirings 40 to 42 may include a first finger wiring 40, a second finger wiring 41, and a third finger wiring 42.

[0064] The first finger wiring 40 and the second finger wiring 41 extend from the base wiring 38 along the periphery of the chip 2 in opposite directions to each other, and as a whole surround the main surface electrode film 31. As a result, the entire area defined by the outer periphery of the main surface electrode film 31 is disposed within the area surrounded by the first finger wiring 40 and the second finger wiring 41. In this embodiment, the entire main surface electrode film 31 is disposed within the area sandwiched between the first finger wiring 40 and the second finger wiring 41. The first finger wiring 40 extends from the base wiring 38 in the first direction X along the first side surface 5A and the third side surface 5C in this order, and has a first tip portion 43 at a corner C of the chip 2 where the third side surface 5C and the second side surface 5B intersect. The second finger wiring 41 extends from the base wiring 38 in the first direction X along the first side surface 5A and the fourth side surface 5D in that order, and has a second tip portion 44 at the corner C of the chip 2 where the fourth side surface 5D and the second side surface 5B intersect.

[0065] The first finger wiring 40 and the second finger wiring 41 are each formed in a substantially L-shape in plan view so as to overlap the first extending portion 23 and the second extending portion 24, respectively, and have a corner C3 at a position corresponding to the corner C of the chip 2. The first finger wiring 40 may be referred to as, for example, a "first peripheral wiring," a "first peripheral electrode," a "first peripheral finger wiring," a "first peripheral finger electrode," etc. The second finger wiring 41 may be referred to as, for example, a "second peripheral wiring," a "second peripheral electrode," a "second peripheral finger wiring," a "second peripheral finger electrode," etc. The first finger wiring 40 and the second finger wiring 41 may be collectively referred to as a "peripheral wiring," a "peripheral electrode," a "peripheral finger wiring," a "peripheral finger electrode," etc. that surround the active region 6.

[0066] The third finger wiring 42 extends from the base wiring 38 toward the center of the chip 2 and crosses the main surface electrode film 31. The third finger wiring 42 may extend from the base wiring 38 toward the second side surface 5B and divide the main surface electrode film 31 into a first electrode region 33 and a second electrode region 34. The third finger wiring 42 has a third tip portion 45 inside the region surrounded by the first finger wiring 40 and the second finger wiring 41. The third finger wiring 42 may be referred to as, for example, a "central wiring," a "central electrode," a "central finger wiring," a "central finger electrode," or the like.

[0067] 1 , semiconductor device 1 includes a protective film 46 that selectively covers main surface electrode film 31 and interlayer insulating film 29 on first main surface 3. Protective film 46 includes a gate pad opening 48 that exposes a portion of gate pad electrode 36 as a gate pad 47. Protective film 46 covers the periphery of gate pad electrode 36 and the entire area of ​​gate wiring 37. Gate pad opening 48 is formed in a quadrangular shape in a plan view.

[0068] 1 , the protective film 46 includes a first source pad opening 50 that exposes a part of the first electrode region 33 as a first source pad 49, and a second source pad opening 52 that exposes a part of the second electrode region 34 as a second source pad 51. The protective film 46 covers the peripheral edge of the first electrode region 33 and the peripheral edge of the second electrode region 34.

[0069] The first source pad opening 50 is formed in a polygonal shape that follows the periphery of the first electrode region 33 in a plan view. The second source pad opening 52 is formed in a polygonal shape that follows the periphery of the second electrode region 34 in a plan view. The plane areas of the first source pad opening 50 and the second source pad opening 52 are preferably larger than the plane area of ​​the gate pad opening 48.

[0070] The protective film 46 may have a layered structure including, for example, an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side. The protective film 46 may include at least one of an inorganic insulating film and an organic insulating film, and does not necessarily have to include both an inorganic insulating film and an organic insulating film at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film preferably includes an insulating material different from that of the interlayer insulating film 29. The organic insulating film is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0071] The semiconductor device 1 includes a drain pad electrode 7 covering the second main surface 4. The drain pad electrode 7 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 7 is mechanically and electrically connected to the first semiconductor layer 9. The drain pad electrode 7 forms ohmic contact with the first semiconductor layer 9.

[0072] The drain pad electrode 7 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 7 may also cover part of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0073] A breakdown voltage that can be applied between the main surface electrode film 31 and the drain pad electrode 7 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0074] (2) Layout of Well Region 13 FIG. 5 is a perspective view showing the layout of the well region 13. FIG. 6 is a plan view showing the layout of the well region 13. In FIGS. 5 and 6, thick solid lines indicate the outline of the well region 13, and thick dashed lines indicate the outline of the main surface contact region 53. The hatched rings are the field regions 17. Furthermore, in FIG. 6, the outlines of the main surface electrode film 31 and the gate electrode film 32 are indicated by dashed lines.

[0075] 5 and 6, the well region 13 is disposed at a distance inward from the outer periphery of the chip 2. The well region 13 is a planar region surrounded by a thick solid line, and has an outer periphery spaced inward from the first to fourth side surfaces 5A to 5D. In this embodiment, the well region 13 is rectangular in plan view. The well region 13 has first to fourth well peripheries 54A to 54D that are parallel to the first to fourth side surfaces 5A to 5D, respectively. The first well periphery 54A is parallel to the first side surface 5A, the second well periphery 54B is parallel to the second side surface 5B, the third well periphery 54C is parallel to the third side surface 5C, and the fourth well periphery 54D is parallel to the fourth side surface 5D. A plurality of field regions 17 are disposed in the regions between the first to fourth well peripheries 54A to 54D and the first to fourth side surfaces 5A to 5D.

[0076] 5, well region 13 includes active well region 14 and outer well region 15. Active well region 14 is a region located inside active region 6 indicated by a thin dashed dotted line. Outer well region 15 is a region located outside active region 6. Outer well region 15 extends from active well region 14 to outer peripheral region 8 located outside gate electrode film 32. Active well region 14 and outer well region 15 are integral, and the boundary between them does not need to be visible.

[0077] 5 and 6, the main surface contact region 53 is disposed inwardly and spaced from the first to fourth well peripheries 54A to 54D (the outer peripheral edge of the outer well region 15) of the well region 13. The main surface contact region 53 is an annular region defined by a thick dashed line.

[0078] The main surface contact region 53 crosses the gate electrode film 32 and spans the active region 6 and the outer well region 15. The main surface contact region 53 has first to fourth outer peripheral edges 55A to 55D that are spaced inward from the first to fourth well peripheries 54A to 54D and positioned outside the gate electrode film 32. The first outer peripheral edge 55A is parallel to the first side surface 5A, the second outer peripheral edge 55B is parallel to the second side surface 5B, the third outer peripheral edge 55C is parallel to the third side surface 5C, and the fourth outer peripheral edge 55D is parallel to the fourth side surface 5D.

[0079] The main surface contact region 53 further has first to fourth inner peripheries 56A to 56D located inside the gate electrode film 32. The first inner periphery 56A is parallel to the first side surface 5A, the second inner periphery 56B is parallel to the second side surface 5B, the third inner periphery 56C is parallel to the third side surface 5C, and the fourth inner periphery 56D is parallel to the fourth side surface 5D. In this embodiment, the main surface contact region 53 is formed in an annular shape in plan view in an inner region of the well region 13 spaced inward from the first to fourth well peripheries 54A to 54D. The planar shape of the main surface contact region 53 may be a square shape as shown in FIGS. 5 and 6, or a circle.

[0080] 6 , the main surface contact region 53 overlaps, in the thickness direction of the chip 2, with first finger wiring 40 and second finger wiring 41, which are examples of outer finger portions, of the finger wirings 39 of the gate electrode film 32. The first finger wiring 40 and the second finger wiring 41 may be entirely disposed in an inner region of the main surface contact region 53. The first finger wiring 40 and the second finger wiring 41 may not have portions that protrude from or cross the main surface contact region 53.

[0081] 6 , the main surface contact region 53 overlaps a portion of the main surface electrode film 31 in the thickness direction of the chip 2. The main surface contact region 53 may selectively overlap the peripheral portion of the main surface electrode film 31 with respect to the entire main surface electrode film 31. In this embodiment, the main surface contact region 53 overlaps a portion of the peripheral portion of the first electrode region 33 that is aligned with the first finger wiring 40, a portion of the peripheral portion of the second electrode region 34 that is aligned with the second finger wiring 41, and a peripheral portion of the main surface electrode film 31 on the second side surface 5B side including the connection region 35.

[0082] (3) Structure of the Active Region 6 of the Semiconductor Device 1 FIG. 7 is an enlarged view of the portion surrounded by the two-dot chain line VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 7. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 7. FIG. 12 is a cross-sectional view showing the boundary between the active region 6 and the peripheral region 8. FIGS. 13 to 16 are enlarged cross-sectional views showing a main portion of the active region 6. The structure of the active region 6 will be mainly described in detail with reference to FIGS. 7 to 16.

[0083] The semiconductor device 1 includes a p-type active well region 14 formed in a surface layer portion of the first main surface 3. A source potential may be applied to the active well region 14. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The active well region 14 may also be referred to as a "body region," a "channel region," or the like.

[0084] The active well region 14 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 10. The active well region 14 has a p-type impurity concentration of, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３The active well region 14 may have the following p-type impurity concentration as a peak value. The active well region 14 is formed in the inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this embodiment, the active well region 14 is formed over the entire active region 6. The active well region 14 is formed in the surface layer portion of the second semiconductor layer 10, and extends in a layered form along the first main surface 3.

[0085] The active well region 14 is formed at a distance from the bottom of the second semiconductor layer 10 (first semiconductor layer 9) toward the first main surface 3, and faces the first semiconductor layer 9 across a part of the second semiconductor layer 10. The active well region 14 is formed at a distance from a depth position in the middle of the second semiconductor layer 10 toward the first main surface 3.

[0086] The active well region 14 is formed in a region on the first main surface 3 side of the second semiconductor layer 10 in a cross-sectional view, and is electrically connected to the second semiconductor layer 10. The active well region 14 forms a pn junction (body diode) with the second semiconductor layer 10. The active well region 14 spreads a depletion layer into the second semiconductor layer 10 when a reverse bias voltage is applied. The depletion layer originating from the active well region 14 spreads in the horizontal direction and thickness direction within the second semiconductor layer 10.

[0087] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 12 formed in an inner portion of the first main surface 3. The plurality of gate structures 12 penetrate the active well region 14 to reach the second semiconductor layer 10. The plurality of gate structures 12 are formed at intervals from the depth position of the bottom of the second semiconductor layer 10 toward the first main surface 3, and face the first semiconductor layer 9 with a portion of the second semiconductor layer 10 sandwiched therebetween.

[0088] The multiple gate structures 12 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor layer 10 toward the first major surface 3, or may be located on the bottom side (second major surface 4 side) of the second semiconductor layer 10 with respect to the depth position of the intermediate portion of the second semiconductor layer 10. The multiple gate structures 12 are formed approximately perpendicular to the first major surface 3. The multiple gate structures 12 may be formed in a shape that tapers toward the bottom of the second semiconductor layer 10.

[0089] The side walls (long sides) of the plurality of gate structures 12 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 12 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 12. The side walls of the plurality of gate structures 12, together with the first main surface 3, define an opening end curved in an arc shape (circular arc shape).

[0090] The bottom walls of the gate structures 12 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 12 preferably extend substantially flat in the horizontal direction. The bottom walls of the gate structures 12 may be curved in an arc shape toward the second main surface 4.

[0091] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 12 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0092] The gate structure 12 may have a width of 0.1 μm to 2 μm. The width of the gate structure 12 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The width of the gate structure 12 is preferably 1 μm or less.

[0093] The gate structure 12 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 12 is measured from the first main surface 3. The depth of the gate structure 12 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 12 is preferably 0.5 μm or more and 1.5 μm or less.

[0094] The gate structure 12 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 12 is the ratio of the depth of the gate structure 12 to the width of the gate structure 12. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0095] The multiple gate structures 12 may be arranged at intervals of 0.1 μm to 2 μm. The interval between the gate structures 12 is the distance between the multiple gate structures 12 in the horizontal direction (second direction Y). The interval between the gate structures 12 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The interval between the gate structures 12 is preferably 1 μm or less.

[0096] Each of the gate structures 12 includes a trench 57, an insulating film 58, a buried electrode 59, and a buried insulator 60. The trench 57 may be referred to as a "gate trench," the insulating film 58 may be referred to as a "gate insulating film," the buried electrode 59 may be referred to as a "gate electrode," and the buried insulator 60 may be referred to as a "cap insulator (film)." The trench 57 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structures 12.

[0097] The insulating film 58 covers the wall surface of the trench 57. In this embodiment, the insulating film 58 has an upper end portion positioned on the bottom wall side of the trench 57 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 57. The upper end portion of the insulating film 58 is preferably positioned on the opening side of the trench 57 relative to the depth position of the intermediate part of the trench 57.

[0098] The insulating film 58 includes a first film portion 63 and a second film portion 64. The first film portion 63 has a relatively small first thickness and covers the wall surfaces of the inner portion of the trench 57. The first film portion 63 is formed as a main body portion of the insulating film 58 (gate insulating film). The first film portion 63 covers the wall surfaces of the inner portion of the trench 57 at a distance inward from the longitudinal ends (both ends in this embodiment) of the trench 57. The first film portion 63 covers the side walls and bottom wall of the trench 57.

[0099] The ratio of the covering area (hiding area) of the first film portion 63 to the surface area of ​​the wall surface of the trench 57 may be 0.5 or more and less than 1. The ratio of the first film portion 63 may have a value belonging to at least one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0100] In this embodiment, the first film portion 63 has an upper end portion positioned on the bottom wall side of the trench 57 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 57. The upper end portion of the first film portion 63 forms the upper end portion of the insulating film 58 in the inner part of the trench 57. It is preferable that the upper end portion of the first film portion 63 be positioned on the opening side of the trench 57 relative to the depth position of the intermediate part of the trench 57.

[0101] The first film portion 63 has a single-layer structure made of a first insulating film 65. The first insulating film 65 directly covers the wall surfaces of the trench 57 in a film-like manner. The first insulating film 65 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0102] In this embodiment, the first insulating film 65 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of a silicon oxide film without impurities added, a silicon oxide film containing phosphorus, or a silicon oxide film containing both phosphorus and boron.

[0103] A silicon oxide film without added impurities may be called an NSG film (nondoped silicate glass film), a silicon oxide film containing phosphorus may be called a PSG film (phosphorus silicon glass film), and a silicon oxide film containing both phosphorus and boron may be called a BPSG film (boron phosphorus silicon glass film).

[0104] The first film portion 63 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the first insulating film 65 is made of an NSG film. Of course, the first film portion 63 (first insulating film 65) may also be made of a silicon oxide film made of the oxide of the chip 2.

[0105] The first thickness of the first film portion 63 (the thickness of the first insulating film 65) may be 10 nm or more and 250 nm or less. The first thickness may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or more, and 225 nm or more and 250 nm or less.

[0106] The second film portion 64 has a second thickness greater than the first thickness of the first film portion 63, and covers the wall surfaces at the ends (both ends in this embodiment) of the trench 57. The second film portion 64 covers the area outside the first film portion 63 on the wall surfaces on the end sides of the trench 57, and is continuous with the first film portion 63. The second film portion 64 covers the side walls and bottom wall of the trench 57.

[0107] The ratio of the coverage area (concealment area) of the second film portion 64 to the surface area of ​​the wall surface of the trench 57 is less than the ratio of the coverage area (concealment area) of the first film portion 63 to the surface area of ​​the wall surface of the trench 57. The ratio of the second film portion 64 may be greater than 0 and less than 0.5. The ratio of the second film portion 64 may have a value belonging to at least one of the ranges greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to less than 0.5.

[0108] In this embodiment, the second film portion 64 has an upper end portion positioned on the bottom wall side of the trench 57 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 57. The upper end portion of the second film portion 64 forms the upper end portion of the insulating film 58 at the end of the trench 57. It is preferable that the upper end portion of the second film portion 64 be positioned on the opening side of the trench 57 relative to the depth position of the intermediate part of the trench 57.

[0109] The second film portion 64 has a layered structure including a second insulating film 66 and a third insulating film 67, which are layered in this order from the bottom wall side of the trench 57. The second insulating film 66 directly covers the wall surface of the trench 57 at the end of the trench 57 in a film-like manner. The second insulating film 66 also covers the sidewalls and bottom wall of the trench 57 in a film-like manner.

[0110] 12 , the second insulating film 66 is formed in the trench 57 in a terminated shape and defines the end of the second film portion 64. The second insulating film 66 has ends on the sidewalls and bottom wall of the trench 57. The ends of the second insulating film 66 may have inclined portions that are obliquely inclined with respect to the wall surfaces of the trench 57.

[0111] The second insulating film 66 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 66 may include an insulator that is the same as or different from that of the first insulating film 65. In this embodiment, the second insulating film 66 has a single-layer structure made of a silicon oxide film.

[0112] The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The second insulating film 66 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the second insulating film 66 is made of an NSG film. The thickness of the second insulating film 66 may be greater or smaller than the first thickness of the first insulating film 65 (first film portion 63). The thickness of the second insulating film 66 may be approximately equal to the first thickness of the first insulating film 65 (first film portion 63).

[0113] The thickness of the second insulating film 66 may be 10 nm or more and 250 nm or less. The thickness of the second insulating film 66 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0114] The third insulating film 67 directly covers the second insulating film 66 in the trench 57. The third insulating film 67 covers the sidewalls and bottom wall of the trench 57 with the second insulating film 66 sandwiched therebetween. With reference to FIG. 12 , the third insulating film 67 has a covering portion for covering the end of the second insulating film 66, and is connected to the first insulating film 65 at the end of the second insulating film 66.

[0115] The third insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third insulating film 67 may include an insulator that is the same as or different from the first insulating film 65. The third insulating film 67 may include an insulator that is the same as or different from the second insulating film 66.

[0116] In this embodiment, the third insulating film 67 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the third insulating film 67 is made of an NSG film.

[0117] In this embodiment, the third insulating film 67 is made of the same insulating film as the first insulating film 65 and is formed integrally with the first insulating film 65. The third insulating film 67 is formed by a portion of the first insulating film 65 that covers the second insulating film 66. In other words, the first insulating film 65 extends from the wall surface of the trench 57 onto the second insulating film 66 as the third insulating film 67, and covers the second insulating film 66 in a film-like manner.

[0118] The thickness of the third insulating film 67 is approximately equal to the first thickness of the first insulating film 65 (first film portion 63). The thickness of the third insulating film 67 may be greater or smaller than the thickness of the first insulating film 65. The thickness of the third insulating film 67 may be greater or smaller than the thickness of the second insulating film 66. The thickness of the third insulating film 67 may be approximately equal to the thickness of the second insulating film 66.

[0119] The thickness of the third insulating film 67 may be 10 nm or more and 250 nm or less. The thickness of the third insulating film 67 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0120] The second thickness of the second film portion 64 (the total thickness of the second insulating film 66 and the third insulating film 67) may be 20 nm to 500 nm. The second thickness may have a value belonging to at least one of the ranges of 20 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0121] The buried electrode 59 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 59 is preferably made of n-type conductive polysilicon. The buried electrode 59 is buried in the trench 57 with an insulating film 58 interposed therebetween, and faces the second semiconductor layer 10 and the active well region 14 with the insulating film 58 interposed therebetween.

[0122] The buried electrode 59 is buried in the trench 57 with the first film portion 63 and the second film portion 64 sandwiched therebetween, and is in contact with the first film portion 63 and the second film portion 64 within the trench 57. The buried electrode 59 is in contact with the first insulating film 65 and the third insulating film 67. The buried electrode 59 has a portion that is in contact with the step between the first film portion 63 and the second film portion 64.

[0123] The buried electrode 59 faces the second semiconductor layer 10 and the active well region 14 across the first film portion 63 at the inner part of the trench 57, and faces the second semiconductor layer 10 and the active well region 14 across the second film portion 64 at the end of the trench 57.

[0124] The buried electrode 59 has an electrode surface exposed from the trench 57. The electrode surface is located on the bottom wall side of the trench 57 at a distance from the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the intermediate portion of the trench 57. The electrode surface may also be located on the bottom wall side of the trench 57 with respect to the depth position of the intermediate portion of the trench 57.

[0125] The electrode surface is located closer to the bottom wall of the trench 57 than the upper end of the insulating film 58, and exposes a portion of the insulating film 58 that covers the side wall at the opening side of the trench 57. The electrode surface may be located closer to the first main surface 3 than the upper end of the insulating film 58. The electrode surface and the side wall of the trench 57 define a recess space within the trench 57.

[0126] The electrode surface is located in the inner part of the trench 57 closer to the bottom wall of the trench 57 than the upper end of the first film portion 63. The electrode surface may be located closer to the first main surface 3 than the upper end of the first film portion 63. The electrode surface is located at the end of the trench 57 closer to the bottom wall of the trench 57 than the upper end of the second film portion 64. The electrode surface may be located closer to the first main surface 3 than the upper end of the second film portion 64.

[0127] The buried insulator 60 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It may have a single-layer structure including a single silicon oxide film or a stacked structure including multiple silicon oxide films. The single or multiple silicon oxide films may include at least one of an NSG film, a PSG film, and a BPSG film.

[0128] The buried insulator 60 is buried above the buried electrode 59 in the trench 57 and covers the buried electrode 59. In this embodiment, the buried insulator 60 is buried in the trench 57 with the insulating film 58 sandwiched therebetween, and is in contact with the insulating film 58 and the buried electrode 59 within the trench 57. The buried insulator 60 has a portion that faces the chip 2 in the horizontal direction with the insulating film 58 sandwiched therebetween, and exposes the first main surface 3.

[0129] The buried insulator 60 is buried in the trench 57 with the first film portion 63 and the second film portion 64 sandwiched therebetween, and is in contact with the first film portion 63 and the second film portion 64 within the trench 57. The buried insulator 60 is in contact with the first insulating film 65 and the third insulating film 67. The buried insulator 60 has a portion that is in contact with the step between the first film portion 63 and the second film portion 64.

[0130] The buried insulator 60 faces the second semiconductor layer 10 and the active well region 14 at the inner part of the trench 57, with a first film portion 63 in between, and faces the second semiconductor layer 10 and the active well region 14 at the end of the trench 57, with a second film portion 64 in between. The buried insulator 60 is buried in the trench 57 at a distance from the height position of the first main surface 3 to the bottom wall side of the trench 57, and exposes a part of the chip 2 from the opening end of the trench 57.

[0131] The buried insulator 60 has an insulating surface exposed from the trench 57. The insulating surface is located on the bottom wall side of the trench 57 relative to the height of the first main surface 3. The insulating surface is located on the opening side of the trench 57 relative to the depth of the intermediate portion of the trench 57. The insulating surface may also be located on the bottom wall side of the trench 57 relative to the depth of the intermediate portion of the trench 57.

[0132] The insulating surface exposes the upper end of the insulating film 58. In this embodiment, the insulating surface is flat and continuous with the upper end of the insulating film 58. The insulating surface is formed flush with the upper end of the insulating film 58. The insulating surface may be formed flush with the first main surface 3 together with the upper end of the insulating film 58. The insulating surface may be located closer to the first main surface 3 or closer to the bottom wall of the trench 57 than the upper end of the insulating film 58.

[0133] In this embodiment, the insulating surface has a raised portion that rises from the sidewall of the trench 57 toward the inside of the trench 57. The raised portion of the insulating surface is located closer to the bottom wall of the trench 57 than the height position of the first main surface 3. The raised portion of the insulating surface may protrude above the height position of the first main surface 3. Instead of the raised portion, the insulating surface may have a recess that sinks from the sidewall of the trench 57 toward the inside of the trench 57. The insulating surface may be formed flush with the first main surface 3.

[0134] In this embodiment, the buried insulator 60 has a thickness greater than the thickness of the insulating film 58 in the depth direction of the trench 57. The thickness of the buried insulator 60 is preferably greater than the second thickness of the second film portion 64. The thickness of the buried insulator 60 is preferably less than the thickness of the buried electrode 59.

[0135] The ratio of the thickness of the buried insulator 60 to the depth of the trench 57 may be greater than 0 and less than or equal to 0.5. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0136] The semiconductor device 1 includes a plurality of mesa portions 68 defined on the first main surface 3 in the active region 6. Each mesa portion 68 provides a unit cell UC of a trench-gate transistor. Each mesa portion 68 includes at least an active well region 14 and a source region 71 (described later), and may be the minimum unit that functions as a MIS transistor.

[0137] The multiple mesa portions 68 are defined in regions between adjacent multiple gate structures 12. The multiple mesa portions 68 are defined at intervals in the second direction Y, following the layout of the multiple gate structures 12, and each extend in a band shape in the first direction X. The multiple mesa portions 68 extend in a stripe shape in the first direction X. The width of each mesa portion 68 corresponds to the spacing between the multiple gate structures 12.

[0138] The semiconductor device 1 includes a plurality of p-type bottom well regions 16 formed in the chip 2 (second semiconductor layer 10). The plurality of bottom well regions 16 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 10, and convert the conductivity type of the second semiconductor layer 10 from n-type to p-type. A source potential is applied to the plurality of bottom well regions 16.

[0139] The plurality of bottom well regions 16 are formed in the second semiconductor layer 10 in regions below (specifically, directly below) the plurality of gate structures 12, spaced apart from one another in the horizontal direction (second direction Y). The plurality of bottom well regions 16 are formed in the thickness range between the bottom of the second semiconductor layer 10 and the bottom walls of the plurality of gate structures 12, and overlap with the plurality of gate structures 12 in a one-to-one correspondence in the thickness direction.

[0140] The bottom well regions 16 each extend in a strip shape in the first direction X in plan view, following the extension direction of the corresponding gate structures 12. The bottom well regions 16 are arranged in a stripe shape in plan view, extending in the first direction X. The extension direction of the bottom well regions 16 coincides with the off-direction of the SiC single crystal.

[0141] 12 , with respect to the first direction X, both ends of the plurality of bottom well regions 16 may be located inward of both ends of the plurality of gate structures 12, or may be located at positions coinciding with both ends of the plurality of gate structures 12. The plurality of bottom well regions 16 may extend in the second direction Y according to the extension direction of the plurality of gate structures 12. In this case, the plurality of bottom well regions 16 intersect (specifically, orthogonal to) the off-direction.

[0142] The plurality of bottom well regions 16 are formed at intervals from the bottom of the second semiconductor layer 10 to the bottom wall sides of the plurality of gate structures 12, and face the first semiconductor layer 9 across a part of the second semiconductor layer 10. Each of the plurality of bottom well regions 16 has an upper end located on the bottom wall side of the corresponding gate structure 12, and a bottom located on the bottom side of the second semiconductor layer 10.

[0143] The upper ends of the plurality of bottom well regions 16 are formed at intervals from the bottom of the active well region 14 toward the bottom wall of the corresponding gate structure 12. The upper ends of the plurality of bottom well regions 16 are connected to the bottom wall of the corresponding gate structure 12 and face the buried electrode 59 via the insulating film 58.

[0144] In this embodiment, the plurality of bottom well regions 16 each have a portion that is aligned with the first film portion 63 and a portion that is aligned with the second film portion 64. The plurality of bottom well regions 16 each have a portion that faces the buried electrode 59 across the first film portion 63, and a portion that faces the buried electrode 59 across the second film portion 64.

[0145] The upper ends of the plurality of bottom well regions 16 may have portions that extend along the sidewalls of the corresponding gate structures 12. The plurality of bottom well regions 16 may each have a portion that extends along the first film portion 63 and a portion that extends along the second film portion 64 on the sidewalls of the corresponding gate structures 12. The upper ends of the plurality of bottom well regions 16 may be formed at an interval from the bottom wall of the corresponding gate structure 12 toward the bottom of the second semiconductor layer 10.

[0146] The bottoms of the plurality of bottom well regions 16 may be located on the bottom wall side of the plurality of gate structures 12 or on the bottom side (second main surface 4 side) of the second semiconductor layer 10 relative to the depth position of the intermediate portion of the second semiconductor layer 10. The bottoms of the plurality of bottom well regions 16 are directly connected to the second semiconductor layer 10. The plurality of bottom well regions 16 form a JFET region Tj (Junction Field-Effect Transistor region) together with the second semiconductor layer 10 in the region below the gate structure 12.

[0147] In this embodiment, the depth of the bottom well region 16 relative to the bottom wall of the gate structure 12 is smaller than the depth of the gate structure 12 relative to the first main surface 3. The depth of the bottom well region 16 may be greater than the depth of the gate structure 12 relative to the first main surface 3.

[0148] The depth of the bottom well region 16 may be 0.5 μm or more and 5 μm or less. The depth of the bottom well region 16 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0149] The plurality of bottom well regions 16 each include a first well region 69 located on the bottom wall side of the gate structure 12 and a second well region 70 located on the bottom side of the second semiconductor layer 10. The first well region 69 is located on the bottom wall side of the gate structure 12 with respect to the depth position of the middle part of the bottom well region 16, and forms the upper end part of the bottom well region 16.

[0150] In the first direction X, both ends of the first well region 69 may be located inward of both ends of the gate structure 12, or may be located at positions coinciding with both ends of the plurality of gate structures 12. The first well region 69 may face the buried electrode 59 via the insulating film 58. The first well region 69 may have a portion facing the buried electrode 59 with the first film portion 63 interposed therebetween, and a portion facing the buried electrode 59 with the second film portion 64 interposed therebetween.

[0151] In this embodiment, the first well region 69 has a portion that is aligned with the first film portion 63 and a portion that is aligned with the second film portion 64. The first well region 69 has a portion that faces the buried electrode 59 across the first film portion 63, and a portion that faces the buried electrode 59 across the second film portion 64.

[0152] The first well region 69 may have a portion that extends along the sidewall of the gate structure 12. The first well region 69 may have a portion that extends along the first film portion 63 and a portion that extends along the second film portion 64 on the sidewall of the gate structure 12. The first well region 69 may be formed at an interval from the bottom wall of the gate structure 12 toward the bottom of the second semiconductor layer 10.

[0153] The ratio of the depth of the first well region 69 to the depth of the bottom well region 16 (first depth ratio) may be greater than 0 and less than or equal to 0.5. The first depth ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5. The first depth ratio is preferably less than 0.5.

[0154] The depth of the first well region 69 is smaller than the depth of the gate structure 12. The depth of the first well region 69 may be greater than 0 μm and less than or equal to 1 μm. The depth of the first well region 69 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The depth of the first well region 69 is preferably less than or equal to 0.5 μm.

[0155] The second well region 70 is located on the bottom side of the second semiconductor layer 10 relative to the first well region 69, and forms the bottom of the bottom well region 16. The second well region 70 extends in a strip shape in the first direction X following the extension direction of the gate structure 12. With respect to the first direction X, both ends of the second well region 70 may be located on the inward side of the gate structure 12 relative to both ends of the gate structure 12, or may be located at positions coinciding with both ends of the multiple gate structures 12.

[0156] In this embodiment, the second well region 70 has a portion located on the bottom wall side of the gate structure 12 corresponding to the depth position of the middle part of the bottom well region 16, and a portion located on the bottom side of the second semiconductor layer 10 corresponding to the depth position of the middle part of the bottom well region 16.

[0157] In this embodiment, the second well region 70 has a portion that is aligned with the first film portion 63 and a portion that is aligned with the second film portion 64. The second well region 70 has a portion that faces the first film portion 63 across the first well region 69, and a portion that faces the second film portion 64 across the first well region 69.

[0158] The depth of the second well region 70 is obtained by subtracting the depth of the first well region 69 from the depth of the bottom well region 16. The depth of the second well region 70 is the depth when the bottom of the first well region 69 is used as the reference. The ratio of the depth of the second well region 70 to the depth of the bottom well region 16 (second depth ratio) is calculated by "1 - first depth ratio".

[0159] The second depth ratio is preferably equal to or greater than 0.5. It is particularly preferable that the second depth ratio is greater than 0.5. In this embodiment, the depth of the second well region 70 is smaller than the depth of the gate structure 12. The depth of the second well region 70 may be greater than the depth of the gate structure 12.

[0160] The depth of the second well region 70 may be 0.5 μm or more and 5 μm or less. The depth of the second well region 70 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0161] The semiconductor device 1 includes a plurality of n-type source regions 71 formed in the active well region 14. The source regions 71 have a higher n-type impurity concentration than the p-type impurity concentration of the active well region 14, and convert the conductivity type of the active well region 14 from p-type to n-type. The n-type impurity concentration of the source regions 71 is higher than the n-type impurity concentration of the second semiconductor layer 10. The source regions 71 have a conductivity of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0162] The plurality of source regions 71 are formed in the plurality of mesa portions 68 in the surface layer portion of the active well region 14. In this embodiment, the plurality of source regions 71 are formed at intervals in the first direction X in a one-to-many correspondence with the plurality of mesa portions 68, and are adjacent to two gate structures 12 corresponding to each other in the second direction Y. In this embodiment, the plurality of source regions 71 each extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 12 in a plan view.

[0163] The plurality of source regions 71 on one side in the second direction Y face the plurality of source regions 71 on the other side in the second direction Y, with a corresponding gate structure 12 sandwiched between them. The plurality of source regions 71 are arranged in a line in the second direction Y in plan view. In this embodiment, the plurality of source regions 71 are arranged in a matrix with intervals in the first direction X and the second direction Y in plan view.

[0164] The plurality of source regions 71 on one side in the second direction Y may face regions between the plurality of source regions 71 on the other side in the second direction Y, with a corresponding gate structure 12 sandwiched therebetween. The plurality of source regions 71 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0165] The multiple source regions 71 each have a thickness (depth) less than the thickness (depth) of the active well region 14, and are formed at intervals from the bottom of the active well region 14 toward the first main surface 3. The multiple source regions 71 face the second semiconductor layer 10 with a part (bottom) of the active well region 14 between them.

[0166] The plurality of source regions 71 each have a bottom located closer to the bottom of the active well region 14 than the height of the electrode surfaces of the plurality of buried electrodes 59. The plurality of source regions 71 each have a portion located closer to the bottom walls of the plurality of trenches 57 than the electrode surfaces of the plurality of buried electrodes 59, and a portion located closer to the first main surface 3 than the electrode surfaces of the plurality of buried electrodes 59.

[0167] Each of the plurality of source regions 71 has a portion that faces the corresponding buried electrode 59 in the horizontal direction, with the corresponding insulating film 58 interposed therebetween, and a portion that faces the buried insulator 60 in the horizontal direction, with the corresponding insulating film 58 interposed therebetween. Each of the plurality of source regions 71 has a portion that faces the buried electrode 59, with the corresponding first film portion 63 interposed therebetween, and a portion that faces the buried insulator 60, with the corresponding first film portion 63 interposed therebetween.

[0168] 7, in this embodiment, the multiple source regions 71 are formed in portions along the first film portion 63 and spaced apart inward from the second film portion 64. In this embodiment, the multiple outermost source regions 71 are each formed inward from the second film portion 64 and spaced apart, and do not have portions along the second film portion 64. Of course, the one or more outermost source regions 71 may have a portion facing the buried electrode 59 across the corresponding second film portion 64, and a portion facing the buried insulator 60 across the corresponding second film portion 64.

[0169] The plurality of source regions 71 each have a portion located on the bottom wall side of the plurality of trenches 57 with respect to the insulating surfaces of the plurality of buried insulators 60, and a portion located on the first main surface 3 side with respect to the insulating surfaces of the plurality of buried insulators 60. In this embodiment, the plurality of source regions 71 each have a portion exposed from the opening end of the corresponding trench 57.

[0170] The source region 71 has a thickness (depth) greater than the thickness between the bottom of the active well region 14 and the bottom of the source region 71. The thickness of the source region 71 may be less than the thickness between the bottom of the active well region 14 and the bottom of the source region 71. Referring to Fig. 15, the thickness (depth) of the peripheral portions of the multiple source regions 71 gradually decreases along the first direction X from the bottom side of the active well region 14 toward the first main surface 3. The multiple source regions 71, together with the second semiconductor layer 10, define a channel CH that serves as a current path in the active well region 14.

[0171] The channel CH may have a channel length greater than 0 nm and less than or equal to 300 nm. The channel length is the shortest distance between the bottom of the active well region 14 and the bottom of the source region 71. The channel length may have a value belonging to at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0172] The semiconductor device 1 includes a plurality of active contact regions 72 formed in the chip 2 (second semiconductor layer 10) in the active region 6. A source potential is applied to the active contact regions 72. The active contact regions 72 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 10. The p-type impurity concentration of the active contact regions 72 is higher than the p-type impurity concentration of the active well region 14.

[0173] The p-type impurity concentration of the active contact region 72 is higher than the p-type impurity concentration of the second well region 70. The p-type impurity concentration of the active contact region 72 may be higher or lower than the p-type impurity concentration of the first well region 69. The p-type impurity concentration of the active contact region 72 may be higher or lower than the n-type impurity concentration of the source region 71.

[0174] The active contact regions 72 are formed in regions along the gate structures 12, respectively. The active contact regions 72 are formed at intervals in the first direction X in a one-to-many correspondence with the gate structures 12. Referring to Fig. 7 , in this embodiment, the active contact regions 72 are formed in a portion along the first film portion 63 at intervals inward from the second film portion 64.

[0175] The active contact regions 72 are respectively interposed in regions between the source regions 71. The active contact regions 72 may be connected to the source regions 71 in the first direction X. The active contact regions 72 may be formed at intervals from the source regions 71 in the first direction X. In this case, the active contact regions 72 may face the source regions 71 with a part of the active well region 14 sandwiched therebetween.

[0176] With respect to one and the other gate structures 12, the active contact regions 72 along one gate structure 12 face the active contact regions 72 along the other gate structure 12 in the second direction Y in a plan view. The active contact regions 72 are generally arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view.

[0177] In plan view, one of the plurality of active contact regions 72 may face a region between the other of the plurality of active contact regions 72 in the second direction Y. The plurality of active contact regions 72 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y in plan view.

[0178] The active contact regions 72 may extend in a strip-like shape in the first direction X in a plan view, following the extension direction of the gate structures 12. The lengths of the active contact regions 72 in the first direction X may be equal to or different from one another. The lengths of the active contact regions 72 in the first direction X are adjusted depending on the area of ​​the channel to be formed.

[0179] The channel area is the total area of ​​the portions of the source regions 71 exposed from the regions between the gate structures 12. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the active contact regions 72. The total planar area of ​​the active contact regions 72 is preferably less than the channel area. In the regions between the gate structures 12, the total planar area of ​​the active contact regions 72 is preferably less than the planar area of ​​the source regions 71.

[0180] The length of the active contact region 72 may be greater or less than the width of the gate structure 12. The length of the active contact region 72 may be greater or less than the spacing between the multiple gate structures 12 (the width of the mesa portion 68). The spacing between the multiple active contact regions 72 may be greater or less than the width of the gate structure 12. The spacing between the active contact regions 72 may be greater or less than the spacing between the multiple gate structures 12.

[0181] 16 , the plurality of active contact regions 72 each include a first region 72A, a second region 72B, and a third region 72C. The first region 72A is a portion extending along the bottom wall of the corresponding gate structure 12. The first region 72A is interposed in a region between the bottom wall of the corresponding gate structure 12 and the bottom of the corresponding bottom well region 16, and is connected to the bottom wall of the corresponding gate structure 12 and the corresponding bottom well region 16.

[0182] The first region 72A faces the buried electrode 59 via the insulating film 58. In this embodiment, the first region 72A faces the buried electrode 59 across the first film portion 63. Of course, if the active contact region 72 is formed in a portion along the second film portion 64, the first region 72A may face the buried electrode 59 across the second film portion 64.

[0183] The first region 72A has a thickness greater than that of the first well region 69, and has a bottom located closer to the bottom of the second well region 70 than the depth position of the lower end (bottom) of the first well region 69. The thickness of the first region 72A is the thickness of the first region 72A in the vertical direction Z, with the bottom wall of the gate structure 12 as the reference.

[0184] The bottom of the first region 72A is formed at a distance from the bottom of the second well region 70 toward the bottom wall of the gate structure 12, and faces the second semiconductor layer 10 across a part of the second well region 70. The bottom of the first region 72A may be located on the bottom wall side of the gate structure 12 relative to the depth position of the intermediate portion of the second well region 70. The bottom of the first region 72A may be located on the bottom side of the second well region 70 relative to the depth position of the intermediate portion of the second well region 70.

[0185] The first region 72A has a width greater than that of the gate structure 12, and extends horizontally from a region directly below the corresponding gate structure 12 to both sides of the corresponding gate structure 12. The first region 72A is connected to the first well region 69 and the second well region 70, and increases the p-type impurity concentration of the first well region 69 and the p-type impurity concentration of the second well region 70.

[0186] The first region 72A may have a thickness less than that of the first well region 69, and may be formed at a distance from the depth position of the lower end of the first well region 69 toward the bottom wall of the gate structure 12. In this case, the first region 72A may face the second well region 70 with a part of the first well region 69 interposed therebetween.

[0187] The second region 72B is a portion that extends along the sidewall of the gate structure 12. In this embodiment, the second region 72B faces the buried electrode 59 across the first film portion 63. Of course, if the active contact region 72 is formed in a portion that is along the second film portion 64, the second region 72B may face the buried electrode 59 across the second film portion 64.

[0188] The second region 72B has a thickness less than that of the first region 72A. The thickness of the second region 72B is the horizontal thickness of the second region 72B based on the sidewall of the gate structure 12. The second region 72B is connected to the first region 72A on the bottom wall side of the gate structure 12, and is connected to the active well region 14 on the first main surface 3 side.

[0189] The second region 72B electrically connects the corresponding bottom well region 16 to the active well region 14. This prevents the bottom well region 16 from being electrically floating, improving the electrical response characteristics of the bottom well region 16.

[0190] The third region 72C is a portion that extends in a layer shape along the first main surface 3 in the surface layer portion of the first main surface 3 and is exposed from the first main surface 3. The third region 72C forms the upper end portion of the active contact region 72. In this embodiment, the upper end portion of the third region 72C is exposed from the sidewall of the trench 57 at the opening end of the trench 57.

[0191] The third region 72C is formed integrally with the third region 72C of the adjacent active contact region 72. The multiple active contact regions 72 are electrically connected to one another via the multiple third regions 72C. The third region 72C has a thickness (depth) less than the thickness (depth) of the active well region 14, and faces the second semiconductor layer 10 with a portion (bottom) of the active well region 14 interposed therebetween. The thickness of the third region 72C is the thickness of the third region 72C in the vertical direction Z, with the first main surface 3 as the reference.

[0192] The third region 72C has a bottom portion positioned on the first main surface 3 side relative to the height position of the electrode surfaces of the plurality of buried electrodes 59. The third region 72C has portions positioned on the opening end side of the plurality of trenches 57 relative to the electrode surfaces of the plurality of buried electrodes 59. The third region 72C has a portion facing the buried insulator 60 with the corresponding insulating film 58 interposed therebetween. The third region 72C has a portion facing the buried insulator 60 with the corresponding first film portion 63 interposed therebetween.

[0193] When the active contact region 72 is formed in a portion along the second film portion 64, the third region 72C may have a portion facing the embedded insulator 60 across the corresponding second film portion 64.

[0194] The third region 72C has portions located on the bottom wall side of the trenches 57 with respect to the insulating surfaces of the buried insulators 60, and portions located on the first main surface 3 side with respect to the insulating surfaces of the buried insulators 60. In this embodiment, the third region 72C has portions exposed from the opening ends of the corresponding trenches 57.

[0195] The thickness of the third region 72C is greater than the thickness of the second region 72B. The thickness of the third region 72C may be approximately equal to the thickness of the first region 72A. The thickness of the third region 72C may be greater or less than the thickness of the first region 72A. The thickness of the third region 72C is less than the thickness (depth) of the source region 71. The third region 72C has a bottom located closer to the first main surface 3 than the bottom of the source region 71.

[0196] The thickness of the third region 72C may be greater than the thickness of the source region 71. The thickness of the third region 72C may be less than the thickness between the bottom of the active well region 14 and the bottom of the third region 72C. The thickness of the third region 72C may be less than the thickness between the bottom of the active well region 14 and the bottom of the third region 72C.

[0197] (4) Well Structure in Peripheral Region 8 Next, the well structure in the peripheral region 8 of the semiconductor device 1 will be described with reference to FIGS.

[0198] 7 , semiconductor device 1 includes a p-type outer well region 15 formed in the surface layer portion of first main surface 3 in peripheral region 8 (the peripheral portion of first main surface 3). Outer well region 15 is a region that extends integrally from active well region 14 toward the peripheral portion of chip 2.

[0199] A source potential is applied to the outer well region 15. The outer well region 15 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 10. The p-type impurity concentration of the outer well region 15 may be higher or lower than the p-type impurity concentration of the active well region 14.

[0200] The p-type impurity concentration of the outer well region 15 is lower than the p-type impurity concentration of the active contact region 72. The p-type impurity concentration of the outer well region 15 is lower than the p-type impurity concentration of the first well region 69. The p-type impurity concentration of the outer well region 15 may be higher or lower than the p-type impurity concentration of the second well region 70.

[0201] The outer well region 15 is formed in a surface layer portion of the second semiconductor layer 10. The outer well region 15 extends in a layered manner along the first main surface 3. The outer well region 15 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the plurality of gate structures 12. The outer well region 15 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 6) in a plan view.

[0202] The outer well region 15 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 6) of the first main surface 3. The outer well region 15 collectively surrounds the multiple gate structures 12. At the longitudinal ends of the multiple gate structures 12, the outer well region 15 extends across the multiple mesa portions 68.

[0203] The outer well region 15 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 15 has an inner edge portion on the side of the multiple gate structures 12 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 15 defines the boundary between the active region 6 and the outer periphery region 8.

[0204] The inner edge of the outer well region 15 is connected to the ends of the multiple gate structures 12 in a portion extending in the second direction Y. The inner edge of the outer well region 15 faces the buried electrode 59 with the insulating film 58 interposed therebetween. The outer well region 15 has a portion that extends along the second film portion 64 and faces the buried electrode 59 with the second film portion 64 interposed therebetween.

[0205] The inner edge of the outer well region 15 may be located closer to the inside of the gate structures 12 than the ends of the gate structures 12. The inner edge of the outer well region 15 may have a portion located in a region between the gate structures 12 and connected to the active well region 14. The outer edge of the outer well region 15 is spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 15.

[0206] The outer well region 15 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 15 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0207] 12 , the outer well region 15 is formed at a distance from the bottom of the second semiconductor layer 10 toward the first main surface 3, and faces the first semiconductor layer 9 across a part of the second semiconductor layer 10. The outer well region 15 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 10 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 10 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 10.

[0208] In this embodiment, the outer well region 15 is formed at a distance from the depth position of the bottom walls of the plurality of gate structures 12 toward the first main surface 3. The depth of the outer well region 15 may be greater or smaller than the depth of the active well region 14.

[0209] The outer well region 15 may have a portion located on the bottom side of the second semiconductor layer 10 relative to the depth positions of the bottom walls of the plurality of gate structures 12. In this case, the outer well region 15 may be connected to either or both of the first well region 69 and the second well region 70.

[0210] The outer well region 15 forms a pn junction with the second semiconductor layer 10. The outer well region 15 spreads a depletion layer into the second semiconductor layer 10 when a reverse bias voltage is applied. The depletion layer in the outer well region 15 spreads horizontally and in the thickness direction, and integrates with the depletion layers spreading from the active well region 14 and the bottom well region 16. The outer well region 15 expands the depletion layers spreading from the active well region 14 and the bottom well region 16 toward the peripheral edge of the first main surface 3, thereby mitigating the electric field intensity (electric field concentration) in the peripheral portion (outer peripheral region 8) of the first main surface 3.

[0211] 12 , semiconductor device 1 includes at least one (in this embodiment, multiple) p-type field region 17 formed in a surface layer portion of first main surface 3 in peripheral region 8 (the peripheral portion of first main surface 3). Multiple field regions 17 may be formed in an electrically floating state. Multiple field regions 17 may be fixed to the source potential.

[0212] The number of field regions 17 is arbitrary. The number of field regions 17 may be 1 or more and 20 or less. The number of field regions 17 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 17 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes three field regions 17.

[0213] The plurality of field regions 17 are formed at intervals from one another in the surface layer portion of the second semiconductor layer 10. The plurality of field regions 17 are formed at intervals inward from the periphery of the first main surface 3 in regions between the periphery of the first main surface 3 and the plurality of gate structures 12 (active regions 6). Specifically, the plurality of field regions 17 are formed in regions between the periphery of the first main surface 3 and the outer well region 15.

[0214] The field regions 17 extend in a strip shape along the gate structures 12 (active regions 6) in a plan view. Specifically, the field regions 17 extend in a strip shape along the outer well region 15. Each of the field regions 17 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0215] In this embodiment, the plurality of field regions 17 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the plurality of gate structures 12 (active regions 6) in plan view. The plurality of field regions 17 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0216] The plurality of field regions 17 are formed at intervals from the bottom of the second semiconductor layer 10 toward the first major surface 3, and face the first semiconductor layer 9 across a part of the second semiconductor layer 10. The plurality of field regions 17 may be formed at intervals from a depth position of the middle part of the second semiconductor layer 10 toward the first major surface 3, or may be located on the bottom side of the second semiconductor layer 10 (toward the second major surface 4) with respect to the depth position of the middle part of the second semiconductor layer 10.

[0217] In this embodiment, the field regions 17 are formed at intervals from the depth position of the bottom walls of the gate structures 12 toward the first main surface 3. The depth of the field regions 17 may be greater or smaller than the depth of the active well region 14 and the outer well region 15. The field regions 17 may have portions located on the bottom side of the second semiconductor layer 10 relative to the depth position of the bottom walls of the gate structures 12.

[0218] The plurality of field regions 17 form pn junctions with the second semiconductor layer 10. The plurality of field regions 17 expand a depletion layer into the second semiconductor layer 10 when a reverse bias voltage is applied. The depletion layers in the plurality of field regions 17 expand in the horizontal and thickness directions and integrate with the depletion layers expanding from the active well region 14 and the outer well region 15. The plurality of field regions 17 expand the depletion layers expanding from the active well region 14 and the outer well region 15 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 8) of the first main surface 3.

[0219] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 17 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 17 may be substantially uniform or non-uniform. The width of the multiple field regions 17 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 17 may gradually decrease toward the periphery of the first main surface 3.

[0220] The depth of the multiple field regions 17 may be approximately constant or non-uniform. The depth of the multiple field regions 17 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 17 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 17 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0221] The spacing between the multiple field regions 17 may be substantially uniform or non-uniform. The spacing between the multiple field regions 17 may gradually increase toward the peripheral edge of the first main surface 3. The spacing between the multiple field regions 17 may gradually decrease toward the peripheral edge of the first main surface 3.

[0222] The p-type impurity concentrations of the multiple field regions 17 may be substantially constant or non-uniform. The p-type impurity concentrations of the multiple field regions 17 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the multiple field regions 17 may gradually decrease toward the periphery of the first main surface 3.

[0223] The plurality of field regions 17 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the plurality of active well regions 14. The p-type impurity concentration of the plurality of field regions 17 may be higher or lower than the p-type impurity concentration of the plurality of active well regions 14.

[0224] The plurality of field regions 17 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the active contact region 72. The p-type impurity concentration of the plurality of field regions 17 may be higher or lower than the p-type impurity concentration of the active contact region 72.

[0225] The plurality of field regions 17 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the outer well region 15. The p-type impurity concentration of the plurality of field regions 17 may be higher or lower than the p-type impurity concentration of the outer well region 15.

[0226] (5) Structure of Main Surface Contact Region 53 (Direction Across Trench 57) Fig. 17 is a cross-sectional perspective view showing a main part of the boundary between the active region 6 and the peripheral region 8. Next, the structure of the main surface contact region 53 in the direction A across the trench 57 in the second direction Y will be described with reference to Figs.

[0227] The semiconductor device 1 includes a main surface contact region 53 formed in a surface layer portion of the well region 13 including the active well region 14 and the outer well region 15. The main surface contact region 53 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 15. The p-type impurity concentration of the main surface contact region 53 is higher than the p-type impurity concentration of the active well region 14.

[0228] The p-type impurity concentration of the main surface contact region 53 may be approximately equal to the p-type impurity concentration of the active contact region 72. The p-type impurity concentration of the main surface contact region 53 may be higher or lower than the p-type impurity concentration of the active contact region 72.

[0229] The main surface contact region 53 straddles the active well region 14 and the outer well region 15. A portion of the main surface contact region 53 may be formed in the active well region 14, and the remainder may be formed in the outer well region 15. As described above, the main surface contact region 53 may be formed in a ring shape in a planar view. In this embodiment, the main surface contact region 53 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a planar view, and surrounds the multiple gate structures 12 (active regions 6). The main surface contact region 53 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0230] The main surface contact region 53 may include an inner edge portion 73 in the active well region 14 and an outer edge portion 74 in the outer well region 15. In this embodiment, both the inner edge portion 73 and the outer edge portion 74 may be formed in an annular shape in plan view. The inner edge portion 73 and the outer edge portion 74 are formed in a continuous, concentric shape toward the peripheral edge side of the chip 2, thereby forming an integral main surface contact region 53 that is annular in plan view.

[0231] The main surface contact region 53 extends across the mesa portions 68 in the second direction Y at the longitudinal ends of the gate structures 12. The longitudinal ends of the gate structures 12 are covered with the main surface contact region 53.

[0232] 7 , the main surface contact region 53 is a region physically separated from the active contact region 72 that functions as a part of the MIS transistor. For example, the main surface contact region 53 may be physically separated from the outer end of the regularly arranged structure of the source regions 71 and the active contact regions 72 in a plan view.

[0233] In this configuration, source regions 71 and active contact regions 72 are alternately and regularly arranged in each mesa portion 68. In Fig. 7, the source region 71 is located at the outermost end of the repeated structure of source regions 71 and active contact regions 72. The main surface contact region 53 is physically separated from the outermost source region 71 by a portion of the active well region 14 interposed between the main surface contact region 53 and the source region 71 that constitutes the outermost end of the repeated structure.

[0234] 11 and 12, the main surface contact region 53 is formed at a distance from the bottom of the active well region 14 and the outer well region 15 toward the first main surface 3, and faces the second semiconductor layer 10 across a portion of the active well region 14 and the outer well region 15.

[0235] 11 and 17 , the plurality of main surface contact regions 53 each include a first region 53A, a second region 53B, and a third region 53C. The first region 53A is a portion extending along the bottom wall of the corresponding gate structure 12. The first region 53A is interposed in a region between the bottom wall of the corresponding gate structure 12 and the bottom of the corresponding bottom well region 16, and is connected to the bottom wall of the corresponding gate structure 12 and the corresponding bottom well region 16.

[0236] The first region 53A faces the buried electrode 59 via the insulating film 58. In this embodiment, the first region 53A faces the buried electrode 59 with the second film portion 64 sandwiched therebetween. The first region 53A has a thickness greater than that of the first well region 69, and has a bottom located closer to the bottom of the second well region 70 than the depth position of the lower end (bottom) of the first well region 69. The thickness of the first region 53A is the thickness of the first region 53A in the vertical direction Z, with the bottom wall of the gate structure 12 as the reference.

[0237] The bottom of the first region 53A is formed at a distance from the bottom of the second well region 70 toward the bottom wall of the gate structure 12, and faces the second semiconductor layer 10 across a part of the second well region 70. The bottom of the first region 53A may be located on the bottom wall side of the gate structure 12 with respect to the depth position of the intermediate portion of the second well region 70. The bottom of the first region 53A may be located on the bottom side of the second well region 70 with respect to the depth position of the intermediate portion of the second well region 70.

[0238] The first regions 53A have a width greater than that of the gate structures 12, and extend horizontally from the region directly below the corresponding gate structures 12 to both sides ( FIG. 11 ) and outside the longitudinal ends ( FIG. 12 ) of the corresponding gate structures 12. The first regions 53A are connected to the first well region 69 and the second well region 70, and increase the p-type impurity concentration of the first well region 69 and the p-type impurity concentration of the second well region 70.

[0239] The first region 53A may have a thickness less than that of the first well region 69, and may be formed at a distance from the depth position of the lower end of the first well region 69 toward the bottom wall of the gate structure 12. In this case, the first region 53A may face the second well region 70 with a part of the first well region 69 in between.

[0240] The second region 53B is a portion extending along the sidewall of the gate structure 12. The second region 53B faces the buried electrode 59 with the second film portion 64 interposed therebetween. The second region 53B has a thickness less than that of the first region 53A. The thickness of the second region 53B is the horizontal thickness of the second region 53B based on the sidewall of the gate structure 12. The second region 53B is connected to the first region 53A on the bottom wall side of the gate structure 12, and is connected to the active well region 14 and the outer well region 15 on the first main surface 3 side.

[0241] The second region 53B electrically connects the corresponding bottom well region 16 to the active well region 14 and the outer well region 15. This prevents the bottom well region 16 from being electrically floating, improving the electrical response characteristics of the bottom well region 16.

[0242] The third region 53C is a portion that extends in a layer shape along the first main surface 3 in the surface layer portion of the first main surface 3 and is exposed from the first main surface 3. The third region 53C forms the upper end portion of the main surface contact region 53. In this embodiment, the upper end portion of the third region 53C is exposed from the sidewall of the trench 57 at the opening end of the trench 57.

[0243] The third region 53C is formed integrally with the third region 53C of the adjacent main surface contact region 53. The multiple main surface contact regions 53 are electrically connected to each other via the multiple third regions 53C. The third region 53C has a thickness (depth) less than the thicknesses (depths) of the active well region 14 and the outer well region 15, and faces the second semiconductor layer 10 with a portion (bottom) of the active well region 14 and a portion (bottom) of the outer well region 15 sandwiched between them. The thickness of the third region 53C is the thickness of the third region 53C in the vertical direction Z, with the first main surface 3 as the reference.

[0244] 7 , the third regions 53C formed at the ends of the multiple mesas 68 are integrated with the peripheral region 8. The integrated third regions 53C extend toward the periphery of the chip 2 in the first direction X and cross the gate electrode film 32. In a plan view, the third regions 53C are covered with the gate electrode film 32.

[0245] The end of the third region 53C in the first direction X may be located closer to the periphery of the chip 2 (first to fourth side faces 5A to 5D) than the gate electrode film 32. The end of the third region 53C in the first direction X may be located directly below the gate electrode film 32. The end of the third region 53C in the first direction X may be located closer to the periphery of the chip 2 (first to fourth side faces 5A to 5D) than the underlying wiring layer 20 (extension 22). The end of the third region 53C in the first direction X may be located directly below the underlying wiring layer 20 (extension 22).

[0246] The third region 53C has a bottom portion positioned on the first main surface 3 side relative to the height position of the electrode surfaces of the plurality of embedded electrodes 59. The third region 53C has portions positioned on the opening end side of the plurality of trenches 57 relative to the electrode surfaces of the plurality of embedded electrodes 59. The third region 53C has a portion facing the embedded insulator 60 with the corresponding insulating film 58 interposed therebetween. The third region 53C has a portion facing the embedded insulator 60 with the corresponding second film portion 64 interposed therebetween.

[0247] The third region 53C has portions located on the bottom wall side of the trenches 57 with respect to the insulating surfaces of the buried insulators 60, and portions located on the first main surface 3 side with respect to the insulating surfaces of the buried insulators 60. The third region 53C has portions exposed from the opening ends of the corresponding trenches 57.

[0248] The thickness of the third region 53C is greater than the thickness of the second region 53B. The thickness of the third region 53C may be approximately equal to the thickness of the first region 53A. The thickness of the third region 53C may be greater or less than the thickness of the first region 53A. The thickness of the third region 53C is less than the thickness (depth) of the source region 71. The third region 53C has a bottom located closer to the first main surface 3 than the bottom of the source region 71.

[0249] The thickness of the third region 53C may be greater than the thickness of the source region 71. The thickness of the third region 53C may be less than the thickness between the bottom of the active well region 14 and the bottom of the third region 53C. The thickness of the third region 53C may be less than the thickness between the bottom of the active well region 14 and the bottom of the third region 53C.

[0250] (6) Structure of the Main Surface Contact Region 53 (Direction Along the Trench 57) Fig. 18 is an enlarged view of the portion surrounded by the two-dot chain line XVIII shown in Fig. 4. Fig. 19 is a cross-sectional view taken along the line IXX-IXX shown in Fig. 8. Fig. 20 is a cross-sectional view taken along the line XX-XX shown in Fig. 8.

[0251] 18 to 20 , in a region adjacent to the plurality of gate structures 12 arranged in a stripe pattern, the main surface contact region 53 extends along the trench 57. A portion of the main surface contact region 53 extending along the trench 57 may be an extension of the third region 72C of the active contact region 72. Referring to FIG. 18 , the main surface contact region 53 extending in the first direction X along the trench 57 intersects with and is connected to the third region 72C of the active contact region 72 which extends across the trench 57 in the second direction Y.

[0252] In plan view, the main surface contact region 53 extending along the trench 57 is covered with the main surface electrode film 31. The main surface contact region 53 faces the connection region 35 of the main surface electrode film 31.

[0253] (7) Laminated Structure on First Main Surface 3 Next, the laminated structure on the first main surface 3 will be described with reference to Figs. 21 and 22 in addition to Figs. 7 to 20. Fig. 21 is an enlarged view of the portion surrounded by the two-dot chain line XXI shown in Fig. 4. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21.

[0254] The semiconductor device 1 includes a surface insulating film 18 that selectively covers the first main surface 3. The surface insulating film 18 may also be referred to as a "main surface insulating film" or an "outer surface insulating film," etc. The surface insulating film 18 covers the first main surface 3 in the peripheral region 8 in a film-like manner.

[0255] The surface insulating film 18 covers the outer well region 15, the main surface contact region 53, and the plurality of field regions 17 in the peripheral region 8. The surface insulating film 18 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 18 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0256] The surface insulating film 18 extends from the peripheral region 8 to the active region 6 and covers the peripheries of the ends of the plurality of gate structures 12 in the active region 6. The surface insulating film 18 is connected to the insulating films 58 of the plurality of gate structures 12 and exposes the buried electrodes 59 and buried insulators 60. The surface insulating film 18 has portions located in regions between the plurality of gate structures 12. The surface insulating film 18 is connected to the insulating films 58 at both the portions of the ends of the plurality of gate structures 12 that extend in the first direction X and the portions that extend in the second direction Y.

[0257] The surface insulating film 18 includes a first surface film portion 75 and a second surface film portion 76. The first surface film portion 75 has a relatively small third thickness and covers the peripheries of the ends of the multiple gate structures 12. The first surface film portion 75 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The first surface film portion 75 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the multiple gate structures 12 (active regions 6) in a plan view.

[0258] The first surface film portion 75 is connected to the second film portion 64 of the insulating film 58 at the ends of the plurality of gate structures 12, and exposes the buried electrode 59 and the buried insulator 60. The first surface film portion 75 has a portion located in a region between the plurality of gate structures 12, and covers either or both of the active well region 14 and the outer well region 15.

[0259] The first surface film portion 75 is connected to the second film portion 64 at both the portions of the ends of the multiple gate structures 12 that extend in the first direction X and the portions that extend in the second direction Y. The first surface film portion 75 may or may not be connected to the first film portion 63.

[0260] 12 , the first surface film portion 75 is formed in a region between ends of the plurality of gate structures 12 and the plurality of field regions 17, and covers the outer well region 15. The first surface film portion 75 covers a region of the first main surface 3 that is closer to the inner side than the outer edge of the outer well region 15. The first surface film portion 75 covers a region of the first main surface 3 that is closer to the inner side than the outer edge of the main surface contact region 53.

[0261] The first surface film portion 75 has a width greater than the width of the gate structure 12. Of course, the width of the first surface film portion 75 may be smaller than the width of the gate structure 12. The width of the first surface film portion 75 is the width from the end of the gate structure 12 toward the periphery of the first main surface 3.

[0262] The width of the first surface film portion 75 may be greater than 0 μm and less than 5 μm. The width of the first surface film portion 75 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4 μm to 5 μm.

[0263] The first surface film portion 75 has a laminated structure including a first surface insulating film 77 and a second surface insulating film 78 laminated in this order from the first main surface 3 side. The first surface insulating film 77 covers the peripheries of the ends of the plurality of gate structures 12. The first surface insulating film 77 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The first surface insulating film 77 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 12 (active regions 6) in a plan view.

[0264] The first surface insulating film 77 is connected to the second insulating film 66 at ends of the plurality of gate structures 12, and exposes the buried electrodes 59 and the buried insulators 60. The first surface insulating film 77 has portions located in regions between the plurality of gate structures 12, and covers either or both of the active well region 14 and the outer well region 15. The first surface insulating film 77 is connected to the second insulating film 66 at both portions of the ends of the plurality of gate structures 12 that extend in the first direction X and the second direction Y.

[0265] The first surface insulating film 77 is formed in regions between the ends of the plurality of gate structures 12 and the plurality of field regions 17, and covers the outer well region 15. The first surface insulating film 77 covers a region closer to the ends of the plurality of gate structures 12 than the outer edge of the outer well region 15. The first surface insulating film 77 covers a region on the inner side of the first main surface 3 than the outer edge of the main surface contact region 53.

[0266] The first surface insulating film 77 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first surface insulating film 77 may include an insulator that is the same as or different from the first insulating film 65. The first surface insulating film 77 may include an insulator that is the same as or different from the second insulating film 66. The first surface insulating film 77 may include an insulator that is the same as or different from the third insulating film 67.

[0267] In this embodiment, the first surface insulating film 77 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The first surface insulating film 77 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the first surface insulating film 77 is made of an NSG film.

[0268] In this embodiment, the first surface insulating film 77 is made of the same insulating film as the second insulating film 66, and is formed integrally with the second insulating film 66. The first surface insulating film 77 is formed as an extension portion of the second insulating film 66, and is extended from the trench 57 onto the first main surface 3.

[0269] The thickness of the first surface insulating film 77 may be greater or less than the thickness of the first insulating film 65. The thickness of the first surface insulating film 77 may be greater or less than the thickness of the second insulating film 66. The thickness of the first surface insulating film 77 may be greater or less than the thickness of the third insulating film 67.

[0270] The thickness of the first surface insulating film 77 may be greater or less than the first thickness of the first film portion 63 (first insulating film 65). The thickness of the first surface insulating film 77 may be greater or less than the second thickness of the second film portion 64. In this embodiment, the thickness of the first surface insulating film 77 is approximately equal to the thickness of the second insulating film 66.

[0271] The thickness of the first surface insulating film 77 may be 10 nm or more and 250 nm or less. The thickness of the first surface insulating film 77 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0272] The second surface insulating film 78 directly covers the first surface insulating film 77 around the ends of the plurality of gate structures 12. The second surface insulating film 78 may have a portion extending in a strip shape in the first direction X following the extension direction of the first surface insulating film 77, and a portion extending in a strip shape in the second direction Y. The second surface insulating film 78 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 12 (active regions 6) in plan view.

[0273] The second surface insulating film 78 is connected to the third insulating film 67 of the insulating film 58 at ends of the plurality of gate structures 12, and exposes the buried electrodes 59 and the buried insulators 60. The second surface insulating film 78 has portions located in regions between the plurality of gate structures 12, and covers either or both of the active well region 14 and the outer well region 15 across the first surface insulating film 77. The second surface insulating film 78 is connected to the third insulating film 67 at both portions of the ends of the plurality of gate structures 12 that extend in the first direction X and that extend in the second direction Y.

[0274] The second surface insulating film 78 is formed in regions between ends of the plurality of gate structures 12 and the plurality of field regions 17, and covers the outer well region 15 across the first surface insulating film 77. The second surface insulating film 78 covers a region of the first main surface 3 that is closer to the inner side than the outer edge of the outer well region 15.

[0275] The second surface insulating film 78 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second surface insulating film 78 may include an insulator that is the same as or different from that of the first insulating film 65. The second surface insulating film 78 may include an insulator that is the same as or different from that of the second insulating film 66. The second surface insulating film 78 may include an insulator that is the same as or different from that of the third insulating film 67.

[0276] The second surface insulating film 78 may contain the same or a different insulator as the first surface insulating film 77. In this embodiment, the second surface insulating film 78 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the second surface insulating film 78 is made of an NSG film.

[0277] In this embodiment, the second surface insulating film 78 is made of the same insulating film as the third insulating film 67, and is formed integrally with the first insulating film 65 and the third insulating film 67. The second surface insulating film 78 is formed as an extension portion of the third insulating film 67 (first insulating film 65), and is extended from the trench 57 onto the first main surface 3.

[0278] The thickness of the second surface insulating film 78 may be greater or less than the first thickness of the first film portion 63. The thickness of the second surface insulating film 78 may be greater or less than the second thickness of the second film portion 64. The thickness of the second surface insulating film 78 may be greater or less than the thickness of the second insulating film 66. The thickness of the second surface insulating film 78 may be greater or less than the thickness of the third insulating film 67. The thickness of the second surface insulating film 78 may be greater or less than the thickness of the first surface insulating film 77. In this embodiment, the thickness of the second surface insulating film 78 is approximately equal to the thickness of the third insulating film 67.

[0279] The thickness of the second surface insulating film 78 may be 10 nm or more and 250 nm or less. The thickness of the second surface insulating film 78 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0280] The third thickness of the first surface film portion 75 (the total thickness of the first surface insulating film 77 and the second surface insulating film 78) is greater than the first thickness of the first film portion 63. In this embodiment, the third thickness is approximately equal to the second thickness of the second film portion 64. The third thickness may be greater or smaller than the second thickness of the second film portion 64.

[0281] The third thickness may be 20 nm to 500 nm. The third thickness may have a value belonging to at least one of the ranges of 20 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0282] The second surface film portion 76 has a fourth thickness different from the third thickness, and directly covers the first main surface 3 around the first surface film portion 75. The second surface film portion 76 has a width greater than the width of the first surface film portion 75, and covers in a film-like manner an area on the peripheral side of the first main surface 3 relative to the first surface film portion 75. The distance between the multiple gate structures 12 and the second surface film portion 76 corresponds to the width of the first surface film portion 75.

[0283] The second surface film portion 76 covers the outer well region 15 and the plurality of field regions 17 across the first surface film portion 75. The second surface film portion 76 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0284] The second surface film portion 76 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 12 (active regions 6) in a plan view. The second surface film portion 76 is continuous with the first to fourth side surfaces 5A to 5D. The second surface film portion 76 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0285] The second surface film portion 76 has a laminated structure including a third surface insulating film 79, a fourth surface insulating film 80, and a fifth surface insulating film 81, which are laminated in this order from the first main surface 3 side around the first surface film portion 75.

[0286] The third surface insulating film 79 directly covers the first main surface 3 around the first surface film portion 75. The third surface insulating film 79 covers, in film form, the region on the peripheral side of the first main surface 3 with respect to the first surface film portion 75. The third surface insulating film 79 covers the outer well region 15, the main surface contact region 53, and the plurality of field regions 17.

[0287] The third surface insulating film 79 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y. The third surface insulating film 79 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 12 (active regions 6) in a plan view. The second surface film portion 76 is continuous with the first to fourth side surfaces 5A to 5D. The third surface insulating film 79 is continuous with the first to fourth side surfaces 5A to 5D. The third surface insulating film 79 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose the peripheral edge portion of the first main surface 3.

[0288] The third surface insulating film 79 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third surface insulating film 79 may include an insulator that is the same as or different from the first insulating film 65. The third surface insulating film 79 may include an insulator that is the same as or different from the second insulating film 66. The third surface insulating film 79 may include an insulator that is the same as or different from the third insulating film 67.

[0289] The third surface insulating film 79 may contain the same or a different insulator as the first surface insulating film 77. The third surface insulating film 79 may contain the same or a different insulator as the second surface insulating film 78. In this embodiment, the third surface insulating film 79 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. It is preferable that the third surface insulating film 79 contains an oxide other than the oxide of the chip 2. In this embodiment, the third surface insulating film 79 is made of an NSG film.

[0290] The thickness of the third surface insulating film 79 may be greater or less than the first thickness of the first film portion 63. The thickness of the third surface insulating film 79 may be greater or less than the second thickness of the second film portion 64. The thickness of the third surface insulating film 79 may be greater or less than the thickness of the second insulating film 66. The thickness of the third surface insulating film 79 may be greater or less than the thickness of the third insulating film 67.

[0291] The thickness of the third surface insulating film 79 may be greater or smaller than the third thickness of the first surface film portion 75. The thickness of the third surface insulating film 79 may be greater or smaller than the thickness of the first surface insulating film 77. The thickness of the third surface insulating film 79 may be greater or smaller than the thickness of the second surface insulating film 78. In this embodiment, the thickness of the third surface insulating film 79 is greater than the thicknesses of the first insulating film 65, the second insulating film 66, the third insulating film 67, the first surface insulating film 77, and the second surface insulating film 78.

[0292] The thickness of the third surface insulating film 79 may be 10 nm or more and 1000 nm or less. The thickness of the third surface insulating film 79 may have a value belonging to at least one of the ranges of 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, 450 nm or more and 500 nm or less, 500 nm or more and 600 nm or less, 600 nm or more and 700 nm or less, 700 nm or more and 800 nm or less, 800 nm or more and 900 nm or more and 900 nm or more and 1000 nm or less.

[0293] The fourth surface insulating film 80 directly covers the third surface insulating film 79 around the first surface film portion 75. The fourth surface insulating film 80 covers the third surface insulating film 79 in a film-like manner in a region on the peripheral side of the first main surface 3 relative to the first surface film portion 75. The fourth surface insulating film 80 covers the outer well region 15, the main surface contact region 53, and the plurality of field regions 17 with the third surface insulating film 79 sandwiched therebetween.

[0294] The fourth surface insulating film 80 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y. The fourth surface insulating film 80 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 12 (active regions 6) in a plan view. The fourth surface insulating film 80 is continuous with the first to fourth side surfaces 5A to 5D. The fourth surface insulating film 80 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge portion of the first main surface 3 and the third surface insulating film 79.

[0295] The fourth surface insulating film 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fourth surface insulating film 80 may include an insulator that is the same as or different from the first insulating film 65. The fourth surface insulating film 80 may include an insulator that is the same as or different from the second insulating film 66. The fourth surface insulating film 80 may include an insulator that is the same as or different from the third insulating film 67.

[0296] The fourth surface insulating film 80 may include an insulator that is the same as or different from that of the first surface insulating film 77. The fourth surface insulating film 80 may include an insulator that is the same as or different from that of the second surface insulating film 78. The fourth surface insulating film 80 may include an insulator that is the same as or different from that of the third surface insulating film 79.

[0297] In this embodiment, the fourth surface insulating film 80 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the fourth surface insulating film 80 is made of an NSG film.

[0298] In this embodiment, the fourth surface insulating film 80 is made of the same insulating film as the first surface insulating film 77, and is connected to the first surface insulating film 77. The fourth surface insulating film 80 is formed integrally with the second insulating film 66 and the first surface insulating film 77. The fourth surface insulating film 80 is formed as an extension portion of the first surface insulating film 77, and is extended from above the first main surface 3 onto the third surface insulating film 79.

[0299] The thickness of the fourth surface insulating film 80 may be greater or less than the first thickness of the first film portion 63. The thickness of the fourth surface insulating film 80 may be greater or less than the second thickness of the second film portion 64. The thickness of the fourth surface insulating film 80 may be greater or less than the thickness of the second insulating film 66. The thickness of the fourth surface insulating film 80 may be greater or less than the thickness of the third insulating film 67.

[0300] The thickness of the fourth surface insulating film 80 may be greater or less than the third thickness of the first surface film portion 75. The thickness of the fourth surface insulating film 80 may be greater or less than the thickness of the first surface insulating film 77. The thickness of the fourth surface insulating film 80 may be greater or less than the thickness of the second surface insulating film 78. The thickness of the fourth surface insulating film 80 may be greater or less than the thickness of the third surface insulating film 79. In this embodiment, the thickness of the fourth surface insulating film 80 is approximately equal to the thickness of the second insulating film 66 and the thickness of the first surface insulating film 77.

[0301] The thickness of the fourth surface insulating film 80 may be 10 nm or more and 250 nm or less. The thickness of the fourth surface insulating film 80 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0302] The fifth surface insulating film 81 directly covers the fourth surface insulating film 80 around the first surface film portion 75. The fifth surface insulating film 81 covers the fourth surface insulating film 80 in a film-like manner in a region on the peripheral side of the first main surface 3 relative to the first surface film portion 75. The fifth surface insulating film 81 covers the outer well region 15, the main surface contact region 53, and the plurality of field regions 17 with the third surface insulating film 79 and the fourth surface insulating film 80 sandwiched therebetween.

[0303] The fifth surface insulating film 81 is continuous with the first to fourth side surfaces 5A to 5D. The fifth surface insulating film 81 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose at least one of the peripheral portion of the first main surface 3, the third surface insulating film 79, and the fourth surface insulating film 80.

[0304] The fifth surface insulating film 81 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fifth surface insulating film 81 may include an insulator that is the same as or different from the first insulating film 65. The fifth surface insulating film 81 may include an insulator that is the same as or different from the second insulating film 66. The fifth surface insulating film 81 may include an insulator that is the same as or different from the third insulating film 67.

[0305] The fifth surface insulating film 81 may include an insulator that is the same as or different from the first surface insulating film 77. The fifth surface insulating film 81 may include an insulator that is the same as or different from the second surface insulating film 78. The fifth surface insulating film 81 may include an insulator that is the same as or different from the third surface insulating film 79. The fifth surface insulating film 81 may include an insulator that is the same as or different from the fourth surface insulating film 80.

[0306] In this embodiment, the fifth surface insulating film 81 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. In this embodiment, the fifth surface insulating film 81 is made of an NSG film.

[0307] In this embodiment, the fifth surface insulating film 81 is made of the same insulating film as the second surface insulating film 78, and is connected to the second surface insulating film 78. The fifth surface insulating film 81 is formed integrally with the third insulating film 67 and the second surface insulating film 78. The fifth surface insulating film 81 is formed as an extension portion of the second surface insulating film 78, and is extended from above the first main surface 3 onto the fourth surface insulating film 80.

[0308] The thickness of the fifth surface insulating film 81 may be greater or less than the first thickness of the first film portion 63. The thickness of the fifth surface insulating film 81 may be greater or less than the second thickness of the second film portion 64. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the second insulating film 66. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the third insulating film 67.

[0309] The thickness of the fifth surface insulating film 81 may be greater or less than the third thickness of the first surface film portion 75. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the first surface insulating film 77. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the second surface insulating film 78. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the third surface insulating film 79. The thickness of the fifth surface insulating film 81 may be greater or less than the thickness of the fourth surface insulating film 80. In this embodiment, the thickness of the fifth surface insulating film 81 is approximately equal to the thickness of the third insulating film 67 and the thickness of the second surface insulating film 78.

[0310] The thickness of the fifth surface insulating film 81 may be 10 nm or more and 250 nm or less. The thickness of the fifth surface insulating film 81 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0311] The fourth thickness of the second surface film portion 76 (the total thickness of the third surface insulating film 79, the fourth surface insulating film 80, and the fifth surface insulating film 81) is greater than the first thickness, the second thickness, and the third thickness. The thickness ratio of the fourth thickness to the third thickness may be greater than 1 and less than or equal to 20. The thickness ratio may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 2.5, 2.5 to 5, 5 to 7.5, 7.5 to 10, 10 to 12.5, 12.5 to 15, 15 to 17.5, and 17.5 to 20.

[0312] The fourth thickness may be equal to or greater than 30 nm and equal to or less than 1500 nm. The fourth thickness may have a value belonging to at least one of the ranges of 30 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, 450 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, 900 nm to 1000 nm, 1000 nm to 1100 nm, 1100 nm to 1200 nm, 1200 nm to 1300 nm, 1300 nm to 1400 nm, and 1400 nm to 1500 nm.

[0313] The semiconductor device 1 includes an underlying wiring layer 20 disposed on the surface insulating film 18. The underlying wiring layer 20 includes a base portion 21 and an extension portion 22.

[0314] 7, 11 and 12, the extension portion 22 is selectively routed onto the surface insulating film 18 at intervals from the periphery of the first main surface 3 toward the multiple gate structures 12, and faces the outer well region 15 across the surface insulating film 18.

[0315] The extension portion 22 extends in a strip shape along the periphery of the plurality of gate structures 12. The extension portion 22 has a portion extending in the first direction X and a portion extending in the second direction Y. The extension portion 22 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 12.

[0316] The extension portion 22 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the extension portion 22 is disposed on the first surface film portion 75 and faces the outer well region 15 across the first surface film portion 75. The inner edge portion of the extension portion 22 covers the ends (both ends in this embodiment) of the multiple gate structures 12 and is mechanically and electrically connected to the multiple gate structures 12.

[0317] Specifically, the inner edge of the extension portion 22 is mechanically and electrically connected to the plurality of embedded electrodes 59. In this embodiment, the inner edge of the extension portion 22 is integrally formed with the plurality of embedded electrodes 59. The extension portion 22 is formed as an extension portion of the plurality of embedded electrodes 59, and is extended from the trench 57 onto the first surface film portion 75.

[0318] The inner edge of the extension 22 has a portion located in a region between the plurality of gate structures 12, and faces either or both of the active well region 14 and the outer well region 15 across the first surface film portion 75 (surface insulating film 18). The inner edge of the extension 22 is formed at a distance from the outermost source regions 71 and active contact regions 72 on the peripheral side of the first main surface 3.

[0319] The outer edge of the extension portion 22 is formed as an extension portion that is extended from above the first surface film portion 75 onto the second surface film portion 76, and is disposed on the second surface film portion 76. The outer edge of the extension portion 22 faces the outer well region 15 and the main surface contact region 53 with the second surface film portion 76 in between.

[0320] The outer edge of the extension 22 is formed at a distance from the field regions 17 toward the gate structures 12. Specifically, the outer edge of the extension 22 is formed at a distance from the outer edge of the outer well region 15 toward the gate structures 12.

[0321] The outer concealing area of ​​the extension portion 22 relative to the second surface film portion 76 is larger than the inner concealing area of ​​the extension portion 22 relative to the first surface film portion 75. The area ratio of the outer concealing area to the inner concealing area may be greater than 1 and less than or equal to 25.

[0322] The area ratio may have a value belonging to at least one of the ranges of greater than 1 and 2.5 or less, 2.5 or more and 5 or less, 5 or more and 7.5 or less, 7.5 or more and 10 or less, 10 or more and 12.5 or less, 12.5 or more and 15 or less, 15 or more and 17.5 or less, 17.5 or more and 20 or less, 20 or more and 22.5 or less, and 22.5 or more and 25 or less. The area ratio is preferably 5 or more. The area ratio is preferably 15 or less.

[0323] 21 and 22 , the base portion 21 faces the outer well region 15 with the surface insulating film 18 interposed therebetween. In this embodiment, the base portion 21 is disposed on the second surface film portion 76 and faces the outer well region 15 and the main surface contact region 53 with the second surface film portion 76 interposed therebetween.

[0324] The base portion 21 is formed in a ring shape in plan view that surrounds the gate pad electrode 36. In this embodiment, the base portion 21 is formed in a quadrangular ring shape that is parallel to the four sides of the quadrangular gate pad electrode 36 in plan view. The base portion 21 has a first portion 82, a second portion 83, a third portion 84, and a fourth portion 85 that correspond to the respective sides of the quadrangular ring shape.

[0325] The first portion 82 is disposed in a position of the base portion 21 close to the side surface of the chip 2 (in this embodiment, the first side surface 5A). The first portion 82 is the base end portion of the first extension portion 23 and the second extension portion 24, and may integrally form a strip-shaped finger base portion with the first extension portion 23 and the second extension portion 24. The first portion 82 has a gate protrusion 86 that protrudes toward the inside of the gate pad electrode 36 in a plan view. The gate protrusion 86 is disposed at a distance from the third portion 84 and the fourth portion 85. As a result, the internal opening 97 of the annular base portion 21 has spaces 87 that selectively protrude between the gate protrusion 86 and the third portion 84 and the fourth portion 85.

[0326] The second portion 83 is disposed on the opposite side of the gate pad electrode 36 from the first portion 82. The second portion 83 is a base end portion of the third extension portion 25, and is formed in a strip shape that is perpendicular to the third extension portion 25. The first portion 82 and the second portion 83 provide a pair of sides of the base portion 21 that face each other.

[0327] The third portion 84 and the fourth portion 85 face each other in the first direction X across the gate pad electrode 36, and connect the first portion 82 and the second portion 83. The third portion 84 and the fourth portion 85 provide a pair of opposing sides of the base portion 21. A plurality of embedded electrodes 59 extend in the first direction X with the third portion 84 and the fourth portion 85 as base ends.

[0328] The semiconductor device 1 includes an insulating interlayer insulating film 29 that covers the surface insulating film 18. The interlayer insulating film 29 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer insulating film 29 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0329] The interlayer insulating film 29 may contain the same or a different insulator as the first surface insulating film 77. The interlayer insulating film 29 may contain the same or a different insulator as the second surface insulating film 78. The interlayer insulating film 29 may contain the same or a different insulator as the third surface insulating film 79. The interlayer insulating film 29 may contain the same or a different insulator as the fourth surface insulating film 80. The interlayer insulating film 29 may contain the same or a different insulator as the fifth surface insulating film 81.

[0330] The interlayer insulating film 29 may have a single-layer structure made of a single silicon oxide film or a multi-layer structure including multiple silicon oxide films. The single or multiple silicon oxide films may include at least one of an NSG film, a PSG film, and a BPSG film. The interlayer insulating film 29 preferably includes the same type of insulator as the buried insulator 60.

[0331] The interlayer insulating film 29 covers the surface insulating film 18 in the peripheral region 8. Specifically, the interlayer insulating film 29 directly covers the second surface film portion 76 in the form of a film, and faces the outer well region 15, the main surface contact region 53, and the plurality of field regions 17 with the second surface film portion 76 in between.

[0332] The interlayer insulating film 29 covers the underlying wiring layer 20. The interlayer insulating film 29 covers the entire extension portion 22 and the entire base portion 21. The interlayer insulating film 29 has a portion facing the first surface film portion 75 across the extension portion 22 and a portion facing the second surface film portion 76 across the extension portion 22. The interlayer insulating film 29 has a portion facing the outer well region 15 across the extension portion 22 and a portion facing the outer well region 15 across the base portion 21. The interlayer insulating film 29 has a portion facing the main surface contact region 53 across the extension portion 22 and a portion facing the main surface contact region 53 across the base portion 21.

[0333] The interlayer insulating film 29 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer insulating film 29 is disposed in the active region 6. The inner edge portion of the interlayer insulating film 29 is positioned on the inner side of the first main surface 3 with respect to the inner edge portion of the extension portion 22 and the peripheral edge portion of the base portion 21, and covers the ends of the multiple gate structures 12.

[0334] The inner edge of the interlayer insulating film 29 covers the buried electrodes 59 at the ends of the multiple gate structures 12 and is connected to the buried insulator 60. In this embodiment, the interlayer insulating film 29 is formed integrally with the buried insulator 60. The portion of the interlayer insulating film 29 located inside the trench 57 is formed as the buried insulator 60. The connection portion of the interlayer insulating film 29 to the buried insulator 60 may be regarded as part of the buried insulator 60 or may be regarded as part of the interlayer insulating film 29.

[0335] The inner edge portion of the interlayer insulating film 29 has a portion located in a region between the plurality of gate structures 12. The inner edge portion of the interlayer insulating film 29 covers either or both of the active well region 14 and the outer well region 15 in the region between the plurality of gate structures 12, with the surface insulating film 18 (first surface film portion 75) sandwiched therebetween.

[0336] The outer edge of the interlayer insulating film 29 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer insulating film 29 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 18. The outer edge of the interlayer insulating film 29 may expose at least one of the peripheral edge of the first main surface 3, the third surface insulating film 79, the fourth surface insulating film 80, and the fifth surface insulating film 81.

[0337] The thickness of the interlayer insulating film 29 may be greater or less than the first thickness of the first film portion 63. The thickness of the interlayer insulating film 29 may be greater or less than the second thickness of the second film portion 64. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the first insulating film 65. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the second insulating film 66. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the third insulating film 67.

[0338] The thickness of the interlayer insulating film 29 may be greater or less than the third thickness of the first surface film portion 75. The thickness of the interlayer insulating film 29 may be greater or less than the fourth thickness of the second surface film portion 76. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the first surface insulating film 77. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the second surface insulating film 78. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the third surface insulating film 79. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the fourth surface insulating film 80. The thickness of the interlayer insulating film 29 may be greater or less than the thickness of the fifth surface insulating film 81.

[0339] In this embodiment, the thickness of the interlayer insulating film 29 is greater than the first thickness, the second thickness, the third thickness, and the fourth thickness. The thickness of the interlayer insulating film 29 may be 0.01 μm or more and 5 μm or less. The thickness of the interlayer insulating film 29 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less.

[0340] The semiconductor device 1 includes one or more (one in this embodiment) contact openings 30 formed in the interlayer insulating film 29. The contact opening 30 penetrates the interlayer insulating film 29 in the inner portion of the active region 6, and collectively exposes the inner edges of the plurality of gate structures 12, the plurality of mesa portions 68, and the main surface contact region 53. In this embodiment, the contact opening 30 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion along the base portion 21).

[0341] The contact openings 30 are formed inwardly of the first main surface 3 at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 12, and expose the inner portions of the plurality of gate structures 12 and the inner portions of the plurality of mesa portions 68. Specifically, the contact openings 30 expose the insulating film 58 and the buried insulator 60 in the inner portions of the plurality of gate structures 12. The contact openings 30 expose at least the first film portion 63 of the insulating film 58. The contact openings 30 may also expose a portion of the second film portion 64 of the insulating film 58.

[0342] The semiconductor device 1 includes the aforementioned main surface electrode film 31 disposed on the first main surface 3. The main surface electrode film 31 collectively covers the region of the interlayer insulating film 29 where the contact opening 30 is formed, and extends from above the interlayer insulating film 29 into the contact opening 30. The main surface electrode film 31 has a portion that covers the interlayer insulating film 29 in a film-like manner, a portion that covers the wall surface of the contact opening 30 in a film-like manner, and a portion that covers the first main surface 3 within the contact opening 30 in a film-like manner.

[0343] The principal surface electrode film 31 has a portion that covers the plurality of gate structures 12 in the contact opening 30 and a portion that covers the plurality of mesa portions 68. The principal surface electrode film 31 directly covers the plurality of buried insulators 60 in the portion that covers the plurality of gate structures 12, and is electrically isolated from the plurality of buried electrodes 59 by the plurality of buried insulators 60.

[0344] In this embodiment, the principal surface electrode film 31 enters the plurality of trenches 57 from above the first principal surface 3 and covers the plurality of embedded insulators 60 within the plurality of trenches 57. The principal surface electrode film 31 has a portion that covers the insulating surfaces of the plurality of embedded insulators 60 in an area on the bottom wall side of the plurality of trenches 57 relative to the height position of the first principal surface 3.

[0345] The main surface electrode film 31 has portions that cover the side walls and opening ends of the plurality of trenches 57 within the plurality of trenches 57. The main surface electrode film 31 is mechanically and electrically connected to the plurality of source regions 71, the plurality of active contact regions 72, and the plurality of main surface contact regions 53 in the portions that cover the plurality of mesa portions 68.

[0346] The principal surface electrode film 31 has a peripheral edge portion that faces the ends (both ends) of the plurality of gate structures 12 across the interlayer insulating film 29. The peripheral edge portion of the principal surface electrode film 31 is drawn from the active region 6 to the peripheral region 8, and faces a part of the extension portion 22 across the interlayer insulating film 29.

[0347] The peripheral portion of the principal surface electrode film 31 has a portion facing the first surface film portion 75 across the extension portion 22 and the interlayer insulating film 29, and a portion facing the second surface film portion 76 across the extension portion 22 and the interlayer insulating film 29. The peripheral portion of the principal surface electrode film 31 has a portion facing the outer well region 15 across the extension portion 22 and the first surface film portion 75 in the stacking direction, and a portion facing the outer well region 15 across the extension portion 22 and the second surface film portion 76.

[0348] The peripheral portion of the principal surface electrode film 31 is formed at a distance from the plurality of field regions 17 toward the plurality of gate structures 12. Specifically, the peripheral portion of the principal surface electrode film 31 is formed at a distance from the outer edge of the outer well region 15 toward the plurality of gate structures 12. The peripheral portion of the principal surface electrode film 31 is formed at a distance from the outer edge of the extension portion 22 toward the inner edge of the extension portion 22. The peripheral portion of the principal surface electrode film 31 may be formed at a distance from the middle of the extension portion 22 toward the inner edge of the extension portion 22.

[0349] The peripheral edge portion of the principal surface electrode film 31 may be disposed on the inner side of the first principal surface 3 with respect to the second surface film portion 76, and may face the first surface film portion 75 in the stacking direction. The peripheral edge portion of the principal surface electrode film 31 may be formed at a distance from the extension portion 22 on the inner side of the first principal surface 3.

[0350] In this embodiment, the main surface electrode film 31 has a laminated structure including a lower electrode film 88 and a main electrode film 89 laminated in this order from the chip 2 side. With reference to Figures 13 and 14, in this embodiment, the lower electrode film 88 has a laminated structure including a first electrode film 90 and a second electrode film 91.

[0351] In this embodiment, the first electrode film 90 includes a Ti film, and the second electrode film 91 includes a TiN film. The lower electrode film 88 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 90 (Ti film) or the second electrode film 91 (TiN film).

[0352] The first electrode film 90 has a thickness less than the thickness of the interlayer insulating film 29. The thickness of the first electrode film 90 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 90 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0353] The second electrode film 91 has a thickness less than that of the interlayer insulating film 29. The thickness of the second electrode film 91 is preferably greater than that of the first electrode film 90. The thickness of the second electrode film 91 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 91 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0354] The first electrode film 90 covers the entire region of the interlayer insulating film 29 where the contact opening 30 is formed, and extends into the contact opening 30 from above the interlayer insulating film 29. The first electrode film 90 has a portion that covers the insulating surface of the interlayer insulating film 29 in a film-like manner, a portion that covers the wall surface of the contact opening 30 in a film-like manner, and a portion that covers the first main surface 3 within the contact opening 30 in a film-like manner.

[0355] The first electrode film 90 has a portion that covers the plurality of gate structures 12 in the contact opening 30 and a portion that covers the plurality of mesa portions 68. The first electrode film 90 directly covers the plurality of buried insulators 60 in the portion that covers the plurality of gate structures 12, and is electrically isolated from the plurality of buried electrodes 59 by the plurality of buried insulators 60.

[0356] In this embodiment, the first electrode film 90 enters the trenches 57 from above the first main surface 3 and covers the embedded insulators 60 within the trenches 57. In this embodiment, the first electrode film 90 has a portion that covers the insulating surfaces of the embedded insulators 60 in a region on the bottom wall side of the trenches 57 relative to the height position of the first main surface 3.

[0357] The first electrode film 90 has portions that cover the sidewalls and opening ends of the trenches 57 within the trenches 57. The first electrode film 90 is mechanically and electrically connected to the source regions 71, the active contact regions 72, and the main surface contact regions 53 in the portions that cover the sidewalls and opening ends of the trenches 57. The first electrode film 90 is mechanically and electrically connected to the source regions 71, the active contact regions 72, and the main surface contact regions 53 in the portions that cover the mesas 68.

[0358] The first electrode film 90 has a peripheral portion that faces the ends (both ends) of the multiple gate structures 12 across the interlayer insulating film 29. In this embodiment, the peripheral portion of the first electrode film 90 is drawn from the active region 6 to the peripheral region 8, and faces a part of the extension portion 22 across the interlayer insulating film 29.

[0359] The peripheral portion of the first electrode film 90 has a portion facing the first surface film portion 75 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween, and a portion facing the second surface film portion 76 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween. The peripheral portion of the first electrode film 90 has a portion facing the outer well region 15 with the extension portion 22 and the first surface film portion 75 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 15 with the extension portion 22 and the second surface film portion 76 sandwiched therebetween.

[0360] The peripheral portion of the first electrode film 90 is formed at a distance from the plurality of field regions 17 toward the plurality of gate structures 12. Specifically, the peripheral portion of the first electrode film 90 is formed at a distance from the outer edge of the outer well region 15 toward the plurality of gate structures 12. The peripheral portion of the first electrode film 90 is formed at a distance from the outer edge of the extension portion 22 toward the inner edge of the extension portion 22. The peripheral portion of the first electrode film 90 may be formed at a distance from the middle of the extension portion 22 toward the inner edge of the extension portion 22.

[0361] The second electrode film 91 directly covers the first electrode film 90. The second electrode film 91 collectively covers the region of the interlayer insulating film 29 where the contact opening 30 is formed, sandwiching the first electrode film 90 therebetween, and extends from above the interlayer insulating film 29 into the contact opening 30.

[0362] The second electrode film 91 has a portion that covers the interlayer insulating film 29 in a film state with the first electrode film 90 sandwiched between them, a portion that covers the wall surface of the contact opening 30 in a film state with the first electrode film 90 sandwiched between them, and a portion that covers the first main surface 3 in a film state with the first electrode film 90 sandwiched between them within the contact opening 30. The second electrode film 91 has a portion that covers the multiple gate structures 12 in the contact opening 30 with the first electrode film 90 sandwiched between them, and a portion that covers the multiple mesa portions 68 with the first electrode film 90 sandwiched between them.

[0363] The second electrode film 91 covers the plurality of embedded insulators 60 with the first electrode film 90 sandwiched therebetween, and is electrically isolated from the plurality of embedded electrodes 59. In this embodiment, the second electrode film 91 enters the plurality of trenches 57 from above the first main surface 3, and covers the plurality of embedded insulators 60 within the plurality of trenches 57 with the first electrode film 90 sandwiched therebetween.

[0364] In this embodiment, the second electrode film 91 covers the first electrode film 90 in regions on the bottom wall side of the plurality of trenches 57 relative to the height position of the first main surface 3. In this embodiment, the second electrode film 91 has portions that cover the side walls and opening ends of the plurality of trenches 57 with the first electrode film 90 sandwiched therebetween.

[0365] The second electrode film 91 is electrically connected to the source regions 71, the active contact regions 72, and the main surface contact regions 53 via the first electrode film 90 in a portion covering the sidewalls and opening ends of the trenches 57. The second electrode film 91 may be connected to the first electrode film 90 above the first main surface 3. The second electrode film 91 is electrically connected to the source regions 71, the active contact regions 72, and the main surface contact regions 53 via the first electrode film 90 in a portion covering the mesas 68.

[0366] The second electrode film 91 has a peripheral portion that faces the ends (both ends) of the plurality of gate structures 12, with the interlayer insulating film 29 and the first electrode film 90 sandwiched between them. The peripheral portion of the second electrode film 91 is drawn out from the active region 6 to the peripheral region 8, and faces a part of the extension portion 22, with the interlayer insulating film 29 and the first electrode film 90 sandwiched between them.

[0367] The peripheral portion of the second electrode film 91 has a portion facing the first surface film portion 75 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween, and a portion facing the second surface film portion 76 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween. The peripheral portion of the second electrode film 91 has a portion facing the outer well region 15 with the extension portion 22 and the first surface film portion 75 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 15 with the extension portion 22 and the second surface film portion 76 sandwiched therebetween.

[0368] The peripheral portion of the second electrode film 91 is formed at a distance from the plurality of field regions 17 toward the plurality of gate structures 12. Specifically, the peripheral portion of the second electrode film 91 is formed at a distance from the outer edge of the outer well region 15 toward the plurality of gate structures 12. The peripheral portion of the second electrode film 91 is formed at a distance from the outer edge of the extension portion 22 toward the inner edge of the extension portion 22. The peripheral portion of the second electrode film 91 may be formed at a distance from the middle of the extension portion 22 toward the inner edge of the extension portion 22.

[0369] The main electrode film 89 contains a metal material different from the metal material of the lower electrode film 88 (first electrode film 90 and second electrode film 91). The main electrode film 89 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film (Cu alloy film) may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 89 has a thickness greater than the thickness (total thickness) of the lower electrode film 88. The thickness of the main electrode film 89 is preferably greater than the thickness of the interlayer insulating film 29.

[0370] The thickness of the main electrode film 89 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 89 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0371] The main electrode film 89 directly covers the lower electrode film 88 (second electrode film 91). The main electrode film 89 backfills the contact opening 30 and collectively covers the region of the interlayer insulating film 29 where the contact opening 30 is formed. The main electrode film 89 has a portion that covers the interlayer insulating film 29 with the lower electrode film 88 in between, a portion that covers the wall surface of the contact opening 30 with the lower electrode film 88 in between, and a portion that covers the first main surface 3 with the lower electrode film 88 in between.

[0372] The main electrode film 89 has a portion that covers the plurality of gate structures 12 with the lower electrode film 88 sandwiched therebetween in the contact opening 30, and a portion that covers the plurality of mesa portions 68 with the lower electrode film 88 sandwiched therebetween. The main electrode film 89 covers the plurality of buried insulators 60 with the lower electrode film 88 sandwiched therebetween, and is electrically isolated from the plurality of buried electrodes 59.

[0373] The main electrode film 89 may extend into the plurality of trenches 57 from above the first main surface 3 and cover the plurality of embedded insulators 60 within the plurality of trenches 57 with the lower electrode film 88 sandwiched therebetween. In this case, the main electrode film 89 may have a portion that covers the sidewalls and opening ends of the plurality of trenches 57 with the lower electrode film 88 sandwiched therebetween in an area on the bottom wall side of the plurality of trenches 57 with respect to the height position of the first main surface 3. The main electrode film 89 may be connected to the lower electrode film 88 above the first main surface 3.

[0374] The main electrode film 89, in a portion covering the sidewalls and opening ends of the plurality of trenches 57, is electrically connected to the plurality of source regions 71, the plurality of active contact regions 72, and the plurality of main surface contact regions 53 via the lower electrode film 88. The main electrode film 89, in a portion covering the plurality of mesa portions 68, is electrically connected to the plurality of source regions 71, the plurality of active contact regions 72, and the plurality of main surface contact regions 53 via the lower electrode film 88.

[0375] The main electrode film 89 has a peripheral edge portion that faces the ends (both ends) of the plurality of gate structures 12, with the interlayer insulating film 29 and the lower electrode film 88 sandwiched therebetween. The peripheral edge portion of the main electrode film 89 may be drawn out from the active region 6 to the peripheral region 8, and may face a part of the extension portion 22, with the interlayer insulating film 29 and the lower electrode film 88 sandwiched therebetween.

[0376] The peripheral portion of the main electrode film 89 has a portion facing the first surface film portion 75 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween, and a portion facing the second surface film portion 76 with the extension portion 22 and the interlayer insulating film 29 sandwiched therebetween. The peripheral portion of the main electrode film 89 has a portion facing the outer well region 15 with the extension portion 22 and the first surface film portion 75 sandwiched therebetween in the stacking direction, and a portion facing the outer well region 15 with the extension portion 22 and the second surface film portion 76 sandwiched therebetween.

[0377] The peripheral portion of the main electrode film 89 is formed at a distance from the plurality of field regions 17 toward the plurality of gate structures 12. Specifically, the peripheral portion of the main electrode film 89 is formed at a distance from the outer edge of the outer well region 15 toward the plurality of gate structures 12. The peripheral portion of the main electrode film 89 is formed at a distance from the outer edge of the extension portion 22 toward the inner edge of the extension portion 22. The peripheral portion of the main electrode film 89 may also be formed at a distance from the middle of the extension portion 22 toward the inner edge of the extension portion 22.

[0378] 12 , 18 , 21 and 22 , the semiconductor device 1 includes one or more (a plurality in this embodiment) gate contact openings 92 formed in the interlayer insulating film 29. The plurality of gate contact openings 92 penetrate the interlayer insulating film 29. The plurality of gate contact openings 92 include a base gate contact opening 93, a pad contact opening 94, a peripheral gate contact opening 95 and an inner gate contact opening 96.

[0379] The base gate contact opening 93 is disposed directly above the second portion 83, the third portion 84, and the fourth portion 85 of the base portion 21 of the underlying wiring layer 20. The pad contact opening 94 is disposed directly above the gate protrusion 86 of the base portion 21 of the underlying wiring layer 20. The peripheral gate contact opening 95 is disposed directly above the first portion 82, the first extension portion 23, and the second extension portion 24 of the base portion 21 of the underlying wiring layer 20. The inner gate contact opening 96 is disposed directly above the third extension portion 25 of the underlying wiring layer 20.

[0380] The first extension 23, the second extension 24, the third extension 25, the base 21, and the gate protrusion 86 of the underlying wiring layer 20 are each formed in a strip shape or in a ring shape made up of a combination of strip-shaped portions. The multiple gate contact openings 92 are strip-shaped and extend along the longitudinal direction of the strip-shaped underlying wiring layer 20. The multiple gate contact openings 92 may be arranged at intervals in a direction perpendicular to the extension direction of the underlying wiring layer 20. The multiple gate contact openings 92 may extend parallel to each other.

[0381] The semiconductor device 1 includes the aforementioned gate electrode film 32 disposed on the first main surface 3 at a distance from the main surface electrode film 31. The gate electrode film 32 includes a gate pad electrode 36 and a gate wiring 37. The gate pad electrode 36 and the gate wiring 37 are disposed on the interlayer insulating film 29 at a distance from the main surface electrode film 31.

[0382] In this embodiment, the gate pad electrode 36 is disposed on a portion of the interlayer insulating film 29 that covers the base portion 21, and faces the base portion 21 across the interlayer insulating film 29. The gate pad electrode 36 may be mechanically and electrically connected to the base portion 21 via one or more gate contact openings 92.

[0383] The gate pad electrode 36 faces the outer well region 15 with the interlayer insulating film 29 and the base portion 21 sandwiched therebetween. In this embodiment, the gate pad electrode 36 is formed at a distance from the ends (both ends) of the plurality of gate structures 12. The gate pad electrode 36 does not face the plurality of gate structures 12 in the stacking direction. Of course, the gate structure 12 may have a portion facing a part (for example, an end) of the gate structure 12 with the interlayer insulating film 29 sandwiched therebetween.

[0384] In this embodiment, the peripheral edge of the gate pad electrode 36 faces the second surface film portion 76 in the stacking direction. The gate pad electrode 36 does not face the first surface film portion 75 in the stacking direction. Like the main surface electrode film 31, the gate pad electrode 36 includes a lower electrode film 88 and a main electrode film 89 which are stacked in this order from the interlayer insulating film 29 side. In this embodiment, the lower electrode film 88 has a stacked structure including a first electrode film 90 and a second electrode film 91.

[0385] The gate wiring 37 is drawn out from the gate pad electrode 36 onto a portion of the interlayer insulating film 29 that covers the extension portion 22. The gate wiring 37 is routed in a strip-like manner around the periphery of the first main surface 3 and in the region between the main surface electrode film 31. The gate wiring 37 has a portion that extends in a strip-like manner in the first direction X and a portion that extends in a strip-like manner in the second direction Y in plan view.

[0386] The gate wiring 37 enters the plurality of gate contact openings 92 from above the interlayer insulating film 29, and is mechanically and electrically connected to the extensions 22 within the plurality of gate contact openings 92. As a result, the gate potential applied to the gate pad electrode 36 is applied to the plurality of gate structures 12 via the gate wiring 37.

[0387] The gate wiring 37 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 37 is formed at a distance from the ends of the multiple gate structures 12 toward the peripheral side of the first main surface 3. The gate wiring 37 does not face the multiple gate structures 12 in the stacking direction.

[0388] In this embodiment, the peripheral edge of the gate wiring 37 is disposed at a distance from the first surface film portion 75 toward the peripheral edge of the first main surface 3, and faces the second surface film portion 76 in the stacking direction. The gate wiring 37 does not face the first surface film portion 75 in the stacking direction. The inner edge of the gate wiring 37 may be disposed on the inner side of the first main surface 3 with respect to the second surface film portion 76, and face the first surface film portion 75 in the stacking direction.

[0389] In this embodiment, the gate wiring 37 has a laminated structure including a lower electrode film 88 and a main electrode film 89 laminated in this order from the chip 2 side, similar to the main surface electrode film 31. In this embodiment, the lower electrode film 88 has a laminated structure including a first electrode film 90 and a second electrode film 91.

[0390] (8) Example of Effects of Semiconductor Device 1 According to the semiconductor device 1, as shown in FIG. 2 , the entire main surface electrode film 31 is disposed within the region sandwiched between the first finger wiring 40 and the second finger wiring 41. The main surface electrode film 31 (source metal) does not include a lead-out wiring surrounding the first finger wiring 40 and the second finger wiring 41. Since the installation space for the source lead-out wiring can be eliminated, the space available for the active region 6 can be expanded. As a result, the area of ​​the active region 6 can be increased, and the current density of the MIS transistor can be improved.

[0391] 7 and 12 , the main surface contact region 53 crosses the gate electrode film 32 and extends across the active region 6 and the outer well region 15. This allows the source ground potential (the potential of the main surface electrode film 31) to extend from the active region 6 across the gate electrode film 32 to the outer periphery region 8. As a result, the potential at a position outside the gate electrode film 32 can be fixed to the source ground potential, thereby improving the breakdown voltage in the outer periphery region 8.

[0392] 5 and 6, the main surface contact region 53 is formed in a ring shape in plan view in an inner region of the well region 13 spaced inward from the first to fourth well peripheries 54A to 54D. This allows the active region 6 to be fixed at the same potential (in this embodiment, the source ground potential) all around, thereby maintaining potential stability. As described above, the main surface contact region 53 extends to the outer well region 15, and this structure contributes to maintaining the breakdown voltage particularly in the outer peripheral region 8.

[0393] 12 , the semiconductor device 1 may include a surface insulating film 18. The surface insulating film 18 may cover the first main surface 3 around the end of the gate structure 12 and be connected to the insulating film 58. With this configuration, the dielectric strength around the end of the gate structure 12 is improved by the surface insulating film 18. The surface insulating film 18 may include a first surface film portion 75 and a second surface film portion 76. The first surface film portion 75 may cover the periphery of the end of the gate structure 12 and may have a thickness greater than the thickness of the first film portion 63 of the insulating film 58.

[0394] According to this configuration, the dielectric strength around the end of the gate structure 12 is improved by the first surface film portion 75, which is thicker than the first film portion 63. The second surface film portion 76 covers the periphery of the first surface film portion 75 and may have a thickness greater than the thickness of the second film portion 64 of the insulating film 58. According to this configuration, the dielectric strength around the periphery of the first surface film portion 75 is improved by the second surface film portion 76, which is thicker than the second film portion 64.

[0395] 12, the gate finger wiring 39 is disposed on the second surface film portion 76 of the surface insulating film 18. Referring to FIG. 22, the gate pad electrode 36 is disposed on the second surface film portion 76 of the surface insulating film 18. The surface insulating film 18 may be damaged during ion implantation to form the main surface contact region 53. However, the gate pad electrode 36 and the finger wiring 39 are disposed on the second surface film portion 76, which is a part of the surface insulating film 18 that is thicker than the insulating film 58 and is relatively thick within the surface insulating film 18. Therefore, even if the main surface contact region 53, which is fixed to the source potential, is disposed below the gate electrode film 32, the second surface film portion 76 can prevent a short circuit between the gate and the source.

[0396] 9 and other figures, semiconductor device 1 includes p-type active well region 14, gate structure 12, and p-type active contact region 72. Active well region 14 is formed in a surface layer portion of first main surface 3. Gate structure 12 is formed on first main surface 3 so as to penetrate active well region 14. Active contact region 72 extends along the sidewall of gate structure 12 and electrically connects bottom well region 16 to active well region 14. With this configuration, the electrical response characteristics of bottom well region 16 can be appropriately improved.

[0397] 18 , in a plan view, the main surface contact region 53 extending along the trench 57 is covered with the main surface electrode film 31. The main surface contact region 53 faces the connection region 35 of the main surface electrode film 31. This ensures connection between the main surface contact region 53 and the main surface electrode film 31 even in the region below the connection region 35.

[0398] (9) Layout Variations of the Gate Electrode Film 32 Next, with reference to Figures 23 to 27, variations of the layout example of the gate electrode film 32 will be described. Figures 23 to 27 are diagrams showing first to fifth modified examples of the layout of the gate electrode film 32, respectively.

[0399] 23 , first finger wiring 40 and second finger wiring 41, which are examples of outer finger portions, may be connected to each other to provide, as a whole, a closed-loop finger wiring 39. In this case, a third tip portion 45 of third finger wiring 42 may be connected to the closed-loop finger wiring 39.

[0400] 24 , the first finger wiring 40 and the second finger wiring 41, which are examples of outer finger portions, may be connected to each other to provide a closed-loop finger wiring 39 as a whole. In this case, the third tip portion 45 of the third finger wiring 42 may be disposed at a distance from the closed-loop finger wiring 39. This ensures a space for the connection region 35 of the main-surface electrode film 31.

[0401] 25 , the first finger wiring 40 may extend from the base wiring 38 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in this order, and have a first tip portion 43 in a central portion of the fourth side surface 5D in the first direction X. The second finger wiring 41 may extend from the base wiring 38 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in this order, and have a second tip portion 44 in a central portion of the fourth side surface 5D in the first direction X. The first tip portion 43 and the second tip portion 44 may face each other in the first direction X with a space S therebetween.

[0402] Referring to FIG. 26, the gate electrode film 32 does not necessarily have to include the third finger interconnection 42 .

[0403] 27 , the first finger wiring 40 and the second finger wiring 41, which are examples of outer finger portions, may be connected to each other to provide, as a whole, a closed-loop finger wiring 39. In this case, the gate electrode film 32 may not include the third finger wiring 42.

[0404] 28 to 29, variations of the layout of the main surface contact region 53 will be described. Figures 28 to 29 are diagrams showing first and second modified examples of the layout of the main surface contact region 53, respectively.

[0405] 28 , the main surface contact region 53 may include a first main surface contact region 98 and a second main surface contact region 99 that are physically separated from each other. The first main surface contact region 98 and the second main surface contact region 99 are arranged at an interval in the first direction X. The first main surface contact region 98 and the second main surface contact region 99 may each have a strip shape extending along the second direction Y.

[0406] The first main surface contact region 98 and the second main surface contact region 99 may be strip-shaped and extend parallel to each other. The first main surface contact region 98 and the second main surface contact region 99 are formed in strip-shaped shapes in inner regions of the well region 13 spaced inward from the first to fourth well peripheries 54A to 54D.

[0407] The first main surface contact region 98 and the second main surface contact region 99 may each cross the gate electrode film 32 and extend across the active region 6 and the outer well region 15 .

[0408] 29 , the main surface contact region 53 may include a first main surface contact region 100 and a second main surface contact region 101 that are physically separated from each other. The first main surface contact region 100 and the second main surface contact region 101 are arranged at an interval in the second direction Y. The first main surface contact region 100 and the second main surface contact region 101 may each have a strip shape extending along the first direction X.

[0409] The first main surface contact region 100 and the second main surface contact region 101 may be strip-shaped and extend parallel to each other. The first main surface contact region 100 and the second main surface contact region 101 are formed in strip-shaped shapes in inner regions of the well region 13 spaced inward from the first to fourth well peripheries 54A to 54D.

[0410] The first main surface contact region 100 and the second main surface contact region 101 may each cross the gate electrode film 32 and extend across the active region 6 and the outer well region 15 .

[0411] (11) Modifications of Various Insulating Films Below are shown modifications applied to various insulating films of the semiconductor device 1. Figures 30 to 34 are diagrams showing first to fifth modifications of various insulating films of the semiconductor device 1, respectively.

[0412] 30 , the upper end of the insulating film 58 may be located at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 57. The insulating film 58 may expose the chip 2 from the side wall and the opening end of the trench 57.

[0413] The electrode surface of the buried electrode 59 may protrude toward the first main surface 3 beyond the upper end of the insulating film 58. The electrode surface of the buried electrode 59 may be located closer to the bottom wall of the trench 57 than the upper end of the insulating film 58. The buried insulator 60 may be buried in the trench 57 above the upper end of the insulating film 58 and the electrode surface of the buried electrode 59.

[0414] The buried insulator 60 may cover the upper end of the insulating film 58 and the electrode surface of the buried electrode 59. The buried insulator 60 may have a portion that directly covers the sidewall of the trench 57. The active well region 14, the source region 71, and the active contact region 72 may each have a portion that directly contacts the buried insulator 60 in a portion along the gate structure 12.

[0415] 31 , the semiconductor device 1 does not necessarily have to have the second surface film portion 76. In this case, the surface insulating film 18 may be configured to have a laminated structure including a first surface insulating film 77 and a second surface insulating film 78.

[0416] 32 , semiconductor device 1 does not necessarily have to have first film portion 63 of insulating film 58. In this case, insulating film 58 may be composed of second film portion 64. Insulating film 58 has a layered structure including second insulating film 66 and third insulating film 67, and may not have first insulating film 65.

[0417] 33 , semiconductor device 1 does not necessarily have to have second film portion 64 of insulating film 58. In this case, semiconductor device 1 may have insulating film 58 configured with a single-layer structure made of first insulating film 65. In this embodiment, first insulating film 65 covers the sidewalls and bottom wall of trench 57 in the inner portion and end portion of gate structure 12.

[0418] The surface insulating film 18 includes a first surface film portion 75 and a second surface film portion 76. In this embodiment, the first surface film portion 75 has a single-layer structure made of a first surface insulating film 77. The first surface insulating film 77 covers the periphery of the end portion of the gate structure 12 and is connected to the first insulating film 65. The first surface insulating film 77 is formed integrally with the first insulating film 65.

[0419] In this embodiment, the second surface film portion 76 is configured with a layered structure including a third surface insulating film 79 and a fourth surface insulating film 80. The third surface insulating film 79 is formed in the same layout as in the embodiment described above. The fourth surface insulating film 80 directly covers the third surface insulating film 79 and is connected to the first surface insulating film 77. The fourth surface insulating film 80 is formed integrally with the first insulating film 65 and the first surface insulating film 77.

[0420] 34, semiconductor device 1 does not have buried insulator 60 in the plurality of gate structures 12. Surface insulating film 18 includes active insulating film 102 that selectively covers first main surface 3 in active region 6.

[0421] The active insulating film 102 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The active insulating film 102 may include an insulator that is the same as or different from the first insulating film 65. The active insulating film 102 may include an insulator that is the same as or different from the second insulating film 66. The active insulating film 102 may include an insulator that is the same as or different from the third insulating film 67.

[0422] The active insulating film 102 may include an insulator that is the same as or different from the first surface insulating film 77. The active insulating film 102 may include an insulator that is the same as or different from the second surface insulating film 78. The active insulating film 102 may include an insulator that is the same as or different from the third surface insulating film 79. The active insulating film 102 may include an insulator that is the same as or different from the fourth surface insulating film 80. The active insulating film 102 may include an insulator that is the same as or different from the fifth surface insulating film 81.

[0423] In this embodiment, the active insulating film 102 has a single-layer structure made of a silicon oxide film. The silicon oxide film may be made of an NSG film, a PSG film, or a BPSG film. The active insulating film 102 preferably contains an oxide other than the oxide of the chip 2. In this embodiment, the active insulating film 102 is made of an NSG film.

[0424] The active insulating film 102 directly covers the first main surface 3 (the mesa portions 68) around the inner portions of the gate structures 12, and is connected to the insulating films 58. Specifically, the active insulating film 102 is connected to the first insulating films 65, and exposes the buried electrodes 59.

[0425] In this embodiment, the active insulating film 102 is made of the same insulating film as the first insulating film 65, the third insulating film 67, the second surface insulating film 78, and the fourth surface insulating film 80. The active insulating film 102 is formed integrally with the first insulating film 65 and the third insulating film 67, and is formed as an extension portion of the first insulating film 65 and the third insulating film 67 that is extended from the trench 57 onto the first main surface 3.

[0426] In this embodiment, the interlayer insulating film 29 collectively covers the plurality of gate structures 12 in the active region 6 .

[0427] The interlayer insulating film 29 collectively covers the plurality of gate structures 12 and the active insulating film 102 in the active region 6. The interlayer insulating film 29 extends into the trench 57 from above the active insulating film 102, and covers the buried electrode 59, the first insulating film 65, the second insulating film 66, and the third insulating film 67 within the trench 57. The interlayer insulating film 29 has portions that cover the plurality of source regions 71 and the plurality of active contact regions 72 with the active insulating film 102 sandwiched therebetween.

[0428] In this embodiment, the semiconductor device 1 includes a plurality of contact openings 30 formed in the interlayer insulating film 29. The plurality of contact openings 30 penetrate the interlayer insulating film 29 and the active insulating film 102, and selectively expose a plurality of mesa portions 68. The plurality of contact openings 30 may be formed in a one-to-one correspondence with one mesa portion 68.

[0429] The main surface electrode film 31 extends from above the interlayer insulating film 29 into the plurality of contact openings 30 and is electrically connected to the plurality of source regions 71 and the plurality of active contact regions 72 within the plurality of contact openings 30 .

[0430] 35 and 36 are cross-sectional views showing a main part of a planar gate structure. Referring to Fig. 35 and Fig. 36, the transistor structure Tr of the semiconductor device 1 of this embodiment has a planar gate vertical structure.

[0431] The semiconductor device 1 includes a plurality of p-type active well regions 103 formed in the active region 6. In this embodiment, the plurality of active well regions 103 are arranged at intervals in the second direction Y, and are each formed in a strip shape extending in the first direction X. The plurality of active well regions 103 are arranged in a stripe shape as a whole. Each active well region 103 provides a unit cell UC of a planar gate transistor. Each unit cell UC includes at least the active well region 103 and a source region 104 (described later), and may be the minimum unit that functions as a MIS transistor. The plurality of active well regions 103 may have a size of, for example, 1×10 １５ cm －３ 1x10 or more １８ cm－３ The p-type impurity concentration may have the following peak value:

[0432] The semiconductor device 1 includes one or more n-type source regions 104 formed in the surface layer of each of the active well regions 103 in the active region 6. The source regions 104 have a higher n-type impurity concentration than the n-type impurity concentration of the drift region 11. The source regions 104 have a concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0433] The plurality of source regions 104 may each extend in a strip shape along the extension direction of the corresponding active well region 103. Of course, the plurality of source regions 104 may be formed at intervals along the extension direction of the corresponding active well region 103. The plurality of source regions 104 are formed at intervals from the bottom of the corresponding active well region 103 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding active well region 103. The plurality of source regions 104 define a channel CH along the first main surface 3 at the periphery of the active well region 103.

[0434] The semiconductor device 1 includes one or more p-type active contact regions 105 formed in the surface layer portions of the plurality of active well regions 103 in the active region 6. One active contact region 105 is formed in a region between the plurality of source regions 104 adjacent to each other in the surface layer portion of each active well region 103.

[0435] The active contact regions 105 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the active well regions 103. The active contact regions 105 have a p-type impurity concentration (peak value) of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0436] The multiple active contact regions 105 may each extend in a strip shape along the extension direction of the corresponding active well region 103. Of course, the multiple active contact regions 105 may be formed at intervals along the extension direction of the corresponding active well region 103. The multiple active contact regions 105 are formed at intervals from the bottom of the corresponding active well region 103 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding active well region 103.

[0437] The semiconductor device 1 includes a plurality of planar electrode type gate structures 106 arranged on the first main surface 3 in the active region 6. The gate structures 106 may also be referred to as "planar structures" or "planar gate structures." The plurality of gate structures 106 are arranged at intervals on the first main surface 3 so as to overlap at least one channel CH in the stacking direction. A gate potential is applied to the plurality of gate structures 106 as a control potential.

[0438] In this embodiment, the multiple gate structures 106 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple gate structures 106 are each arranged so as to straddle two adjacent active well regions 103, and each cover the multiple source regions 104 located in one and the other active well regions 103.

[0439] Each of the multiple gate structures 106 has a stacked structure including an insulating film 58 disposed on the first main surface 3 and a gate electrode 107 disposed on the insulating film 58. The insulating film 58 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 58 has a single-layer structure made of a silicon oxide film.

[0440] The interlayer insulating film 29 collectively covers the plurality of gate structures 106 in the active region 6. In this embodiment, the semiconductor device 1 includes a plurality of contact openings 30 formed in the interlayer insulating film 29. The plurality of contact openings 30 penetrate the interlayer insulating film 29 and selectively expose the plurality of source regions 104 and the plurality of active contact regions 105. The plurality of contact openings 30 may be formed in a one-to-one correspondence with one active well region 103.

[0441] The main surface electrode film 31 extends from above the interlayer insulating film 29 into the plurality of contact openings 30 and is electrically connected to the plurality of source regions 104 and the plurality of active contact regions 105 within the plurality of contact openings 30 .

[0442] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0443] For example, in each of the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 9 may include a silicon single crystal. The second semiconductor layer 10 may include a silicon single crystal.

[0444] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0445] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0446] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0447] [Supplementary Note 1-1] A chip (2) having a main surface (3) including an active region (6), first impurity regions (10, 11) of a first conductivity type in a surface layer portion of the main surface (3), second impurity regions (13, 14, 15) of a second conductivity type in a surface layer portion of the first impurity regions (10, 11), a third impurity region (71) of the first conductivity type in a surface layer portion of the second impurity regions (13, 14, 15) in the active region (6), and a MIS transistor structure including a gate structure (12) facing a channel region (CH) in the second impurity regions (13, 14, 15) in the active region (6) and configured to be able to control conduction of a channel (CH) between the first impurity regions (10, 11) and the third impurity region (71), and an insulating layer (29) on the main surface (3), a gate electrode film (32) on the insulating layer (29) and electrically connected to the gate structure (12), the gate electrode film (32) including a pad portion (36) and a finger portion (39) extending in a line from the pad portion (36) and surrounding the active region (6); a main surface electrode film (31) on the insulating layer (29) in the active region (6) and electrically connected to the third impurity region (71); and a main surface contact region (53) of a second conductivity type on a part of a surface portion of the second impurity region (13, 14, 15) along the finger portion (39) at the outer periphery of the active region (6), electrically connected to the main surface electrode film (31), and having an impurity concentration higher than that of the second impurity region (13, 14, 15).

[0448] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the second impurity region (13, 14, 15) includes an active well region (14) in the active region (6) and an outer well region (15) extending from the active well region (14) to a peripheral region outside the gate electrode film (32), and the main surface contact region (53) crosses the gate electrode film (32) and spans the active region (6) and the outer well region (15).

[0449] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein the main surface contact region (53) is formed in a ring shape in a plan view in an inner region of the second impurity region (13, 14, 15) spaced inward from an outer peripheral edge (54A to 54D) of the outer well region (15).

[0450] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3 further includes a surface insulating film (18) including a first surface film portion (75) covering the periphery of the gate structure (12) on the main surface (3), and a second surface film portion (76) covering the periphery of the first surface film portion (75) on the main surface (3) and having a thickness greater than a thickness of the first surface film portion (75), wherein the gate electrode film (32) faces the outer well region (15) across the second surface film portion (76).

[0451] [Supplementary Note 1-5] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-4, wherein a plurality of unit cells (UC) of the MIS transistor structure are regularly arranged in a region inward of the main surface contact region (53) in the active region (6), the third impurity region (71) and a second conductivity type active contact region (72) having an impurity concentration higher than that of the second impurity region (13, 14, 15) are adjacent to each other on the main surface (3) of each of the unit cells (UC), and the main surface contact region (53) is separated from the third impurity region (71) and the active contact region (72) by a part of the second impurity region (13, 14, 15) in plan view.

[0452] [Appendix 1-6] The semiconductor device (1) according to appendix 1-5, wherein the plurality of unit cells (UC) are arranged in a stripe pattern extending in a first direction (X), and the main surface contact region (53) is arranged at a position away from the third impurity region (71) and the active contact region (72) at an end of the plurality of unit cells (UC) in the longitudinal direction, and extends across the plurality of unit cells (UC) in a second direction (Y) intersecting the first direction (X).

[0453] [Appendix 1-7] The semiconductor device (1) according to appendix 1-5 or appendix 1-6, wherein the insulating layer (29) has a contact opening (30) that exposes the third impurity region (71), the active contact region (72), and the main surface contact region (53) all at once, and the main surface electrode film (31) is connected to the third impurity region (71), the active contact region (72), and the main surface contact region (53) within the contact opening (30).

[0454] [Supplementary Note 1-8] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-4, wherein a plurality of unit cells (UC) of the MIS transistor structure are regularly arranged in a region inward of the main surface contact region (53) in the active region (6), and the MIS transistor structure includes a trench gate structure (12) including a gate trench (57) that defines a mesa portion (68) that provides the plurality of unit cells (UC), a gate insulating film (58) formed on an inner surface of the gate trench (57), and a gate electrode (59) embedded in the gate trench (57) via the gate insulating film (58).

[0455] [Appendix 1-9] The semiconductor device (1) according to appendix 1-8 further includes: a well region (16) of a second conductivity type formed below the trench gate structure (12) in the first impurity region (10, 11); and lead-out regions (53A-53C) of the second conductivity type drawn from the well region (16) along the sidewall of the gate trench (57) and the main surface (3) and connected to the main surface contact region (53).

[0456] [Appendix 1-10] The semiconductor device (1) according to appendix 1-8, further comprising trench contact regions (53A-53C) located in a surface layer portion of the first impurity regions (10, 11) and having a higher impurity concentration than the second impurity regions (13, 14, 15), wherein the trench contact regions (53A-53C) integrally include a first region (53A) extending along a bottom wall of the gate trench (57), a second region (53B) extending along a sidewall of the gate trench (57), and a third region (53C) extending along the main surface (3), and wherein the main surface contact region (53) includes an extension of the third region (53C).

[0457] [Supplementary Note 1-11] The semiconductor device (1) according to any one of Supplementary Notes 1-8 to 1-10, further comprising an integral insulating film including the gate insulating film (58) and a surface insulating film (18) integrally drawn out from the gate insulating film (58) onto the main surface (3), wherein the integral insulating film includes a first film portion (63) facing the channel (CH) of the MIS transistor structure, and a second film portion (76) disposed on an end of the gate trench (57) in a longitudinal direction and on the main surface (3), the second film portion having a thickness greater than that of the first film portion (63), and wherein the gate electrode film (32) is disposed on the second film portion (76).

[0458] [Appendix 1-12] The semiconductor device (1) according to any one of Appendices 1-8 to 1-11, wherein the finger portion (39) includes a central finger portion (42) extending from the pad portion (36) across a central portion of the chip (2) and dividing the main surface electrode film (31) into a first electrode region (33) and a second electrode region (34), the main surface electrode film (31) further includes a connection region (35) connecting the first electrode region (33) and the second electrode region (34) at an end (45) in the longitudinal direction of the central finger portion (42), the connection region (35) facing a part of the main surface contact region (53) in the thickness direction of the chip (2).

[0459] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-8 to 1-12, wherein the finger portion (39) includes outer finger portions (40, 41) extending from the pad portion (36) along the outer periphery (5A to 5D) of the chip (2) and surrounding the main surface electrode film (31), and the entire area defined by the outer periphery of the main surface electrode film (31) is disposed within the area surrounded by the outer finger portions (40, 41).

[0460] [Appendix 1-14] The semiconductor device (1) according to Appendix 1-13, wherein the chip (2) has a rectangular shape in a plan view, the pad portion (36) is arranged on an outer peripheral edge (5A) of one side of the chip (2), the outer finger portions (40, 41) include a first outer finger portion (40) and a second outer finger portion (41) extending in opposite directions from the pad portion (36), and the entire main surface electrode film (31) is arranged within a region sandwiched between the first outer finger portion (40) and the second outer finger portion (41).

[0461] [Appendix 1-15] The semiconductor device (1) according to Appendix 1-13, wherein the chip (2) has a rectangular shape in a plan view, the pad portion (36) is arranged on an outer peripheral edge (5A) of one side of the chip (2), the outer finger portions (40, 41) are closed rings having one end and the other end connected to the pad portion (36), and the entire main surface electrode film (31) is arranged within an area closed by the outer finger portions (40, 41).

[0462] [Appendix 1-16] The semiconductor device (1) according to any one of Appendices 1-1 to 1-15, wherein the MIS transistor structure includes a body region (14) made of the second impurity region (13, 14, 15) and a source region (71) made of the third impurity region (71).

[0463] [Appendix 1-17] The semiconductor device (1) according to any one of Appendices 1-1 to 1-16, wherein the chip (2) includes a SiC chip (2).

[0464] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Active region 7: Drain pad electrode 8: Peripheral region 9: First semiconductor layer 10: Second semiconductor layer 11: Drift region 12: Gate structure 13: Well region 14: Active well region 15: Outer well region 16: Bottom well region 17: Field region 18: Surface insulating film 20: Underlying wiring layer 21: Base portion 22: Extension portion 23: First extension portion 24: Second extension portion 25: Third extension portion 26: First tip portion 27: Second tip portion 28: Third tip portion 29: Interlayer insulating film 30: Contact opening 31: Main surface electrode film 32: Gate electrode film 33: First electrode region 34: Second electrode region 35: Connection region 36: Gate pad electrode 37: Gate wiring 38: Base wiring 39: Finger wiring 40: First finger wiring 41: Second finger wiring 42: Third finger wiring 43: First tip portion 44: Second tip portion 45: Third tip portion 46: Protective film 47: Gate pad 48: Gate pad opening 49: First source pad 50: First source pad opening 51: Second source pad 52: Second source pad opening 53: Main surface contact region 53A: First region 53B: Second region 53C: Third region 54A: First well periphery 54B : Second well periphery 54C : Third well periphery 54D : Fourth well periphery 55A : First outer periphery 55B : Second outer periphery 55C : Third outer periphery 55D : Fourth outer periphery 56A : First inner periphery 56B : Second inner periphery 56C : Third inner periphery 56C : Fourth inner periphery 56D : Fourth inner periphery 57 : Trench 58 : Insulating film59: Buried electrode 60: Buried insulator 61: First active region 62: Second active region 63: First film portion 64: Second film portion 65: First insulating film 66: Second insulating film 67: Third insulating film 68: Mesa portion 69: First well region 70: Second well region 71: Source region 72: Active contact region 72A: First region 72B: Second region 72C: Third region 73: Inner edge portion 74: Outer edge portion 75: First surface film portion 76: Second surface film portion 77: First surface insulating film 78: Second surface insulating film 79: Third surface insulating film 80: Fourth surface insulating film 81: Fifth surface insulating film 82: First portion 83: Second portion 84 : Third portion 85 : Fourth portion 86 : Gate protrusion 87 : Space 88 : Lower electrode film 89 : Main electrode film 90 : First electrode film 91 : Second electrode film 92 : Gate contact opening 93 : Base gate contact opening 94 : Pad contact opening 95 : Peripheral gate contact opening 96 : Inner gate contact opening 97 : Inner opening 98 : First main surface contact region 99 : Second main surface contact region 100 : First main surface contact region 101 : Second main surface contact region 102 : Active insulating film 103 : Active well region 104 : Source region 105 : Active contact region 106 : Gate structure 107 : Gate electrode

Claims

a MIS transistor structure including: a first impurity region of a first conductivity type in a surface layer portion of the main surface; a second impurity region of a second conductivity type in a surface layer portion of the first impurity region; a third impurity region of the first conductivity type in a surface layer portion of the second impurity region in the active region; and a gate structure facing a channel region in the second impurity region in the active region and configured to be able to control conduction of a channel between the first impurity region and the third impurity region; an insulating layer on the main surface; a gate electrode film on the insulating layer and electrically connected to the gate structure, the gate electrode film including a pad portion and finger portions extending in a line from the pad portion and surrounding the active region; a main surface electrode film on the insulating layer in the active region and electrically connected to the third impurity region; and a main surface contact region of a second conductivity type on a part of the surface layer portion of the second impurity region along the finger portion at the outer periphery of the active region, electrically connected to the main surface electrode film, the main surface contact region having an impurity concentration higher than that of the second impurity region.

2. The semiconductor device according to claim 1, wherein the second impurity region includes an active well region within the active region and an outer well region extending from the active well region to a peripheral region outside the gate electrode film, and the main surface contact region crosses the gate electrode film and spans the active region and the outer well region.

3. The semiconductor device according to claim 2, wherein said main surface contact region is formed in a ring shape in plan view in an inner region of said second impurity region spaced inward from the outer periphery of said outer well region.

4. The semiconductor device according to claim 2 or 3, further comprising a surface insulating film including a first surface film portion covering the periphery of the gate structure on the main surface, and a second surface film portion covering the periphery of the first surface film portion on the main surface and having a thickness greater than that of the first surface film portion, wherein the gate electrode film faces the outer well region across the second surface film portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein a plurality of unit cells of the MIS transistor structure are regularly arranged in a region inward of the main surface contact region in the active region, the third impurity region and an active contact region of a second conductivity type having an impurity concentration higher than that of the second impurity region are adjacent to each other on the main surface of each unit cell, and the main surface contact region is separated from the third impurity region and the active contact region by a part of the second impurity region in a plan view.

6. The semiconductor device according to claim 5, wherein the plurality of unit cells are arranged in a stripe pattern extending in a first direction, and the main surface contact region is located at a position away from the third impurity region and the active contact region at an end of the plurality of unit cells in the longitudinal direction, and extends across the plurality of unit cells in a second direction intersecting the first direction.

7. The semiconductor device according to claim 5 or 6, wherein the insulating layer has a contact opening that exposes the third impurity region, the active contact region, and the main surface contact region all at once, and the main surface electrode film is connected to the third impurity region, the active contact region, and the main surface contact region within the contact opening.

8. A semiconductor device according to any one of claims 1 to 4, wherein a plurality of unit cells of the MIS transistor structure are regularly arranged in a region inward of the main surface contact region in the active region, and the MIS transistor structure includes a trench gate structure including a gate trench defining a mesa portion providing the plurality of unit cells, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film.

9. The semiconductor device according to claim 8, further comprising: a well region of a second conductivity type formed in the first impurity region below the trench gate structure; and a lead-out region of the second conductivity type drawn from the well region along the sidewall of the gate trench and the main surface and connected to the main surface contact region.

10. The semiconductor device described in claim 8, further comprising a trench contact region located in a surface layer portion of the first impurity region and having a higher impurity concentration than the second impurity region, wherein the trench contact region integrally comprises a first region extending along the bottom wall of the gate trench, a second region extending along the sidewall of the gate trench, and a third region extending along the main surface, and wherein the main surface contact region includes an extension of the third region.

11. A semiconductor device according to any one of claims 8 to 10, comprising an integral insulating film including the gate insulating film and a surface insulating film integrally drawn out from the gate insulating film onto the main surface, the integral insulating film including a first film portion facing the channel of the MIS transistor structure, and a second film portion disposed on an end of the gate trench in the longitudinal direction and on the main surface, the second film portion having a thickness greater than that of the first film portion, and the gate electrode film being disposed on the second film portion.

12. A semiconductor device as claimed in any one of claims 8 to 11, wherein the finger portion includes a central finger portion extending from the pad portion across the central portion of the chip and dividing the main surface electrode film into a first electrode region and a second electrode region, the main surface electrode film further including a connection region at an end in the longitudinal direction of the central finger portion that connects the first electrode region and the second electrode region, and the connection region faces a portion of the main surface contact region in the thickness direction of the chip.

13. A semiconductor device according to any one of claims 8 to 12, wherein the finger portion includes outer finger portions extending from the pad portion along the outer periphery of the chip and surrounding the main surface electrode film, and the entire area defined by the outer periphery of the main surface electrode film is disposed within the area surrounded by the outer finger portions.

14. The semiconductor device described in claim 13, wherein the chip is rectangular in plan view, the pad portion is arranged on the outer peripheral edge of one side of the chip, the outer finger portion includes a first outer finger portion and a second outer finger portion extending in opposite directions from the pad portion, and the entire main surface electrode film is arranged within a region sandwiched between the first outer finger portion and the second outer finger portion.

15. The semiconductor device described in claim 13, wherein the chip is rectangular in plan view, the pad portion is arranged on the outer peripheral edge of one side of the chip, the outer finger portion is a closed ring having one end and the other end connected to the pad portion, and the entire main surface electrode film is arranged within an area closed by the outer finger portion.

16. The semiconductor device according to any one of claims 1 to 15, wherein the MIS transistor structure includes a body region made of the second impurity region and a source region made of the third impurity region.

17. The semiconductor device according to any one of claims 1 to 16, wherein the chip includes a SiC chip.

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