Semiconductor device

Abstract

This semiconductor device comprises a plurality of mesa parts including first mesa parts each having a first width and second mesa parts having a second width in a direction crossing a trench in a chip, a second impurity region of a second conductivity type and a third impurity region of a first conductivity type formed in a surface layer part of a first impurity region in at least the first mesa parts, a control electrode facing the second impurity region via a control insulating film, a Schottky region provided at least in the second mesa part by the first impurity region, a first electrode forming a Schottky junction part between the first electrode and the Schottky region, and a second electrode ohmic-connected to the first impurity region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-114885 filed with the Japan Patent Office on July 18, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a SiC semiconductor layer, a gate trench formed in a first main surface, a gate insulating layer formed on an inner wall of the gate trench, a gate electrode embedded in the gate trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed on a side of the gate trench in a surface layer portion of the first main surface, a second conductivity type body region formed in a region on the second main surface side relative to the source region in the surface layer portion of the first main surface, a first conductivity type drift region formed in a region on the second main surface side relative to the body region in the SiC semiconductor layer, and ２０ cm －３ and a second conductivity type contact region formed in a surface layer portion of the first main surface in a region on the opposite side of the source region from the gate trench, the second conductivity type contact region having the following second conductivity type impurity concentration:

[0004] Japanese Patent Application Laid-Open No. 2023-179690

[0005] a first impurity region of a first conductivity type in a surface layer portion of the first main surface; a plurality of trenches in the first main surface; a plurality of mesa portions partitioned by the plurality of trenches, the plurality of mesa portions including a first mesa portion having a first width in a direction crossing the trenches and a second mesa portion having a second width wider than the first width; a second impurity region of a second conductivity type and a third impurity region of the first conductivity type in a surface layer portion of the first impurity region in at least the first mesa portion and arranged in this order from the second main surface side along a side surface of the trench; a control electrode buried in at least the trench adjacent to the first mesa portion and facing the second impurity region via a control insulating film; a Schottky region provided by the first impurity region in at least the second mesa portion; a first electrode ohmically connected to the third impurity region and forming a Schottky junction with the Schottky region; and a second electrode ohmically connected to the first impurity region.

[0006] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a perspective view showing an active region and a gate structure according to a first embodiment. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is the same cross-sectional view as FIG. 6 but mainly shows dimensions of various components. FIG. 9 is the same cross-sectional view as FIG. 7 but mainly shows dimensions of various components. FIG. 10 is an enlarged plan view showing a main portion of an active region. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 . FIG. 12 is a cross-sectional view showing a peripheral region. FIG. 13 is a cross-sectional view showing a first modified example of the first embodiment. FIG. 14 is a cross-sectional view showing a second modified example of the first embodiment. FIG. 15 is a cross-sectional view showing a third modified example of the first embodiment. FIG. 16 is a cross-sectional view showing a fourth modified example of the first embodiment. FIG. 17 is a plan view showing a fourth modified example of the first embodiment. FIG. 18 is a cross-sectional view showing a fourth modified example of the first embodiment. FIG. 19 is a cross-sectional view showing a fifth modified example of the first embodiment. FIG. 20 is a cross-sectional view showing a sixth modified example of the first embodiment. FIG. 21 is a cross-sectional view showing a seventh modified example of the first embodiment. FIG. 22 is a cross-sectional view showing an eighth modified example of the first embodiment. FIG. 23 is an enlarged plan view showing a main portion of an active region. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. 23. FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 23. FIG. 26 is a cross-sectional view taken along line XXVI-XXVII shown in FIG. 23. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII shown in FIG. 23. FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in FIG. 23. FIG. 29 is a cross-sectional view showing a first modified example of the second embodiment. FIG. 30 is a cross-sectional view showing a first modified example of the second embodiment. FIG. 31 is a cross-sectional view showing a second modified example of the second embodiment. Fig. 32 is a cross-sectional view showing a second modified example of the second embodiment, Fig. 33 is a cross-sectional view showing a second modified example of the second embodiment, and Fig. 34 is a cross-sectional view showing a second modified example of the second embodiment.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) Overall Configuration of Semiconductor Device 1 Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0012] 1 to 4, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0013] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B each extend in a first direction X along the first main surface 3 and face opposite each other in a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D each extend in the second direction Y and face opposite each other in the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0022] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0023] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0024] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 6 as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0025] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate (i.e., a SiC substrate) made of SiC single crystal. The first semiconductor layer 6 has the off direction Do and off angle θo described above.

[0026] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0027] The first semiconductor layer 6 may have a first thickness T1 of 10 μm to 500 μm. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0028] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0029] In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the off-direction Do and off-angle θo described above. The second semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first semiconductor layer 6.

[0030] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the ending point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0031] The second semiconductor layer 7 includes an n-type drift region 8 as an example of a first impurity region. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor layer 7.

[0032] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 7 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the first semiconductor layer 6.

[0033] The second semiconductor layer 7 may have a lower n-type impurity concentration than the first semiconductor layer 6. The second semiconductor layer 7 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １７ cm －３ The second semiconductor layer 7 may have the following peak n-type impurity concentration: It is preferable that the second semiconductor layer 7 has a substantially constant n-type impurity concentration in the thickness direction.

[0034] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0035] The semiconductor device 1 includes an active region 9 defined in a chip 2. The active region 9 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0036] The active region 9 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0037] The ratio (area ratio) of the planar area of ​​the active region 9 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0038] The semiconductor device 1 includes a peripheral region 10 set outside the active region 9 in the chip 2. The peripheral region 10 is a region that does not include a device structure (transistor structure Tr). The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a planar view. The peripheral region 10 extends in a strip shape along the active region 9 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0039] The semiconductor device 1 includes a plurality of trench electrode type gate structures 11 formed on the first main surface 3 in the active region 9. The gate structures 11 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 11 as a control potential.

[0040] The multiple gate structures 11 are arranged at intervals inward from the periphery of the active region 9. In this embodiment, the multiple gate structures 11 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the multiple gate structures 11 are arranged at intervals in the m-axis direction and each extend in the a-axis direction.

[0041] In this embodiment, the multiple gate structures 11 are arranged in stripes extending in the a-axis direction (second direction Y). The extending direction of the multiple gate structures 11 coincides with the off-direction Do of the second semiconductor layer 7. The multiple gate structures 11 are formed at intervals from the lower end (first semiconductor layer 6) of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.

[0042] The semiconductor device 1 includes a plurality of p-type bottom well regions 12 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. Specifically, the plurality of bottom well regions 12 are formed at the bottom of the gate structure 11, respectively.

[0043] The semiconductor device 1 includes a p-type outer well region 13 and a p-type field region 14 formed in a surface layer portion of the first main surface 3 in a peripheral region 10 (the peripheral portion of the first main surface 3).

[0044] The semiconductor device 1 includes a surface insulating film 15 that selectively covers the first main surface 3. The surface insulating film 15 may also be referred to as an "outer surface insulating film," etc. The surface insulating film 15 covers the first main surface 3 in the peripheral region 10 in a film-like manner.

[0045] Specifically, the surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14 in the peripheral region 10. The surface insulating film 15 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0046] The semiconductor device 1 includes one or more (one in this embodiment) gate wirings 17 arranged on the first main surface 3 in the peripheral region 10. The gate wiring 17 is arranged on a surface insulating film 15.

[0047] 3 , the gate wiring 17 extends in a strip shape along the periphery of the plurality of gate structures 11. The gate wiring 17 has a portion extending in a first direction X and a portion extending in a second direction Y. The gate wiring 17 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 11.

[0048] In this embodiment, the gate wiring 17 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the plurality of gate structures 11 (active regions 9). Of course, the gate wiring 17 may be formed in a strip shape with ends. The gate wiring 17 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape).

[0049] The semiconductor device 1 includes a gate pad wiring 18 arranged on the first main surface 3 in the peripheral region 10. The gate pad wiring 18 is electrically connected to the gate wiring 17 and applies a gate potential to the gate wiring 17.

[0050] The semiconductor device 1 includes an insulating interlayer insulating film 16 that covers the surface insulating film 15. The interlayer insulating film 16 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0051] The semiconductor device 1 includes a source pad electrode 20 disposed on the first main surface 3. The source pad electrode 20 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source electrode," or the like. The source pad electrode 20 is disposed on the interlayer insulating film 16.

[0052] In this embodiment, the source pad electrode 20 has a first pad portion 21, a second pad portion 22, and a third pad portion 23. The first pad portion 21 has a relatively large planar area and forms the main body of the source pad electrode 20. In this embodiment, the first pad portion 21 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0053] The second pad portion 22 has a planar area smaller than that of the first pad portion 21, and is drawn out in a strip shape (rectangular shape) from one end portion of the first pad portion 21 in the second direction Y (the end portion on the first side surface 5A side) toward the third side surface 5C. The third pad portion 23 has a planar area smaller than that of the first pad portion 21, and is drawn out in a strip shape (rectangular shape) from the other end portion of the first pad portion 21 in the second direction Y (the end portion on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 22 in the second direction Y.

[0054] The planar area of ​​the third pad portion 23 may be approximately equal to the planar area of ​​the second pad portion 22. The planar area of ​​the third pad portion 23 may be larger or smaller than the planar area of ​​the second pad portion 22. Either or both of the second pad portion 22 and the third pad portion 23 may be used as a terminal portion for monitoring a current.

[0055] The source pad electrode 20 does not necessarily have to have both the second pad portion 22 and the third pad portion 23. The source pad electrode 20 may have only one of the second pad portion 22 and the third pad portion 23. The source pad electrode 20 may be composed of only the first pad portion 21, and may not have both the second pad portion 22 and the third pad portion 23.

[0056] The source pad electrode 20 covers the entire region of the interlayer insulating film 16 where the source opening 19 is formed, and extends into the source opening 19 from above the interlayer insulating film 16. The source pad electrode 20 has a portion that covers the interlayer insulating film 16 in a film form, a portion that covers the wall surface of the source opening 19 in a film form, and a portion that covers the first main surface 3 within the source opening 19 in a film form.

[0057] The semiconductor device 1 includes a gate pad electrode 24 disposed on the first main surface 3 at a distance from the source pad electrode 20. The gate pad electrode 24 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate electrode," or the like. The gate pad electrode 24 is disposed on the interlayer insulating film 16 at a distance from the source pad electrode 20.

[0058] In this embodiment, the gate pad electrode 24 is disposed on a portion of the interlayer insulating film 16 that covers the gate pad wiring 18, and faces the gate pad wiring 18 across the interlayer insulating film 16. In this embodiment, the gate pad electrode 24 does not have a direct electrical connection to the gate pad wiring 18. Of course, the gate pad electrode 24 may be mechanically and electrically connected to the gate pad wiring 18 via one or more gate openings.

[0059] The gate pad electrode 24 is disposed in a region on the third side surface 5C side of the first pad portion 21, and faces the center of the third side surface 5C and the first pad portion 21 in the first direction X. The gate pad electrode 24 is interposed in a region between the second pad portion 22 and the third pad portion 23, and faces both the second pad portion 22 and the third pad portion 23 in the second direction Y.

[0060] The gate pad electrode 24 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 24 has a planar area smaller than the planar area of ​​the source pad electrode 20. The gate pad electrode 24 has a planar area smaller than the planar area of ​​the first pad portion 21. The gate pad electrode 24 may also have a planar area smaller than the planar area of ​​the second pad portion 22 (third pad portion 23).

[0061] The gate pad electrode 24 faces the outer well region 13 across the interlayer insulating film 16 and the gate pad wiring 18. In this embodiment, the gate pad electrode 24 is formed at a distance from the ends (both ends) of the plurality of gate structures 11. In other words, the gate pad electrode 24 does not face the plurality of gate structures 11 in the stacking direction. Of course, the gate structure 11 may have a portion that faces a part (for example, an end) of the gate structure 11 across the interlayer insulating film 16.

[0062] The semiconductor device 1 includes gate finger electrodes 25 extending from the gate pad electrode 24 onto the first main surface 3. The gate finger electrodes 25 may also be referred to as "gate wiring" or "gate fingers." The gate finger electrodes 25 transmit the gate potential applied to the gate pad electrode 24 to other regions.

[0063] The gate finger electrodes 25 are drawn out from the gate pad electrode 24 onto a portion of the interlayer insulating film 16 that covers the gate wiring 17. The gate finger electrodes 25 are routed in a strip shape around the periphery of the first main surface 3 and in a region between the source pad electrode 20. The gate finger electrodes 25 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0064] In this embodiment, the gate finger electrode 25 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 20. The gate finger electrode 25 is arranged closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 11. The gate finger electrode 25 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0065] The semiconductor device 1 includes a first slit portion 26 defined in a region between the source pad electrode 20 and the gate finger electrode 25. The first slit portion 26 exposes the interlayer insulating film 16.

[0066] The semiconductor device 1 includes source finger electrodes 27 extending from the source pad electrode 20 onto the first main surface 3. The source finger electrodes 27 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 27 transmit the source potential applied to the source pad electrode 20 to other regions.

[0067] The source finger electrodes 27 are arranged at intervals from the gate pad electrode 24 and the gate finger electrodes 25. The source finger electrodes 27 are arranged in regions on the peripheral edge side of the first main surface 3 with respect to both end portions of the plurality of gate structures 11.

[0068] The source finger electrodes 27 are drawn out from the source pad electrode 20 onto the interlayer insulating film 16. The source finger electrodes 27 are routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrodes 20. The source finger electrodes 27 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0069] In this embodiment, source finger electrode 27 is formed in a strip shape with four sides parallel to the periphery of first main surface 3, and surrounds source pad electrode 20 and gate finger electrode 25. Outer well region 13 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in an arc shape (preferably a quarter arc shape).

[0070] Semiconductor device 1 includes second slit portions 28 defined in regions between gate finger electrodes 25 and source finger electrodes 27. Second slit portions 28 are defined in regions between the outer edge of gate wiring 17 and the outer edge of outer well region 13, and overlap first main surface 3 in the stacking direction.

[0071] The semiconductor device 1 includes a drain pad electrode 29 covering the second main surface 4. The drain pad electrode 29 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 29 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 29 forms ohmic contact with the first semiconductor layer 6.

[0072] The drain pad electrode 29 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 29 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0073] A breakdown voltage that can be applied between source pad electrode 20 and drain pad electrode 29 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0074] (2) Detailed Structure of the Active Region 9 of the Semiconductor Device 1 According to the First Embodiment FIG. 5 is a perspective view showing the active region 9 and gate structure 11 according to the first embodiment. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. FIG. 8 is the same cross-sectional view as FIG. 6, but mainly shows the dimensions of each part. FIG. 9 is the same cross-sectional view as FIG. 7, but mainly shows the dimensions of each part.

[0075] In the following, for clarity of the drawings, the dimensions (thickness, width, depth, etc.) of each part of the semiconductor device 1 are shown in Figures 8 and 9, and are omitted from Figures 5 to 7. In Figures 8 and 9, in addition to the dimensions of each part, reference numerals are used to denote the main components.

[0076] 5 to 9, semiconductor device 1 includes a p-type body region 30 formed in a surface layer portion of drift region 8. In this embodiment, body region 30, which is an example of a second impurity region, is formed in a layer shape extending along first main surface 3. Referring to Fig. 5, body region 30 is formed at an interval from the lower end of second semiconductor layer 7 toward first main surface 3. Body region 30 forms a body diode BD between itself and drift region 8.

[0077] The body region 30 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0078] As described above, the semiconductor device 1 includes gate structures 11. With reference to Figures 8 and 9, each gate structure 11 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 (see Figure 4) of the second semiconductor layer 7. The trench width WT may be not less than 0.1 µm and not more than 5 µm.

[0079] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0080] The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. In other words, the multiple gate structures 11 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0081] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0082] The plurality of gate structures 11 are arranged at intervals in the first direction X. A plurality of pitches are set as the pitches between the plurality of gate structures 11. The plurality of pitches includes a first pitch PT1 and a second pitch PT2. The first pitch PT1 and the second pitch PT2 may be referred to as a "first trench pitch" and a "second trench pitch," respectively.

[0083] The second pitch PT2 is larger than the first pitch PT1, and is, for example, more than 1 time and not more than 4 times the first pitch PT1. The second pitch PT2 may be a size that falls within any one of the following ranges: more than 1 time and not more than 1.5 times the first pitch PT1, 1.5 times to 2 times, 2 times to 2.5 times, 2.5 times to 3 times, 3 times to 3.5 times, and 3.5 times to 4 times the first pitch PT1.

[0084] The first pitch PT1 and the second pitch PT2 are preferably less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT.

[0085] The first pitch PT1 may be 0.1 μm or more and 5 μm or less. The first pitch PT1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The trench pitch PT is preferably 0.5 μm or more and 3 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0086] The second pitch PT2 may be 0.5 μm or more and 5.0 μm or less. The second pitch PT2 may have a value belonging to any one of the following ranges: 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, 3.5 μm or more and 4.0 μm or less, 4.0 μm or more and 4.5 μm or less, and 4.5 μm or more and 5.0 μm or less. The second pitch PT2 is preferably 1.0 μm or more and 5.0 μm or less, and more preferably 1.5 μm or more and 3.0 μm or less.

[0087] 5 to 7 , each gate structure 11 includes a trench 31, a trench insulating film 32 as an example of a control insulating film, and a buried conductive layer 33 as an example of a control electrode. The trench 31 may be referred to as an "element trench," a "gate trench," or the like. The trench insulating film 32 may be referred to as a "control insulating film," an "element insulating film," a "gate insulating film," or the like. The buried conductive layer 33 may be referred to as a "control electrode," a "buried electrode," a "gate electrode," or the like.

[0088] The trenches 31 are formed in the first main surface 3 and define the inner surfaces (side surfaces 34 and bottom surfaces 35 shown in FIGS. 6 and 7 ) of the gate structure 11. The bottom surfaces 35 of the trenches 31 preferably have flat portions. Between adjacent trenches 31, mesa portions 36 are formed by part of the second semiconductor layer 7. The mesa portions 36 may also be referred to as "element mesa portions."

[0089] 5, the gate structures 11 (trenches 31) and mesa portions 36 are strip-shaped extending along the second direction Y and are arranged alternately in the first direction X. The first direction X may be a direction crossing the trenches 31. The trenches 31 and mesa portions 36 are arranged in a stripe pattern as a whole.

[0090] The plurality of mesas 36 include a plurality of mesas 36 having different widths. In this embodiment, the plurality of mesas 36 include a first mesa 36A having a first width WM1 and a second mesa 36B having a second width WM2 wider than the first width WM1. The first width WM1 is the length in a direction crossing the plurality of trenches 31. The first mesa 36A has the first width WM1 in the first direction X. The second width WM2 is the length in a direction crossing the plurality of trenches 31. The second mesa 36B has the second width WM2 in the first direction X. The first mesa 36A is a mesa defined between the plurality of trenches 31 arranged at a first pitch PT1. The second mesa 36B is a mesa defined between the plurality of trenches 31 arranged at a second pitch PT2.

[0091] The arrangement pattern of the first mesa portions 36A and the second mesa portions 36B is not particularly limited. For example, as shown in Fig. 5, one second mesa portion 36B may be arranged between a plurality of first mesa portions 36A arranged in a stripe pattern, or a plurality of first mesa portions 36A and a plurality of second mesa portions 36B may be arranged alternately. The arrangement pattern of the first mesa portions 36A and the second mesa portions 36B can be changed as appropriate to suit the specifications of the semiconductor device 1.

[0092] The first mesa portion 36A provides a first unit cell UC1 of a trench-gate transistor. The first unit cell UC1 includes at least a body region 30 and a source region 45 (described later) and may be the minimum unit functioning as a MIS transistor Tr. The second mesa portion 36B provides a second unit cell UC2 of a Schottky barrier diode. The second unit cell UC2 includes at least a Schottky region 67 (described later) and may be the minimum unit functioning as a Schottky barrier diode SBD.

[0093] 6 and 7 , it is particularly preferable that the flat portion of the bottom surface 35 of the trench 31 extends substantially parallel to the first major surface 3. That is, it is preferable that the bottom wall of the trench 31 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do (see FIG. 4 ) with respect to the c-plane. That is, it is preferable that the bottom surface 35 of the trench 31 has a flat portion extending in the off direction Do. Of course, the bottom surface 35 of the trench 31 may be curved in an arc shape toward the lower end side of the second semiconductor layer 7.

[0094] The trench insulating film 32 covers the inner surface of the trench 31. The trench insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 32 has a single-layer structure made of a silicon oxide film. The trench insulating film 32 may include a silicon oxide film made of an oxide of the chip 2.

[0095] The buried conductive layer 33 is buried in the trench 31 and faces the body region 30 (first channel region 37) across the trench insulating film 32. The buried conductive layer 33 may include p-type or n-type conductive polysilicon.

[0096] 6 and 7 , the buried conductive layer 33 is buried up to the middle of the trench 31 in the depth direction. The buried conductive layer 33 has an upper surface 38 located closer to the second main surface 4 than the first main surface 3. A low step 39 is formed on the second main surface 4 side between the upper surface 38 of the buried conductive layer 33 and the first main surface 3. This step 39 forms a recess 40 in the upper part of the trench 31, which is defined by the upper surface 38 of the buried conductive layer 33 and the side surface 34 of the trench 31.

[0097] The recess 40 is a space sandwiched between both side surfaces 34 of the trench 31 and an upper surface 38 of the buried conductive layer 33. As shown in Fig. 5, the recess 40 is formed in a continuous strip shape in the depth direction (second direction Y) of the trench 31. The depth direction of the trench 31 may also be referred to as the "length direction of the trench 31," the "depth direction of the mesa portion 36," or the "length direction of the mesa portion 36."

[0098] The trench insulating film 32 is selectively formed in the region sandwiched between the inner surface of the trench 31 and the buried conductive layer 33, and the side surface 34 of the recess 40 (part of the side surface 34 of the trench 31) is exposed from the trench insulating film 32.

[0099] Due to the formation of the recess 40, a part of the mesa portion 36 in the depth direction of the trench 31 protrudes as a protruding portion 41 toward the first main surface 3 (upward) beyond the buried conductive layer 33. As shown in Fig. 5, the protruding portion 41 of the mesa portion 36 is a portion of the mesa portion 36 sandwiched between adjacent recesses 40, and is formed in a continuous band shape in the depth direction of the trench 31.

[0100] As described above, the semiconductor device 1 includes the bottom well region 12. The bottom well region 12 is formed at the bottom of the gate structure 11. More specifically, the bottom well region 12 is individually formed at the bottom of each trench 31. With reference to FIGS. 8 and 9 , the bottom well regions 12 are arranged at intervals of a first pitch PT1 or a second pitch PT2. The pitch between the bottom well regions 12 of the trenches 31 sandwiching the first mesa portion 36A is the first pitch PT1, and the pitch between the bottom well regions 12 of the trenches 31 sandwiching the second mesa portion 36B is the second pitch PT2.

[0101] The bottom well region 12 is exposed from the bottom surface 35 of the trench 31 and is in contact with the trench insulating film 32. Therefore, the upper end of the bottom well region 12 is exposed at the bottom surface 35 of the gate structure 11 (trench 31). The bottom well region 12 may also be referred to as an "electric field relaxation layer."

[0102] The bottom well region 12 faces the buried conductive layer 33 via the trench insulating film 32 in the depth direction of the trench 31. At the bottom of the trench 31, the trench insulating film 32 is sandwiched between the buried conductive layer 33 and the bottom well region 12.

[0103] 5, bottom well region 12 is formed in the bottom of trench 31 over the entire depth of trench 31, and is formed in a strip shape extending in the depth direction of trench 31. Referring to FIGS. 6 and 7, bottom well region 12 is formed across the width of trench 31, spanning between one end and the other end of trench 31. In this embodiment, bottom well region 12 has, in the depth direction of trench 31, one side surface 42 formed on substantially the same plane as one side surface 34 of trench 31 in the width direction, and the other side surface 42 formed on substantially the same plane as the other side surface 34 of trench 31 in the width direction.

[0104] In other words, each bottom well region 12 has a side surface 42 that is flush with both side surfaces 34 of the trench 31 in the depth direction of the gate structure 11. The side surface 42 of the bottom well region 12 extends in the depth direction of the gate structure 11 and forms a boundary surface with the second semiconductor layer 7 (drift region 8). Therefore, the bottom well region 12 is physically separated from the body region 30 in the depth direction of the gate structure 11 and forms the entire bottom surface 35 of the gate structure 11.

[0105] In this embodiment, the bottom well region 12 has a stacked structure of a first layer 43 and a second layer 44. The first layer 43 is a layer formed away from the bottom of the trench 31 (bottom surface 35 in this embodiment) toward the second main surface 4. The second layer 44 is a layer formed between the first layer 43 and the bottom of the trench 31 (bottom surface 35 in this embodiment). The second layer 44 is exposed from the bottom surface 35 of the trench 31 and contacts the trench insulating film 32. The second layer 44 is sandwiched between the first layer 43 and the trench 31.

[0106] Regarding the impurity concentration of the bottom well region 12, the first layer 43 has a first impurity concentration, and the second layer 44 has a second impurity concentration. In this embodiment, the second impurity concentration of the second layer 44 is higher than the first impurity concentration of the first layer 43. Furthermore, the first impurity concentration of the first layer 43 may be equal to the impurity concentration of the body region 30. The second impurity concentration of the second layer 44 may be higher than the impurity concentration of the body region 30.

[0107] For example, the first impurity concentration of the first layer 43 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The second layer 44 may have a p-type impurity concentration of 1×10 or less as a peak value. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0108] The stacked structure of the first layer 43 and the second layer 44 is continuous in the depth direction of the trench 31. In this embodiment, as shown in FIG. 5 , the bottom well region 12 is formed in a strip shape extending in the depth direction of the trench 31 so that the stacked structure of the first layer 43 and the second layer 44 is continuous throughout the entire depth direction of the trench 31. For example, the multiple bottom well regions 12 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple bottom well regions 12 are formed in a stripe shape extending in the a-axis direction (second direction Y), and the extending direction of the multiple bottom well regions 12 coincides with the off-direction Do (see FIG. 4 ) of the second semiconductor layer 7.

[0109] The bottom well regions 12 overlap the gate structures 11 in the depth direction of the trench 31. Specifically, the bottom well regions 12 overlap the gate structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this configuration, the bottom well regions 12 are connected to the bottom surfaces 35 of the corresponding gate structures 11.

[0110] 8 and 9, bottom well region 12 has a relaxation depth DR in the vertical direction Z.

[0111] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 1.5 μm to 2.5 μm.

[0112] Each of the bottom well regions 12 has a relaxed width WR in the arrangement direction. The relaxed width WR may be 0.25 μm or more and 5 μm or less. The relaxed width WR may have a value in any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0113] 5 and 6 , semiconductor device 1 includes a source region 45 as an example of a third impurity region in a surface layer portion of first main surface 3 in first mesa portion 36A. Source region 45 is formed in a region between a plurality of gate structures 11. Source region 45 is formed in a surface layer portion of body region 30 in first mesa portion 36A.

[0114] In this embodiment, a plurality of source regions 45 are formed across the first mesa portion 36A in the width direction, extending from one side surface 34 of the first mesa portion 36A to the other side surface 34 (one side surface 34 and the other side surface 34 of the trench 31). The plurality of source regions 45 are arranged at intervals in each first mesa portion 36A along the depth direction of the trench 31. As a result, in each first mesa portion 36A, a plurality of channel sections 46 are arranged at intervals in the second direction Y (depth direction of the trench 31). In the channel sections 46, channels are formed on both side surfaces 34 of the trench 31 on both sides of the first mesa portion 36A in the first direction X.

[0115] The source region 45 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0116] 8 , source region 45 has a source thickness ST1. Source thickness ST1 may be the thickness of source region 45 in vertical direction Z from first main surface 3. Source thickness ST1 may be, for example, not less than 0.2 μm and not more than 1.0 μm, preferably not less than 0.4 μm and not more than 0.8 μm.

[0117] 5 and 7 , semiconductor device 1 includes a first contact region 47 in a surface layer portion of first main surface 3 in first mesa portion 36A. First contact region 47 is formed in a region between multiple gate structures 11. First contact region 47 is formed adjacent to source region 45 in a surface layer portion of body region 30 in the depth direction of first mesa portion 36A.

[0118] In this embodiment, a plurality of first contact regions 47 are formed across the first mesa portion 36A in the width direction, from one side surface 34 to the other side surface 34 of the first mesa portion 36A. In each first mesa portion 36A, the plurality of source regions 45 and the plurality of first contact regions 47 are alternately arranged along the depth direction of the trench 31. Each source region 45 and each first contact region 47 is exposed from both side surfaces 34 of the trench 31 (both side surfaces 34 of the first mesa portion 36A).

[0119] 6 and 7 , the body region 30 includes a first body portion 48 ( FIG. 6 ) formed directly below the source region 45 and a second body portion 49 ( FIG. 7 ) formed directly below the first contact region 47. The first body portion 48 is a portion of the body region 30 that is sandwiched between the source region 45 and the drift region 8 in the depth direction of the trench 31. The second body portion 49 is a portion of the body region 30 that is sandwiched between the first contact region 47 and the drift region 8 in the depth direction of the trench 31.

[0120] 8 and 9, the first body portion 48 has a first body thickness BT1, and the second body portion 49 has a second body thickness BT2. The second body thickness BT2 is greater than the first body thickness BT1. Referring to FIGS. 5 to 7, the body region 30 forms a base interface 50 with the drift region 8. The base interface 50 is located at a certain depth from the bottom surface 35 of the trench 31 along the depth direction of the trench 31. As shown in FIG. 5, the body region 30 has a body protrusion 51 that selectively protrudes toward the first main surface 3 directly below the first contact region 47. The body protrusion 51 causes the body region 30 to have a second body portion 49 that is selectively thicker than the base interface 50.

[0121] 6 , a first boundary surface 52 between the first body portion 48 and the source region 45 is located closer to the second main surface 4 than the upper surface 38 of the buried conductive layer 33. The first boundary surface 52 is formed at a position lower than the upper surface 38 of the buried conductive layer 33, and a first step 53 is formed between the upper surface 38 of the buried conductive layer 33 and the first boundary surface 52. A part of the source region 45 (for example, the lower end) faces the buried conductive layer 33 via the trench insulating film 32. This ensures the formation of a channel between the source and the drain.

[0122] 7 , a second boundary surface 54 between the second body portion 49 and the first contact region 47 is located closer to the first major surface 3 than the upper surface 38 of the buried conductive layer 33. The second boundary surface 54 is formed at a position higher than the upper surface 38 of the buried conductive layer 33, and a second step 55 is formed between the upper surface 38 of the buried conductive layer 33 and the second boundary surface 54. A portion (e.g., an upper end) of the second body portion 49 protrudes toward the first major surface 3 (upper side) than the buried conductive layer 33. The first contact region 47 does not directly contribute to the formation of a channel between the source and drain, and therefore, unlike the source region 45, does not need to face the buried conductive layer 33 via the trench insulating film 32. In FIG. 7 , the first boundary surface 52 is indicated by a dashed line for reference of the difference in elevation between the first boundary surface 52 and the second boundary surface 54.

[0123] The first contact region 47 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 30. The p-type impurity concentration (peak value) of the first contact region 47 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0124] 5 and 7 , the semiconductor device 1 includes a second contact region 56 in a surface layer portion of the first main surface 3. The second contact region 56 is connected to the first contact region 47 and the bottom well region 12. The second contact region 56 is formed along the side surface 34 of the trench 31 from the first contact region 47 toward the second main surface 4 and is connected to the bottom well region 12. In this embodiment, the second contact region 56 is formed from the first contact region 47 exposed from both side surfaces 34 of the first mesa portion 36A along both the one side surface 34 and the other side surface 34 of the first mesa portion 36A.

[0125] The second contact region 56 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 30. The p-type impurity concentration (peak value) of the second contact region 56 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0126] The second contact region 56 is formed over the entire depth direction of the trench 31 from the top to the bottom of the trench 31. The second contact region 56 has a lower end near the bottom of the trench 31 and an upper end near the top of the trench 31.

[0127] The second contact region 56 penetrates the body region 30 and straddles between the body region 30 and the bottom well region 12. The second contact region 56 forms a boundary with the body region 30 and is connected to the body region 30. The second contact region 56 is further connected to the second semiconductor layer 7 (drift region 8) below the body region 30. That is, a pn junction is formed by the second contact region 56 and the drift region 8 in the section between the body region 30 and the bottom well region 12.

[0128] 7 , the second contact region 56 is exposed from the side surface 34 of the trench 31 and is in contact with the trench insulating film 32 at the side surface 34 of the trench 31. The lower end of the second contact region 56 is in contact with the second layer 44 of the bottom well region 12. As a result, a p-type integral impurity region 57 is formed in the second semiconductor layer 7 by the first contact region 47, the second contact region 56, and the second layer 44.

[0129] 7 , on the side surface 34 and bottom surface 35 of trench 31, integral impurity region 57 partially covers buried conductive layer 33 via trench insulating film 32. More specifically, corners 81 at both ends in the width direction of trench 31 are covered by integral impurity region 57 having a generally Z-shaped cross section in second relaxation portion 59. This makes it possible to suppress electric field concentration at corners 81 of trench 31.

[0130] 6 , in the first relaxation section 58, a part of the bottom well region 12 (second layer 44) may be spaced apart from the corner of the trench 31. That is, in the depth direction of the trench 31, the corner 81 of the trench 31 may have a part that is covered with the bottom well region 12 and a part that is not covered with the bottom well region 12.

[0131] In this embodiment, a plurality of integral impurity regions 57 are formed at intervals along the depth direction of the trench 31. The first contact region 47 and the second contact region 56 have the same width along the depth direction of the trench 31, and form strip-shaped integral impurity regions 57 of a constant width on the top surface (first main surface 3) of the mesa portion 36 and on the side surface 34 of the mesa portion 36 (side surface 34 of the trench 31).

[0132] 6 and 7, the integral impurity region 57 has a width greater than that of the first layer 43 of the bottom well region 12 in the width direction of the trench 31. This is because the second contact region 56 is connected to the side of the second layer 44, and the portion of the second layer 44 that is integral with the second contact region 56 is selectively wider.

[0133] 9 , the second contact region 56 has a second contact thickness CT2. The second contact thickness CT2 may be the thickness of the second contact region 56 in the horizontal direction from the side surface 34 of the trench 31. The second contact thickness CT2 may be, for example, not less than 10 nm and not more than 200 nm, preferably not less than 20 nm and not more than 100 nm.

[0134] 9 , the first contact region 47 has a first contact thickness CT1. The first contact thickness CT1 may be the thickness of the first contact region 47 in the vertical direction Z from the first main surface 3. In this embodiment, the first contact thickness CT1 is greater than the second contact thickness CT2. The first contact thickness CT1 may be, for example, not less than 0.1 μm and not more than 1.0 μm, preferably not less than 0.2 μm and not more than 0.5 μm.

[0135] 8 and 9, in this embodiment, the ratio of the thickness of the first layer 43 to the second layer 44 of the bottom well region 12 is different between the first relaxation portion 58 (FIG. 6) formed directly below the source region 45 and the second relaxation portion 59 (FIG. 7) formed directly below the first contact region 47.

[0136] More specifically, it is assumed that the first layer 43 has a first relaxation thickness RT1A (RT1B) and the second layer 44 has a second relaxation thickness RT2A (RT2B). In this case, the thickness ratio (RT2A / RT1A) of the second relaxation thickness RT2A to the first relaxation thickness RT1A in the first relaxation portion 58 shown in Figure 8 is smaller than the thickness ratio (RT2B / RT1B) in the second relaxation portion 59 shown in Figure 9. Of course, the thickness ratio (RT2A / RT1A) may be the same as the thickness ratio (RT2B / RT1B).

[0137] For example, if the total thickness RT0 (RT1A+RT2A or RT1B+RT2B) defined by the relaxation depth DR of bottom well region 12 is the same in first relaxation portion 58 and second relaxation portion 59, the first relaxation thickness RT1A in first relaxation portion 58 is greater than the first relaxation thickness RT1B in second relaxation portion 59. Conversely, the second relaxation thickness RT2A in first relaxation portion 58 is less than the second relaxation thickness RT2B in second relaxation portion 59. However, if the thickness ratio (RT2A / RT1A) is the same as the thickness ratio (RT2B / RT1B), the first relaxation thickness RT1A may be equal to the first relaxation thickness RT1B, and the second relaxation thickness RT2A may be equal to the second relaxation thickness RT2B.

[0138] In this embodiment, the first relaxation thickness RT1A may be 0.2 μm or more and 1.0 μm or less, and the second relaxation thickness RT2A may be 0.2 μm or more and 1.0 μm or less. The first relaxation thickness RT1A is preferably 0.4 μm or more and 0.8 μm or less, and the second relaxation thickness RT2A is preferably 0.4 μm or more and 0.8 μm or less.

[0139] The first relaxation thickness RT1B may be 0.1 μm or more and 0.6 μm or less, and the second relaxation thickness RT2B may be 0.1 μm or more and 0.6 μm or less. The first relaxation thickness RT1B is preferably 0.2 μm or more and 0.5 μm or less, and the second relaxation thickness RT2B is preferably 0.2 μm or more and 0.5 μm or less.

[0140] 6 and 7 , a first boundary surface 60 between the first layer 43 and the second layer 44 in the first relaxation section 58 is located closer to the first main surface 3 than a second boundary surface 61 between the first layer 43 and the second layer 44 in the second relaxation section 59. Conversely, the second boundary surface 61 is located closer to the second main surface 4 than the first boundary surface 60.

[0141] The semiconductor device 1 includes a buried insulating layer 62 buried in the recess 40 of the second semiconductor layer 7. The buried insulating layer 62 may also be referred to as an "interlayer insulating layer," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this form, the buried insulating layer 62 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0142] 6 and 7 , the buried insulating layer 62 is buried in the recess 40 such that an upper edge 63 of the trench 31 is exposed from the first main surface 3. The upper edge 63 of the trench 31 may be a portion at the top of the trench 31 where the side surface 34 of the trench 31 intersects with the first main surface 3. In other words, the buried insulating layer 62 does not cover the periphery of the trench 31 on the first main surface 3, but is contained within the inner region of the trench 31 in the width direction of the trench 31. In this embodiment, the upper surface 64 of the buried insulating layer 62 is located closer to the bottom of the trench 31 than the first main surface 3 in the depth direction of the trench 31.

[0143] 5, buried insulating layer 62 is embedded in recess 40 over the entire depth direction of trench 31, and is formed in a strip shape extending in the depth direction of trench 31. Referring to Figures 6 and 7, buried insulating layer 62 contacts source region 45 and first contact region 47 on side surface 34 of recess 40 (side surface 34 of trench 31).

[0144] 8 and 9, the thickness IT of the buried insulating layer 62 may be, for example, 0.05 μm or more and 0.8 μm or less. The thickness IT may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.3 μm or less, 0.3 μm or more and 0.55 μm or less, and 0.55 μm or more and 0.8 μm or less.

[0145] 6 and 7 , semiconductor device 1 includes silicide layers 65 formed on the surfaces of source region 45 and first contact region 47. Formation of silicide layer 65 can reduce contact resistance with source region 45 and first contact region 47.

[0146] In this embodiment, the silicide layer 65 is selectively formed on the protruding portion 41 of each mesa portion 36. More specifically, the silicide layer 65 is formed along the upper surface (first main surface 3) and side surface 34 (side surface 34 of the recess 40) of the protruding portion 41 of the first mesa portion 36A. A non-silicide portion 66 defined by the silicide layer 65 (surrounded on three sides) may be formed in the inner portion of the protruding portion 41 of the first mesa portion 36A, spaced inward from the upper surface (first main surface 3) and side surface 34 of the first mesa portion 36A.

[0147] The silicide layer 65 may be, for example, nickel silicide, titanium silicide, aluminum silicide, copper silicide, etc. The thickness ST2 of the silicide layer 65 may be, for example, 50 nm or more and 500 nm or less in the vertical direction Z from the upper surface (first main surface 3) and side surface 34 of the protruding portion 41 of the mesa portion 36. The thickness ST2 of the silicide layer 65 is preferably 80 nm or more and 300 nm or less.

[0148] 5 to 7, semiconductor device 1 includes a Schottky region 67 in second mesa portion 36B in a surface layer portion of first main surface 3. Schottky region 67 is formed in a region between a plurality of gate structures 11. Schottky region 67 is provided by a part of drift region 8 in second mesa portion 36B.

[0149] In this embodiment, the Schottky region 67 is formed across the second mesa portion 36B in the width direction, from one side surface 34 of the second mesa portion 36B to the other side surface 34 (one side surface 34 and the other side surface 34 of the trench 31). The Schottky region 67 extends continuously in a strip shape along the depth direction of the trench 31 in each second mesa portion 36B.

[0150] The Schottky region 67 is in contact with the trench insulating film 32 on one side surface 34 and the other side surface 34 of the second mesa portion 36B. The Schottky region 67 faces the buried conductive layer 33 across the trench insulating film 32. The Schottky region 67 is in contact with the buried insulating layer 62 on one side surface 34 and the other side surface 34 of the second mesa portion 36B.

[0151] The Schottky region 67 extends from the bottom surface 35 of the trench 31 to the first main surface 3 in the thickness direction of the chip 2 and is exposed from the first main surface 3. The Schottky region 67 may straddle the trench insulating film 32 and the buried insulating layer 62 in the depth direction of the trench 31. The Schottky region 67 may cross the boundary between the trench insulating film 32 and the buried insulating layer 62 in the depth direction of the trench 31. The Schottky region 67 may cover the boundary between the trench insulating film 32 and the buried insulating layer 62 in the depth direction of the trench 31.

[0152] The Schottky region 67 has the same n-type impurity concentration (peak value) as the second semiconductor layer 7 (drift region 8). １５ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration may have the following peak value:

[0153] 8 and 9 , the Schottky region 67 has a Schottky thickness SBT. The Schottky thickness SBT is the thickness of the Schottky region 67 in the vertical direction Z. For example, the Schottky thickness SBT may be the thickness from a Schottky junction 68 (described later) to the bottom surface 35 of the trench 31 in the vertical direction Z. In this embodiment, the Schottky thickness SBT may be the thickness from the first main surface 3 to the bottom surface 35 of the trench 31. The Schottky thickness SBT may be, for example, not less than 0.1 μm and not more than 1.5 μm, preferably not less than 0.5 μm and not more than 1.5 μm.

[0154] The surface of the Schottky region 67 may be a non-silicide portion 69 where no silicide is formed. In this embodiment, in the Schottky junction 68, the entire first main surface 3 between the one side surface 34 and the other side surface 34 of the second mesa portion 36B is the non-silicide portion 69. This allows a good Schottky barrier to be formed in the Schottky junction 68.

[0155] 6 and 7 , semiconductor device 1 includes a first principal surface electrode 70. First principal surface electrode 70 is formed on first principal surface 3 so as to cover buried insulating layer 62. First principal surface electrode 70 has a layered structure including a barrier layer 71 and a main body layer 72, which are layered in this order from the first principal surface 3 side.

[0156] The barrier layer 71 is formed in a film shape along the first main surface 3 and the inner surfaces of the recess 40 (the side surfaces 34 of the recess 40 and the upper surface 64 of the buried insulating layer 62). The barrier layer 71 is in ohmic contact with the silicide layer 65 and forms a Schottky junction 68 with the Schottky region 67. The Schottky junction 68 is formed along the first main surface 3 from one side surface 34 to the other side surface 34 in the width direction of the second mesa portion 36B. The barrier layer 71 further defines a second recess 73 within the recess 40.

[0157] The barrier layer 71 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 71 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 71 is preferably 0.1 μm or more and 0.2 μm or less.

[0158] The main body layer 72 is formed on the barrier layer 71. The main body layer 72 covers the entire main surface of the barrier layer 71. The main body layer 72 is partially embedded in the second recess 73. The main body layer 72 is ohmically connected to the source region 45 and the first contact region 47 via the barrier layer 71 and the silicide layer 65. In this embodiment, the first main surface electrode 70 is connected to the source region 45 and the first contact region 47 at the side surface 34 of the recess 40 and the first main surface 3. Therefore, in the semiconductor device 1, the first main surface electrode 70 may include the source pad electrode 20 described above. The bottom well region 12 is fixed to the source potential via the first contact region 47 and the second contact region 56.

[0159] Furthermore, the main body layer 72 is in Schottky contact with the Schottky region 67 via the barrier layer 71. As a result, the semiconductor device 1 has a Schottky barrier diode SBD built in between the first main surface electrode 70 and the Schottky region 67 on the first main surface 3.

[0160] The main body layer 72 includes at least one of a pure Al layer (meaning an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0161] The thickness of the main layer 72 exceeds the thickness of the barrier layer 71. The thickness of the main layer 72 may be 1 μm or more and 10 μm or less. The thickness of the main layer 72 is preferably 3 μm or more and 6 μm or less.

[0162] The semiconductor device 1 includes a resin layer 74 that covers the first principal surface electrode 70. The resin layer 74 is formed in a film shape along the principal surface of the first principal surface electrode 70. The resin layer 74 may include a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 74 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 74 includes polybenzoxazole.

[0163] (3) Detailed Structure of the Vicinity of the Peripheral Region 10 of the Semiconductor Device 1 Fig. 10 is an enlarged plan view showing a main portion of the active region 9. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 10. Fig. 12 is a cross-sectional view showing the peripheral region 10. Detailed structures of the active region 9 near the peripheral region 10 and the peripheral region 10 will be described with reference to Figs. 10 to 12.

[0164] 11 and 12 , the aforementioned outer well region 13 is formed in the surface layer portion of the first main surface 3 in the peripheral region 10 (the peripheral portion of the first main surface 3). A source potential is applied to the outer well region 13. The outer well region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the body region 30.

[0165] The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the first contact region 47. The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the second layer 44 of the bottom well region 12. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the first layer 43 of the bottom well region 12.

[0166] The outer well region 13 is formed in a surface layer portion of the second semiconductor layer 7. The outer well region 13 extends in a layered manner along the first main surface 3. The outer well region 13 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the plurality of gate structures 11. The outer well region 13 extends in a strip shape along the periphery (periphery of the active region 9) of the first main surface 3 in a plan view.

[0167] In this embodiment, the outer well region 13 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. In other words, the outer well region 13 collectively surrounds the plurality of gate structures 11.

[0168] The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 13 has an inner edge portion on the side of the multiple gate structures 11 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 13 defines the boundary between the active region 9 and the outer periphery region 10.

[0169] The inner edge of the outer well region 13 is connected to the ends of the multiple gate structures 11 in a portion extending in the first direction X. The inner edge of the outer well region 13 faces the buried conductive layer 33 with the trench insulating film 32 interposed therebetween.

[0170] The inner edge of the outer well region 13 may be located closer to the inner side of the plurality of gate structures 11 than the ends of the plurality of gate structures 11. The inner edge of the outer well region 13 may have a portion located in a region between the plurality of gate structures 11 and connected to the body region 30. The outer edge of the outer well region 13 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 13.

[0171] The outer well region 13 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 13 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0172] The outer well region 13 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 13 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0173] In this embodiment, the outer well region 13 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 11. The depth of the outer well region 13 may be greater or smaller than the depth of the body region 30.

[0174] The outer well region 13 may have a portion located on the bottom side of the second semiconductor layer 7 relative to the depth positions of the bottom walls of the plurality of gate structures 11. In this case, the outer well region 13 may be connected to either or both of the second layer 44 of the bottom well region 12 and the first layer 43 of the bottom well region 12.

[0175] The outer well region 13 forms a pn junction with the second semiconductor layer 7. The outer well region 13 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 13 spreads horizontally and in the thickness direction, and integrates with the depletion layers spreading from the body region 30 and the bottom well region 12. The outer well region 13 expands the depletion layers spreading from the body region 30 and the bottom well region 12 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 10) of the first main surface 3.

[0176] The semiconductor device 1 includes a p-type outer contact region 75 formed in a surface layer portion of the outer well region 13. The outer contact region 75 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 13. The p-type impurity concentration of the outer contact region 75 is higher than the p-type impurity concentration of the body region 30.

[0177] The p-type impurity concentration of the outer contact region 75 may be approximately equal to the p-type impurity concentration of the first contact region 47. The p-type impurity concentration of the outer contact region 75 may be higher or lower than the p-type impurity concentration of the first contact region 47.

[0178] The outer contact region 75 is formed at a distance from the bottom of the outer well region 13 toward the first main surface 3, and faces the second semiconductor layer 7 across a part of the outer well region 13. The outer contact region 75 extends in a strip shape along the outer well region 13 (active region 9) in a plan view.

[0179] In this embodiment, the outer contact region 75 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 75 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0180] The semiconductor device 1 may include a plurality of outer contact regions 75 arranged at intervals along the extension direction of the outer well region 13 so as to surround the plurality of gate structures 11. In this case, the plurality of outer contact regions 75 may each extend in a strip shape along the extension direction of the outer well region 13.

[0181] The outer contact region 75 has a width less than the width of the outer well region 13 and is formed in the outer well region 13. The outer contact region 75 is formed in the inner part of the outer well region 13 with a gap between both edges of the outer well region 13. The outer contact region 75 is biased toward the outer edge of the outer well region 13 relative to the central part of the outer well region 13. The outer contact region 75 may be formed in the central part of the outer well region 13.

[0182] 11 and 12 , the above-mentioned surface insulating film 15 extends from the peripheral region 10 to the active region 9 and covers the peripheries of the ends of the plurality of gate structures 11 in the active region 9. The surface insulating film 15 is connected to the trench insulating films 32 of the plurality of gate structures 11 and exposes the buried conductive layer 33 and the buried insulating layer 62. The surface insulating film 15 has portions located in regions between the plurality of gate structures 11. The surface insulating film 15 is connected to the trench insulating films 32 at both the portions of the ends of the plurality of gate structures 11 that extend in the first direction X and the portions that extend in the second direction Y.

[0183] The surface insulating film 15 directly covers the first main surface 3 around the plurality of gate structures 11. The surface insulating film 15 selectively covers the peripheral region of the first main surface 3 relative to the plurality of gate structures 11 in a film-like manner.

[0184] The surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14. The surface insulating film 15 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The surface insulating film 15 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 11 (active regions 9) in plan view.

[0185] The surface insulating film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0186] The semiconductor device 1 includes a main surface insulating film 76 formed on the first main surface 3. The main surface insulating film 76 extends from the peripheral region 10 toward the active region 9 to the gate structure 11, and is formed integrally with the trench insulating film 32. The main surface insulating film 76 may be an extension portion that is extended from the gate structure 11 toward the peripheral region 10.

[0187] The main surface insulating film 76 covers the first main surface 3 and the surface insulating film 15 exposed between the gate structure 11 and the surface insulating film 15. The main surface insulating film 76 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 76 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D.

[0188] The main surface insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0189] The aforementioned gate wiring 17 is disposed on the main surface insulating film 76 and the surface insulating film 15. The gate wiring 17 is selectively routed on the main surface insulating film 76 and the surface insulating film 15 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 11, and faces the outer well region 13 with the main surface insulating film 76 and the surface insulating film 15 interposed therebetween.

[0190] The gate wiring 17 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 17 is disposed on the main surface insulating film 76 and faces the outer well region 13 with the main surface insulating film 76 in between. The inner edge portion of the gate wiring 17 covers the ends (both ends in this embodiment) of the multiple gate structures 11 and is mechanically and electrically connected to the multiple gate structures 11.

[0191] Specifically, the inner edge of the gate wiring 17 is mechanically and electrically connected to the plurality of buried conductive layers 33. In this embodiment, the inner edge of the gate wiring 17 is integrally formed with the plurality of buried conductive layers 33. In other words, the gate wiring 17 is formed as an extension of the plurality of buried conductive layers 33, and is drawn out from the trench 31 onto the main surface insulating film 76.

[0192] The outer edge of the gate wiring 17 is formed as an extension portion that is extended from above the main surface insulating film 76 onto the laminated structure of the main surface insulating film 76 and the surface insulating film 15, and is disposed on this laminated structure. The outer edge of the gate wiring 17 faces the outer well region 13 with the main surface insulating film 76 and the surface insulating film 15 sandwiched therebetween.

[0193] The outer edge of the gate wiring 17 is formed at a distance from the plurality of field regions 14 toward the plurality of gate structures 11. Specifically, the outer edge of the gate wiring 17 is formed at a distance from the outer edge of the outer well region 13 toward the plurality of gate structures 11. The outer edge of the gate wiring 17 is formed at a distance from the inner edge of the outer contact region 75 toward the plurality of gate structures 11.

[0194] The semiconductor device 1 may include a plurality of gate wirings 17. In this case, the plurality of gate wirings 17 may be arranged at least at both ends of the plurality of gate structures 11. One of the gate wirings 17 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) one end of the plurality of gate structures 11. The other of the gate wirings 17 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) the other end of the plurality of gate structures 11. Of course, the plurality of gate wirings 17 may have a portion extending in the second direction Y.

[0195] The aforementioned interlayer insulating film 16 covers the main surface insulating film 76 in a film-like manner in the peripheral region 10. Specifically, the interlayer insulating film 16 directly covers the main surface insulating film 76 in a film-like manner, and faces the outer well region 13, the outer contact region 75, and the plurality of field regions 14 with the main surface insulating film 76 interposed therebetween.

[0196] The interlayer insulating film 16 covers the gate wiring 17 and the gate pad wiring 18. The interlayer insulating film 16 covers the entire gate wiring 17 and the entire gate pad wiring 18. The interlayer insulating film 16 has a portion facing the main surface insulating film 76 with the gate wiring 17 interposed therebetween, and a portion facing the main surface insulating film 76 with the gate wiring 17 interposed therebetween. The interlayer insulating film 16 has a portion facing the outer well region 13 with the gate wiring 17 interposed therebetween, and a portion facing the outer well region 13 with the gate pad wiring 18 interposed therebetween.

[0197] The interlayer insulating film 16 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer insulating film 16 is disposed in the active region 9. The inner edge portion of the interlayer insulating film 16 is positioned on the inner side of the first main surface 3 with respect to the inner edge portions of the gate wiring 17 and the peripheral edge portion of the gate pad wiring 18, and covers the ends of the multiple gate structures 11.

[0198] The inner edge of the interlayer insulating film 16 covers the buried conductive layer 33 at the ends of the multiple gate structures 11 and is connected to the buried insulating layer 62. In this embodiment, the interlayer insulating film 16 is formed integrally with the buried insulating layer 62. The portion of the interlayer insulating film 16 located inside the trench 31 is formed as the buried insulating layer 62. The connection portion of the interlayer insulating film 16 with the buried insulating layer 62 may be considered to be part of the buried insulating layer 62 or may be considered to be part of the interlayer insulating film 16.

[0199] The inner edge of the interlayer insulating film 16 has a portion located in a region between the plurality of gate structures 11. The inner edge of the interlayer insulating film 16 covers either or both of the body region 30 and the outer well region 13 in the region between the plurality of gate structures 11, with the surface insulating film 15 sandwiched therebetween.

[0200] The outer edge of the interlayer insulating film 16 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer insulating film 16 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 15.

[0201] The semiconductor device 1 includes one or more (one in this embodiment) source openings 19 formed in the interlayer insulating film 16. The source opening 19 penetrates the interlayer insulating film 16 in the inner part of the active region 9, and collectively exposes the multiple gate structures 11 and the multiple mesa portions 36. In this embodiment, the source opening 19 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion recessed along the gate pad wiring 18).

[0202] The source openings 19 are formed at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 11 toward the inner portion of the first main surface 3, and expose the inner portions of the plurality of gate structures 11 and the inner portions of the plurality of mesa portions 36. Specifically, the source openings 19 expose the trench insulating film 32 and the buried insulating layer 62 in the inner portions of the plurality of gate structures 11.

[0203] The above-described gate finger electrode 25 may be a part of the first main surface electrode 70. Like the source pad electrode 20, the gate finger electrode 25 has a laminated structure including a barrier layer 71 and a main body layer 72 laminated in this order from the first main surface 3 side.

[0204] The gate finger electrodes 25 extend into the plurality of gate openings 77 from above the interlayer insulating film 16, and are mechanically and electrically connected to the gate wiring 17 within the plurality of gate openings 77. As a result, the gate potential applied to the gate pad electrode 24 is applied to the plurality of gate structures 11 via the gate finger electrodes 25. More specifically, the gate finger electrodes 25 are mechanically and electrically connected to the gate wiring 17 through the gate openings 77.

[0205] The plurality of gate openings 77 penetrate the interlayer insulating film 16 and selectively expose the gate wiring 17. In this embodiment, the plurality of gate openings 77 extend in a strip shape following the direction in which the gate wiring 17 extends.

[0206] The plurality of gate openings 77 may be formed at intervals along the extension direction of the gate wiring 17. The plurality of gate openings 77 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 11 may be formed in a quadrangular or hexagonal shape in a plan view.

[0207] The plurality of gate openings 77 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 77 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0208] Gate finger electrode 25 has an inner edge portion on the inward side of first main surface 3 and an outer edge portion on the peripheral side of first main surface 3. The inner edge portion of gate finger electrode 25 is formed at a distance from the ends of the multiple gate structures 11 toward the peripheral side of first main surface 3. In other words, gate finger electrode 25 does not face the multiple gate structures 11 in the stacking direction.

[0209] The inner edge of the gate finger electrode 25 is disposed on the gate wiring 17. The inner edge of the gate finger electrode 25 faces the peripheral edge of the source pad electrode 20 in the horizontal direction above the gate wiring 17. The inner edge of the gate finger electrode 25 is formed at a distance from the middle of the gate wiring 17 towards the peripheral edge of the first main surface 3.

[0210] The outer edge of the gate finger electrode 25 is drawn out from above the gate wiring 17 toward the periphery of the first main surface 3, and is disposed on the interlayer insulating film 16 in a region outside the gate wiring 17. In other words, the outer edge of the gate finger electrode 25 does not face the gate wiring 17 in the stacking direction. The outer edge of the gate finger electrode 25 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0211] The outer edge of gate finger electrode 25 is disposed at a distance from the outer edge of outer well region 13 toward the inside of first main surface 3, and faces outer well region 13 across surface insulating film 15 and interlayer insulating film 16. The outer edge of gate finger electrode 25 is disposed on the peripheral side of first main surface 3 relative to the outer edge of outer well region 13, and may face second semiconductor layer 7 in the stacking direction.

[0212] The above-described source finger electrodes 27 may be part of the first principal surface electrode 70. Like the source pad electrode 20, the source finger electrodes 27 have a laminated structure including a barrier layer 71 and a main body layer 72 laminated in this order from the first principal surface 3 side.

[0213] Source finger electrodes 27 extend into the plurality of outer openings 80 from above interlayer insulating film 16, and are mechanically and electrically connected to outer contact regions 75 within the plurality of outer openings 80. As a result, a source potential applied to source pad electrode 20 is applied to the plurality of source regions 45, first contact regions 47, and Schottky region 67 via source finger electrodes 27.

[0214] The outer opening 80 is formed at a distance from the gate wiring 17 on the peripheral edge side of the first main surface 3. The outer opening 80 penetrates the surface insulating film 15 and the interlayer insulating film 16 to expose the outer contact region 75.

[0215] The outer opening 80 has a width less than the width of the outer contact region 75 and is spaced apart from the inner and outer edges of the outer contact region 75 to expose an inner portion of the outer contact region 75. The outer opening 80 may expose the outer well region 13.

[0216] In this embodiment, the outer opening 80 extends in a band shape following the extension direction of the outer contact region 75. In this embodiment, the outer opening 80 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 75 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0217] The semiconductor device 1 may have a plurality of outer openings 80. In this case, the plurality of outer openings 80 may be formed at intervals following the extension direction of the outer contact region 75. Furthermore, the plurality of outer openings 80 may each extend in a strip shape following the extension direction of the outer contact region 75.

[0218] Source finger electrodes 27 have inner edge portions on the inner side of first main surface 3 and outer edge portions on the peripheral side of first main surface 3. The inner edge portions of source finger electrodes 27 are arranged at a distance from gate finger electrodes 25 on the peripheral side of first main surface 3, and face gate finger electrodes 25 in the horizontal direction.

[0219] The inner edge of source finger electrode 27 is formed at a distance from the middle of outer contact region 75 toward the inside of first main surface 3. The inner edge of source finger electrode 27 may be disposed on outer well region 13 or on outer contact region 75.

[0220] The outer edge portions of source finger electrodes 27 are drawn out from above outer contact region 75 toward the peripheral edge of first main surface 3, and are arranged on interlayer insulating film 16 in a region outside outer contact region 75. The outer edge portions of source finger electrodes 27 are arranged at a distance from innermost field region 14 on the inward side of first main surface 3.

[0221] The outer edge of source finger electrode 27 is disposed at a distance from the outer edge of outer well region 13 toward the inside of first main surface 3, and faces outer well region 13 across interlayer insulating film 16. The outer edge of source finger electrode 27 may be drawn out from the outer edge of outer well region 13 to the peripheral edge of first main surface 3, and faces second semiconductor layer 7 across interlayer insulating film 16.

[0222] (4) Effects of the Semiconductor Device 1 According to the First Embodiment The semiconductor device 1 is used, for example, as a switching element. In this case, the current flowing through the load is turned on and off by turning the gate voltage on and off while a voltage that makes the drift region 8 side positive is applied between the source region 45 and the drift region 8. When the load is inductive, blocking the current flowing through the load (i.e., turning the gate voltage off) generates a back electromotive force in the load. Due to this back electromotive force, a voltage that makes the source region 45 side positive may be applied between the source region 45 and the drift region 8.

[0223] In such a case, if the rectification of the body diode BD causes a current to flow to the load as, for example, a reflux current, the following problems occur.

[0224] For example, when holes move from the body region 30 constituting the body diode BD to the drift region 8 and cause a current to flow, electrons of the majority carriers may recombine with the holes that have moved from the body region 30 near the trench 31 in the drift region 8 (for example, on the side of the trench 31). Therefore, the energy generated by this recombination may cause crystal defects in the SiC of the second semiconductor layer 7 (drift region 8) to expand in a direction parallel to the stacking direction of the second semiconductor layer 7, potentially reaching the path of the drain current (for example, the channel) when the semiconductor device 1 is on. This may result in an increase in on-resistance when the semiconductor device 1 forms a channel in the first channel region 37 and performs a switching operation.

[0225] In such a case, current flows preferentially through the Schottky diode SBD, and the current flowing through the body diode BD can be reduced or eliminated. Thus, the current flowing through the semiconductor device 1 can be passed to a load as, for example, a return current. Since the current during the off-state flows to the drift region 8 via the Schottky region 67 of the second mesa portion 36B, almost no carrier movement occurs between the body region 30 and the drift region 8. This prevents the recombination of holes and electrons in the drift region 8. As a result, the expansion of crystal defects in SiC in the second semiconductor layer 7 can be suppressed, thereby suppressing an increase in the on-resistance of the transistor Tr.

[0226] According to the semiconductor device 1, for example, referring to FIG. 6 , an MIS transistor structure Tr is disposed in a first mesa portion 36A. The Schottky barrier diode SBD is disposed in a second mesa portion 36B that is wider than the first mesa portion 36A. Because the second mesa portion 36B is wider than the first mesa portion 36A, the voltage drop across the second mesa portion 36B in the thickness direction of the chip 2 can be kept low during operation of the Schottky barrier diode SBD. As a result, the potential difference between the drift region 8 and the body region 30, which is fixed to the source potential when a back electromotive force is generated, can be kept small. This delays the start of current flow through the body diode BD even when the body diode BD is turned on, thereby suppressing the expansion of crystal defects in SiC in the second semiconductor layer 7.

[0227] (5) Modifications of the active region 9 according to the first embodiment Modifications applied to the active region 9 according to the first embodiment are shown below. Figures 13 to 22 are diagrams showing first to eighth modifications of the semiconductor device 1.

[0228] 13 , the body region 30 and the source region 45 are further formed between the trench 31 and the Schottky region 67 in the second mesa portion 36B. In this embodiment, the body region 30 and the source region 45 are formed along the side surface 34 of each of the pair of trenches 31 that sandwich the second mesa portion 36B, on the Schottky region 67 side. The Schottky region 67 is sandwiched between the stacked structures of the body region 30 and the source region 45 on both sides in the first direction X. As a result, the first channel region 37 is also formed in the body region 30 on the second mesa portion 36B side, thereby improving the current density of the MIS transistor Tr.

[0229] 14 , a stacked structure of the body region 30 and the source region 45 is formed across the second mesa portion 36B in the width direction, from one side surface 34 to the other side surface 34 of the second mesa portion 36B (one side surface 34 and the other side surface 34 of the trench 31). This provides a portion of the second mesa portion 36B that functions as the MIS transistor Tr. Since the first channel region 37 is also formed in the body region 30 on the second mesa portion 36B side, the current density of the MIS transistor Tr can be improved.

[0230] The Schottky region 67 is disposed below the body region 30 throughout the entire second mesa portion 36B. The Schottky region 67 faces the source pad electrode 20 in the thickness direction of the chip 2, sandwiching the body region 30 and the source region 45 therebetween. The Schottky region 67 is not in contact with the source pad electrode 20 and is physically separated from it.

[0231] A buried electrode 82 for forming a Schottky junction 68 is buried in one of the pair of trenches 31 that define the second mesa portion 36B, instead of the gate structure 11. The buried electrode 82 is buried up to the middle of the trench 31 in the depth direction. The buried electrode 82 has an upper surface 83 that is located closer to the second main surface 4 than the first main surface 3. A low step 84 is formed on the second main surface 4 side between the upper surface 83 of the buried electrode 82 and the first main surface 3. This step 84 forms a recess 85 in the upper part of the trench 31, which is defined by the upper surface 83 of the buried electrode 82 and the side surface 34 of the trench 31.

[0232] The buried electrode 82 extends from the bottom surface 35 toward the first main surface 3 in the depth direction of the trench 31 across the Schottky region 67, the body region 30, and the source region 45. The buried electrode 82 vertically crosses the boundary between the Schottky region 67 and the body region 30 and the boundary between the body region 30 and the source region 45.

[0233] The buried electrode 82 contacts the Schottky region 67 along the side surface 34 of the trench 31. In this embodiment, the buried electrode 82 further contacts the body region 30 and the source region 45 along the side surface of the trench 31. The buried electrode 82 forms a Schottky junction 68 with the Schottky region 67.

[0234] The buried electrode 82 is made of a conductor capable of forming the Schottky junction 68. For example, the buried electrode 82 may be made of a metal material such as tungsten, titanium, nickel, cobalt, or a silicide alloy film of these metals.

[0235] The barrier layer 71 is formed in a film shape along the inner surface of the recess 85 (the side surface 34 of the recess 85 and the upper surface 83 of the buried electrode 82). The barrier layer 71 is in ohmic contact with the buried electrode 82. The body layer 72 is in ohmic contact with the buried electrode 82 via the barrier layer 71. As a result, the semiconductor device 1 includes a Schottky barrier diode SBD embedded between the first principal surface electrode 70 and the Schottky region 67 on the side surface 34 of the trench 31. The Schottky barrier diode SBD is disposed at a position spaced apart from the first principal surface 3 in the depth direction. In this configuration, the Schottky barrier diode SBD is disposed near the bottom surface 35 of the trench 31. This further reduces the voltage drop across the second mesa portion 36B in the thickness direction of the chip 2 during operation of the Schottky barrier diode SBD. As a result, the potential difference between the body region 30 and the drift region 8 can be maintained even smaller.

[0236] 15 , the semiconductor device 1 further includes a second well region 86 disposed between the bottom well regions 12 at the bottoms of a pair of trenches 31 that sandwich the second mesa portion 36B. The second well region 86 is disposed in the drift region 8. The second well region 86 is disposed at the same depth as the bottom well region 12 in the thickness direction of the chip 2. The second well region 86 is disposed below the Schottky region 67. A portion of the drift region 8 is interposed between the second well region 86 and the bottom well regions 12 of the pair of trenches 31. This ensures a current path 87 of the Schottky barrier diode SBD.

[0237] The bottom well regions 12 and the second well regions 86 are arranged at a first pitch PT1 as a whole. In the arrangement direction of the trenches 31 (in this embodiment, the first direction X), the bottom well regions 12 and the second well regions 86 are arranged at equal intervals from each other. This makes it possible to maintain a balanced breakdown voltage below the trenches 31.

[0238] In this embodiment, the second well region 86 has a stacked structure of a first layer 88 and a second layer 89. The first layer 88 may be formed to the same thickness and impurity concentration as the first layer 43. The second layer 89 may be formed to the same thickness and impurity concentration as the second layer 44. The stacked structure of the first layer 88 and the second layer 89 is continuous in the depth direction of the trench 31.

[0239] The second well region 86 may extend laterally along the first major surface 3 and be connected to the bottom well region 12. As a result, the second well region 86 is fixed to the source potential via the bottom well region 12. In this configuration, the second well region 86 is connected to the bottom well region 12 by the connection between the second layer 89 and the second layer 44. It is preferable that the second layer 89 selectively extends to one side of a pair of trenches 31 that sandwich the second mesa portion 36B, thereby connecting to the second layer 89 of the bottom well region 12 on one side. This reliably ensures a current path 87 between the second well region 86 and the trench 31 on the other side.

[0240] 16 , the second well region 86 may not be connected to adjacent bottom well regions 12, but may be physically separated from the plurality of bottom well regions 12. In this case, referring to FIGS. 17 and 18 , the second well region 86 may be electrically connected to the body region 30 at the end of the trench 31 in the depth direction.

[0241] The semiconductor device 1 includes a third contact region 90 formed at an end of the Schottky region 67 in the depth direction of the trench 31. The third contact region 90 connects the outer well region 13 and the second well region 86. More specifically, it connects the outer contact region 75 and the second layer 89. The third contact region 90 is formed along the side surface of the Schottky region 67 from the outer contact region 75 toward the second main surface 4, and is connected to the second well region 86.

[0242] The third contact region 90 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 30. The p-type impurity concentration (peak value) of the third contact region 90 is 1×10 １８ cm－３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0243] 19, the semiconductor device 1 according to the fifth modification has a structure that combines the structure according to the first modification (FIG. 13) and the structure according to the third modification (FIG. 15).

[0244] 20, the semiconductor device 1 according to the sixth modification has a structure that combines the structure according to the second modification (FIG. 14) and the structure according to the third modification (FIG. 15).

[0245] 21, the semiconductor device 1 according to the seventh modification has a structure (FIG. 16) that combines the structure according to the first modification (FIG. 13) and the structure according to the fourth modification.

[0246] 22, the semiconductor device 1 according to the eighth modification has a structure that combines the structure according to the second modification (FIG. 14) and the structure according to the fourth modification (FIG. 16).

[0247] (6) Detailed Structure of Active Region 9 of Semiconductor Device 1 According to Second Embodiment FIG. 23 is a plan view showing the active region 9 and gate structure 11 according to the second embodiment. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 23. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 23. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 23. FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 23.

[0248] 23 to 28, semiconductor device 1 includes a p-type bottom well region 91 instead of bottom well region 12 and second well region 86 individually formed at the bottom of each trench 31. For clarity, bottom well region 91 is shown by dot hatching in FIGS.

[0249] The bottom well region 91 may have a single layer structure of a p-type region in which the p-type impurity concentration is approximately constant in the thickness direction of the chip 2. The impurity concentration of the bottom well region 12 is 1×10 １５cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0250] 23 , the bottom well region 91 has a linear shape in a plan view that continuously crosses the plurality of trenches 31, the first mesa portion 36A, and the second mesa portion 36B. In this configuration, the plurality of bottom well regions 91 are arranged at intervals from one another in the longitudinal direction of the trench 31. As a result, a plurality of first line regions 92 each consisting of the plurality of bottom well regions 91 and a plurality of second line regions 93 each consisting of the drift region 8 (Schottky region 67) sandwiched between the plurality of bottom well regions 91 are alternately arranged in the longitudinal direction of the trench 31.

[0251] There are no particular limitations on the first line width LW1 of the first line region 92 and the second line width LW2 of the second line region 93 in the length direction of the trench 31. The first line width LW1 and the second line width LW2 can be changed as appropriate depending on the specifications of the semiconductor device 1. For example, from the perspective of ensuring a current path in the first mesa portion 36A, it is preferable that the second line width LW2 be larger than the first line width LW1.

[0252] 25 to 28, bottom well region 91 includes a base portion 94, a first extension portion 95, and a second extension portion 96 in a cross section across trench 31.

[0253] The base portion 94 has a linear shape in a plan view that continuously crosses the plurality of trenches 31, the first mesa portion 36A, and the second mesa portion 36B. The base portion 94 straddles the plurality of trenches 31 and integrally covers the bottoms of the plurality of trenches 31.

[0254] The first extension 95 extends from the base 94 in the first mesa 36A toward the first main surface 3. The first extension 95 has an upper end 97 in the middle of the first mesa 36A in the thickness direction of the chip 2. The upper end 97 of the first extension 95 is integrally connected to the body region 30. In FIG. 25 , the upper end 97 of the first extension 95 is indicated by a dashed line.

[0255] The second extension 96 extends from the base 94 in the second mesa 36B toward the first main surface 3. The second extension 96 has an upper end 98 in the middle of the second mesa 36B in the thickness direction of the chip 2. The upper end 98 of the second extension 96 is connected to the Schottky region 67. The upper end 98 of the second extension 96 is located at a position spaced apart from the first main surface 3, with the Schottky region 67 interposed therebetween. As a result, the second extension 96 faces the first main surface electrode 70 (source pad electrode 20) in the thickness direction of the chip 2, with the Schottky region 67 interposed therebetween.

[0256] 24, 25, and 28, in a cross-sectional view of the second mesa portion 36B in the length direction of the trench 31, the Schottky region 67 includes a main surface region 99 and an extension region 100.

[0257] The main surface region 99 continuously crosses the multiple first line regions 92 and the multiple second line regions 93 in the longitudinal direction of the trench 31. The main surface region 99 extends in a band shape in the longitudinal direction of the trench 31 along the first main surface 3, and is exposed from the first main surface 3 at both the multiple first line regions 92 and the multiple second line regions 93. The main surface region 99 is exposed from the first main surface 3 as a band-shaped region.

[0258] The extension region 100 extends from the main surface region 99 toward the second main surface 4 in the second line region 93. The extension region 100 extends in the thickness direction of the chip 2 between the bottom well regions 91 adjacent in the length direction of the trench 31, and provides a vertical current path between the first main surface 3 and the second main surface 4 in the second mesa portion 36B.

[0259] (7) Effects of the Semiconductor Device 1 According to the Second Embodiment In the semiconductor device 1 according to the second embodiment, as in the first embodiment, the Schottky barrier diode SBD is disposed in the second mesa portion 36B, which is wider than the first mesa portion 36A. Because the second mesa portion 36B is wider than the first mesa portion 36A, the voltage drop across the second mesa portion 36B in the thickness direction of the chip 2 can be kept low during operation of the Schottky barrier diode SBD. As a result, the potential difference between the drift region 8 and the body region 30, which is fixed to the source potential when a back electromotive force is generated, can be kept small. This delays the start of current flow through the body diode BD even when the body diode BD is turned on, thereby suppressing the expansion of crystal defects in SiC in the second semiconductor layer 7.

[0260] 23 , a plurality of bottom well regions 91 are arranged at regular intervals in the longitudinal direction of the trench 31. This makes it possible to maintain a good breakdown voltage below the first mesa portion 36A and the second mesa portion 36B in addition to maintaining a good breakdown voltage below the trench 31. In other words, a balanced breakdown voltage can be maintained throughout the entire active region 9.

[0261] (8) Modifications of the Active Region 9 According to the Second Embodiment Modifications applied to the active region 9 according to the second embodiment are shown below. Figures 29 to 34 are diagrams showing first and second modifications of the semiconductor device 1.

[0262] 29 and 30 , the second extension portion 96 of the bottom well region 91 may extend from the base portion 94 in the second mesa portion 36B toward the first main surface 3 and be exposed from the first main surface 3. An upper end portion 98 of the second extension portion 96 is exposed from the first main surface 3 and is connected to the first main surface electrode 70 (source pad electrode 20).

[0263] 30 , in the second mesa portion 36B, the multiple Schottky regions 67 are separated from one another by second extension portions 96. The second extension portions 96 may be wall portions that physically divide the Schottky region 67 into multiple portions in the longitudinal direction of the trench 31. The multiple Schottky regions 67 are each independently connected to the first principal surface electrode 70 (source pad electrode 20). Currents flowing from the source pad electrode 20 toward the drain pad electrode 29 flow from the source pad electrode 20 to each of the multiple Schottky regions 67 and join together near the bottom of the bottom well region 91.

[0264] 31 to 34 , the bottom well region 91 does not necessarily have the first extension portion 95 and the second extension portion 96. The bottom well region 91 may be formed by a base portion 94. The bottom well region 91 is arranged in the first mesa portion 36A with the drift region 8 sandwiched between the bottom well region 91 and the body region 30. The bottom well region 91 is connected to the Schottky region 67 in the second mesa portion 36B.

[0265] The semiconductor device 1 includes a fourth contact region 101 arranged along the side surface 34 of the trench 31. The fourth contact region 101 connects the body region 30 and the bottom well region 91. The fourth contact region 101 is formed in the first line region 92 from the bottom surface 35 of the trench 31 along the side surface 34. Referring to FIG. 31 , the fourth contact region 101 is arranged at an interval in the first direction X from the adjacent trench 31. This ensures an extension region 103 (described later) of the drift region 8 as a current region for the transistor between the adjacent trench 31 and the fourth contact region 101.

[0266] The fourth contact region 101 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 30. The p-type impurity concentration (peak value) of the fourth contact region 101 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0267] 31 and 33, in a cross-sectional view of first mesa portion 36A in the longitudinal direction of trench 31, drift region 8 includes intermediate region 102 and extension region 103.

[0268] The intermediate region 102 continuously crosses the plurality of first line regions 92 and the plurality of second line regions 93 in the length direction of the trench 31. The plurality of first line regions 92 are disposed between the trench 31 and the fourth contact region 101. The intermediate region 102 extends in a strip shape in the length direction of the trench 31 along the first main surface 3, and is in contact with the body region 30 at both the plurality of first line regions 92 and the plurality of second line regions 93. The intermediate region 102 is connected to the body region 30 as a strip-shaped region. This allows the first channel region 37 to be formed throughout the entire length direction of the trench 31, thereby improving the current density of the MIS transistor Tr.

[0269] The extension region 103 extends from the intermediate region 102 in the second line region 93 toward the second main surface 4. The extension region 103 extends in the thickness direction of the chip 2 between the bottom well regions 91 adjacent in the length direction of the trench 31, and provides a vertical current path between the first main surface 3 and the second main surface 4 in the first mesa portion 36A.

[0270] 31 and 34, in a cross-sectional view of the second mesa portion 36B in the longitudinal direction of the trench 31, the Schottky region 67 includes a main surface region 104 and an extension region 105.

[0271] The main surface region 104 continuously crosses the multiple first line regions 92 and the multiple second line regions 93 in the length direction of the trench 31. The main surface region 104 extends in a band shape in the length direction of the trench 31 along the first main surface 3, and is exposed from the first main surface 3 at both the multiple first line regions 92 and the multiple second line regions 93. The main surface region 104 is exposed from the first main surface 3 as a band-shaped region.

[0272] The extension region 105 extends from the main surface region 104 toward the second main surface 4 in the second line region 93. The extension region 105 extends in the thickness direction of the chip 2 between the bottom well regions 91 adjacent in the length direction of the trench 31, and provides a vertical current path between the first main surface 3 and the second main surface 4 in the second mesa portion 36B.

[0273] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0274] For example, in each of the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 6 may include a silicon single crystal. The second semiconductor layer 7 may include a silicon single crystal.

[0275] In the above-described embodiment, the trench pitch of the plurality of trenches 31 is divided into a first pitch PT1 and a second pitch PT2, thereby forming the wide second mesa portion 36B. Alternatively, even if the trench pitch of the plurality of trenches 31 is constant, the wide second mesa portion 36B may be formed by forming at least one trench 31 with a narrower width than the other trenches 31. In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0276] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0277] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0278] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4); first impurity regions (7, 8) of a first conductivity type in a surface layer portion of the first main surface (3); a plurality of trenches (31) in the first main surface (3); a plurality of mesa portions (36) partitioned by the plurality of trenches (31), the plurality of mesa portions (36) including, in a direction across the trenches (31), a first mesa portion (36A) each having a first width (WM1) and a second mesa portion (36B) each having a second width (WM2) wider than the first width (WM1); a second impurity region (30) of a second conductivity type and a third impurity region (45) of a first conductivity type, which are located in a surface layer portion of the first impurity region (7, 8) at least in the first mesa portion (36A) and arranged in this order from the second main surface (4) side along a side surface (34) of the trench (31); a control electrode (33) buried in at least the trench (31) adjacent to the first mesa portion (36A) and facing the second impurity region (30) via a control insulating film (32); a Schottky region (67) provided by the first impurity region (7, 8) at least in the second mesa portion (36B); a first electrode (20) ohmically connected to the third impurity region (45) and forming a Schottky junction (68) with the Schottky region (67); and a second electrode (29) ohmically connected to the first impurity region (7, 8).

[0279] [Appendix 1-2] The semiconductor device (1) according to appendix 1-1, wherein the plurality of trenches (31) are striped, the first mesa portion (36A) is defined between the plurality of trenches (31) arranged at a first pitch (PT1), and the second mesa portion (36B) is defined between the plurality of trenches (31) arranged at a second pitch (PT2) wider than the first pitch (PT1).

[0280] [Supplementary Note 1-2-1] The semiconductor device (1) according to Supplementary Note 1-2, wherein the plurality of trenches (31) have the same width.

[0281] [Appendix 1-3] The semiconductor device (1) according to appendix 1-2, wherein the second pitch (PT2) is more than 1 time and not more than 4 times the first pitch (PT1).

[0282] [Supplementary Note 1-4] The semiconductor device (1) according to Supplementary Note 1-2, wherein the Schottky region (67) extends from a bottom of the trench (31) to the first main surface (3) in a thickness direction of the chip (2) and is exposed from the first main surface (3), and the first electrode (20) includes a first main surface (3) electrode that is disposed on the first main surface (3) and forms the Schottky junction (68) between the Schottky region (67) and the first main surface (3) along the first main surface (3).

[0283] [Supplementary Note 1-4-2] The semiconductor device (1) according to Supplementary Note 1-4, wherein the second pitch (PT2) is more than 1 time and not more than 4 times the first pitch (PT1).

[0284] [Supplementary Note 1-5] The semiconductor device (1) according to Supplementary Note 1-2, wherein the first electrode (20) includes a first main surface electrode arranged on the first main surface (3) and a first buried electrode (82) buried in the trench (31) adjacent to the second mesa portion (36B), and the first buried electrode (82) forms the Schottky junction (68) between the Schottky region (67) and the first buried electrode (82) along a side surface (34) of the trench (31) adjacent to the second mesa portion (36B).

[0285] [Supplementary Note 1-5-2] The semiconductor device (1) according to Supplementary Note 1-5, wherein the second pitch (PT2) is more than 1 time and not more than 4 times the first pitch (PT1).

[0286] [Appendix 1-6] The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, including a well region (91) of a second conductivity type that is linear in a plan view and continuously crosses the plurality of trenches (31), the first mesa portion (36A), and the second mesa portion (36B), and integrally covers the bottoms of the plurality of trenches (31).

[0287] [Appendix 1-7] The semiconductor device (1) according to Appendix 1-6, wherein a plurality of first line regions (92) each consisting of a plurality of the well regions (91) and a plurality of second line regions (93) each consisting of the first impurity regions (7, 8) sandwiched between the plurality of well regions (91) are alternately arranged in the longitudinal direction of the plurality of trenches (31).

[0288] [Appendix 1-8] The semiconductor device (1) according to Appendix 1-7, wherein a second line width (LW2) of the second line region (93) in the length direction of the plurality of trenches (31) is larger than a first line width (LW1) of the first line region (92).

[0289] [Supplementary Note 1-9] The semiconductor device further includes a well region (91) of a second conductivity type including a base portion (94), a first extension portion (95), and a second extension portion (96), and crossing the plurality of trenches (31) in a surface layer portion of the first impurity region (7, 8), wherein the base portion (94) has a linear shape in a plan view continuously crossing the plurality of trenches (31), the first mesa portion (36A), and the second mesa portion (36B), and integrally covers the bottoms of the plurality of trenches (31), and the first extension portion (95) extends from the base portion (94) in the first mesa portion (36A) toward the first main surface (3) and is integrally connected to the second impurity region (30), The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, wherein the second extension portion (96) extends from the base portion (94) toward the first main surface (3) in the second mesa portion (36B) and has an upper end portion (98) at a position spaced apart from the first main surface (3) across the Schottky region (67).

[0290] [Supplementary Note 1-10] The semiconductor device (1) according to Supplementary Note 1-9, wherein a plurality of first regions (92) and a plurality of second regions (93) are alternately arranged in the longitudinal direction of the plurality of trenches (31), the first regions (92) are regions that overlap the well region (91) in a planar view, the second regions (93) are regions between the first regions (92) adjacent to each other in a planar view, and the Schottky region (67) includes a main surface region (99) that continuously crosses the first regions (92) and the second regions (93) in the longitudinal direction of the plurality of trenches (31) and forms the Schottky junction (68), and an extension region (100) that extends from the main surface region (99) toward the second main surface (4) in the second region (93).

[0291] [Supplementary Note 1-11] The semiconductor device further includes a well region (91) of a second conductivity type including a base portion (94), a first extension portion (95), and a second extension portion (96), and crossing the plurality of trenches (31) in a surface layer portion of the first impurity region (7, 8), wherein the base portion (94) has a linear shape in a plan view continuously crossing the plurality of trenches (31), the first mesa portion (36A), and the second mesa portion (36B), and integrally covers the bottoms of the plurality of trenches (31), and the first extension portion (95) extends from the base portion (94) in the first mesa portion (36A) toward the first main surface (3) and is integrally connected to the second impurity region (30), The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, wherein the second extension portion (96) extends from the base portion (94) toward the first main surface (3) in the second mesa portion (36B) and is exposed from the first main surface (3).

[0292] [Appendix 1-12] The semiconductor device (1) according to appendix 1-11, wherein the Schottky regions (67) in the second mesa portion (36B) are separated from each other by the second extension portion (96).

[0293] [Supplementary Note 1-13] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, further comprising: a well region (91) of a second conductivity type that is linear in a plan view and continuously crosses the plurality of trenches (31), the first mesa portion (36A), and the second mesa portion (36B) and integrally covers bottoms of the plurality of trenches (31), wherein the well region (91) is disposed between the well region (91) and the second impurity region (30) in the first mesa portion (36A) with the first impurity region (7, 8) interposed therebetween, and the well region (91) is connected to the Schottky region (67) in the second mesa portion (36B).

[0294] [Appendix 1-14] The semiconductor device (1) according to appendix 1-13, further comprising a contact region (101) arranged along a side surface (34) of the trench (31) and connecting the second impurity region (30) and the well region (91).

[0295] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, including: first well regions (12) of a second conductivity type individually arranged at the bottoms of the plurality of trenches (31) in the first impurity regions (7, 8); and second well regions (86) of the second conductivity type arranged between the first well regions (12) of the plurality of trenches (31) adjacent to each other in the first impurity regions (7, 8).

[0296] [Appendix 1-15-1] The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, including first well regions (12) of a second conductivity type individually arranged at the bottoms of the plurality of trenches (31) in the first impurity regions (7, 8).

[0297] [Appendix 1-16] The semiconductor device (1) according to appendix 1-15, wherein the first well region (12) and the second well region (86) are arranged at the first pitch (PT1).

[0298] [Appendix 1-17] The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, wherein the second impurity region (30) and the third impurity region (45) are further present between the trench (31) and the Schottky region (67) in the second mesa portion (36B).

[0299] [Appendix 1-18] The semiconductor device (1) according to any one of Appendices 1-1 to 1-17, wherein the chip (2) includes a SiC chip (2).

[0300] REFERENCE SIGNS LIST 1...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor layer, 7...Second semiconductor layer, 8...Drift region, 9...Active region, 10...Peripheral region, 11...Gate structure, 12...Bottom well region, 13...Outer well region, 14...Field region, 15...Surface insulating film, 16...Interlayer insulating film, 17...Gate wiring, 18...Gate pad wiring, 19...Source opening, 20...Source pad electrode, 21...First pad portion, 22...Second pad portion, 23...Third pad portion, 24...Gate pad electrode, 2 5...gate finger electrode, 26...first slit portion, 27...source finger electrode, 28...second slit portion, 29...drain pad electrode, 30...body region, 31...trench, 32...trench insulating film, 33...buried conductive layer, 34...side surface, 35...bottom surface, 36...mesa portion, 36A...first mesa portion, 36B...second mesa portion, 37...first channel region, 38...upper surface, 39...step, 40...recess, 41...protrusion portion, 42...side surface, 43...first layer, 44...second layer, 45...source region, 46...channel section, 47...first contact region, 48...first body portion, 49...second body portion, 50...base boundary surface, 51...body protrusion, 52...first boundary surface, 53...first step, 54...second boundary surface, 55...second step, 56...second contact region, 57...integral impurity region, 58...first relaxation portion, 59...second relaxation portion, 60...first boundary surface, 61...second boundary surface, 62...buried insulating layer, 63...upper edge, 64...upper surface, 65...silicide layer, 66...non-silicide portion, 67...Schottky region, 68...Schottky junction portion, 69...non-silicide portion, 70...first main surface electrode, 71...barrier layer, 72...main body layer, 73...second recess, 74...resin layer, 75...outer contact region region, 76...main surface insulating film, 77...gate opening, 80...outer opening, 81...corner portion, 82...buried electrode, 83...upper surface, 84...step, 85...recess, 86...second well region, 87...current path, 88...first layer, 89...second layer, 90...third contact region, 91...bottom well region, 92...first line region, 93...second line region, 94...base portion, 95...first extension portion, 96...second extension portion, 97...upper end portion, 98...upper end portion, 99...main surface region, 100...extension region, 101...fourth contact region, 102...intermediate region, 103...extension region, 104...main surface region, 105...extension region

Claims

a first impurity region of a first conductivity type in a surface layer portion of the first principal surface; a plurality of trenches in the first principal surface; a plurality of mesa portions partitioned by the plurality of trenches, each mesa portion having a first width and a second mesa portion having a second width wider than the first width in a direction crossing the trenches; a second impurity region of a second conductivity type and a third impurity region of the first conductivity type in at least a surface layer portion of the first impurity region in the first mesa portion, the second impurity region and the third impurity region of the first conductivity type being arranged in this order from the second principal surface side along a side surface of the trench; a control electrode buried in at least the trench adjacent to the first mesa portion and facing the second impurity region via a control insulating film; a Schottky region provided by the first impurity region in at least the second mesa portion; a first electrode ohmically connected to the third impurity region and forming a Schottky junction with the Schottky region; and a second electrode ohmically connected to the first impurity region.

2. The semiconductor device according to claim 1, wherein the plurality of trenches are striped, the first mesa portion is defined between the plurality of trenches arranged at a first pitch, and the second mesa portion is defined between the plurality of trenches arranged at a second pitch wider than the first pitch.

3. The semiconductor device according to claim 2, wherein the second pitch is greater than 1 time and less than 4 times the first pitch.

4. The semiconductor device according to claim 2, wherein the Schottky region extends from the bottom of the trench to the first main surface in the thickness direction of the chip and is exposed from the first main surface, and the first electrode includes a first main surface electrode disposed on the first main surface and forming the Schottky junction with the Schottky region along the first main surface.

5. The semiconductor device according to claim 2, wherein the first electrode includes a first main surface electrode disposed on the first main surface and a first buried electrode buried in the trench adjacent to the second mesa portion, and the first buried electrode forms the Schottky junction between the Schottky region and the first buried electrode along a side surface of the trench adjacent to the second mesa portion.

6. A semiconductor device according to any one of claims 1 to 5, including a well region of the second conductivity type that is linear in plan view and continuously crosses the plurality of trenches, the first mesa portion, and the second mesa portion, and that integrally covers the bottoms of the plurality of trenches.

7. The semiconductor device according to claim 6, wherein a plurality of first line regions each consisting of a plurality of well regions and a plurality of second line regions each consisting of a first impurity region sandwiched between a plurality of well regions are alternately arranged in the longitudinal direction of the plurality of trenches.

8. The semiconductor device according to claim 7, wherein a second line width of said second line region in the length direction of said plurality of trenches is larger than a first line width of said first line region.

9. The semiconductor device according to any one of claims 1 to 5, further comprising a well region of a second conductivity type including a base portion, a first extension portion, and a second extension portion, and crossing the plurality of trenches in a surface layer portion of the first impurity region, wherein the base portion has a linear shape in a plan view continuously crossing the plurality of trenches, the first mesa portion, and the second mesa portion, and integrally covers the bottoms of the plurality of trenches, wherein the first extension portion extends from the base portion toward the first main surface in the first mesa portion and is integrally connected to the second impurity region, and wherein the second extension portion extends from the base portion toward the first main surface in the second mesa portion, and has an upper end at a position spaced apart from the first main surface with the Schottky region sandwiched therebetween.

10. The semiconductor device of claim 9, wherein a plurality of first regions and a plurality of second regions are alternately arranged in the longitudinal direction of the plurality of trenches, the first regions are regions that overlap the well region in a planar view, the second regions are regions between adjacent first regions in a planar view, and the Schottky region includes a main surface region that continuously crosses the first regions and the second regions in the longitudinal direction of the plurality of trenches and forms the Schottky junction, and an extension region in the second region that extends from the main surface region toward the second main surface.

11. The semiconductor device according to any one of claims 1 to 5, further comprising a well region of a second conductivity type including a base portion, a first extension portion, and a second extension portion, and crossing the plurality of trenches in a surface layer portion of the first impurity region, wherein the base portion has a linear shape in a plan view continuously crossing the plurality of trenches, the first mesa portion, and the second mesa portion, and integrally covers the bottoms of the plurality of trenches, wherein the first extension portion extends from the base portion toward the first main surface in the first mesa portion and is integrally connected to the second impurity region, and wherein the second extension portion extends from the base portion toward the first main surface in the second mesa portion and is exposed from the first main surface.

12. The semiconductor device according to claim 11, wherein the Schottky regions in the second mesa portion are separated from each other by the second extension portion.

13. The semiconductor device according to any one of claims 1 to 5, further comprising a second conductivity type well region that is linear in plan view and continuously crosses the plurality of trenches, the first mesa portion, and the second mesa portion, and integrally covers the bottoms of the plurality of trenches, the well region being disposed in the first mesa portion with the first impurity region sandwiched between the well region and the second impurity region, and being connected to the Schottky region in the second mesa portion.

14. The semiconductor device according to claim 13, further comprising a contact region disposed along a side surface of said trench, said contact region connecting said second impurity region and said well region.

15. The semiconductor device according to any one of claims 1 to 5, comprising: first well regions of a second conductivity type individually disposed at the bottoms of the plurality of trenches in the first impurity region; and second well regions of the second conductivity type disposed between the first well regions of the plurality of trenches adjacent to each other in the first impurity region.

16. The semiconductor device according to claim 15, wherein the first well region and the second well region are arranged at the first pitch.

17. The semiconductor device according to any one of claims 1 to 5, wherein the second impurity region and the third impurity region are further present between the trench and the Schottky region in the second mesa portion.

18. The semiconductor device according to any one of claims 1 to 17, wherein the chip includes a SiC chip.

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