Semiconductor device

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate which has an upper surface and a lower surface; a plurality of trench sections which extend in a first direction on the upper surface; a first active gate runner which extends above the upper surface of the semiconductor substrate, in a second direction that intersects the first direction; a second active gate runner which extends in the second direction and which is spaced apart from the first active gate runner in the second direction; and a separation area which is provided along the second direction between the first active gate runner and the second active gate runner, wherein the plurality of trench sections have a first gate trench section, and the first gate trench section is provided with a first extension portion which extends up to the separation area in the first direction and a first connection portion which is provided in the separation area and which connects the first extension portion to the first active gate runner.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, a configuration in which a gate runner layer made of metal and a gate electrode are electrically connected without polysilicon therebetween is known (see, for example, Patent Document 1). Also, a semiconductor device including an emitter bridge portion that connects a first region and a second region of an emitter electrode is known (see, for example, Patent Document 2). [Prior Art Literature] [Patent Document] [Patent Document 1] JP 2017-103400 A [Patent Document 2] JP 2019-68036 A General disclosure

[0003] (Problem to be Solved) In a semiconductor device, it is preferable to suppress gate delay. (Means for Solving the Problem)

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; a plurality of trench portions extending inward from the upper surface of the semiconductor substrate in a first direction on the upper surface; a first active gate runner extending above the upper surface of the semiconductor substrate in a second direction intersecting the first direction; a second active gate runner extending in the second direction and spaced apart from the first active gate runner in the second direction; and a separation region extending between the first active gate runner and the second active gate runner along the second direction. In the semiconductor device, the plurality of trench portions may include a first gate trench portion. In any of the semiconductor devices described above, the first gate trench portion may include a first extension portion extending in the first direction to the separation region. In any of the semiconductor devices described above, the first gate trench portion may include a first connection portion provided in the separation region and connecting the first extension portion to the first active gate runner.

[0005] In any of the above semiconductor devices, the first active gate runner may have a first end edge, and the second active gate runner may have a second end edge facing the first end edge in the second direction. In any of the above semiconductor devices, the first connection portion may intersect with the first end edge.

[0006] In any of the above semiconductor devices, the first connection portion may extend to a portion overlapping the first active gate runner.

[0007] In any of the above semiconductor devices, the first connection portion may have a first linear portion extending in the second direction.

[0008] In any of the above semiconductor devices, the first connecting portion may have a first curved portion connecting the first straight portion and the first extending portion.

[0009] In any of the above semiconductor devices, the plurality of trench portions may include second gate trench portions. In any of the above semiconductor devices, the second gate trench portion may have a second extension portion extending in the first direction to the separation region. In any of the above semiconductor devices, the second gate trench portion may have a second connection portion provided in the separation region and connecting the second extension portion to the second active gate runner.

[0010] Any of the above semiconductor devices may include a first emitter electrode provided above the top surface of the semiconductor substrate. Any of the above semiconductor devices may include a second emitter electrode arranged to face the first emitter electrode, sandwiching the first active gate runner, the second active gate runner, and the separation region in the first direction. In any of the above semiconductor devices, the first gate trench portion and the second gate trench portion may extend in the first direction from below the first emitter electrode to the separation region.

[0011] In any of the above semiconductor devices, the plurality of trench portions may include a third gate trench portion. In any of the above semiconductor devices, the third gate trench portion may have a third extension portion extending in the first direction from below the second emitter electrode to the separation region. In any of the above semiconductor devices, the third gate trench portion may have a third connection portion provided in the separation region and connecting the third extension portion to the first active gate runner.

[0012] In any of the above semiconductor devices, the plurality of trench portions may include a fourth gate trench portion. In any of the above semiconductor devices, the fourth gate trench portion may have a fourth extension portion extending in the first direction from below the second emitter electrode to the separation region. In any of the above semiconductor devices, the fourth gate trench portion may have a fourth connection portion provided in the separation region and connecting the fourth extension portion to the second active gate runner.

[0013] Any of the above semiconductor devices may have a bridge electrode portion provided in the separation region and connecting the first emitter electrode and the second emitter electrode.

[0014] In any of the above semiconductor devices, the plurality of trench portions may include a fifth gate trench portion positioned farther from the first active gate runner in the second direction than the first gate trench portion. In any of the above semiconductor devices, the fifth gate trench portion may have a fifth extension portion extending in the first direction to the separation region. In any of the above semiconductor devices, the fifth gate trench portion may have a fifth connection portion provided in the separation region and connecting the fifth extension portion to the first active gate runner. In any of the above semiconductor devices, the fifth extension portion may extend further into the separation region in the first direction than the first extension portion.

[0015] In any of the above semiconductor devices, a distance a in the second direction between the plurality of trench portions extending in the first direction to the separation region and a distance b in the first direction between the plurality of trench portions in the separation region may satisfy the following relationship: 0.01<b / a<1

[0016] In any of the above semiconductor devices, the plurality of trench portions may include a sixth gate trench portion connected to the first connection portion.

[0017] In any of the above semiconductor devices, a distance a in the second direction between the plurality of trench portions extending in the first direction to the separation region, a distance b in the first direction between the plurality of trench portions in the separation region, a length c of the separation region in the second direction, a length d of the first active gate runner in the first direction, and a number n of the sixth gate trench portions connected to one first connection portion may satisfy the following relationship: 2×(c / a)×(n+1)≧d / b

[0018] In any of the above semiconductor devices, the first active gate runner and the second active gate runner may be formed of metal.

[0019] In any of the above semiconductor devices, polysilicon gate runners may not be provided between the first and second active gate runners and the upper surface of the semiconductor substrate.

[0020] In any of the above semiconductor devices, the first gate trench portion may have a gate conductive portion made of polysilicon. In any of the above semiconductor devices, an upper end of the gate conductive portion may be in contact with the first active gate runner.

[0021] In any of the above semiconductor devices, a polysilicon gate runner connecting the first active gate runner and the second active gate runner may not be provided in the separation region.

[0022] In any of the semiconductor devices described above, the trench portions may include a seventh gate trench portion facing the first active gate runner in the first direction. In any of the semiconductor devices described above, the seventh gate trench portion may extend in the first direction to below the first active gate runner and be connected to the first active gate runner.

[0023] In any of the semiconductor devices described above, the plurality of trenches may include a first dummy trench provided between the first gate trench and the fifth gate trench, and the first dummy trench may extend in the first direction to the separation region.

[0024] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type, and an emitter region of the first conductivity type provided on the upper surface of the semiconductor substrate and having a higher concentration than the drift region. In any of the above semiconductor devices, the emitter region may also be provided in the separation region.

[0025] In any of the semiconductor devices described above, a transistor portion may be provided in the separation region near the first end side and the second end side, and a diode portion may be provided in the separation region between the transistor portions in the second direction.

[0026] Any of the above semiconductor devices may include a first emitter electrode and a second emitter electrode provided above the upper surface of the semiconductor substrate and arranged on either side of the first active gate runner, the second active gate runner, and the separation region in the first direction. In the diode section of any of the above semiconductor devices, the plurality of trench sections may include second dummy trench sections provided from below the first emitter electrode to below the second emitter electrode.

[0027] Any of the above semiconductor devices may include an emitter electrode provided above the top surface of the semiconductor substrate, a temperature sensing portion at least partially provided in the separation region, and a third active gate runner provided between the temperature sensing portion and the emitter electrode. In any of the above semiconductor devices, the plurality of trench portions may include an eighth gate trench portion connected to the third active gate runner. In any of the above semiconductor devices, the plurality of trench portions may include a plurality of the first gate trench portions and a first trench connection portion connecting the plurality of first connection portions to each other. In any of the above semiconductor devices, the plurality of trench portions may include a plurality of the second gate trench portions and a second trench connection portion connecting the plurality of second connection portions to each other. In any of the above semiconductor devices, the plurality of trench portions may include a plurality of the third gate trench portions and a third trench connection portion connecting the plurality of third connection portions to each other. Any of the above semiconductor devices may have a fourth trench connection portion that connects the first connection portion and the third connection portion to each other.

[0028] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0029] 9A is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. FIG. 1 is an enlarged view of region A in FIG. 1. FIG. 2 is a diagram illustrating a separation region 180. FIG. 3 is a diagram illustrating an example of the arrangement of contact holes 54 in region A. FIG. 4 is a diagram illustrating another example of a trench portion in region A. FIG. 5 is a diagram illustrating another example of a trench portion in region A. FIG. 6 is a diagram illustrating region A of a semiconductor device 200 in a comparative example. FIG. 7 is a diagram illustrating a B-B' cross section of the semiconductor device 200 shown in FIG. 3A. FIG. 8A is an enlarged top view of the vicinity of the first active gate runner 131-1 in FIG. 2A. FIG. 9B is a diagram illustrating a CC' cross section in FIG. 4. FIG. 10 is a diagram illustrating an invalid region formed in a manufacturing process of the semiconductor device 200 in the comparative example. FIG. 11 is an enlarged top view of the vicinity of the second active gate runner 131-2 in FIG. 2A. FIG. 12 is a top view of region A in a modified example of the semiconductor device 100. FIG. 13 is a diagram illustrating length c. FIG. 14 is a diagram illustrating another example of a trench portion in the example of FIG. 14A. FIG. 15 is a diagram illustrating another example of a trench portion in the example of FIG. 15A. 12A . FIG. 12B is a diagram illustrating another example of the trench portion in the example of FIG. 9A . FIG. 13 is a top view of region A in a modified example of the semiconductor device 100. FIG. 14 is a diagram illustrating an example of the arrangement of contact holes 54 in the example of FIG. 10A . FIG. 15 is a diagram illustrating another example of the trench portion in the example of FIG. 10A . FIG. 16 is a diagram illustrating another example of the trench portion in the example of FIG. 16A . FIG. 17 is a diagram illustrating another example of the trench portion in the example of FIG. 17A . FIG. 18 is a diagram illustrating another example of the trench portion in the example of FIG. 18A . FIG. 19 is a diagram illustrating an example of the arrangement of contact holes 54 in the example of FIG. 19A .

[0030] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0032] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0033] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0034] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0035] In this specification, when terms such as "same" or "equal" are used, it may include cases where there is an error due to manufacturing variations or the like. The error is, for example, within 10%. Furthermore, when terms such as "parallel" or "perpendicular" are used, it may include an error of, for example, within 5°.

[0036] In this specification, the conductivity type of a doped region doped with an impurity is described as p-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a p-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a p-type conductivity.

[0037] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0038] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.

[0039] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors formed by dopants uniformly contained in the ingot that serves as the base for the semiconductor substrate during its production. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the p-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). In this example, the ingot is manufactured by the MCZ method. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, the semiconductor substrate may be a non-doped substrate that does not contain dopants such as phosphorus. In this case, the bulk donor concentration (D0) of the non-doped substrate may be, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0040] In this specification, when p+ type or n+ type is described, it means that the doping concentration is higher than that of p type or n type, and when p- type or n- type is described, it means that the doping concentration is lower than that of p type or n type. Furthermore, when p++ type or n++ type is described in this specification, it means that the doping concentration is higher than that of p+ type or n+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0041] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0042] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0043] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0044] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. The semiconductor substrate may be silicon, silicon carbide, gallium nitride, diamond, or gallium oxide.

[0045] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0046] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0047] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0048] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). However, the transistor section 70 may be provided with a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor). The active section 160 may further be provided with a diode section including a diode element such as a free wheel diode (FWD).

[0049] The transistor section 70 has a p-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an n-type emitter region, a p-type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0050] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0051] A gate voltage is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate runner that connects the gate pad 112 and the gate trench portion. In FIG. 1, the gate runner is hatched with diagonal lines.

[0052] The gate runner of this example has a peripheral gate runner 130 and an active gate runner 131. The peripheral gate runner 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate runner 130 of this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate runner 130 in a top view may be the active portion 160. A well region is formed below the gate runner. The well region is a p-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0053] The peripheral gate runner 130 is connected to the gate pad 112. The peripheral gate runner 130 is disposed above the semiconductor substrate 10. The peripheral gate runner 130 may be a laminate of polysilicon and a metal such as aluminum, or may be a wiring made of metal only.

[0054] The active gate runner 131 is provided in the active section 160. The active gate runner 131 may be metal wiring containing aluminum or the like. The peripheral gate runner 130 and the active gate runner 131 are connected to the gate trench section of the active section 160. By providing the active gate runner 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 112 for each region of the semiconductor substrate 10. The peripheral gate runner 130 and the active gate runner 131 are arranged above the top surface of the semiconductor substrate 10.

[0055] The active gate runner 131 in this example includes a first active gate runner 131-1 and a second active gate runner 131-2. The first active gate runner 131-1 and the second active gate runner 131-2 extend in a second direction above the top surface of the semiconductor substrate 10. The first active gate runner 131-1 and the second active gate runner 131-2 are spaced apart from each other in the second direction. A separation region, which will be described later, is provided between the first active gate runner 131-1 and the second active gate runner 131-2 in the second direction. In this example, the second direction is the X-axis direction.

[0056] The active gate runner 131 may be connected to the peripheral gate runner 130. In this example, the first active gate runner 131-1 extends in the second direction from one of the two peripheral gate runners 130 that sandwich the active portion 160 in the X-axis direction toward the center of the active portion 160. In this example, the second active gate runner 131-2 extends in the second direction from the other of the two peripheral gate runners 130 that sandwich the active portion 160 in the X-axis direction toward the center of the active portion 160.

[0057] The semiconductor device 100 may also include a temperature sensing section which is a pn junction diode formed of polysilicon or the like, as described below, and a current detection section which simulates the operation of a transistor section provided in the active section 160, although neither is shown.

[0058] In the present example, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 90 in the present example is disposed between the peripheral gate runner 130 and the edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0059] 2A is an enlarged view of region A in FIG. 1. In region A, a first active gate runner 131-1 and a second active gate runner 131-2 are spaced apart from each other in the X-axis direction. A separation region 180 is a region between the end of the first active gate runner 131-1 on the second active gate runner 131-2 side and the end of the second active gate runner 131-2 on the first active gate runner 131-1 side in the X-axis direction. Region A includes the transistor section 70, the first active gate runner 131-1, the second active gate runner 131-2, and the separation region 180. In FIG. 2A and subsequent figures, the separation region 180 is indicated by a dashed line. The separation region 180 will be described later.

[0060] The semiconductor device 100 of this example includes a trench portion, a well region 17, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active gate runner 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active gate runner 131 are provided separately from each other.

[0061] The semiconductor device 100 of this example includes a first emitter electrode 52-1 and a second emitter electrode 52-2 as emitter electrodes 52. The first emitter electrode 52-1 and the second emitter electrode 52-2 are arranged to face each other in a first direction, sandwiching the first active gate runner 131-1, the second active gate runner 131-2, and the separation region 180 therebetween. The first direction intersects with the second direction. In this example, the first direction is the Y-axis direction. That is, the first direction and the second direction may be perpendicular to each other. An interlayer insulating film is provided between the emitter electrode 52 and the active gate runner 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 2A .

[0062] The emitter electrode 52 is provided above the gate trench portion 40, the well region 17, the emitter region 12, the base region 14, and the contact region 15. In FIG. 2A , the range in which the emitter electrode 52 is provided is indicated by a dotted line. That is, the first emitter electrode 52-1 is provided on the positive side of the Y-axis relative to the active gate runner 131, and the second emitter electrode 52-2 is provided on the negative side of the Y-axis relative to the active gate runner 131. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through contact holes, but the contact holes are omitted in FIG. 2A .

[0063] The semiconductor device 100 has a bridge electrode portion 58 that connects the first emitter electrode 52-1 and the second emitter electrode 52-2. The bridge electrode portion 58 is provided in the separation region 180. The first active gate runner 131-1 and the second active gate runner 131-2 are not connected to the bridge electrode portion 58. The bridge electrode portion 58 sets the first emitter electrode 52-1 and the second emitter electrode 52-2 to the same potential.

[0064] The bridge electrode portion 58 can reduce the inductance between the first emitter electrode 52-1 and the second emitter electrode 52-2. Without the bridge electrode portion 58, the first emitter electrode 52-1 and the second emitter electrode 52-2 would be electrically connected via an external terminal such as a bonding wire. This increases the inductance between the first emitter electrode 52-1 and the second emitter electrode 52-2, resulting in a slight difference in their respective potentials, which can cause a slight delay (imbalance) in the current and oscillation in the current waveform. On the other hand, connecting the first emitter electrode 52-1 and the second emitter electrode 52-2 with the bridge electrode portion 58 reduces the inductance between the first emitter electrode 52-1 and the second emitter electrode 52-2. This reduces the imbalance in current between the first emitter electrode 52-1 and the second emitter electrode 52-2, thereby suppressing oscillation of the current waveform.

[0065] The emitter electrode 52 is formed of a material containing metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0066] The well region 17 is provided so as to overlap with the active gate runner 131. The well region 17 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active gate runner 131. In this example, the well region 17 is provided from the area overlapping with the active gate runner 131 to the area overlapping with the emitter electrode 52. The well region 17 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is p- type, and the well region 17 is p+ type.

[0067] The semiconductor device 100 includes a plurality of trenches extending from the upper surface of the semiconductor substrate 10 toward the interior thereof in a first direction. The plurality of trenches includes a plurality of gate trenches 40. In this example, the plurality of gate trenches 40 are arranged at intervals along a second direction. A gate voltage is transmitted to the gate trenches 40 from a gate pad 112.

[0068] The trench portions in this example include a seventh gate trench portion 40-7 that faces the first active gate runner 131-1 in the first direction. The seventh gate trench portion 40-7 extends in the first direction to below the first active gate runner 131-1 and is connected to the first active gate runner 131-1. The active gate runner 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.

[0069] The seventh gate trench portion 40-7 in this example has two extension portions (portions of the trench that are linear along the extension direction) extending along the first direction and a tip portion 41-7 connecting the two extension portions. At least a portion of the tip portion 41-7 is preferably curved in a top view. By connecting the ends of the two extension portions in the first direction with the tip portion 41-7, electric field concentration at the ends of the extension portions can be alleviated. The same may be true for the other gate trench portion 40 facing the second active gate runner 131-2 in the first direction.

[0070] The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40. The end of the gate trench portion 40 is provided in the well region 17 when viewed from above. In other words, at the end of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 17. This makes it possible to alleviate electric field concentration at the bottom of each trench portion. In FIG. 2A and subsequent figures, the range where the well region 17 is provided is indicated by a two-dot chain line. In this example, the separation region 180 is included in the well region 17 when viewed from above.

[0071] A mesa portion 60 is provided between each trench portion in the arrangement direction. The mesa portion 60 refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. The mesa portion 60 in this example is provided on the upper surface of the semiconductor substrate 10, extending in a first direction along the trench. The mesa portion 60 in this example is provided in the transistor portion 70.

[0072] A base region 14 is provided in each mesa portion 60. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60, the region located closest to the active gate runner 131 is referred to as base region 14-e. While FIG. 2A shows base region 14-e located at one end of each mesa portion 60 in the extension direction, base region 14-e is also located at the other end of each mesa portion 60.

[0073] Each mesa portion 60 may have at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is n+ type, and the contact region 15 is p+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0074] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0075] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction (first direction) of the trench portions.

[0076] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0077] A contact hole is provided above each mesa portion. The contact holes are arranged in a region sandwiched between the base regions 14-e. The contact holes are provided above the contact region 15, the base region 14, and the emitter region 12. However, the contact holes are not shown in FIG. 2A. The contact holes are not provided in the regions corresponding to the base region 14-e and the well region 17. The contact holes may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0078] The plurality of trench portions includes a first gate trench portion 40-1. The first gate trench portion 40-1 has a first extension portion and a first connection portion 46-1. The first extension portion extends in a first direction to a separation region 180 between the first active gate runner 131-1 and the second active gate runner 131-2. The first connection portion 46-1 is provided in the separation region 180 and connects the first extension portion to the first active gate runner 131-1. The first extension portion will be described below.

[0079] In this configuration, the gate voltage is transmitted directly from the first active gate runner 131-1 to the gate conductive portion of the first gate trench portion 40 without passing through a polysilicon runner. The polysilicon runner is a planar polysilicon layer formed above the upper surface 21 of the semiconductor substrate 10, and transmits the gate signal to the gate conductive portion of each gate trench portion 40. This configuration suppresses the gate voltage transmission delay inherent to polysilicon runners and prevents a decrease in withstand capability due to current imbalance during turn-off. As an example, the polysilicon runner is a polysilicon layer described later in FIGS. 3A and 3B . The first gate trench portion 40 may be a trench portion facing the separation region 180 in the first direction. The first gate trench portion 40-1 is a trench portion whose distance from the first active gate runner 131-1 is shorter than that from the second active gate runner 131-2. That is, the first gate trench portion 40-1 is a trench portion located near the first active gate runner 131-1.

[0080] FIG. 2B is a diagram illustrating the separation region 180. Like FIG. 2A, FIG. 2B shows region A. However, FIG. 2B omits the well region 17, the emitter region 12, the base region 14, and the contact region 15, as well as the emitter electrode 52. The separation region 180 is a region between the first active gate runner 131-1 and the second active gate runner 131-2 in the second direction. In FIG. 2B, the separation region 180 is indicated by a dashed dotted line. The separation region 180 may be provided in the center of the active portion 160 in the second direction.

[0081] The width of the separation region 180 in the second direction may be equal to the distance between the first active gate runner 131-1 and the second active gate runner 131-2 in the second direction. The width of the separation region 180 in the first direction may be the length over which the first active gate runner 131-1 and the second active gate runner 131-2 overlap in the second direction. In this example, the width of the separation region 180 in the first direction is equal to the width of the first active gate runner 131-1 and the width of the second active gate runner 131-2 in the first direction.

[0082] 2B shows the first extension portion 49-1 of the first gate trench portion 40-1. As described above, the first extension portion 49-1 extends in the first direction to the separation region 180. The first extension portion 49-1 may extend in the first direction from below the first emitter electrode 52-1 to the separation region 180.

[0083] The first connection portion 46-1 connects the first extension portion 49-1 and the first active gate runner 131-1 in the separation region 180. The first connection portion 46-1 may extend in the second direction. The portion of the first connection portion 46-1 that connects to the first extension portion 49-1 may be curved in top view. In this case, the sidewall of the first gate trench portion 40-1 at the portion that connects to the first extension portion 49-1 has a curved surface. The first connection portion 46-1 may be provided so as to intersect with the first end edge 133-1 of the first active gate runner 131-1.

[0084] The plurality of trench portions may include a second gate trench portion 40-2. The second gate trench portion 40-2 is a trench portion that is closer to the second active gate runner 131-2 than to the first active gate runner 131-1. In other words, the second gate trench portion 40-2 is a trench portion that is disposed closer to the second active gate runner 131-2.

[0085] The second gate trench portion 40-2 has a second extension portion 49-2 and a second connection portion 46-2. The second extension portion 49-2 extends in a first direction to the separation region 180. The second connection portion 46-2 is provided in the separation region 180 and connects the second extension portion 49-2 to the second active gate runner 131-2. The second connection portion 46-2 may extend in a second direction. The portion of the second connection portion 46-2 that connects to the second extension portion 49-2 may be curved in a top view. In this case, the sidewall of the second gate trench portion 40-2 at the portion that connects to the second extension portion 49-2 has a curved surface. The second connection portion 46-2 may be provided so as to intersect with a second end edge 133-2 (described later) of the second active gate runner 131-2.

[0086] The first gate trench portion 40-1 and the second gate trench portion 40-2 may extend in a first direction from below the first emitter electrode 52-1 to the separation region 180. In this example, the first extension portion 49-1 and the second extension portion 49-2 extend in the first direction from below the first emitter electrode 52-1 (toward the lower surface 23) to the separation region 180.

[0087] The plurality of trench portions may include a third gate trench portion 40-3. The third gate trench portion 40-3 is a trench portion that is closer to the first active gate runner 131-1 than to the second active gate runner 131-2. In other words, the third gate trench portion 40-3 is a trench portion that is disposed closer to the first active gate runner 131-1.

[0088] The third gate trench portion 40-3 has a third extension portion 49-3 and a third connection portion 46-3. The third extension portion 49-3 extends in a first direction from below the second emitter electrode 52-2 to the separation region 180. The third connection portion 46-3 is provided in the separation region 180 and connects the third extension portion 49-3 to the first active gate runner 131-1. The third connection portion 46-3 may extend in a second direction. The portion of the third connection portion 46-3 that connects to the third extension portion 49-3 may be curved in top view. In this case, the sidewall of the third gate trench portion 40-3 at the portion that connects to the third extension portion 49-3 has a curved surface. The third connection portion 46-3 may be provided so as to intersect with a second end edge 133-2 (described later) of the second active gate runner 131-2.

[0089] The plurality of trench portions may include a fourth gate trench portion 40-4. The fourth gate trench portion 40-4 is a trench portion that is closer to the second active gate runner 131-2 than to the first active gate runner 131-1. In other words, the fourth gate trench portion 40-4 is a trench portion that is disposed closer to the second active gate runner 131-2.

[0090] The fourth gate trench portion 40-4 has a fourth extension portion 49-4 and a fourth connection portion 46-4. The fourth extension portion 49-4 extends in a first direction from below the second emitter electrode 52-2 to the separation region 180. The fourth connection portion 46-4 is provided in the separation region 180 and connects the fourth extension portion 49-4 to the second active gate runner 131-2. The fourth connection portion 46-4 may extend in a second direction. The portion of the fourth connection portion 46-4 that connects to the fourth extension portion 49-4 may be curved in a top view. In this case, the sidewall of the fourth gate trench portion 40-4 at the portion that connects to the fourth extension portion 49-4 has a curved surface. The fourth connection portion 46-4 may be provided so as to intersect with a second end edge 133-2 (described later) of the second active gate runner 131-2.

[0091] The plurality of trench portions may include a fifth gate trench portion 40-5. The fifth gate trench portion 40-5 may refer to any of the plurality of first gate trench portions 40-1. As described above, the first gate trench portion 40-1 is a trench portion that faces the separation region 180 in the first direction and is closer to the first active gate runner 131-1 than to the second active gate runner 131-2. Therefore, the fifth gate trench portion 40-5 is a trench portion that is closer to the first active gate runner 131-1 than to the second active gate runner 131-2. In other words, the fifth gate trench portion 40-5 is a trench portion that is disposed near the first active gate runner 131-1. The fifth gate trench portion 40-5 is disposed farther from the first active gate runner 131-1 in the second direction than either of the first gate trench portions 40-1. In other words, of the two first gate trench portions 40-1 aligned in the second direction, the one closer to the first active gate runner 131-1 may be referred to as the first gate trench portion 40-1, and the one farther from the first active gate runner 131-1 may be referred to as the fifth gate trench portion 40-5. Unless otherwise specified, the fifth gate trench portion 40-5 may be treated as the first gate trench portion 40-1.

[0092] The fifth gate trench portion 40-5 has a fifth extension portion 49-5 and a fifth connection portion 46-5. The fifth extension portion 49-5 extends in the first direction to the separation region 180. The fifth connection portion 46-5 is provided in the separation region 180 and connects the fifth extension portion 49-5 to the first active gate runner 131-1. In this example, the fifth extension portion 49-5 extends further in the first direction into the separation region 180 than the first extension portion 49-1. With this configuration, multiple trench portions facing the separation region 180 can be connected to the same active gate runner 131, thereby suppressing gate delay.

[0093] The fifth gate trench portion 40-5 may extend in the first direction from below the first emitter electrode 52-1 to the separation region 180. In this example, the fifth extension portion 49-5 extends in the first direction from below the first emitter electrode 52-1 to the separation region 180.

[0094] In the semiconductor device 100 of this example, the second gate trench portion 40-2 also has a gate trench portion 40 corresponding to the fifth gate trench portion 40-5 in the first gate trench portion 40-1. In other words, a plurality of second gate trench portions 40-2 are provided. The same is true for the third gate trench portion 40-3 and the fourth gate trench portion 40-4.

[0095] The distance in the second direction between the plurality of trench portions extending in the first direction to the separation region 180 is defined as distance a. Distance a may be the distance between the extension portions 49 of the plurality of adjacent trench portions. Furthermore, the distance in the first direction between the plurality of trench portions in the separation region 180 is defined as distance b. Distance b may be the distance between the connection portions 46 of the plurality of adjacent trench portions. Distance a and distance b may satisfy the following relationship: 0.01<b / a<1

[0096] The interval a is the width of the mesa portion in the active section 160, and a predetermined width is required to form the emitter region 12 and the contact region 15. On the other hand, the interval b may be smaller than the interval a because the emitter region 12 and the contact region 15 are not formed. In other words, the emitter region 12 and the contact region 15 do not need to be formed between the connection portions 46 of the adjacent trench portions. b / a may be 0.05 or more and 0.5 or less, or may be 0.08 or more and 0.2 or less. When the multiple trench portions include dummy trench portions described later, the interval a may be the interval between the adjacent gate trench portions 40 and the dummy trench portions.

[0097] In a top view, the first active gate runner 131-1 has a first end edge 133-1. In a top view, the second active gate runner 131-2 has a second end edge 133-2 that faces the first end edge 133-1 in the second direction. The first end edge 133-1 and the second end edge 133-2 may be the shortest straight end edge of each active gate runner 131. In this example, the first end edge 133-1 and the second end edge 133-2 are parallel to the first direction. The first end edge 133-1 and the second end edge 133-2 may be the end edges of the separation region 180 in the second direction.

[0098] In a top view, the first active gate runner 131-1 has a first long side 135-1. In a top view, the second active gate runner 131-2 has a second long side 135-2. Each long side may be the longest straight side among the sides of each active gate runner 131. Each long side may be parallel to the second direction. In this example, the first active gate runner 131-1 has two first long sides 135-1 facing each other. In this example, the second active gate runner 131-2 has two second long sides 135-2 facing each other. The first long side 135-1 and the second long side 135-2 may define ends of the separation region 180 in the first direction. In this example, the seventh gate trench portion 40-7 extends in the first direction and intersects with the first long side 135-1.

[0099] The isolation region 180 does not need to be provided with a polysilicon gate runner connecting the first active gate runner 131-1 and the second active gate runner 131-2. As described above, the first gate trench portion 40-1 in this example extends to a portion overlapping with the first active gate runner 131. Similarly, the second gate trench portion 40-2 to the fifth gate trench portion 40-5 also extend to a position overlapping with one of the active gate runners 131. Therefore, even if a polysilicon gate runner is not provided in the isolation region 180, the first gate trench portion 40-1 to the fifth gate trench portion 40-5 can be connected to the active gate runner 131. Furthermore, by directly connecting the first gate trench portion 40-1 to the fifth gate trench portion 40-5 to the active gate runner 131, the transmission delay of the gate voltage can be reduced.

[0100] FIG. 2C is a diagram showing an example of the arrangement of contact holes 54 in region A. The contact holes 54 are provided in the interlayer insulating film above each mesa portion 60. The contact holes connect the emitter region 12 and the contact region 15 to the emitter electrode 52. In region A, the contact holes 54 are provided above the emitter region 12 and the contact region 15, but are not provided above the base region 14 or the well region 17. The contact holes 54 in this example extend in a first direction. The end of the contact hole 54 in the first direction is located above the contact region 15 that contacts the base region 14-e in the first direction. The contact holes 54 are also provided in the mesa portion 60 facing the separation region 180 in the first direction, but the contact holes 54 in this example are not provided in the separation region 180.

[0101] 2D is a diagram illustrating another example of a trench portion in region A. FIG. 2D differs from FIG. 2A in that the semiconductor device 100 includes a trench connection portion 401 and a trench connection portion 402. The semiconductor device 100 may include a trench connection portion that connects a plurality of connection portions 46 to each other. The semiconductor device 100 may include a first trench connection portion that connects a plurality of first connection portions 46-1 to each other. The plurality of first connection portions 46-1 refers to the first connection portions 46-1 of each first gate trench portion 40-1 when there are a plurality of first gate trench portions 40-1.

[0102] The semiconductor device 100 may have a second trench connection portion that connects the plurality of second connection portions 46-2 to one another. The "plurality of second connection portions 46-2" refers to the second connection portions 46-2 of the respective second gate trench portions 40-2 when there are a plurality of second gate trench portions 40-2.

[0103] The semiconductor device 100 may have a third trench connection portion that connects the plurality of third connection portions 46-3 to one another. The plurality of third connection portions 46-3 refers to the third connection portions 46-3 of the respective third gate trench portions 40-3 when there are a plurality of third gate trench portions 40-3.

[0104] The semiconductor device 100 may have a fourth trench connection portion connecting the first connection portion 46-1 and the third connection portion 46-3 to each other. The semiconductor device 100 may have a fifth trench connection portion connecting multiple fourth connection portions 46-4 to each other. The multiple fourth connection portions 46-4 refer to the fourth connection portions 46-4 of each fourth gate trench portion 40-4 when there are multiple fourth gate trench portions 40-4. In FIG. 2D , for example, a trench portion adjacent to the fourth gate trench portion 40-4 may also be considered as the fourth gate trench portion 40-4. The semiconductor device 100 may have a sixth trench connection portion connecting the second connection portion 46-2 and the fourth connection portion 46-4 to each other.

[0105] The trench connection portion 401 of this example is an example of a first trench connection portion, a third trench connection portion, and a fourth trench connection portion. The trench connection portion 401 of this example connects the plurality of first connection portions 46-1 and the plurality of third connection portions 46-3 that connect to the first active gate runner 131-1, respectively. The trench connection portion 402 of this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 of this example connects the plurality of second connection portions 46-2 and the plurality of fourth connection portions 46-4 that connect to the second active gate runner 131-2, respectively.

[0106] The trench connection portion 401 and the trench connection portion 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portion 401 and the trench connection portion 402, isolated ends of the gate trench portions 40 are eliminated. This prevents the gate oxide film from being formed imperfectly in a trench portion having a single end, and prevents a decrease in the dielectric strength voltage of the gate oxide film. The trench connection portion 401 and the trench connection portion 402 may be connected to a seventh gate trench portion 40.

[0107] FIG. 2E is a diagram illustrating another example of trench portions in region A. In FIG. 2E, the shapes of trench connection portions 401 and 402 differ from those in FIG. 2D. The semiconductor device 100 of this example includes a plurality of trench connection portions 401 (trench connection portion 401-1, trench connection portion 401-2, and trench connection portion 401-3) and a plurality of trench connection portions 402 (trench connection portion 402-1, trench connection portion 402-2, and trench connection portion 402-3). The trench connection portion 401-1 of this example is an example of a first trench connection portion. In FIG. 2E, the trench connection portion 401-1 connects two adjacent first connection portions 46-1 of the plurality of first connection portions 46-1 connected to the first active gate runner 131-1. The trench connection portion 401-2 of this example is an example of a third trench connection portion. In Figure 2E, trench connection portion 401-2 connects two adjacent third connection portions 46-3 of the multiple third connection portions 46-3 connected to first active gate runner 131-1. Trench connection portion 401-3 in this example is an example of a fourth trench connection portion. In Figure 2E, trench connection portion 401-3 connects first connection portion 46-1 and third connection portion 46-3 connected to first active gate runner 131-1. Each trench connection portion 401 in this example is arc-shaped.

[0108] The trench connection portion 402-1 in this example is an example of a second trench connection portion. In FIG. 2E, the trench connection portion 402-1 connects two adjacent second connection portions 46-2 of the multiple second connection portions 46-2 connected to the second active gate runner 131-2. The trench connection portion 402-2 in this example is an example of a fifth trench connection portion. In FIG. 2E, the trench connection portion 402-2 connects two adjacent fourth connection portions 46-4 of the multiple fourth connection portions 46-4 connected to the second active gate runner 131-2. The trench connection portion 402-3 in this example is an example of a sixth trench connection portion. In FIG. 2E, the trench connection portion 402-3 connects the second connection portion 46-2 and the fourth connection portion 46-4 connected to the second active gate runner 131-2. Each trench connection 402 in this example is arc-shaped.

[0109] The trench connection portions 401 and 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portions 401 and 402, isolated ends of the gate trench portions 40 are eliminated. Furthermore, by forming the trench connection portions into an arc shape, mechanical and electrical stress on the gate oxide film can be further alleviated. This can suppress incomplete formation of the gate oxide film in trench portions having a single end, and suppress a decrease in the dielectric strength voltage of the gate oxide film.

[0110] 3A is a diagram showing region A of a semiconductor device 200 in a comparative example. In the semiconductor device 200, a polysilicon layer 151 is provided between the upper surface of the semiconductor substrate 10 and the active gate runner 131. In other words, the gate runner that crosses the active portion 160 is a laminate of polysilicon and metal. The polysilicon layer 151 is also provided above the isolation region 180. In the semiconductor device 200, a contact hole 54 is formed that connects the first active gate runner 131-1 and the polysilicon layer 151. Similarly, a contact hole 54 is formed that connects the second active gate runner 131-2 and the polysilicon layer 151.

[0111] Fig. 3B is a diagram showing a cross section taken along line BB' of the semiconductor device 200 shown in Fig. 3A. Fig. 3B shows only the upper surface 21 of the semiconductor substrate 10, and does not show the lower surface. The semiconductor substrate 10 has a drift region 18 of the first conductivity type.

[0112] A well region 17 of the second conductivity type is provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. The well region 17 is formed deeper than the gate trench portion 40. A polysilicon layer 151 is provided above the upper surface 21 of the semiconductor substrate 10 with a gate insulating film 42 interposed therebetween. The polysilicon layer 151 is connected to a conductive portion of the gate trench portion 40 at the upper surface 21. The conductive portion may be formed of polysilicon.

[0113] A first active gate runner 131-1, a second active gate runner 131-2, and a bridge electrode portion 58 are provided above the polysilicon layer 151 via an interlayer insulating film 38. The first active gate runner 131-1 and the second active gate runner 131-2 are connected to the polysilicon layer 151 via contact holes 54 provided in the interlayer insulating film 38.

[0114] A gate voltage is transmitted from the active gate runner 131 to the gate trench portion 40 around the separation region 180 of the semiconductor device 200 via the polysilicon layer 151. When the resistance value at each point in the gate trench portion 40 in a top view of the semiconductor device 200 was calculated, the resistance value around the separation region 180 was the highest. This is thought to be because the resistivity of polysilicon is several orders of magnitude higher than the resistivity of aluminum, and therefore the magnitude of the transmission delay of the gate voltage around the separation region 180 is determined by the polysilicon layer 151. In other words, transmission delay is particularly likely to occur around the separation region 180.

[0115] The voltage of the gate trench portion 40 rises to a predetermined voltage as the polysilicon layer 151 and the conductive portion of the gate trench portion 40 are charged. Around the separation region 180 of the semiconductor device 200, the gate trench portions 40 are charged in order starting from the gate trench portion 40 closest to the active gate runner 131 in the second direction, and the gate trench portions 40 farther from the active gate runner 131 are charged more slowly. Therefore, gate delay is likely to occur in the gate trench portions 40 farther from the active gate runner 131.

[0116] Furthermore, when transmitting gate voltage, the semiconductor device is equivalent to charging a circuit with a time constant RC, in which a resistor (resistance value R) and a capacitor (capacitance value C) are connected in series. In the comparative example, since a polysilicon layer 151 is present on the top surface, the capacitance C is larger than in the semiconductor device 100 of the embodiment. Regarding the resistance value R, the farther the gate trench portion is from the active gate runner 131, the longer the distance and the larger the resistance value R. Therefore, since both the increase in capacitance C and the increase in resistance value R are multiplied, the time constant RC becomes significantly larger than in the embodiment.

[0117] In the semiconductor device 100 of the embodiment, there is no polysilicon layer 151, and the first to fifth gate trench portions 40-1 to 40-5 are directly connected to the active gate runner 131. As a result, the resistance value R in each gate trench portion 40 is several orders of magnitude smaller, and the capacitance C is also one order of magnitude smaller, resulting in a significantly smaller time constant RC than in the comparative example. This shortens the time required for charging, suppressing gate delay and preventing a decrease in tolerance due to current imbalance at turn-off.

[0118] 4 is an enlarged top view of the first active gate runner 131-1 and its vicinity in FIG. 2A. In FIG. 4, only the first gate trench portion 40-1 and the fifth gate trench portion 40-5 are shown, and the other trench portions are omitted.

[0119] In this example, the first connection portion 46-1 intersects with the first end side 133-1. The first connection portion 46-1 may intersect with the first end side 133-1 perpendicularly. That is, the first connection portion 46-1 may extend in the second direction. The first gate trench portion 40-1 may not intersect with the first long side 135-1. The fifth connection portion 46-5 similarly intersects with the first end side 133-1.

[0120] In this example, the first connection portion 46-1 extends to the portion overlapping with the first active gate runner 131-1. The first connection portion 46-1 connects to the first active gate runner 131-1 at the portion overlapping with the first active gate runner 131-1. The fifth connection portion 46-5 also extends to the portion overlapping with the first active gate runner 131-1.

[0121] The first connection portion 46-1 may have a first straight portion 47-1 extending in the second direction. In this example, the first straight portion 47-1 intersects with the first end edge 133-1 and extends to a portion overlapping with the first active gate runner 131-1. The width of the first straight portion 47-1 and the width of the first extending portion 49-1 may be equal. The first straight portion 47-1 may be entirely provided in the separation region 180, except for the portion overlapping with the first active gate runner 131-1. The fifth connection portion 46-5 may also have a fifth straight portion 47-5 extending in the second direction.

[0122] The first connection portion 46-1 may have a first curved portion 48-1 connecting the first straight portion 47-1 and the first extension portion 49-1. This allows the first gate trench portion 40-1 to be guided in a direction intersecting with the first end edge 133-1. The entire first curved portion 48-1 may be provided in the separation region 180. Similarly, the fifth connection portion 46-5 may have a fifth curved portion 48-5 connecting the fifth straight portion 47-5 and the fifth extension portion 49-5. In FIG. 4, the boundaries between each extension portion 49 and the curved portion 48 and the boundaries between each curved portion 48 and the straight portion 47 are indicated by dotted lines.

[0123] The other gate trench portions 40 may have a similar configuration. For example, the second connection portion 46-2 may also intersect with the second end side 133-1. The second connection portion 46-2 may also have a second straight portion and a second curved portion. The same applies to the third connection portion 46-3 and the fourth connection portion 46-4.

[0124] Fig. 5 is a view showing a CC' cross section in Fig. 4. The CC' cross section is a YZ cross section that intersects the first connecting portion 46-1 and the fifth connecting portion 46-5. Fig. 5 shows only the upper surface 21 side of the semiconductor substrate 10.

[0125] In the CC' cross section, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, and a first active gate runner 131-1. The semiconductor substrate 10 has an upper surface 21. A drift region 18 and a well region 17 are formed inside the semiconductor substrate 10. The well region 17 is formed between the upper surface 21 of the semiconductor substrate 10 and the drift region 18.

[0126] A plurality of trenches are formed in the semiconductor substrate 10, extending from the upper surface 21 of the semiconductor substrate 10 toward the interior thereof. In FIG. 5, the above-described first gate trench 40-1 and fifth gate trench 40-5 are shown.

[0127] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0128] An interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. A first active gate runner 131-1 is provided above the interlayer insulating film 38. The first active gate runner 131-1 is connected to the gate conductive portion 44 via a contact hole 54 provided in the interlayer insulating film 38.

[0129] The first active gate runner 131-1 may be made of metal, or may be made of metal only, as may the second active gate runner 131-2.

[0130] In this example, no polysilicon gate runner is provided between the first active gate runner 131-1 and the upper surface 21 of the semiconductor substrate 10. The first active gate runner 131-1 does not have to be a stack of metal and polysilicon. By not providing a polysilicon gate runner, the area of ​​the active portion 160 can be increased, as will be described later.

[0131] However, there are cases where the polysilicon of the gate conductive portion 44 is formed above the upper surface immediately above the gate trench portion 40. In this case, polysilicon does not need to be provided between the first active gate runner 131-1 and the upper surface 21 of the semiconductor substrate 10 except for the area immediately above the gate trench portion 40.

[0132] In the semiconductor device 100 of this example, the upper end of the gate conductive portion 44 contacts the first active gate runner 131-1. That is, the first active gate runner 131-1 and the gate conductive portion 44 are in direct contact with each other. The upper end of the gate conductive portion 44 may be flush with the upper surface 21 of the semiconductor substrate 10, or may be located below the upper surface 21. The same may be true for the second active gate runner 131-2.

[0133] 6 is a diagram illustrating an ineffective region formed in the manufacturing process of the semiconductor device 200 of the comparative example. Fig. 6 corresponds to the cross section A-A' crossing the seventh gate trench portion 40-7 in Fig. 3A in the first direction. However, Fig. 6 is a cross-sectional view of the process of forming the emitter region 12 of the semiconductor device 200.

[0134] 6 includes a polysilicon layer 151 above the upper surface 21. The polysilicon layer 151 is provided above an insulating film 39. The insulating film 39 may be a native oxide film or an extension of the gate insulating film 42. An interlayer insulating film 38 is provided above the polysilicon layer 151 and the upper surface 21.

[0135] A resist 92 for forming the emitter region 12 is formed above the interlayer insulating film 38. However, a slope is formed in the resist 92 due to the polysilicon layer 151. If there is a slope, there is a concern that the opening width of the resist 92 will vary, which will result in variations in the dimensions of the emitter region 12. For this reason, the sloped portion may be designated as an ineffective region, and the emitter region 12 will not be formed therein, and the active portion 160 will not be formed therein. In the semiconductor device 100 of this example, the polysilicon layer 151 is not provided, so there is no need to designate an ineffective region, and the area of ​​the active portion 160 can be increased.

[0136] 7 is an enlarged top view of the vicinity of the second active gate runner 131-2 in FIG. 2A. In FIG. 7, the second connection portion 46-2 extends in the second direction and intersects with the second edge 133-2. The second connection portion 46-2 extends to a portion where it overlaps with the second active gate runner 131-2 and is connected to the second active gate runner 131-2 via the contact hole 54.

[0137] The end of the second connection portion 46-2 may be connected by the tip portion 41-2. This can alleviate the electric field concentration at the end of the second connection portion 46-2. The same can be said for the other connection portions 46.

[0138] FIG. 8A is a top view of region A in a modified example of the semiconductor device 100. FIG. 8A differs from the example of FIG. 2A in that the trench portion has a branch. The multiple trench portions in this example include a sixth gate trench portion 40-6. The sixth gate trench portion 40-6 connects to the first connection portion 46-1. In other words, the sixth gate trench portion 40-6 branches off from the first connection portion 46-1. This reduces the total number of connection portions 46 connected to the first active gate runner 131-1, thereby reducing the length d of the first active gate runner 131-1 in the first direction. The sixth gate trench portion 40-6 may branch off from the first linear portion 47-1 of the first connection portion 46-1.

[0139] The trench portion corresponding to the sixth gate trench portion 40-6 may be connected to another connection portion 46. In other words, the trench portion corresponding to the sixth gate trench portion 40-6 may branch off from another connection portion 46. In this example, the trench portion corresponding to the sixth gate trench portion 40-6 branches off from all connection portions 46 from the second connection portion 46-2 to the fourth connection portion 46-4. This allows the length d of the first active gate runner 131-1 or the second active gate runner 131-2 in the first direction to be reduced. Note that the arrangement of the contact holes 54 in the example of FIG. 8A may also be the same as that shown in FIG. 2C.

[0140] FIG. 8B is a diagram illustrating the length c. FIG. 8B is a top view of the same range as FIG. 8A. However, the indications such as n+ and p+ are omitted and the length c is illustrated. The length of the separation region 180 in the second direction is defined as length c. The length of the first active gate runner 131-1 in the first direction is defined as length d. The number of sixth gate trench portions 40-6 connected to one first connection portion 46-1 is defined as number n. In this example, number n is 1. These and the above-mentioned interval a and interval b may satisfy the following relationship: 2×(c / a)×(n+1)≧d / b

[0141] The above relationship represents the relationship between the number (c / a) of extension portions extending into the separation region 180 and the number (d / b) of connection portions 46 connected to the first active gate runner 131-1. The number n may be 0, 2, 3, 4 or more.

[0142] 8C is a diagram illustrating another example of the trench portion in the example of FIG. 8A. FIG. 8C differs from FIG. 8A in that the semiconductor device 100 includes trench connection portions 401 and 402. The trench connection portions 401 in this example are examples of first trench connection portions, third trench connection portions, and fourth trench connection portions. The trench connection portions 401 in this example connect a plurality of first connection portions 46-1 and a plurality of third connection portions 46-3, which are connected to the first active gate runner 131-1. A sixth gate trench portion 40-6 branches off from each of the first connection portions 46-1, and a trench portion corresponding to the sixth gate trench portion 40-6 branches off from each of the third connection portions 46-3.

[0143] The trench connection portion 402 in this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 in this example connects a plurality of second connection portions 46-2 and a plurality of fourth connection portions 46-4, which are connected to the second active gate runner 131-2. A trench portion corresponding to the sixth gate trench portion 40-6 branches off from each of the second connection portions 46-2 and the fourth connection portion 46-4.

[0144] The trench connection portion 401 and the trench connection portion 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portion 401 and the trench connection portion 402, isolated ends of the gate trench portions 40 are eliminated. This prevents the gate oxide film from being poorly formed in a trench portion having a single end, and prevents a decrease in the dielectric strength voltage of the gate oxide film. The trench connection portion 401 and the trench connection portion 402 may be connected to the seventh gate trench portion 40-7.

[0145] 8D is a diagram illustrating another example of the trench portion in the example of FIG. 8A. In FIG. 8D, the shapes of the trench connection portion 401 and the trench connection portion 402 differ from those in FIG. 8C. The trench connection portion 401 in this example is an example of a fourth trench connection portion. In FIG. 8D, the trench connection portion 401 connects the first connection portion 46-1 (the connection portion of the fifth gate trench portion 40-5) that connects to the first active gate runner 131-1, and the third connection portion 46-3 (the connection portion of the gate trench portion 40 that is second from the third gate trench portion 40-3 shown in FIG. 8D toward the positive side of the X-axis).

[0146] The trench connection portion 402 of this example is an example of a sixth trench connection portion. In Figure 8D, the trench connection portion 402 connects the second connection portion 46-2 (the connection portion of the gate trench portion 40 located second from the second gate trench portion 40-2 shown in Figure 8D toward the negative side of the X-axis) that connects to the second active gate runner 131-2, and the fourth connection portion 46-4 (the connection portion of the gate trench portion 40 located second from the fourth gate trench portion 40-4 shown in Figure 8D toward the negative side of the X-axis). The trench connection portion 401 and the trench connection portion 402 of this example are also arc-shaped.

[0147] The trench connection portions 401 and 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portions 401 and 402, isolated ends of the gate trench portions 40 are eliminated. Furthermore, by making the trench connection portions arc-shaped, mechanical and electrical stress on the gate oxide film can be further alleviated. This prevents the gate oxide film from being poorly formed in a trench portion having a single end, and suppresses a decrease in the dielectric strength voltage of the gate oxide film. The first connection portion 46-1 may be connected to the seventh gate trench portion 40-7 below the first active gate runner 131-1. The same applies to the third connection portion 46-3. The second connection portion 46-2 may be connected to the seventh gate trench portion 40-7 below the second active gate runner 131-2. The same applies to the fourth connection portion 46-4.

[0148] 9A is a top view of region A in a modified example of semiconductor device 100. Semiconductor device 100 of this example differs from the example of FIG. 2A in that the multiple trench portions include dummy trench portions 30. Similar to gate trench portion 40, dummy trench portion 30 may have a configuration including a trench provided in semiconductor substrate 10, an insulating film provided on the inner wall of the trench, and a conductive portion insulated from semiconductor substrate 10 by the insulating film. However, the conductive portion of dummy trench portion 30 is not connected to active gate runner 131 but is connected to emitter electrode 52.

[0149] 9A, the dummy trench portion 30 facing the first active gate runner 131-1 in the first direction is shown as the seventh dummy trench portion 30-7. In FIG. 9A, two seventh dummy trench portions 30-7 are provided in the region surrounded by the two seventh gate trench portions 40-7 and the tip portion 41-7. The dummy trench portion 30-7 does not extend to the region overlapping with the first active gate runner 131-1.

[0150] The multiple trench portions may include a first dummy trench portion 30-1 provided between the first gate trench portion 40-1 and the fifth gate trench portion 40-5. In this example, the first dummy trench portion 30-1 extends in a first direction to the separation region 180. By extending the first dummy trench portion 30-1 to the separation region 180, the spacing between the trench portions in the separation region 180 can be set to the spacing a or less. This allows the breakdown voltage to be ensured even if, for example, the well region 17 is not provided in the separation region 180.

[0151] The first dummy trench portion 30-1 may be provided between two first gate trench portions 40-1. The two first dummy trench portions 30-1 may be connected by a tip portion 31-1. Also, in FIG. 9A , a dummy trench portion 30 extending to the separation region 180 is provided adjacent to the second gate trench portion 40-2. The same applies to the third gate trench portion 40-3 and the fourth gate trench portion 40-4. The modified example shown in FIG. 9A may be combined with the modified example shown in FIG. 8A . For example, the first dummy trench portion 30-1 may be provided between two sixth gate trench portions 40-6. Note that, in the example of FIG. 9A , the arrangement of the contact holes 54 may be the same as that shown in FIG. 2C .

[0152] FIG. 9B is a diagram illustrating another example of the trench portion in the example of FIG. 9A . FIG. 9B differs from FIG. 9A in that the semiconductor device 100 includes a trench connection portion 401 and a trench connection portion 402. The trench connection portion 401 in this example is an example of a first trench connection portion, a third trench connection portion, and a fourth trench connection portion. The trench connection portion 401 in this example connects a plurality of first connection portions 46-1 and a plurality of third connection portions 46-3, which are connected to the first active gate runner 131-1. The trench connection portion 402 in this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 in this example connects a plurality of second connection portions 46-2 and a plurality of fourth connection portions 46-4, which are connected to the second active gate runner 131-2.

[0153] The trench connection portions 401 and 402 may be gate trench portions 40. By connecting the ends of the multiple gate trench portions 40 with the trench connection portions 401 and 402, isolated ends of the gate trench portions 40 are eliminated. This makes it possible to suppress insufficient formation of the gate oxide film in a trench portion having a single end, and to suppress a decrease in the dielectric strength voltage of the gate oxide film.

[0154] FIG. 9C is a diagram illustrating another example of the trench portion in the example of FIG. 9A. In FIG. 9C, the shapes of trench connection portion 401 and trench connection portion 402 differ from those in FIG. 9B. The semiconductor device 100 of this example includes a plurality of trench connection portions 401 (trench connection portion 401-1 and trench connection portion 401-2) and a plurality of trench connection portions 402 (trench connection portion 402-1 and trench connection portion 402-2). Trench connection portion 401-1 of this example is an example of a first trench connection portion. Trench connection portion 401-1 of this example connects two adjacent first connection portions 46-1 connected to first active gate runner 131-1. Trench connection portion 401-2 of this example is an example of a third trench connection portion. The trench connection portion 401-2 in this example connects two adjacent third connection portions 46-3 that are connected to the first active gate runner 131-1. Each trench connection portion 401 in this example has an arc shape.

[0155] The trench connection portion 402-1 in this example is an example of a second trench connection portion. The trench connection portion 402-1 in this example connects two adjacent second connection portions 46-2 that connect to the second active gate runner 131-2 to each other. The trench connection portion 402-2 in this example is an example of a fifth trench connection portion. The trench connection portion 402-2 in this example connects two adjacent fourth connection portions 46-4 that connect to the second active gate runner 131-2 to each other. Each trench connection portion 402 in this example is arc-shaped.

[0156] The trench connection portions 401 and 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portions 401 and 402, isolated ends of the gate trench portions 40 are eliminated. Furthermore, by forming the trench connection portions into an arc shape, mechanical and electrical stress on the gate oxide film can be further alleviated. This can suppress incomplete formation of the gate oxide film in trench portions having a single end, and suppress a decrease in the dielectric strength voltage of the gate oxide film.

[0157] 10A is a top view of region A in a modified example of the semiconductor device 100. The emitter region 12 in this example is also provided in the separation region 180, and differs from FIG. 2A in that the well region 17 has a constricted portion 170 in the separation region 180. The emitter region 12 in this example contacts the extension portion 49-1 of the first gate trench portion 40-1 in the separation region 180. The portion of the separation region 180 where the emitter region 12 is provided may also be included in the transistor portion 70. The width of the well region 17 in the first direction (Y-axis direction) in the separation region 180 is smaller than either or both of the width of the first active gate runner 131-1 and the width of the second active gate runner 131-2 in the first direction (Y-axis direction). The number of emitter regions 12 arranged along the trench portion connected to the constricted portion 170 of the well region 17 is greater than the number of emitter regions 12 arranged along the trench portion connected to the non-constricted well region 17. This makes it possible to increase the channel density and the area of ​​the active portion 160.

[0158] The emitter region 12 does not need to be in contact with the connection portion 46-1 in the separation region 180. The same applies to each of the second gate trench portion 40-2 to the fifth gate trench portion 40-5. The modified example shown in FIG. 10A may be combined with the modified example shown in FIG. 8A or 9A.

[0159] 10B is a diagram showing an example of the arrangement of contact holes 54 in the example of FIG. 10A. The contact holes 54 may be provided in the separation region 180. In FIG. 10B, the contact holes 54 provided in the mesa portion 60 facing the separation region 180 in the first direction are extended to the separation region 180. The ends of the contact holes 54 are located above the contact regions 15 in contact with the base region 14-e in the first direction. The bridge electrode portion 58 is electrically connected to the emitter region 12 or the contact region 15 via the contact holes 54.

[0160] 10C is a diagram illustrating another example of the trench portion in the example of FIG. 10A . The trench connection portion 401 in this example is an example of a first trench connection portion, a third trench connection portion, and a fourth trench connection portion. The trench connection portion 401 in this example connects a plurality of first connection portions 46-1 and a plurality of third connection portions 46-3 that are connected to the first active gate runner 131-1. The trench connection portion 402 in this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 in this example connects a plurality of second connection portions 46-2 and a plurality of fourth connection portions 46-4 that are connected to the second active gate runner 131-2.

[0161] The trench connection portion 401 and the trench connection portion 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portion 401 and the trench connection portion 402, isolated ends of the gate trench portions 40 are eliminated. This prevents the gate oxide film from being poorly formed in a trench portion having a single end, and suppresses a decrease in the dielectric strength voltage of the gate oxide film. The trench connection portion 401 and the trench connection portion 402 may be connected to a seventh gate trench portion 40. The end of the trench connection portion 401 in the Y-axis direction may be separated from the gate trench portions 40 that are not connected to the trench connection portion 401 around the trench connection portion 401. The trench connection portion 401 and the surrounding gate trench portions 40 may be separated by a width in the arrangement direction of the gate trench portions 40 or more. The same applies to other examples.

[0162] FIG. 10D is a diagram illustrating another example of the trench portion in the example of FIG. 10A. In FIG. 10D, the shapes of trench connection portion 401 and trench connection portion 402 differ from those in FIG. 2D. The semiconductor device 100 of this example includes multiple trench connection portions 401 (trench connection portion 401-1, trench connection portion 401-2, and trench connection portion 401-3) and multiple trench connection portions 402 (trench connection portion 402-1, trench connection portion 402-2, and trench connection portion 402-3). The trench connection portion 401-1 of this example is an example of a first trench connection portion. In FIG. 10D, the trench connection portion 401-1 connects two adjacent first connection portions 46-1 of the multiple first connection portions 46-1 connected to the first active gate runner 131-1. The trench connection portion 401-2 of this example is an example of a third trench connection portion. In Figure 10D, trench connection portion 401-2 connects two adjacent third connection portions 46-3 of the multiple third connection portions 46-3 connected to first active gate runner 131-1. Trench connection portion 401-3 in this example is an example of a fourth trench connection portion. In Figure 10D, trench connection portion 401-3 connects first connection portion 46-1 and third connection portion 46-3 connected to first active gate runner 131-1. Each trench connection portion 401 in this example is arc-shaped.

[0163] The trench connection portion 402-1 in this example is an example of a second trench connection portion. In FIG. 10D , the trench connection portion 402-1 connects two adjacent second connection portions 46-2 of the multiple second connection portions 46-2 connected to the second active gate runner 131-2. The trench connection portion 402-2 in this example is an example of a fifth trench connection portion. In FIG. 10D , the trench connection portion 402-2 connects two adjacent fourth connection portions 46-4 of the multiple fourth connection portions 46-4 connected to the second active gate runner 131-2. The trench connection portion 402-3 in this example is an example of a sixth trench connection portion. In FIG. 10D , the trench connection portion 402-3 connects the second connection portion 46-2 and the fourth connection portion 46-4 connected to the second active gate runner 131-2. Each trench connection 402 in this example is arc-shaped.

[0164] The trench connection portions 401 and 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portions 401 and 402, isolated ends of the gate trench portions 40 are eliminated. Furthermore, by forming the trench connection portions into an arc shape, mechanical and electrical stress on the gate oxide film can be further alleviated. This can suppress incomplete formation of the gate oxide film in trench portions having a single end, and suppress a decrease in the dielectric strength voltage of the gate oxide film.

[0165] 11 is a top view of the entire semiconductor device 100 according to a modified example. The semiconductor device 100 of this example has a transistor section 70 and a diode section 80. The transistor sections 70 and the diode sections 80 of this example extend in a first direction and are alternately arranged in a second direction. In FIG. 11, the transistor sections 70 are represented by I, and the diode sections 80 are represented by F.

[0166] At least a portion of the transistor portion 70 may face the separation region 180 in the first direction. At least a portion of the diode portion 80 may face the separation region 180 in the first direction. The diode portions 80 that are provided on either side of the separation region 180 in the first direction may be continuous through the separation region 180. The diode portions 80 that are provided on either side of the active gate runner 131 in the first direction are separated by the active gate runner 131.

[0167] FIG. 12A is an enlarged view of region A in FIG. 11 . This example differs from the example of FIG. 2A in that a transistor portion 70 is provided near the first end edge 133-1 and the second end edge 133-2 in the separation region 180. This example also differs from the example of FIG. 2A in that a diode portion 80 is provided between the transistor portions 70 in the second direction in the separation region 180. The diode portion 80 may be a region obtained by projecting a cathode region provided on the underside of the semiconductor substrate 10 (described later) onto the upper surface. This arrangement allows the cathode region and the well region 17 below the active gate runner 131 to be spaced apart, thereby increasing the reverse recovery capability. In this example, the diode portion 80 is provided in the center of the separation region 180. The portion of the separation region 180 where the emitter region 12 is provided may be the transistor portion 70.

[0168] In the diode section 80, the multiple trench sections may include a second dummy trench section 30-2 that extends from below the first emitter electrode 52-1 to below the second emitter electrode 52-2. That is, the second dummy trench section 30-2 penetrates the isolation region 180. The well region 17 is not formed in the center of the isolation region 180. The well region 17 includes a well region 17-1 in the first active gate runner 131-1 and a well region 17-2 in the second active gate runner 131-2, and the well regions 17-1 and 17-2 are separated from each other. On the other hand, both the well region 17-1 and the well region 17-2 are connected to the annular well region 17 formed on the periphery.

[0169] FIG. 12B is a diagram showing an example of the arrangement of the contact holes 54 in the example of FIG. 12A . The contact holes 54 of the diode section 80 may be formed in the separation region 180. This allows the diode section 80 formed in the separation region 180 to operate, thereby increasing the area of ​​the diode section 80. The contact holes 54 do not need to be provided above the well region 17 in the separation region 180. The contact holes 54 in this example are provided from below the first emitter electrode 52-1 to below the second emitter electrode 52-2. That is, the contact holes 54 in this example penetrate the separation region 180. The bridge electrode section 58 is electrically connected to the anode region (base region 14) through the contact holes 54.

[0170] FIG. 12C is a diagram illustrating another example of the trench portion in the example of FIG. 12A. FIG. 12C differs from FIG. 12A in that the semiconductor device 100 includes a trench connection portion 401 and a trench connection portion 402. The trench connection portion 401 in this example is an example of a first trench connection portion, a third trench connection portion, and a fourth trench connection portion. The trench connection portion 401 in this example connects a plurality of first connection portions 46-1 connected to the first active gate runner 131-1 and a plurality of third connection portions 46-3, respectively. The trench connection portion 402 in this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 in this example connects a plurality of second connection portions 46-2 connected to the second active gate runner 131-2 and a plurality of fourth connection portions 46-4, respectively.

[0171] The trench connection portion 401 and the trench connection portion 402 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portion 401 and the trench connection portion 402, isolated ends of the gate trench portions 40 are eliminated. This prevents the gate oxide film from being formed imperfectly in a trench portion having a single end, and prevents a decrease in the dielectric strength voltage of the gate oxide film. The trench connection portion 401 and the trench connection portion 402 may be connected to a seventh gate trench portion 40.

[0172] 13 is a diagram showing an example of the DD' cross section in Figure 12A. The DD' cross section is an XZ plane passing through the emitter region 12 of the transistor section 70 and the base region 14 of the diode section 80. In this cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the first emitter electrode 52-1, and the collector electrode 24.

[0173] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38.

[0174] The first emitter electrode 52-1 is provided above the interlayer insulating film 38. The first emitter electrode 52-1 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The first emitter electrode 52-1 and the collector electrode 24 are formed of a metal material such as aluminum.

[0175] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is n-type. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0176] In the mesa portion 60 of the transistor section 70, an emitter region 12 of a first conductivity type and a base region 14 of a second conductivity type are provided in this order from the upper surface 21 side of the semiconductor substrate 10. In this example, the emitter region 12 is n+ type, and the base region 14 is p-type. A drift region 18 is provided below the base region 14. An n+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0177] The emitter region 12 is provided on the upper surface 21 of the semiconductor substrate 10 and is in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0178] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0179] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an n+-type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0180] A p-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 of the diode portion 80 functions as the anode region of the diode portion 80. The mesa portion 61 of the diode portion 80 is not provided with an emitter region 12. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0181] In each of the transistor section 70 and the diode section 80, an n+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0182] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0183] In the transistor section 70, a p+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0184] In the diode section 80, an n-type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0185] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0186] The transistor section 70 is provided with a gate trench section 40. As described above, the transistor section 70 may be provided with a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but is not provided with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is located at the boundary between the cathode region 82 and the collector region 22.

[0187] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0188] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0189] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 in another cross section. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0190] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0191] The cross section of the transistor portion 70 shown in Figure 2A etc. may be similar to the cross section of the transistor portion 70 shown in Figure 13. In addition, the modified examples shown in Figures 11 to 13 may be combined with any of the modified examples shown in Figure 8A, Figure 9A, or Figure 10A.

[0192] 14 is an overall top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example further includes a temperature sensing section 62, a temperature sensing wiring 64, an anode pad 114, a cathode pad 116, and a third active gate runner 131-3.

[0193] The temperature sensing unit 62 measures the temperature of the semiconductor device 100. One example of the temperature sensing unit 62 is a pn junction diode. At least a portion of the temperature sensing unit 62 in this example is provided in the separation region 180. The anode pad 114 and the cathode pad 116 are connected to the temperature sensing unit 62 via a temperature sensing wiring 64, and output a signal corresponding to the temperature to the outside.

[0194] The third active gate runner 131-3 is arranged along the temperature sensing section 62, the temperature sensing wiring 64, the gate pad 112, the anode pad 114, and the cathode pad 116. The third active gate runner 131-3 is provided in the active section 160, like the other active gate runners 131, and transmits the gate voltage from the gate pad 112 to the gate trench section 40. In FIG. 14 , the third active gate runner 131-3 is indicated by a dashed line.

[0195] 15A is an enlarged view of region A in FIG. 14. At least a portion of the temperature sensing unit 62 in this example is provided in the separation region. The semiconductor device 100 in this example includes a first emitter electrode 52-1, a second emitter electrode 52-2, and a third emitter electrode 52-3. The first emitter electrode 52-1 and the third emitter electrode 52-3 are provided so as to sandwich the temperature sensing wiring 64 in the second direction.

[0196] The third active gate runner 131-3 is provided between the temperature sensing section 62 and the emitter electrode 52. In this example, the third active gate runner 131-3 is also provided between the first emitter electrode 52-1 and the third emitter electrode 52-3 and the temperature sensing wiring 64. In this example, the temperature sensing wiring 64 extends in the first direction. In addition, the third active gate runner 131-3 in this example is also provided between the first active gate runner 131-1 and the second active gate runner 131-2 and the temperature sensing section 62.

[0197] The plurality of trench portions in this example includes an eighth gate trench portion 40-8 that connects to the third active gate runner 131-3. This can suppress gate delay in the eighth gate trench portion 40-8. The eighth gate trench portion 40-8 may connect to the third active gate runner 131-3 in the separation region 180. The eighth gate trench portion 40-8 may connect to a portion of the third active gate runner 131-3 that faces the first end edge 133-1 or the second end edge 133-2 in the second direction. A plurality of eighth gate trench portions may also be provided.

[0198] The eighth gate trench portion 40-8 may have an eighth extension portion 49-8 extending in the first direction. The eighth extension portion 49-8 may or may not extend to the separation region 180. When at least a portion of the temperature sensing portion 62 is provided outside the separation region 180, the eighth extension portion 49-8 may not extend to the separation region 180.

[0199] The eighth gate trench portion 40-8 may have an eighth connection portion 46-8 connecting the eighth extension portion 49-8 to the third active gate runner 131-3. In this example, the eighth connection portion 46-8 is provided in the separation region 180 and has a length in the second direction. However, if the eighth extension portion 49-8 does not extend to the separation region, the eighth connection portion 46-8 may be located outside the separation region 180. As in FIG. 4, the eighth connection portion 46-8 may also have a straight portion and a curved portion.

[0200] The eighth gate trench portion 40-8 may be provided between the first gate trench portion 40-1 and the temperature sensing portion 62, between the second gate trench portion 40-2 and the temperature sensing portion 62, between the third gate trench portion 40-3 and the temperature sensing portion 62, between the fourth gate trench portion 40-4 and the temperature sensing portion 62, or between the fifth gate trench portion 40-5 and the temperature sensing portion 62. The eighth gate trench portion 40-8 may extend from below any one of the emitter electrodes 52 to the separation region 180.

[0201] The plurality of trench portions in this example includes a ninth gate trench portion 40-9 facing the temperature sensing portion 62 in the first direction. The ninth gate trench portion 40-9 may be connected to the third active gate runner 131-3, thereby suppressing delay of the ninth gate trench portion 40-9. The ninth gate trench portion 40-9 may or may not extend to the isolation region 180.

[0202] 15A may also be provided with a bridge electrode portion 58. In that case, the semiconductor device 100 may include a bridge electrode portion 58 that connects the first emitter electrode 52-1 and the second emitter electrode 52-2, and a bridge electrode portion 58 that connects the third emitter electrode 52-3 and the second emitter electrode 52-2.

[0203] 15B is a diagram showing an example of the arrangement of contact holes 54 in the example of FIG. 15A. In this example, too, contact holes 54 are provided above emitter region 12 and contact region 15, but are not provided above base region 14 and well region 17. The end of contact hole 54 in the first direction is located above contact region 15 that contacts base region 14-e in the first direction. Contact holes 54 are also provided in mesa portion 60 that faces separation region 180 in the first direction, but contact holes 54 in this example are not provided in separation region 180.

[0204] FIG. 15C is a diagram illustrating another example of the trench portion in the example of FIG. 15A. FIG. 15C differs from FIG. 15A in that the semiconductor device 100 includes trench connection portions 401, 402, and 403. The trench connection portion 401 in this example is an example of a first trench connection portion, a third trench connection portion, and a fourth trench connection portion. The trench connection portion 401 in this example connects a plurality of first connection portions 46-1 and a plurality of third connection portions 46-3 connected to the first active gate runner 131-1, respectively. The trench connection portion 402 in this example is an example of a second trench connection portion, a fifth trench connection portion, and a sixth trench connection portion. The trench connection portion 402 in this example connects a plurality of second connection portions 46-2 and a plurality of fourth connection portions 46-4 connected to the second active gate runner 131-2, respectively.

[0205] The semiconductor device 100 may have a seventh trench connection portion that connects the multiple eighth connection portions 46-8 to each other. The multiple eighth connection portions 46-8 may be the respective eighth connection portions 46-8 of the eighth gate trench portions provided below different emitter electrodes 52, or may be the respective eighth connection portions 46-8 when multiple eighth gate trench portions 40-8 are provided below the same emitter electrode 52. In Figure 15C, for example, the trench portion adjacent to the eighth gate trench portion 40-8 provided between the first gate trench portion 40-1 and the temperature sensing portion 62 on the positive side of the X-axis may also be considered to be the eighth gate trench portion 40-8.

[0206] The trench connection portion 403 in this example is an example of a seventh trench connection portion. The trench connection portion 403 in this example connects the plurality of eighth connection portions 46-8 that are connected to the third active gate runner 131-3 to each other. A plurality of trench connection portions 403 may be provided.

[0207] The trench connection portion 401, the trench connection portion 402, and the trench connection portion 403 may be gate trench portions 40. By connecting the ends of multiple gate trench portions 40 with the trench connection portion 401, the trench connection portion 402, and the trench connection portion 403, respectively, isolated ends of the gate trench portions 40 are eliminated. This prevents the gate oxide film from being poorly formed in a trench portion having a single end, and prevents a decrease in the dielectric strength voltage of the gate oxide film. The trench connection portion 401 and the trench connection portion 402 may be connected to a seventh gate trench portion 40.

[0208] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0209] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 17...Well region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Insulating film, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate conductive portion, 46...Connection portion, 47...Straight portion, 48...Curved portion, 49...Extended portion, 52...Emitter electrode, 54...Contact hole 1. The semiconductor device includes: 58: bridge electrode portion, 60: mesa portion, 61: mesa portion, 62: temperature sensor portion, 64: temperature sensor wiring, 70: transistor portion, 80: diode portion, 82: cathode region, 90: edge termination structure portion, 92: resist, 100: semiconductor device, 112: gate pad, 114: anode pad, 116: cathode pad, 130: peripheral gate runner, 131: active gate runner, 133: edge, 135: long side, 151: polysilicon layer, 160: active portion, 162: edge, 170: constricted portion, 180: separation region, 200: semiconductor device, 401, 402, 403: trench connection portion

Claims

1. A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; a plurality of trench portions extending inward from the upper surface of the semiconductor substrate in a first direction on the upper surface; a first active gate runner extending above the upper surface of the semiconductor substrate in a second direction intersecting the first direction; a second active gate runner extending in the second direction and spaced apart from the first active gate runner in the second direction; and a separation region provided between the first active gate runner and the second active gate runner along the second direction, wherein the plurality of trench portions have first gate trench portions, and the first gate trench portion has a first extension portion extending in the first direction to the separation region, and a first connection portion provided in the separation region and connecting the first extension portion to the first active gate runner.

2. The semiconductor device of claim 1, wherein, in a top view, the first active gate runner has a first end edge, the second active gate runner has a second end edge facing the first end edge in the second direction, and the first connection portion intersects with the first end edge.

3. The semiconductor device according to claim 2, wherein the first connection portion extends to a portion overlapping the first active gate runner.

4. The semiconductor device according to claim 1, wherein the first connection portion has a first linear portion extending in the second direction.

5. The semiconductor device according to claim 4, wherein the first connecting portion has a first curved portion connecting the first straight portion and the first extending portion.

6. The semiconductor device according to claim 1, wherein the plurality of trench portions comprise second gate trench portions, and the second gate trench portion has: a second extension portion extending in the first direction to the separation region; and a second connection portion provided in the separation region and connecting the second extension portion to the second active gate runner.

7. The semiconductor device described in claim 6, comprising: a first emitter electrode provided above the upper surface of the semiconductor substrate; and a second emitter electrode arranged to face the first emitter electrode, sandwiching the first active gate runner, the second active gate runner, and the separation region in the first direction, wherein the first gate trench portion and the second gate trench portion extend in the first direction from below the first emitter electrode to the separation region.

8. The semiconductor device described in claim 7, wherein the plurality of trench portions comprise third gate trench portions, and the third gate trench portion has: a third extension portion extending in the first direction from below the second emitter electrode to the separation region; and a third connection portion provided in the separation region and connecting the third extension portion to the first active gate runner.

9. The semiconductor device described in claim 8, wherein the plurality of trench portions comprise fourth gate trench portions, and the fourth gate trench portion has: a fourth extension portion extending in the first direction from below the second emitter electrode to the separation region; and a fourth connection portion provided in the separation region and connecting the fourth extension portion to the second active gate runner.

10. The semiconductor device according to claim 7, further comprising a bridge electrode portion provided in the separation region and connecting the first emitter electrode and the second emitter electrode.

11. A semiconductor device as described in any one of claims 1 to 10, wherein the plurality of trench portions include a fifth gate trench portion positioned farther from the first active gate runner in the second direction than the first gate trench portion, and the fifth gate trench portion has a fifth extension portion extending in the first direction to the separation region, and a fifth connection portion provided in the separation region and connecting the fifth extension portion to the first active gate runner, and the fifth extension portion extends further inside the separation region in the first direction than the first extension portion.

12. A semiconductor device described in any one of claims 1 to 10, wherein the spacing a in the second direction between the multiple trench portions extending in the first direction to the separation region and the spacing b in the first direction between the multiple trench portions in the separation region satisfy the following relationship: 0.01 < b / a < 1.

13. The semiconductor device according to any one of claims 1 to 10, wherein the plurality of trench portions include a sixth gate trench portion connected to the first connection portion.

14. The semiconductor device described in claim 13, wherein the spacing a in the second direction between the multiple trench portions extending in the first direction to the separation region, the spacing b in the first direction between the multiple trench portions in the separation region, the length c of the separation region in the second direction, the length d of the first active gate runner in the first direction, and the number n of the sixth gate trench portions connected to one first connection portion satisfy the following relationship: 2×(c / a)×(n+1)≧d / b.

15. The semiconductor device according to any one of claims 1 to 10, wherein the first active gate runner and the second active gate runner are formed of metal.

16. The semiconductor device of claim 15, wherein no polysilicon gate runners are provided between the first and second active gate runners and the top surface of the semiconductor substrate.

17. The semiconductor device according to claim 16, wherein the first gate trench portion has a gate conductive portion made of polysilicon, and an upper end of the gate conductive portion is in contact with the first active gate runner.

18. The semiconductor device according to claim 15, wherein the separation region is free of a polysilicon gate runner connecting the first active gate runner and the second active gate runner.

19. A semiconductor device as described in any one of claims 1 to 10, wherein the plurality of trench portions include a seventh gate trench portion facing the first active gate runner in the first direction, and the seventh gate trench portion extends in the first direction to below the first active gate runner and is connected to the first active gate runner.

20. The semiconductor device described in claim 11, wherein the plurality of trench portions include a first dummy trench portion provided between the first gate trench portion and the fifth gate trench portion, and the first dummy trench portion extends in the first direction to the separation region.

21. A semiconductor device according to any one of claims 1 to 10, wherein the semiconductor substrate has: a drift region of a first conductivity type; and an emitter region of the first conductivity type provided on the upper surface of the semiconductor substrate and having a higher concentration than the drift region, the emitter region also being provided in the separation region.

22. The semiconductor device according to claim 2 or 3, wherein a transistor section is provided in the separation region near the first end edge and the second end edge, and a diode section is provided in the separation region between the transistor sections in the second direction.

23. The semiconductor device described in claim 22, further comprising: a first emitter electrode and a second emitter electrode provided above the upper surface of the semiconductor substrate and arranged in the first direction with the first active gate runner, the second active gate runner, and the separation region sandwiched therebetween; and in the diode portion, the plurality of trench portions include second dummy trench portions provided from below the first emitter electrode to below the second emitter electrode.

24. A semiconductor device according to any one of claims 1 to 6, comprising: an emitter electrode provided above the upper surface of the semiconductor substrate; a temperature sensing portion at least a portion of which is provided in the separation region; and a third active gate runner provided between the temperature sensing portion and the emitter electrode, wherein the plurality of trench portions include an eighth gate trench portion connected to the third active gate runner.

25. The semiconductor device according to claim 1, wherein the plurality of trench portions include a plurality of the first gate trench portions, and a first trench connection portion that connects the plurality of first connection portions to each other.

26. The semiconductor device according to claim 6, wherein the plurality of trench portions include a plurality of second gate trench portions, and a second trench connection portion that connects the plurality of second connection portions to each other.

27. The semiconductor device according to claim 8, wherein the plurality of trench portions include a plurality of the third gate trench portions, and a third trench connection portion that connects the plurality of third connection portions to each other.

28. The semiconductor device according to claim 8, further comprising a fourth trench connection portion that connects the first connection portion and the third connection portion to each other.

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