Semiconductor device

Abstract

This semiconductor device includes: a chip including a trench, a first impurity region, a second impurity region, and a third impurity region; a first embedded conductive layer embedded in the trench of the chip and facing the second impurity region; a trench insulating film between the inner surface of the trench and the first embedded conductive layer; a second embedded conductive layer forming a Schottky junction or a heterojunction with the first impurity region on the inner surface of the trench; a separation insulating film separating the first embedded conductive layer from the second embedded conductive layer; a first electrode electrically connected to the third impurity region and the second embedded conductive layer; and a second electrode electrically connected to the first impurity region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-114879 filed with the Japan Patent Office on July 18, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a SiC semiconductor layer, a gate trench formed in a first main surface, a gate insulating layer formed on an inner wall of the gate trench, a gate electrode embedded in the gate trench with the gate insulating layer sandwiched therebetween, a first conductivity type source region formed on a side of the gate trench in a surface layer portion of the first main surface, a second conductivity type body region formed in a region on the second main surface side relative to the source region in the surface layer portion of the first main surface, a first conductivity type drift region formed in a region on the second main surface side relative to the body region in the SiC semiconductor layer, and ２０ cm －３ and a second conductivity type contact region formed in a surface layer portion of the first main surface in a region on the opposite side of the source region from the gate trench, the second conductivity type contact region having the following second conductivity type impurity concentration:

[0004] Japanese Patent Application Laid-Open No. 2023-179690

[0005] an insulating film between an inner surface of the trench and the control electrode; a buried electrode that is buried in the trench closer to a bottom of the trench than the control electrode and forms a Schottky junction or a heterojunction with the first impurity region at the inner surface of the trench; an isolation insulating film between the control electrode and the buried electrode and separates the control electrode from the buried electrode; a first electrode electrically connected to the third impurity region and the buried electrode; and a second electrode electrically connected to the first impurity region.

[0006] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example chip layout. FIG. 4 is a perspective view showing an example chip layout. FIG. 5 is a perspective view showing an active region and a gate structure of the semiconductor device. FIG. 6 is an enlarged plan view showing a main portion of the active region and the peripheral region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6 . FIG. 9 is the same cross-sectional view as FIG. 7 , but mainly shows the dimensions of each portion. FIG. 10 is a cross-sectional view taken along line XX in FIG. 6 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6 . FIG. 12 is a cross-sectional view showing the peripheral region. FIG. 13 is a cross-sectional view showing the peripheral region. FIG. 14 is a plan view of the active region and the peripheral region of a first modification of the semiconductor device. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 . 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14 . FIG. 18 is a cross-sectional view showing the outer periphery region of a first modified example of the semiconductor device. FIG. 19 is a cross-sectional view showing a second modified example of the semiconductor device. FIG. 20 is a cross-sectional view showing a third modified example of the semiconductor device. FIG. 21 is a cross-sectional view showing a fourth modified example of the semiconductor device. FIG. 22 is a cross-sectional view showing a fifth modified example of the semiconductor device. FIG. 23 is a cross-sectional view showing a sixth modified example of the semiconductor device. FIG. 24 is a cross-sectional view showing a seventh modified example of the semiconductor device. FIG. 25 is a cross-sectional view showing an eighth modified example of the semiconductor device. FIG. 26 is a cross-sectional view showing a ninth modified example of the semiconductor device. FIG. 27 is a cross-sectional view showing a tenth modified example of the semiconductor device. FIG. 28 is a cross-sectional view showing an eleventh modified example of the semiconductor device. FIG. 29 is a cross-sectional view showing a twelfth modified example of the semiconductor device. FIG. 30 is a cross-sectional view showing a thirteenth modified example of the semiconductor device. FIG. 31 is a cross-sectional view showing a fourteenth modified example of the semiconductor device. FIG. 32 is a cross-sectional view showing a fifteenth modified example of the semiconductor device. FIG. 33 is a cross-sectional view of a 16th modification of the semiconductor device.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) Overall Configuration of Semiconductor Device 1 Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0012] 1 to 4, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0013] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B each extend in a first direction X along the first main surface 3 and face opposite each other in a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D each extend in the second direction Y and face opposite each other in the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0022] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0023] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0024] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 6 as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0025] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate (i.e., a SiC substrate) made of SiC single crystal. The first semiconductor layer 6 has the off direction Do and off angle θo described above.

[0026] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0027] The first semiconductor layer 6 may have a first thickness T1 of 10 μm to 500 μm. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0028] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0029] In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the off-direction Do and off-angle θo described above. The second semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first semiconductor layer 6.

[0030] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the ending point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0031] The second semiconductor layer 7 includes an n-type drift region 8 as an example of a first impurity region. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor layer 7.

[0032] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 7 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the first semiconductor layer 6.

[0033] The second semiconductor layer 7 may have a lower n-type impurity concentration than the first semiconductor layer 6. The second semiconductor layer 7 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １７ cm －３ The second semiconductor layer 7 may have the following peak n-type impurity concentration: It is preferable that the second semiconductor layer 7 has a substantially constant n-type impurity concentration in the thickness direction.

[0034] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0035] The semiconductor device 1 includes an active region 9 defined in a chip 2. The active region 9 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0036] The active region 9 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0037] The ratio (area ratio) of the planar area of ​​the active region 9 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0038] The semiconductor device 1 includes a peripheral region 10 set outside the active region 9 in the chip 2. The peripheral region 10 is a region that does not include a device structure (transistor structure Tr). The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a planar view. The peripheral region 10 extends in a strip shape along the active region 9 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0039] The semiconductor device 1 includes a plurality of trench electrode type gate structures 11 formed on the first main surface 3 in the active region 9. The gate structures 11 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 11 as a control potential.

[0040] The multiple gate structures 11 are arranged at intervals inward from the periphery of the active region 9. In this embodiment, the multiple gate structures 11 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the multiple gate structures 11 are arranged at intervals in the m-axis direction and each extend in the a-axis direction.

[0041] In this embodiment, the multiple gate structures 11 are arranged in stripes extending in the a-axis direction (second direction Y). The extending direction of the multiple gate structures 11 coincides with the off-direction Do of the second semiconductor layer 7. The multiple gate structures 11 are formed at intervals from the lower end (first semiconductor layer 6) of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.

[0042] The plurality of gate structures 11 includes a plurality of diode structures 12 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. Specifically, the plurality of diode structures 12 are formed at the bottom of each of the gate structures 11.

[0043] The semiconductor device 1 includes a p-type outer well region 13 and a p-type field region 14 formed in a surface layer portion of the first main surface 3 in a peripheral region 10 (the peripheral portion of the first main surface 3).

[0044] The semiconductor device 1 includes a surface insulating film 15 that selectively covers the first main surface 3. The surface insulating film 15 may also be referred to as an "outer surface insulating film," etc. The surface insulating film 15 covers the first main surface 3 in the peripheral region 10 in a film-like manner.

[0045] Specifically, the surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14 in the peripheral region 10. The surface insulating film 15 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0046] The semiconductor device 1 includes one or more (one in this embodiment) gate wirings 17 arranged on the first main surface 3 in the peripheral region 10. The gate wiring 17 is arranged on a surface insulating film 15.

[0047] 3 , the gate wiring 17 extends in a strip shape along the periphery of the plurality of gate structures 11. The gate wiring 17 has a portion extending in a first direction X and a portion extending in a second direction Y. The gate wiring 17 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 11.

[0048] In this embodiment, the gate wiring 17 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the plurality of gate structures 11 (active regions 9). Of course, the gate wiring 17 may be formed in a strip shape with ends. The gate wiring 17 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape).

[0049] The semiconductor device 1 includes a gate pad wiring 18 arranged on the first main surface 3 in the peripheral region 10. The gate pad wiring 18 is electrically connected to the gate wiring 17 and applies a gate potential to the gate wiring 17.

[0050] The semiconductor device 1 includes an insulating interlayer 16 that covers the surface insulating film 15. The interlayer insulating layer 16 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer insulating layer 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0051] The semiconductor device 1 includes a source pad electrode 20 disposed on the first main surface 3. The source pad electrode 20 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source electrode," etc. The source pad electrode 20 is disposed on the interlayer insulating layer 16.

[0052] In this embodiment, the source pad electrode 20 has a first pad portion 21, a second pad portion 22, and a third pad portion 23. The first pad portion 21 has a relatively large planar area and forms the main body of the source pad electrode 20. In this embodiment, the first pad portion 21 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0053] The second pad portion 22 has a planar area smaller than that of the first pad portion 21, and is drawn out in a strip shape (rectangular shape) from one end portion of the first pad portion 21 in the second direction Y (the end portion on the first side surface 5A side) toward the third side surface 5C. The third pad portion 23 has a planar area smaller than that of the first pad portion 21, and is drawn out in a strip shape (rectangular shape) from the other end portion of the first pad portion 21 in the second direction Y (the end portion on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 22 in the second direction Y.

[0054] The planar area of ​​the third pad portion 23 may be approximately equal to the planar area of ​​the second pad portion 22. The planar area of ​​the third pad portion 23 may be larger or smaller than the planar area of ​​the second pad portion 22. Either or both of the second pad portion 22 and the third pad portion 23 may be used as a terminal portion for monitoring a current.

[0055] The source pad electrode 20 does not necessarily have to have both the second pad portion 22 and the third pad portion 23. The source pad electrode 20 may have only one of the second pad portion 22 and the third pad portion 23. The source pad electrode 20 may be composed of only the first pad portion 21, and may not have both the second pad portion 22 and the third pad portion 23.

[0056] The source pad electrode 20 covers the entire region of the interlayer insulating layer 16 where the source opening 19 is formed, in a film-like manner, and extends into the source opening 19 from above the interlayer insulating layer 16. The source pad electrode 20 has a portion that covers the interlayer insulating layer 16 in a film-like manner, a portion that covers the wall surface of the source opening 19 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 19 in a film-like manner.

[0057] The semiconductor device 1 includes a gate pad electrode 24 disposed on the first main surface 3 at a distance from the source pad electrode 20. The gate pad electrode 24 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate electrode," or the like. The gate pad electrode 24 is disposed on the interlayer insulating layer 16 at a distance from the source pad electrode 20.

[0058] In this embodiment, the gate pad electrode 24 is disposed on a portion of the interlayer insulating layer 16 that covers the gate pad wiring 18, and faces the gate pad wiring 18 across the interlayer insulating layer 16. In this embodiment, the gate pad electrode 24 does not have a direct electrical connection to the gate pad wiring 18. Of course, the gate pad electrode 24 may be mechanically and electrically connected to the gate pad wiring 18 via one or more gate openings.

[0059] The gate pad electrode 24 is disposed in a region on the third side surface 5C side of the first pad portion 21, and faces the center of the third side surface 5C and the first pad portion 21 in the first direction X. The gate pad electrode 24 is interposed in a region between the second pad portion 22 and the third pad portion 23, and faces both the second pad portion 22 and the third pad portion 23 in the second direction Y.

[0060] The gate pad electrode 24 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 24 has a planar area smaller than the planar area of ​​the source pad electrode 20. The gate pad electrode 24 has a planar area smaller than the planar area of ​​the first pad portion 21. The gate pad electrode 24 may also have a planar area smaller than the planar area of ​​the second pad portion 22 (third pad portion 23).

[0061] The gate pad electrode 24 faces the outer well region 13 across the interlayer insulating layer 16 and the gate pad wiring 18. In this embodiment, the gate pad electrode 24 is formed at a distance from the ends (both ends) of the plurality of gate structures 11. In other words, the gate pad electrode 24 does not face the plurality of gate structures 11 in the stacking direction. Of course, the gate structure 11 may have a portion facing a part (for example, an end) of the gate structure 11 across the interlayer insulating layer 16.

[0062] The semiconductor device 1 includes gate finger electrodes 25 extending from the gate pad electrode 24 onto the first main surface 3. The gate finger electrodes 25 may also be referred to as "gate wiring" or "gate fingers." The gate finger electrodes 25 transmit the gate potential applied to the gate pad electrode 24 to other regions.

[0063] The gate finger electrodes 25 are drawn out from the gate pad electrode 24 onto a portion of the interlayer insulating layer 16 that covers the gate wiring 17. The gate finger electrodes 25 are routed in a strip shape around the periphery of the first main surface 3 and in a region between the source pad electrode 20. The gate finger electrodes 25 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0064] In this embodiment, the gate finger electrode 25 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 20. The gate finger electrode 25 is arranged closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 11. The gate finger electrode 25 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0065] The semiconductor device 1 includes a first slit portion 26 defined in a region between the source pad electrode 20 and the gate finger electrode 25. The first slit portion 26 exposes the interlayer insulating layer 16.

[0066] The semiconductor device 1 includes source finger electrodes 27 extending from the source pad electrode 20 onto the first main surface 3. The source finger electrodes 27 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 27 transmit the gate potential applied to the source pad electrode 20 to other regions.

[0067] The source finger electrodes 27 are arranged at intervals from the gate pad electrode 24 and the gate finger electrodes 25. The source finger electrodes 27 are arranged in regions on the peripheral edge side of the first main surface 3 with respect to both end portions of the plurality of gate structures 11.

[0068] The source finger electrodes 27 are drawn out from the source pad electrodes 20 onto the interlayer insulating layer 16. The source finger electrodes 27 are routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrodes 20. The source finger electrodes 27 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0069] In this embodiment, source finger electrode 27 is formed in a strip shape with four sides parallel to the periphery of first main surface 3, and surrounds source pad electrode 20 and gate finger electrode 25. Outer well region 13 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in an arc shape (preferably a quarter arc shape).

[0070] Semiconductor device 1 includes second slit portions 28 defined in regions between gate finger electrodes 25 and source finger electrodes 27. Second slit portions 28 are defined in regions between the outer edge of gate wiring 17 and the outer edge of outer well region 13, and overlap first main surface 3 in the stacking direction.

[0071] The semiconductor device 1 includes a drain pad electrode 29 covering the second main surface 4. The drain pad electrode 29 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 29 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 29 forms ohmic contact with the first semiconductor layer 6.

[0072] The drain pad electrode 29 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 29 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0073] A breakdown voltage that can be applied between source pad electrode 20 and drain pad electrode 29 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0074] (2) Detailed Structure of the Active Region 9 of the Semiconductor Device 1 Figure 5 is a perspective view showing the active region 9 and gate structure 11 of the semiconductor device 1. Figure 6 is an enlarged plan view showing a main portion of the active region 9 and the peripheral region 10. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 6. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 6. Figure 9 is the same cross-sectional view as Figure 7, and mainly shows the dimensions of each portion.

[0075] In the following, for clarity of the drawings, the dimensions (thickness, width, depth, etc.) of each part of the semiconductor device 1 are shown in Fig. 9, and are omitted from Fig. 5 to Fig. 8. In Fig. 9, in addition to the dimensions of each part, reference numerals are used to denote the main components.

[0076] 5 to 9 , semiconductor device 1 includes a p-type body region 30 formed in a surface layer portion of drift region 8. In this embodiment, body region 30, which is an example of a second impurity region, is formed in a layer shape extending along first main surface 3. Body region 30 is formed at an interval from the lower end of second semiconductor layer 7 toward first main surface 3. Body region 30 forms a body diode BD between itself and drift region 8.

[0077] The body region 30 is 1×10１５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0078] As described above, the semiconductor device 1 includes gate structures 11. Referring to Fig. 9, each gate structure 11 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 (see Fig. 4) of the second semiconductor layer 7. The trench width WT may be 0.1 µm or more and 5 µm or less.

[0079] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0080] The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. In other words, the multiple gate structures 11 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0081] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0082] The multiple gate structures 11 are arranged at intervals in the first direction X. The trench pitch PT of the multiple gate structures 11 may be 0.1 μm or more and 5 μm or less. The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The trench pitch PT is preferably 0.5 μm or more and 3 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0083] 5 to 8 , each gate structure 11 includes a trench 31, a trench insulating film 32 as an example of a control insulating film, and a first buried conductive layer 33 as an example of a control electrode. The trench 31 may be referred to as an "element trench," a "gate trench," or the like. The trench insulating film 32 may be referred to as a "control insulating film," an "element insulating film," a "gate insulating film," or the like. The first buried conductive layer 33 may be referred to as a "control electrode," a "buried electrode," a "gate electrode," or the like.

[0084] The trench 31 is formed in the first main surface 3 and defines the inner surface (side surface 34 and bottom surface 35 shown in FIGS. 7 and 8 ) of the gate structure 11. The bottom surface 35 of the trench 31 preferably has a portion that extends flat.

[0085] Between adjacent trenches 31, a mesa portion 36 is formed by a part of the second semiconductor layer 7. The mesa portion 36 may be referred to as an "element mesa portion."

[0086] 5 , the gate structures 11 (trenches 31) and mesa portions 36 are strip-shaped extending along the second direction Y and are arranged alternately in the first direction X. The trenches 31 and mesa portions 36 are arranged in a stripe pattern as a whole. The mesa portions 36 provide unit cells UC of the trench-gate transistor. The unit cell UC includes at least a body region 30 and a source region 45 (described later), and may be the minimum unit that functions as a MIS transistor Tr.

[0087] The width WM of the mesa portion 36 may be smaller or larger than the trench width WT. In this embodiment, the width WM of the mesa portion 36 is larger than the trench width WT. The width WM of the mesa portion 36 may be, for example, not less than 0.2 μm and not more than 3.0 μm.

[0088] 7 and 8 , it is particularly preferable that the flat portion of bottom surface 35 of trench 31 extends substantially parallel to first major surface 3. That is, it is preferable that the bottom wall of trench 31 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do (see FIG. 4 ) with respect to the c-plane. It is preferable that bottom surface 35 of trench 31 has a flat portion extending in off direction Do. Bottom surface 35 of trench 31 may be curved in an arc shape toward the lower end side of second semiconductor layer 7.

[0089] In this embodiment, the bottom surface 35 is a polar surface (c-plane), and the side surface 34 is a non-polar surface (m-plane or a-plane). The c-plane is (0001). The m-plane is the (10-10) plane and other planes equivalent to the (10-10) plane. The a-plane is the (-2110) plane and other planes equivalent to the (-2110) plane. The side surface 34 is an m-plane when the extension direction of the trench 31 is the m-axis direction, and is an a-plane when the extension direction of the trench 31 is the a-axis. The bottom surface 35 may be a non-polar surface, and the side surface 34 may be a polar surface.

[0090] The trench insulating film 32 covers the inner surface of the trench 31. The trench insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 32 has a single-layer structure made of a silicon oxide film. The trench insulating film 32 may also include a silicon oxide film made of an oxide of the chip 2. The trench insulating film 32 may also have a multi-layer structure made of different insulating materials.

[0091] The first buried conductive layer 33 is buried in the trench 31 and faces the body region 30 (channel region 37) across the trench insulating film 32. The first buried conductive layer 33 may include p-type or n-type conductive polysilicon.

[0092] 7 and 8 , the first buried conductive layer 33 is buried up to the middle of the trench 31 in the depth direction. The first buried conductive layer 33 has an upper surface 38 located closer to the second main surface 4 than the first main surface 3. A low step 39 is formed on the second main surface 4 side between the upper surface 38 of the first buried conductive layer 33 and the first main surface 3. This step 39 forms a recess 40 in the upper part of the trench 31, which is defined by the upper surface 38 of the first buried conductive layer 33 and the side surface 34 of the trench 31.

[0093] The recess 40 is a space sandwiched between both side surfaces 34 of the trench 31 and an upper surface 38 of the first buried conductive layer 33. As shown in Fig. 5, the recess 40 is formed in a continuous strip shape in the depth direction (second direction Y) of the trench 31. The depth direction of the trench 31 may also be referred to as the "length direction of the trench 31," the "depth direction of the mesa portion 36," or the "length direction of the mesa portion 36."

[0094] The trench insulating film 32 is selectively formed in the region sandwiched between the inner surface of the trench 31 and the first buried conductive layer 33, and the side surface 34 of the recess 40 (part of the side surface 34 of the trench 31) is exposed from the trench insulating film 32.

[0095] Due to the formation of the recess 40, a part of the mesa portion 36 in the depth direction of the trench 31 protrudes as a protruding portion 41 toward the first main surface 3 (upward) beyond the first buried conductive layer 33. As shown in Fig. 5, the protruding portion 41 of the mesa portion 36 is a portion of the mesa portion 36 sandwiched between adjacent recesses 40, and is formed in a continuous band shape in the depth direction of the trench 31.

[0096] As described above, the gate structure 11 includes the diode structure 12. The diode structure 12 is disposed at the bottom of the gate structure 11 and is electrically isolated from the first buried conductive layer 33. The diode structure 12 is disposed in the trench 31. The diode structure 12 forms a Schottky junction or a heterojunction with the drift region 8 on the inner surface of the trench 31. The diode structure 12 provides a diode Di consisting of the Schottky junction or the heterojunction. In this form, the diode structure 12 provides the diode Di on at least one of the side surface 34 and the bottom surface 35 of the trench 31.

[0097] The diode Di may be referred to as a Schottky barrier diode SBD when the junction between the second buried conductive layer 42 and the drift region 8 is a Schottky junction. The diode Di may be referred to as a heterojunction diode HJD when the junction between the second buried conductive layer 42 and the drift region 8 is a heterojunction.

[0098] The diode structure 12 includes a second buried conductive layer 42 as an example of a buried electrode, and a first buried insulating layer 43 as an example of an isolation layer.

[0099] The second buried conductive layer 42 is buried in the trench 31 closer to the bottom of the trench 31 than the first buried conductive layer 33. The second buried conductive layer 42 and the first buried conductive layer 33 are physically and electrically isolated from each other by an isolation insulating film 44. In this embodiment, a two-layer structure of a first buried insulating layer 43 and a second buried conductive layer 42 stacked in this order from the bottom surface 35 along the side surface 34 is disposed below the first buried conductive layer 33 in the trench 31.

[0100] The isolation insulating film 44 is an insulating film that crosses the trench 31 at the center of the trench 31 in the depth direction. The isolation insulating film 44 may also be referred to as an "intermediate insulating film," an "intermediate insulating layer," or the like. The isolation insulating film 44 covers the top surface of the second buried conductive layer 42 and is integrally connected to the trench insulating film 32 at the side surface 34. The second buried conductive layer 42 is sandwiched between the isolation insulating film 44 and the first buried insulating layer 43 in the depth direction of the trench 31.

[0101] The isolation insulating film 44 may be formed of the same material as the trench insulating film 32. The isolation insulating film 44 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the isolation insulating film 44 has a single-layer structure made of a silicon oxide film. The isolation insulating film 44 may also include a silicon oxide film made of an oxide of the second buried conductive layer 42. The isolation insulating film 44 may have a multi-layer structure made of different insulating materials.

[0102] The isolation insulating film 44 separates at least two conductors, including the first buried conductive layer 33 and the second buried conductive layer 42, in the vertical direction of the trench 31. The gate structure 11 may be referred to as a split gate structure in which the first buried conductive layer 33 (gate electrode) and the second buried conductive layer 42 (diode electrode) are insulated and isolated from each other. The gate structure 11 may also be referred to as a trench gate structure with a built-in diode electrode.

[0103] 5, the second buried conductive layer 42 is formed in a continuous strip shape extending in the depth direction (second direction Y) of the trench 31. Therefore, in the active region 9, a plurality of stripe-shaped diodes Di extending in the second direction Y are arranged at the same trench pitch PT as the trenches 31 (see FIG. 8). In this configuration, the diodes Di are embedded in each gate structure 11 in a one-to-one relationship.

[0104] The second buried conductive layer 42 extends from one side surface 34 to the other side surface 34 along the isolation insulating film 44 in the width direction of the trench 31. The second buried conductive layer 42 is in direct contact with the drift region 8 exposed from both side surfaces 34, i.e., the one side surface 34 and the other side surface 34. The second buried conductive layer 42 has, on both side surfaces 34, junction interfaces 48 that form Schottky junctions or heterojunctions with the drift region 8. The junction interfaces 48 between the second buried conductive layer 42 and the side surfaces 34 are Schottky interfaces or heterojunctions without any insulating layer interposed therebetween.

[0105] The second buried conductive layer 42 is made of various conductive materials capable of forming a Schottky junction or a heterojunction with the drift region 8 (an n-type semiconductor in this embodiment). For example, the second buried conductive layer 42 may include a Schottky metal made of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, a Ni layer, or a silicide thereof, or a heteroelectrode made of polysilicon. The second buried conductive layer 42 may have a single-layer structure made of any of the above materials, or may have a multi-layer structure made of a combination of multiple conductive materials.

[0106] The second buried conductive layer 42 has a width EW2 that is larger than the width EW1 of the first buried conductive layer 33 by the thickness of the trench insulating film 32. The width EW2 may be approximately equal to the trench width WT.

[0107] The first buried insulating layer 43 is disposed in the deepest part of the trench 31. The first buried insulating layer 43 is an insulating film that crosses the trench 31 at the bottom in the depth direction of the trench 31. The first buried insulating layer 43 may also be referred to as a "lower insulating film," "lower insulating layer," "bottom insulating film," "bottom insulating layer," etc.

[0108] The first buried insulating layer 43 is in direct contact with the bottom surface 35 and lower portions of the side surfaces 34 of the trench 31, and covers the bottom surface 35 and lower portions of the side surfaces 34 from inside the trench 31. The first buried insulating layer 43 is interposed between the second buried conductive layer 42 and the bottom surface 35 of the trench 31. The first buried insulating layer 43 prevents contact between the second buried conductive layer 42 and the bottom surface 35, and electrically isolates the second buried conductive layer 42 from the bottom surface 35.

[0109] 5 , the first buried insulating layer 43 is formed in a continuous band shape in the depth direction (second direction Y) of the trench 31. The first buried insulating layer 43 extends from one side surface 34 to the other side surface 34 along the second buried conductive layer 42 in the width direction of the trench 31. The first buried insulating layer 43 is in direct contact with the drift region 8 exposed from both side surfaces 34 of the one side surface 34 and the other side surface 34. Both end portions of an interface 49 between the first buried insulating layer 43 and the second buried conductive layer 42 are in contact with the drift region 8 on both side surfaces 34.

[0110] 9, the thickness of first buried insulating layer 43 may be greater or smaller than the thickness of isolation insulating film 44. For example, thickness MT of isolation insulating film 44 may be 0.02 μm or more and 1.5 μm or less (preferably 0.1 μm or more and 1.0 μm or less), and thickness LT of first buried insulating layer 43 may be 0.02 μm or more and 1.5 μm or less (preferably 0.1 μm or more and 1.0 μm or less).

[0111] The first buried insulating layer 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first buried insulating layer 43 has a single-layer structure made of a silicon oxide film. The first buried insulating layer 43 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The first buried insulating layer 43 may have a multi-layer structure made of different insulating materials.

[0112] The semiconductor device 1 further includes a well region 50 formed in a portion of the drift region 8 surrounding the trench 31. In this embodiment, the well region 50 is formed around the bottom of the trench 31. The well region 50 may also be referred to as a "bottom well region," a "field relaxation region," or a "field relaxation layer."

[0113] The well region 50 covers the first buried insulating layer 43 at the bottom of the trench 31 from the outside of the trench 31. The well region 50 is exposed from the bottom surface 35 and the side surface 34 of the trench 31 and is in contact with the first buried insulating layer 43. Therefore, the upper end of the well region 50 is exposed at the bottom surface 35 and the side surface 34 of the gate structure 11 (trench 31).

[0114] The well region 50 is formed across the width of the trench 31, spanning between one end and the other end of the trench 31. The well region 50 extends from the bottom surface 35 of the trench 31 around to the side surfaces 34, and covers the first buried insulating layer 43 from at least two directions, below and to the sides. In this configuration, the well region 50 covers the first buried insulating layer 43 from three directions, the bottom surface 35 and both side surfaces 34 of the trench 31. The well region 50 is formed in a layer shape along the inner surface of the trench 31, from one side surface 34 of the trench 31 through the bottom surface 35 to the other side surface 34.

[0115] The well region 50 is disposed below (below in the depth direction of the trench 31, on the second main surface 4 side in this embodiment) and away from the interface 49 between the first buried insulating layer 43 and the second buried conductive layer 42. The well region 50 is physically separated from the second buried conductive layer 42. As a result, the first buried insulating layer 43 integrally includes, in the depth direction of the trench 31, a lower insulating portion 54 that is covered by the well region 50 and an upper insulating portion 55 that is not covered by the well region 50. The upper insulating portion 55 is located between the lower insulating portion 54 and the second buried conductive layer 42, and is in direct contact with the drift region 8 on the side surface 34 of the trench 31.

[0116] The well region 50 integrally includes a well side portion 56 and a well bottom portion 57. The well side portion 56 covers the insulating lower portion 54 from the side surface 34 of the trench 31. The well bottom portion 57 covers the insulating lower portion 54 from the bottom surface 35 of the trench 31. Referring to FIG. 9 , the thickness WT1 of the well bottom portion 57 is greater than the thickness WT2 of the well side portion 56.

[0117] 5, well region 50 is formed in the bottom of trench 31 over the entire depth direction of trench 31, and is formed in a strip shape extending in the depth direction of trench 31. With reference to Figures 7 and 8, in this embodiment, well region 50 has side surfaces 59 located outward in the depth direction of trench 31 relative to one side surface 34 and the other side surface 34 in the width direction of trench 31.

[0118] The well side portions 56 protrude outward from both side surfaces 34 of the trench 31, creating a step 58 between the side surface 34 of the trench 31 and a side surface 59 of the well region 50. Due to the presence of the step 58, the well region 50 includes an upper surface 60 facing the body region 30 with the drift region 8 interposed therebetween, and a lower surface 61 facing the second main surface 4 with the drift region 8 interposed therebetween. The well region 50 forms a pn junction (pn diode Di2) with the drift region 8 on at least three surfaces: the upper surface 60, the side surface 59, and the lower surface 61. The pn diode Di2 is electrically connected in parallel to the body diode BD and the diode Di via the drift region 8.

[0119] The p-type impurity concentration of the well region 50 may be the same as or higher than the p-type impurity concentration of the body region 30. The well region 50 has a p-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １９ cm －３ The p-type impurity concentration may be a peak value of 1×10 or less. １４ cm －３ 1x10 or more １７ cm －３ The p-type impurity concentration of the well region 50 may be at a peak value of the following. The p-type impurity concentration of the well region 50 is preferably higher than the p-type impurity concentration of the body region 30. Referring to FIG. 9 , the well region 50 has a well width WR that is larger than the trench width WT. The well width WR may be 0.25 μm or more and 7 μm or less.

[0120] 5 and 7 , semiconductor device 1 includes a source region 45 as an example of a third impurity region in a surface layer portion of first main surface 3 in mesa portion 36. Source region 45 is formed in a region between a plurality of gate structures 11. Source region 45 is formed in a surface layer portion of body region 30 in mesa portion 36.

[0121] In this embodiment, a plurality of source regions 45 are formed across the mesa portion 36 in the width direction, from one side surface 34 of the mesa portion 36 to the other side surface 34 (from one side surface 34 of the trench 31 to the other side surface 34). The plurality of source regions 45 are arranged at intervals in each mesa portion 36 along the depth direction of the trench 31. In each mesa portion 36, a plurality of channel sections 46 are arranged at intervals in the second direction Y (depth direction of the trench 31). In the channel sections 46, channels are formed on both side surfaces 34 of the trench 31 on both sides of the mesa portion 36 in the first direction X.

[0122] 7, a boundary surface 52 between the body region 30 and the source region 45 is located closer to the second main surface 4 than the upper surface 38 of the first buried conductive layer 33. The boundary surface 52 is formed at a position lower than the upper surface 38 of the first buried conductive layer 33, and a step 53 is formed between the upper surface 38 of the first buried conductive layer 33 and the boundary surface 52. A part of the source region 45 (for example, the lower end) faces the first buried conductive layer 33 via the trench insulating film 32. This ensures the formation of a channel between the source and the drain.

[0123] The source region 45 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0124] 5 and 8 , semiconductor device 1 includes a body contact region 47 in a surface layer portion of first main surface 3 in mesa portion 36. Body contact region 47 is formed in a region between multiple gate structures 11. Body contact region 47 is formed adjacent to source region 45 in a surface layer portion of body region 30 in the depth direction of mesa portion 36.

[0125] In this embodiment, a plurality of body contact regions 47 are formed across the mesa portion 36 in the width direction, from one side surface 34 of the mesa portion 36 to the other side surface 34. In each mesa portion 36, the plurality of source regions 45 and the plurality of body contact regions 47 are alternately arranged along the depth direction of the trench 31. Each source region 45 and each body contact region 47 is exposed from both side surfaces 34 of the trench 31 (both side surfaces 34 of the mesa portion 36).

[0126] The body contact region 47 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 30. The p-type impurity concentration (peak value) of the body contact region 47 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0127] The semiconductor device 1 includes a second buried insulating layer 62 buried in the recess 40 of the second semiconductor layer 7. The second buried insulating layer 62 is an insulating film that crosses the trench 31 at an upper portion in the depth direction of the trench 31. The second buried insulating layer 62 may also be referred to as an "upper insulating film," "upper insulating layer," "buried interlayer insulating layer," "interlayer insulating layer," etc. In this form, the second buried insulating layer 62 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0128] 7 and 8 , the second buried insulating layer 62 is buried in the recess 40 so that an upper edge 63 of the trench 31 is exposed from the first main surface 3. The upper edge 63 of the trench 31 may be a portion at the top of the trench 31 where the side surface 34 of the trench 31 intersects with the first main surface 3. In other words, the second buried insulating layer 62 does not cover the periphery of the trench 31 on the first main surface 3, but is contained within the inner region of the trench 31 in the width direction of the trench 31. In this embodiment, the upper surface 64 of the second buried insulating layer 62 is located closer to the bottom of the trench 31 than the first main surface 3 in the depth direction of the trench 31.

[0129] 5, the second buried insulating layer 62 is buried in the recess 40 over the entire depth direction of the trench 31, and is formed in a strip shape extending in the depth direction of the trench 31. With reference to FIGS. 7 and 8, the second buried insulating layer 62 contacts the source region 45 and the body contact region 47 on the side surface 34 of the recess 40 (the side surface 34 of the trench 31).

[0130] 9, the thickness UT of the second buried insulating layer 62 may be, for example, 0.05 μm or more and 0.8 μm or less. The thickness UT may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.3 μm or less, 0.3 μm or more and 0.55 μm or less, and 0.55 μm or more and 0.8 μm or less.

[0131] 7 and 8, semiconductor device 1 includes silicide layers 65 formed on the surfaces of source regions 45 and body contact regions 47. Formation of silicide layers 65 can reduce contact resistance with source regions 45 and body contact regions 47.

[0132] In this embodiment, the silicide layer 65 is selectively formed on the protruding portion 41 of each mesa portion 36. More specifically, the silicide layer 65 is formed along the upper surface (first main surface 3) and side surface 34 (side surface 34 of the recess 40) of the protruding portion 41 of the mesa portion 36. A non-silicide portion 66 defined by the silicide layer 65 (surrounded on three sides) may be formed in the inner portion of the protruding portion 41 of the mesa portion 36, away from the upper surface (first main surface 3) and side surface 34 of the mesa portion 36 inward.

[0133] The silicide layer 65 may be, for example, nickel silicide, titanium silicide, aluminum silicide, copper silicide, etc. The thickness ST of the silicide layer 65 may be, for example, 50 nm or more and 500 nm or less in the vertical direction Z from the upper surface (first main surface 3) and side surface 34 of the protruding portion 41 of the mesa portion 36. The thickness ST of the silicide layer 65 is preferably 80 nm or more and 300 nm or less.

[0134] 7 and 8 , semiconductor device 1 includes a first principal surface electrode 70. First principal surface electrode 70 is formed on first principal surface 3 so as to cover second buried insulating layer 62. First principal surface electrode 70 has a layered structure including a barrier layer 71 and a main body layer 72, which are layered in this order from the first principal surface 3 side.

[0135] The barrier layer 71 is formed in a film shape along the first main surface 3 and the inner surfaces of the recess 40 (the side surfaces 34 of the recess 40 and the upper surface 64 of the second buried insulating layer 62). The barrier layer 71 is in ohmic contact with the silicide layer 65. The barrier layer 71 further defines a second recess 73 within the recess 40.

[0136] The barrier layer 71 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 71 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 71 is preferably 0.1 μm or more and 0.2 μm or less.

[0137] The main body layer 72 is formed on the barrier layer 71. The main body layer 72 covers the entire main surface of the barrier layer 71. The main body layer 72 is partially embedded in the second recess 73. The main body layer 72 is ohmically connected to the source region 45 and the body contact region 47 via the barrier layer 71 and the silicide layer 65. In this embodiment, the first main surface electrode 70 is connected to the source region 45 and the body contact region 47 at the side surface 34 of the recess 40 and the first main surface 3. Therefore, in the semiconductor device 1, the first main surface electrode 70 may include the source pad electrode 20 described above.

[0138] The main body layer 72 includes at least one of a pure Al layer (meaning an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0139] The thickness of the main layer 72 exceeds the thickness of the barrier layer 71. The thickness of the main layer 72 may be 1 μm or more and 10 μm or less. The thickness of the main layer 72 is preferably 3 μm or more and 6 μm or less.

[0140] The semiconductor device 1 includes a resin layer 74 that covers the first principal surface electrode 70. The resin layer 74 is formed in a film shape along the principal surface of the first principal surface electrode 70. The resin layer 74 may include a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 74 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 74 includes polybenzoxazole.

[0141] (3) Detailed Structure of the Vicinity of the Peripheral Region 10 of the Semiconductor Device 1 FIG. 10 is a cross-sectional view taken along line XX in FIG. 6. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6. FIGS. 12 and 13 are cross-sectional views showing the peripheral region 10. FIG. 12 shows a cross-section obtained by cutting the trench 31 in the vertical direction, and FIG. 13 shows a cross-section obtained by cutting the mesa portion 36 in the vertical direction. Detailed structures of the peripheral region 10 and the vicinities of the peripheral region 10 of the active region 9 will be described below with reference to FIG. 6 and FIGS. 10 to 13.

[0142] 6 and 10 to 12, trench 31 extends across the boundary between active region 9 and peripheral region 10 to peripheral region 10. Well region 50 extends to the end of trench 31 in peripheral region 10.

[0143] In the peripheral region 10 , a connection insulating layer 67 and a connection conductive layer 68 are provided within the trench 31 .

[0144] The connection insulating layer 67 covers the side surface 34 and bottom surface 35 of the trench 31. The connection insulating layer 67 is formed integrally with the first buried insulating layer 43. The connection insulating layer 67 is continuous with the first buried insulating layer 43 and extends to the end of the trench 31. The connection insulating layer 67 is thicker than the trench insulating film 32. The thickness of the connection insulating layer 67 may be approximately equal to the thickness of the first buried insulating layer 43.

[0145] The connection insulating layer 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first buried insulating layer 43 has a single-layer structure made of a silicon oxide film. The first buried insulating layer 43 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The connection insulating layer 67 may have a multi-layer structure made of different insulating materials.

[0146] The connection conductive layer 68 is buried in the trench 31 with the connection insulating layer 67 sandwiched therebetween, and faces the drift region 8 and the outer well region 13 with the connection insulating layer 67 sandwiched therebetween. The connection conductive layer 68 is electrically insulated from the drift region 8 and the outer well region 13 by the connection insulating layer 67. The connection conductive layer 68 is formed integrally with the second buried conductive layer 42, and is electrically insulated from the first buried conductive layer 33 by the isolation insulating film 44. The connection conductive layer 68 is formed as an extension portion where the second buried conductive layer 42 is extended to the peripheral region 10.

[0147] Connection conductive layer 68 crosses gate finger electrode 25 and source finger electrode 27, and has an end portion outside source finger electrode 27. With reference to Figures 6 and 10, connection conductive layer 68 has width EW3 that is smaller than width EW1 of first buried conductive layer 33 and width EW2 of second buried conductive layer 42 (both of which are shown in Figure 9).

[0148] The connection conductive layer 68 may be formed of the same material as the second buried conductive layer 42. For example, the connection conductive layer 68 may include a Schottky metal made of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, a Ni layer, or a silicide thereof, or a heteroelectrode made of polysilicon.

[0149] 10 and 13 , the aforementioned outer well region 13 is formed in the surface layer portion of the first main surface 3 in the peripheral region 10 (the peripheral portion of the first main surface 3). A source potential is applied to the outer well region 13. The outer well region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the body region 30.

[0150] The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the body contact region 47. The p-type impurity concentration of the outer well region 13 may be higher or lower than that of the well region 50.

[0151] The outer well region 13 is formed in a surface layer portion of the second semiconductor layer 7. The outer well region 13 extends in a layered manner along the first main surface 3. The outer well region 13 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the plurality of gate structures 11. The outer well region 13 extends in a strip shape along the periphery (periphery of the active region 9) of the first main surface 3 in a plan view.

[0152] In this embodiment, the outer well region 13 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. In other words, the outer well region 13 collectively surrounds the plurality of gate structures 11.

[0153] The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 13 has an inner edge portion on the side of the multiple gate structures 11 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 13 defines the boundary between the active region 9 and the outer periphery region 10.

[0154] The outer well region 13 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 13 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0155] In this embodiment, the outer well region 13 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 11. The depth of the outer well region 13 may be greater or smaller than the depth of the body region 30.

[0156] The outer well region 13 forms a pn junction with the second semiconductor layer 7 (drift region 8). The outer well region 13 spreads a depletion layer in the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 13 spreads horizontally and in the thickness direction, and integrates with the depletion layers spreading from the body region 30 and the well region 50. The outer well region 13 expands the depletion layers spreading from the body region 30 and the well region 50 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (outer peripheral region 10) of the first main surface 3.

[0157] 10, well region 50 extends along both side surfaces 34 of trench 31 toward first main surface 3, and is connected to outer well region 13. As a result, a source potential is applied to well region 50.

[0158] The semiconductor device 1 includes a p-type outer contact region 69 formed in a surface layer portion of the outer well region 13. The outer contact region 69 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 13. The p-type impurity concentration of the outer contact region 69 is higher than the p-type impurity concentration of the body region 30. The p-type impurity concentration of the outer contact region 69 may be approximately equal to the p-type impurity concentration of the body contact region 47. The p-type impurity concentration of the outer contact region 69 may be higher or lower than the p-type impurity concentration of the body contact region 47.

[0159] The outer contact region 69 is formed at a distance from the bottom of the outer well region 13 toward the first main surface 3, and faces the second semiconductor layer 7 across a part of the outer well region 13. The outer contact region 69 extends in a strip shape along the outer well region 13 (active region 9) in a plan view.

[0160] In this embodiment, the outer contact region 69 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 69 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0161] The semiconductor device 1 may include a plurality of outer contact regions 69 arranged at intervals along the extension direction of the outer well region 13 so as to surround the plurality of gate structures 11. In this case, the plurality of outer contact regions 69 may each extend in a strip shape along the extension direction of the outer well region 13.

[0162] 11 to 13 , the surface insulating film 15 described above covers the peripheries of the ends of the plurality of gate structures 11 and the connection conductive layer 68 in the peripheral region 10. The surface insulating film 15 directly covers the first main surface 3 around the plurality of gate structures 11. The surface insulating film 15 selectively covers the region of the first main surface 3 on the peripheral side of the plurality of gate structures 11 in a film-like manner.

[0163] The surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14. The surface insulating film 15 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The surface insulating film 15 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 11 (active regions 9) in plan view.

[0164] The surface insulating film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0165] The semiconductor device 1 includes a main surface insulating film 76 formed on the first main surface 3. The main surface insulating film 76 extends from the peripheral region 10 toward the active region 9 to the gate structure 11, and is formed integrally with the trench insulating film 32 and the isolation insulating film 44. The main surface insulating film 76 may be a drawn-out portion of the trench insulating film 32 drawn out from the gate structure 11 toward the peripheral region 10.

[0166] The main surface insulating film 76 covers the first main surface 3, the surface insulating film 15, and the connection conductive layer 68 exposed between the gate structure 11 and the surface insulating film 15. The main surface insulating film 76 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 76 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D.

[0167] The main surface insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0168] The aforementioned gate wiring 17 is disposed on the main surface insulating film 76 and the surface insulating film 15. The gate wiring 17 is selectively routed on the main surface insulating film 76 and the surface insulating film 15 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 11, and faces the outer well region 13 and the connection conductive layer 68 with the main surface insulating film 76 and the surface insulating film 15 interposed therebetween.

[0169] The gate wiring 17 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 17 is disposed on the main surface insulating film 76 and faces the outer well region 13 and the connection conductive layer 68 with the main surface insulating film 76 in between. The inner edge portion of the gate wiring 17 covers the ends (both ends in this embodiment) of the multiple gate structures 11 and is mechanically and electrically connected to the multiple gate structures 11.

[0170] Specifically, the inner edge of the gate wiring 17 is mechanically and electrically connected to the plurality of first buried conductive layers 33. In this embodiment, the inner edge of the gate wiring 17 is integrally formed with the plurality of first buried conductive layers 33. In other words, the gate wiring 17 is formed as an extension of the plurality of first buried conductive layers 33, and is drawn out from the trench 31 onto the main surface insulating film 76.

[0171] The outer edge of the gate wiring 17 is formed as an extension portion that is extended from above the main surface insulating film 76 onto the laminated structure of the main surface insulating film 76 and the surface insulating film 15, and is disposed on this laminated structure. The outer edge of the gate wiring 17 faces the outer well region 13 and the connection conductive layer 68, with the main surface insulating film 76 and the surface insulating film 15 sandwiched between them.

[0172] The outer edge of the gate wiring 17 is formed at a distance from the plurality of field regions 14 toward the plurality of gate structures 11. Specifically, the outer edge of the gate wiring 17 is formed at a distance from the outer edge of the outer well region 13 toward the plurality of gate structures 11. The outer edge of the gate wiring 17 is formed at a distance from the inner edge of the outer contact region 69 toward the plurality of gate structures 11.

[0173] The semiconductor device 1 may include a plurality of gate wirings 17. In this case, the plurality of gate wirings 17 may be arranged at least at both ends of the plurality of gate structures 11. One of the gate wirings 17 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) one end of the plurality of gate structures 11. The other of the gate wirings 17 may have a portion extending in a strip shape in the first direction X and intersect (specifically, perpendicular to) the other end of the plurality of gate structures 11. Of course, the plurality of gate wirings 17 may have a portion extending in the second direction Y.

[0174] The interlayer insulating layer 16 described above coats the main surface insulating film 76 in a film-like manner in the peripheral region 10. Specifically, the interlayer insulating layer 16 directly coats the main surface insulating film 76 in a film-like manner, and faces the outer well region 13, the outer contact region 69, and the plurality of field regions 14 with the main surface insulating film 76 interposed therebetween.

[0175] The interlayer insulating layer 16 covers the gate wiring 17 and the gate pad wiring 18. The interlayer insulating layer 16 covers the entire gate wiring 17 and the entire gate pad wiring 18. The interlayer insulating layer 16 has a portion facing the main surface insulating film 76 with the gate wiring 17 interposed therebetween, and a portion facing the main surface insulating film 76 with the gate wiring 17 interposed therebetween. The interlayer insulating layer 16 has a portion facing the outer well region 13 with the gate wiring 17 interposed therebetween, and a portion facing the outer well region 13 with the gate pad wiring 18 interposed therebetween.

[0176] The interlayer insulating layer 16 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer insulating layer 16 is disposed in the active region 9. The inner edge portion of the interlayer insulating layer 16 is positioned on the inner side of the first main surface 3 with respect to the inner edge portion of the gate wiring 17 and the peripheral edge portion of the gate pad wiring 18, and covers the ends of the multiple gate structures 11.

[0177] The inner edge of the interlayer insulating layer 16 covers the first buried conductive layer 33 at the ends of the multiple gate structures 11 and is connected to the second buried insulating layer 62. In this embodiment, the interlayer insulating layer 16 is formed integrally with the second buried insulating layer 62. The portion of the interlayer insulating layer 16 located within the trench 31 is formed as the second buried insulating layer 62. The connection portion of the interlayer insulating layer 16 to the second buried insulating layer 62 may be considered to be part of the second buried insulating layer 62 or may be considered to be part of the interlayer insulating layer 16.

[0178] The inner edge of the interlayer insulating layer 16 has a portion located in a region between the plurality of gate structures 11. The inner edge of the interlayer insulating layer 16 covers either or both of the body region 30 and the outer well region 13 in the region between the plurality of gate structures 11, with the surface insulating film 15 sandwiched therebetween.

[0179] The outer edge of the interlayer insulating layer 16 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer insulating layer 16 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 15.

[0180] The semiconductor device 1 includes one or more (one in this embodiment) source openings 19 formed in the interlayer insulating layer 16. The source opening 19 penetrates the interlayer insulating layer 16 in the inner portion of the active region 9, collectively exposing the plurality of gate structures 11 and the plurality of mesa portions 36. In this embodiment, the source opening 19 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion recessed along the gate pad wiring 18).

[0181] The source openings 19 are formed at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 11 toward the inner portion of the first main surface 3, and expose the inner portions of the plurality of gate structures 11 and the inner portions of the plurality of mesa portions 36. Specifically, the source openings 19 expose the trench insulating film 32 and the second buried insulating layer 62 in the inner portions of the plurality of gate structures 11.

[0182] The above-described gate finger electrode 25 may be a part of the first main surface electrode 70. Like the source pad electrode 20, the gate finger electrode 25 has a laminated structure including a barrier layer 71 and a main body layer 72 laminated in this order from the first main surface 3 side.

[0183] The gate finger electrodes 25 extend into the plurality of gate openings 77 from above the interlayer insulating layer 16, and are mechanically and electrically connected to the gate wiring 17 within the plurality of gate openings 77. As a result, the gate potential applied to the gate pad electrode 24 is applied to the plurality of gate structures 11 via the gate finger electrodes 25. More specifically, the gate finger electrodes 25 are mechanically and electrically connected to the gate wiring 17 through the gate openings 77.

[0184] The plurality of gate openings 77 penetrate the interlayer insulating layer 16 and selectively expose the gate wiring 17. In this embodiment, the plurality of gate openings 77 extend in a strip shape following the direction in which the gate wiring 17 extends.

[0185] The plurality of gate openings 77 may be formed at intervals along the extension direction of the gate wiring 17. The plurality of gate openings 77 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 11 may be formed in a quadrangular or hexagonal shape in a plan view.

[0186] The plurality of gate openings 77 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 77 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0187] Gate finger electrode 25 has an inner edge portion on the inward side of first main surface 3 and an outer edge portion on the peripheral side of first main surface 3. The inner edge portion of gate finger electrode 25 is formed at a distance from the ends of the multiple gate structures 11 toward the peripheral side of first main surface 3. In other words, gate finger electrode 25 does not face the multiple gate structures 11 in the stacking direction.

[0188] The inner edge of the gate finger electrode 25 is disposed on the gate wiring 17. The inner edge of the gate finger electrode 25 faces the peripheral edge of the source pad electrode 20 in the horizontal direction above the gate wiring 17. The inner edge of the gate finger electrode 25 is formed at a distance from the middle of the gate wiring 17 towards the peripheral edge of the first main surface 3.

[0189] The outer edge of the gate finger electrode 25 is drawn out from above the gate wiring 17 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer insulating layer 16 in a region outside the gate wiring 17. In other words, the outer edge of the gate finger electrode 25 does not face the gate wiring 17 in the stacking direction. The outer edge of the gate finger electrode 25 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0190] The outer edge of the gate finger electrode 25 is disposed at a distance from the outer edge of the outer well region 13 toward the inside of the first main surface 3, and faces the outer well region 13 across the surface insulating film 15 and the interlayer insulating layer 16. The outer edge of the gate finger electrode 25 is disposed on the peripheral side of the first main surface 3 relative to the outer edge of the outer well region 13, and may face the second semiconductor layer 7 in the stacking direction.

[0191] The above-described source finger electrodes 27 may be part of the first principal surface electrode 70. Like the source pad electrode 20, the source finger electrodes 27 have a laminated structure including a barrier layer 71 and a main body layer 72 laminated in this order from the first principal surface 3 side.

[0192] Source finger electrodes 27 extend into the plurality of outer openings 80 from above interlayer insulating layer 16, and are mechanically and electrically connected to outer contact regions 69 and connection conductive layers 68 within the plurality of outer openings 80. As a result, a source potential applied to source pad electrode 20 is applied to the plurality of source regions 45, body contact regions 47, second buried conductive layer 42, and well region 50 via source finger electrodes 27.

[0193] The outer opening 80 is formed at a distance from the gate wiring 17 toward the peripheral edge of the first main surface 3. The outer opening 80 penetrates the surface insulating film 15 and the interlayer insulating layer 16 to expose the outer contact region 69 and the connection conductive layer 68.

[0194] The outer opening 80 has a width less than the width of the outer contact region 69 and is spaced apart from the inner and outer edges of the outer contact region 69 to expose an inner portion of the outer contact region 69. The outer opening 80 may expose the outer well region 13.

[0195] In this embodiment, the outer opening 80 extends in a strip shape following the extension direction of the outer contact region 69. In this embodiment, the outer opening 80 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 69 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0196] The semiconductor device 1 may have a plurality of outer openings 80. In this case, the plurality of outer openings 80 may be formed at intervals following the extension direction of the outer contact region 69. Furthermore, the plurality of outer openings 80 may each extend in a strip shape following the extension direction of the outer contact region 69.

[0197] Source finger electrodes 27 have inner edge portions on the inner side of first main surface 3 and outer edge portions on the peripheral side of first main surface 3. The inner edge portions of source finger electrodes 27 are arranged at a distance from gate finger electrodes 25 on the peripheral side of first main surface 3, and face gate finger electrodes 25 in the horizontal direction.

[0198] The inner edge of each source finger electrode 27 is formed at a distance from the middle of the outer contact region 69 toward the inside of the first main surface 3. The inner edge of each source finger electrode 27 may be disposed on either the outer well region 13 or the outer contact region 69.

[0199] The outer edge portions of source finger electrodes 27 are drawn out from above outer contact region 69 toward the peripheral edge of first main surface 3, and are arranged on interlayer insulating layer 16 in a region outside outer contact region 69. The outer edge portions of source finger electrodes 27 are arranged at a distance from innermost field region 14 toward the inward side of first main surface 3.

[0200] The outer edge of source finger electrode 27 is disposed at a distance from the outer edge of outer well region 13 toward the inside of first main surface 3, and faces outer well region 13 across interlayer insulating layer 16. The outer edge of source finger electrode 27 may be drawn out from the outer edge of outer well region 13 to the peripheral edge of first main surface 3, and faces second semiconductor layer 7 across interlayer insulating layer 16.

[0201] (4) Effects of the Semiconductor Device 1 The semiconductor device 1 is used, for example, as a switching element. In this case, the current flowing through the load is turned on and off by turning the gate voltage on and off while a voltage that makes the drift region 8 side positive is applied between the source region 45 and the drift region 8. When the load is inductive, blocking the current flowing through the load (i.e., turning the gate voltage off) generates a back electromotive force in the load. Due to this back electromotive force, a voltage that makes the source region 45 side positive may be applied between the source region 45 and the drift region 8.

[0202] In such a case, if the rectification of the body diode BD causes a current to flow to the load as, for example, a reflux current, the following problems occur.

[0203] For example, when holes move from the body region 30 constituting the body diode BD to the drift region 8 and cause a current to flow, electrons of the majority carriers may recombine with the holes that have moved from the body region 30 near the trench 31 in the drift region 8 (for example, on the side of the trench 31). Therefore, the energy generated by this recombination may cause crystal defects in the SiC of the second semiconductor layer 7 (drift region 8) to expand in a direction parallel to the stacking direction of the second semiconductor layer 7, potentially reaching the path of the drain current (for example, the channel) when the semiconductor device 1 is on. This may result in an increase in on-resistance when the semiconductor device 1 forms a channel in the channel region 37 and performs a switching operation.

[0204] In such a case, current flows preferentially through the diode Di, and the current flowing through the body diode BD can be reduced or eliminated. Thus, the current flowing through the semiconductor device 1 can be passed to a load as, for example, a return current. Since the current during the off-state flows directly to the drift region 8 of the mesa portion 36, almost no carrier movement occurs between the body region 30 and the drift region 8. This prevents the recombination of holes and electrons within the drift region 8. As a result, the expansion of crystal defects in SiC in the second semiconductor layer 7 can be suppressed, thereby suppressing an increase in the on-resistance of the transistor Tr.

[0205] 7, in the semiconductor device 1, the diode structure 12 is embedded in the gate structure 11 that constitutes the MIS transistor structure Tr. The bottom of the gate structure 11 can be effectively utilized as a space for the diode Di. Since it is not necessary to provide a space for the diode Di at a position laterally spaced apart from the gate structure 11 along the first main surface 3, most of the active region 9 can be used for the MIS transistor structure Tr.

[0206] In the semiconductor device 1, the first buried insulating layer 43 is disposed at the bottom of the trench 31 and prevents contact between the second buried conductive layer 42 and the bottom surface 35. The second buried conductive layer 42 has a junction interface 48 that forms a Schottky junction or a heterojunction with the drift region 8 at the bottom surface 35 and both side surfaces 34 of the trench 31. In this configuration, the bottom surface 35 is a polar surface (c-plane), and the side surfaces 34 are nonpolar surfaces (m-plane or a-plane). The sizes of the Schottky barrier and the heterojunction barrier vary depending on the SiC plane orientation. Therefore, by limiting the junction interface 48 of the second buried conductive layer 42 to both side surfaces 34, the Schottky barrier and the heterojunction barrier of the diode Di can be maintained constant. Furthermore, since the first buried insulating layer 43 is disposed at the bottom of the trench 31, the breakdown voltage at the bottom of the trench 31 can be improved.

[0207] According to the semiconductor device 1, a p-type well region 50 is formed around the bottom of the trench 31. The well region 50 can reduce the electric field around the bottom of the trench 31. Furthermore, a first buried insulating layer 43 is interposed between the well region 50 and the second buried conductive layer 42. Even if a depletion layer expands from the interface between the well region 50 and the drift region 8 into the well region 50, the first buried insulating layer 43 can prevent the depletion layer from contacting the second buried conductive layer 42 and causing a leakage current to flow. Therefore, the impurity concentration of the well region 50 can be designed low, prioritizing improvement in breakdown voltage over the extent of the expansion of the depletion layer.

[0208] Modifications applied to the semiconductor device 1 will be described below.

[0209] (5) First Modification Fig. 14 is a plan view of the active region 9 and the peripheral region 10 of a first modification of the semiconductor device 1. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 14. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 14. Fig. 17 is a cross-sectional view taken along line XVII-XVII in Fig. 14. Fig. 18 is a cross-sectional view showing the peripheral region 10 of the first modification of the semiconductor device 1.

[0210] 15 , 17 and 18 , trench 31 has an end at the boundary between active region 9 and peripheral region 10. The end in the depth direction of trench 31 is located inside the peripheral edge of source pad electrode 20. The end in the depth direction of trench 31 is located inside gate finger electrode 25.

[0211] 15 to 18, the first buried insulating layer 43 is omitted in the diode structure 12. The second buried conductive layer 42 is in direct contact with the bottom surface 35, one side surface 34, and the other side surface 34 of the trench 31.

[0212] The semiconductor device 1 further includes an isolation well region 81 formed in a portion of the drift region 8 surrounding the trench 31. In this embodiment, the isolation well region 81 is formed around the bottom of the trench 31. The isolation well region 81 may also be referred to as a "bottom well region," a "field relaxation region," or a "field relaxation layer."

[0213] The isolation well region 81 covers the second buried conductive layer 42 from the outside of the trench 31 at the bottom of the trench 31. The isolation well region 81 is exposed from the bottom surface 35 and the side surface 34 of the trench 31 and is in contact with the second buried conductive layer 42. Therefore, the upper end of the isolation well region 81 is exposed at the bottom surface 35 and the side surface 34 of the gate structure 11 (trench 31).

[0214] The isolation well region 81 is formed across one end and the other end of the trench 31 in the width direction of the trench 31. The isolation well region 81 wraps around from the bottom surface 35 to the side surface 34 of the trench 31, and covers the second buried conductive layer 42 from at least two directions, below and to the sides. In this embodiment, the isolation well region 81 covers the second buried conductive layer 42 from three directions, the bottom surface 35 and both side surfaces 34 of the trench 31. The isolation well region 81 is formed in a layer shape along the inner surface of the trench 31, from one side surface 34 of the trench 31 via the bottom surface 35 to the other side surface 34.

[0215] The isolation well region 81 is disposed below the trench insulating film 32 (below in the depth direction of the trench 31, on the second main surface 4 side in this embodiment). The isolation well region 81 is physically separated from the trench insulating film 32. As a result, the second buried conductive layer 42 integrally includes, in the depth direction of the trench 31, a lower electrode portion 82 covered by the isolation well region 81 and an upper electrode portion 83 not covered by the isolation well region 81. The upper electrode portion 83 is located between the lower electrode portion 82 and the trench insulating film 32, and is in direct contact with the drift region 8 on the side surface 34 of the trench 31.

[0216] The isolation well region 81 integrally includes an isolation well side portion 84 and an isolation well bottom portion 85. The isolation well side portion 84 covers the electrode lower portion 82 from the side surface 34 of the trench 31. The isolation well bottom portion 85 covers the electrode lower portion 82 from the bottom surface 35 of the trench 31. A thickness WT3 of the isolation well bottom portion 85 is greater than a thickness WT4 of the isolation well side portion 84.

[0217] 17 and 18, isolation well region 81 is formed at the bottom of trench 31 over the entire depth of trench 31, and is formed in a strip shape extending in the depth direction of trench 31.

[0218] Semiconductor device 1 includes well contact regions 86 formed at the ends of isolation well regions 81 in the depth direction of trench 31. Well contact regions 86 connect outer well region 13 and isolation well region 81. As a result, a source potential applied to source pad electrode 20 is applied to second buried conductive layer 42 via source finger electrodes 27, outer contact regions 69, outer well region 13, well contact regions 86, and isolation well region 81.

[0219] 15 and 16, in this embodiment, the isolation well region 81 has a side surface 87 located outside one side surface 34 and the other side surface 34 in the width direction of the trench 31 in the depth direction of the trench 31.

[0220] Because the isolation well side portions 84 protrude outward from both side surfaces 34 of the trench 31, a step 90 is formed between the side surface 34 of the trench 31 and a side surface 87 of the isolation well region 81. Due to the step 90, the isolation well region 81 includes an upper surface 88 facing the body region 30 with the drift region 8 interposed therebetween, and a lower surface 89 facing the second main surface 4 with the drift region 8 interposed therebetween. The isolation well region 81 forms a pn junction (pn diode Di2) with the drift region 8 on at least three surfaces: the upper surface 88, the side surface 87, and the lower surface 89. The pn diode Di2 is electrically connected in parallel to the body diode BD and the diode Di via the drift region 8.

[0221] The p-type impurity concentration of the isolation well region 81 may be the same as or higher than the p-type impurity concentration of the body region 30. The isolation well region 81 has a p-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may be a peak value of 1×10 or less. １６ cm－３ 1x10 or more １９ cm －３ The p-type impurity concentration of the isolation well region 81 may have the following peak value: The p-type impurity concentration of the isolation well region 81 is preferably higher than the p-type impurity concentration of the body region 30. The width of the isolation well region 81 may be approximately equal to the well width WR of the well region 50 described above.

[0222] In this embodiment, the isolation well region 81 is formed around the bottom of the trench 31 and prevents the second buried conductive layer 42 from contacting the drift region 8 at the bottom surface 35. The second buried conductive layer 42 has a junction interface 48 that forms a Schottky junction or a heterojunction with the drift region 8 at both of the bottom surface 35 and both side surfaces 34 of the trench 31. By limiting the junction interface 48 of the second buried conductive layer 42 to both side surfaces 34, the Schottky barrier and heterojunction barrier of the diode Di can be kept constant. In addition, the isolation well region 81 can reduce the electric field around the bottom of the trench 31.

[0223] (6) Second Modification FIG. 19 is a cross-sectional view of a second modification of the semiconductor device 1. Referring to FIG. 19, the well region 50 is exposed from the bottom surface 35 of the trench 31 and is in contact with the first buried insulating layer 43. The well region 50 does not protrude outward from both side surfaces 34 of the trench 31. In the depth direction of the trench 31, the well region 50 has one side surface 59 formed on substantially the same plane as one side surface 34 of the trench 31 in the width direction, and the other side surface 59 formed on substantially the same plane as the other side surface 34 of the trench 31 in the width direction. The first buried insulating layer 43 is in contact with the side surface 34 of the trench 31 over the entire thickness direction.

[0224] 20 is a cross-sectional view of a third modification of the semiconductor device 1. Referring to FIG. 20, the well region 50 is omitted at the bottom of the trench 31. The first buried insulating layer 43 contacts the side surface 34 and the bottom surface 35 of the trench 31 except for the interface 49.

[0225] 21 is a cross-sectional view of a fourth modification of the semiconductor device 1. The isolation well region 81 is exposed from the bottom surface 35 of the bottom surface 35 and the side surfaces 34 of the trench 31, and is in contact with the second buried conductive layer 42. The isolation well region 81 does not protrude outward from both side surfaces 34 of the trench 31. In the depth direction of the trench 31, the isolation well region 81 has one side surface 87 formed on approximately the same plane as one side surface 34 of the trench 31 in the width direction, and the other side surface 87 formed on approximately the same plane as the other side surface 34 of the trench 31 in the width direction.

[0226] 22 is a cross-sectional view of a fifth modification of the semiconductor device 1. Referring to FIG. 22, the diode structure 12 includes a sidewall insulating layer 91 as an example of an isolation layer. The sidewall insulating layer 91 is interposed between the second buried conductive layer 42 and the side surface 34 of the trench 31. The sidewall insulating layer 91 prevents contact between the second buried conductive layer 42 and the side surface 34 and electrically isolates the second buried conductive layer 42 from the side surface 34.

[0227] The sidewall insulating layer 91 extends integrally from the trench insulating film 32 along both side surfaces 34 of the trench 31, and covers the drift region 8 exposed from both side surfaces 34 of the trench 31. The sidewall insulating layer 91 is formed from the trench insulating film 32 to the bottom surface 35 of the trench 31. In this embodiment, the entire bottom surface 35 of the trench 31 is not covered with the sidewall insulating layer 91, and part of the drift region 8 is exposed from the bottom surface 35.

[0228] The thickness of the sidewall insulating layer 91 may be approximately equal to the thickness of the trench insulating film 32. The thickness of the sidewall insulating layer 91 may be smaller or larger than the thickness of the trench insulating film 32. The sidewall insulating layer 91 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the sidewall insulating layer 91 has a single-layer structure made of a silicon oxide film. The sidewall insulating layer 91 may also include a silicon oxide film made of an oxide of the chip 2. The sidewall insulating layer 91 may have a multi-layer structure made of different insulating materials.

[0229] The second buried conductive layer 42 is buried in the bottom of the trench 31 surrounded by the sidewall insulating layer 91. The second buried conductive layer 42 has a junction interface 92 that forms a Schottky junction or a heterojunction with the drift region 8 at the bottom surface 35 of the trench 31, among the bottom surface 35 and both side surfaces 34. According to this embodiment, by limiting the junction interface 92 of the second buried conductive layer 42 to the bottom surface 35, no Schottky barrier or heterojunction barrier is formed at the side surface 34 of the trench 31. This makes it possible to maintain constant Schottky barriers and heterojunction barriers of the diode Di.

[0230] 23 is a cross-sectional view of a sixth modification of the semiconductor device 1. Referring to FIG. 23, the first buried insulating layer 43 is omitted from the diode structure 12. The semiconductor device 1 further includes an isolation well region 93 formed in a portion of the drift region 8 around the trench 31.

[0231] In this embodiment, the isolation well region 93 is formed around the bottom of the trench 31. The isolation well region 93 may also be referred to as a "bottom well region," "electric field relaxation region," or "electric field relaxation layer." The isolation well region 93 covers the second buried conductive layer 42 at the bottom of the trench 31 from the outside of the trench 31. In this embodiment, the isolation well region 93 covers one of the side surfaces 34 and the other side surface 34 of the trench 31 and the entire bottom surface 35 of the trench 31 from the outside of the trench 31. The isolation well region 93 is exposed from the bottom surface 35 and the side surface 34 of the trench 31 and is in contact with the second buried conductive layer 42.

[0232] The isolation well region 93 is formed across one end and the other end of the trench 31 in the width direction of the trench 31. The isolation well region 93 wraps around from the bottom surface 35 to one side surface 34 of the trench 31, and covers the second buried conductive layer 42 from two directions, below and on one side. The isolation well region 93 is formed in a layer shape along the inner surface of the trench 31 from one side surface 34 to the bottom surface 35 of the trench 31. The isolation well region 93 extends from the bottom of the trench 31 along one side surface 34 of the trench 31, and is connected to the body region 30 at one side surface 34 of the trench 31.

[0233] The isolation well region 93 forms a pn junction (pn diode Di2) between itself and the drift region 8. The pn diode Di2 is electrically connected in parallel to the body diode BD and the diode Di via the drift region 8.

[0234] No isolation well region 93 is formed on the other side surface 34 of the trench 31. At the portion of the other side surface 34 of the trench 31 where the second buried conductive layer 42 contacts, the drift region 8 is exposed over the entire thickness direction of the second buried conductive layer 42. In this configuration, the second buried conductive layer 42 has a side surface on one width direction that forms a junction interface 94 with the isolation well region 93, and a side surface on the other width direction that forms a junction interface 95 (diode Di) with the drift region 8. The junction interface 94 and the junction interface 95 extend parallel to each other in the depth direction of the trench 31.

[0235] According to this embodiment, the junction interface 95 of the diode Di of the second buried conductive layer 42 is limited to the other side surface 34, so that a Schottky barrier and a heterojunction barrier are not formed on one side surface 34 and the bottom surface 35 of the trench 31. This makes it possible to keep the Schottky barrier and the heterojunction barrier of the diode Di constant.

[0236] 24 is a cross-sectional view of a seventh modification of the semiconductor device 1. Referring to FIG. 24, the first buried insulating layer 43 is omitted from the diode structure 12. The second buried conductive layer 42 forms a Schottky junction or a heterojunction with the drift region 8 over the entire portion thereof contacting both side surfaces 34 and the bottom surface 35 of the trench 31.

[0237] According to this embodiment, the junction interface 96 (diode Di) is formed on the entire contact surface between the second buried conductive layer 42 and the inner surface of the trench 31, so that current can be efficiently passed through the diode Di.

[0238] 25 is a cross-sectional view of an eighth modification of the semiconductor device 1. Referring to FIG. 25, the first buried insulating layer 43 is omitted from the diode structure 12. The semiconductor device 1 further includes a well region 97 formed in a portion of the drift region 8 surrounding the trench 31.

[0239] In this embodiment, the well region 97 is formed around the bottom of the trench 31. The well region 97 may also be referred to as a "bottom well region," "electric field relaxation region," or "electric field relaxation layer." The well region 97 covers the second buried conductive layer 42 at the bottom of the trench 31 from the outside of the trench 31. In this embodiment, the well region 97 covers the entire one of the side surfaces 34 and the other side surface 34 of the trench 31 and a portion of the bottom surface 35 of the trench 31 from the outside of the trench 31. The well region 97 is exposed from the bottom surface 35 and the side surface 34 of the trench 31 and is in contact with the second buried conductive layer 42.

[0240] The well region 97 is formed across one end and the other end of the trench 31 in the width direction of the trench 31. The well region 97 wraps around from the bottom surface 35 to one side surface 34 of the trench 31 and covers the second buried conductive layer 42 from two directions, below and to one side. The well region 97 is formed in a layer shape along the inner surface of the trench 31 from one side surface 34 to the bottom surface 35 of the trench 31. The well region 97 extends from the bottom of the trench 31 along one side surface 34 of the trench 31 and is connected to the body region 30 at one side surface 34 of the trench 31.

[0241] The well region 97 forms a pn junction (pn diode Di2) between itself and the drift region 8. The pn diode Di2 is electrically connected in parallel to the body diode BD and the diode Di via the drift region 8.

[0242] The well region 97 is not formed on the other side surface 34 and part of the bottom surface 35 of the trench 31. The drift region 8 is exposed in the portions of the other side surface 34 and part of the bottom surface 35 of the trench 31 where the second buried conductive layer 42 contacts. In this configuration, the second buried conductive layer 42 has a junction interface 98 with the well region 97 on one side in the width direction, and a junction interface 99 (diode Di) with the drift region 8 on the other side in the width direction. Furthermore, the bottom surface of the second buried conductive layer 42 forms a junction interface 100 (diode Di) with the drift region 8. The junction interface 99 and the junction interface 100 intersect at right angles at the bottom of the trench 31.

[0243] According to this embodiment, a junction interface 99 is formed on the side surface 34 of the trench 31, and a junction interface 100 (diode Di) is formed on the bottom surface 35, so that current can be efficiently passed through the diode Di.

[0244] 26 is a cross-sectional view of a ninth modification of the semiconductor device 1. Referring to FIG. 26, the semiconductor device 1 further includes a second trench 101, a second isolation insulating film 102, and a third buried conductive layer 103.

[0245] The second trenches 101 are disposed between adjacent trenches 31. In this embodiment, a plurality of trenches 31 and a plurality of second trenches 101 are alternately arranged at intervals. A mesa portion 36 is defined between the trenches 31 and the second trenches 101. Each second trench 101 has a strip shape extending parallel to the trenches 31 along the second direction Y.

[0246] The second trench 101 penetrates the source region 45 and the body region 30 and has a bottom within the drift region 8. The trench width WT2 of the second trench 101 may be approximately equal to the trench width WT of the trench 31. The trench depth DT2 of the second trench 101 may be approximately equal to the trench depth DT2 of the trench 31.

[0247] The second isolation insulating film 102 covers the inner surface of the second trench 101. The second isolation insulating film 102 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second isolation insulating film 102 has a single-layer structure made of a silicon oxide film. The second isolation insulating film 102 may include a silicon oxide film made of an oxide of the chip 2. The second isolation insulating film 102 may have a multi-layer structure made of different insulating materials.

[0248] The third buried conductive layer 103 is buried in the second trench 101 and faces the body region 30 with the second isolation insulating film 102 sandwiched therebetween. The third buried conductive layer 103 may include p-type or n-type conductive polysilicon. The third buried conductive layer 103 is buried up to the middle of the trench 31 in the depth direction. In this embodiment, the third buried conductive layer 103 is buried up to the upper part of the trench 31 in the depth direction and also faces the source region 45 with the second isolation insulating film 102 sandwiched therebetween.

[0249] The third buried conductive layer 103 has an upper surface 104 located closer to the second main surface 4 than the first main surface 3. The upper surface 104 may be located at the same depth as the upper surface 38 of the first buried conductive layer 33, or may be located closer to the first main surface 3 than the upper surface 38 (closer to the opening end of the second trench 101). The upper surface 104 may be located at the same depth as the upper surface 64 of the second buried insulating layer 62, or may be located closer to the first main surface 3 than the upper surface 64. In this embodiment, the upper surface 104 is closer to the first main surface 3 than the upper surface 38 and is located at the same depth as the upper surface 64.

[0250] A low step 105 is formed on the second main surface 4 side between the top surface 104 of the third buried conductive layer 103 and the first main surface 3. Due to this step 105, a recess 106 defined by the top surface 104 of the third buried conductive layer 103 and the side surface of the second trench 101 is formed in the upper part of the second trench 101.

[0251] A portion of the source pad electrode 20 is buried in the recess 106 and is mechanically and electrically connected to the third buried conductive layer 103. A source potential applied to the source pad electrode 20 is applied to the third buried conductive layer 103 in the second trench 101. Therefore, the second trench 101 may be referred to as a "source trench," a "source potential trench," or the like.

[0252] The semiconductor device 1 further includes a second well region 107 formed in a portion of the drift region 8 surrounding the second trench 101. In this embodiment, the second well region 107 is formed around the bottom of the second trench 101. The second well region 107 may also be referred to as a "second bottom well region," a "second electric field relaxation region," or a "second electric field relaxation layer."

[0253] The second well region 107 covers the third buried conductive layer 103 at the bottom of the second trench 101 from the outside of the second trench 101. The second well region 107 is exposed from the bottom and side surfaces of the second trench 101 and is in contact with the second isolation insulating film 102.

[0254] The second well region 107 is formed across the width of the second trench 101, spanning between one end and the other end of the second trench 101. The second well region 107 extends from the bottom surface of the second trench 101 around to the side surfaces, and covers the third buried conductive layer 103 from at least two directions, namely, below and to the sides. In this configuration, the second well region 107 covers the third buried conductive layer 103 from three directions, namely, the bottom surface and both side surfaces of the second trench 101. The second well region 107 is formed in a layer shape along the inner surface of the second trench 101, from one side surface of the second trench 101, via the bottom surface, to the other side surface.

[0255] The second well region 107 is connected to the outer well region 13 by a structure similar to that of the well contact region 86 shown in FIG.

[0256] (14) Tenth Modification Fig. 27 is a cross-sectional view of a tenth modification of semiconductor device 1. Referring to Fig. 27, well region 50 may be omitted from the ninth modification of Fig. 26. Even if well region 50 is omitted, second well regions 107 are formed in the bottoms of second trenches 101 on both sides of trench 31, thereby improving the breakdown voltage at the bottom of trench 31.

[0257] (15) Eleventh Modification Fig. 28 is a cross-sectional view of an eleventh modification of the semiconductor device 1. Referring to Fig. 28, the first buried insulating layer 43 is omitted from the diode structure 12 of the ninth modification of Fig. 26. The second buried conductive layer 42 forms a Schottky junction or a heterojunction with the drift region 8 over the entire portion thereof contacting both side surfaces 34 and the bottom surface 35 of the trench 31.

[0258] (16) Twelfth Modification Fig. 29 is a cross-sectional view of a twelfth modification of semiconductor device 1. Referring to Fig. 29, well region 50 may be omitted from the eleventh modification of Fig. 28. Even if well region 50 is omitted, second well regions 107 are formed in the bottoms of second trenches 101 on both sides of trench 31, thereby improving the breakdown voltage at the bottom of trench 31.

[0259] (17) Thirteenth Modification Fig. 30 is a cross-sectional view of a thirteenth modification of the semiconductor device 1. Referring to Fig. 30, the diode structure 12 does not have to be formed in all of the gate structures 11. For example, a plurality of gate structures 11 in which the diode structure 12 is formed and a plurality of gate structures 11 in which the diode structure 12 is not formed may be alternately arranged at intervals.

[0260] (18) Fourteenth Modification Figure 31 is a cross-sectional view of a fourteenth modification of the semiconductor device 1. Referring to Figure 31, the semiconductor device 1 does not have the second buried insulating layer 62 in the plurality of gate structures 11. Instead of the second buried insulating layer 62, the plurality of gate structures 11 are covered with an interlayer insulating layer 16 formed on the first main surface 3. Source openings 19 are selectively formed at the positions of the source regions 45 and the body contact regions 47.

[0261] (19) Fifteenth Modification Fig. 32 is a cross-sectional view of a fifteenth modification of the semiconductor device 1. Referring to Fig. 32, in the fifth modification of Fig. 22, the sidewall insulating layer 91 may include an extraction film 108 extracted from the side surface 34 of the trench 31 to the inside of the trench 31. The extraction film 108 may cover a part of the bottom surface 35 of the trench 31 and have a junction opening 109 that exposes the remaining part of the bottom surface 35. The second buried conductive layer 42 has a junction interface 92 in the junction opening 109.

[0262] (20) Sixteenth Modification FIG. 33 is a cross-sectional view of a sixteenth modification of the semiconductor device 1. Referring to FIG. 33, the diode structure 12 does not have to be formed in the gate structure 11 of the transistor structure Tr in which the source, body, and drain are arranged in this order in the thickness direction of the chip 2. In this embodiment, the diode structure 12 is embedded in the gate structure 11 in the peripheral region 10. In this case, the first buried conductive layer 33 can be considered as an electrode that controls the channel. Therefore, the first buried conductive layer 33 and the second buried conductive layer 42 may be referred to as a "first electrode" and a "second electrode" to which different potentials are applied.

[0263] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0264] For example, in each of the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 6 may include a silicon single crystal. The second semiconductor layer 7 may include a silicon single crystal.

[0265] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0266] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0267] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0268] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (8) of a first conductivity type in a surface layer portion of the first main surface (3); a plurality of trenches (31) in the first main surface (3); a second impurity region (30) of a second conductivity type and a third impurity region (45) of the first conductivity type in a surface layer portion of the first impurity region (8) and arranged in this order from the second main surface (4) side along a side surface (34) of the trench (31); a first buried conductive layer (33) buried in the trench (31) and facing the second impurity region (30); and a trench insulating film (32) between an inner surface (34, 35) of the trench (31) and the first buried conductive layer (33). a second buried conductive layer (42) buried in the trench (31) closer to the bottom of the trench (31) than the first buried conductive layer (33) and forming a Schottky junction or a heterojunction with the first impurity region (8) on an inner surface (34, 35) of the trench (31); an isolation insulating film (44) located between the first buried conductive layer (33) and the second buried conductive layer (42) and isolating the first buried conductive layer (33) from the second buried conductive layer (42); a first electrode (20) electrically connected to the third impurity region (45) and the second buried conductive layer (42); and a second electrode (29) electrically connected to the first impurity region (8).

[0269] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1 further includes an isolation layer (43, 81, 91, 93) that covers at least one of the side surface (34) and the bottom surface (35) of the trench (31) and physically isolates the first impurity region (8) from the second buried conductive layer (42), and the second buried conductive layer (42) forms a Schottky junction or a heterojunction with the first impurity region (8) exposed from the other of the side surface (34) and the bottom surface (35) of the trench (31).

[0270] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-2, wherein the separation layer (43, 81, 91, 93) is buried in the bottom of the trench (31) and includes a first buried insulating layer (43) covering the first impurity region (8) exposed from a bottom surface (35) of the trench (31), and the second buried conductive layer (42) forms a Schottky junction or a heterojunction with the first impurity region (8) on a side surface (34) of the trench (31).

[0271] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-3, further comprising a well region (50) of a second conductivity type formed in a portion of the first impurity region (8) around the trench (31) and covering the first buried insulating layer (43) from outside the trench (31) at the bottom of the trench (31).

[0272] [Appendix 1-5] The semiconductor device (1) according to appendix 1-4, wherein the first buried insulating layer (43) includes, in the depth direction of the trench (31), a lower insulating portion (54) that covers the well region (50), and an upper insulating portion (55) that is located between the lower insulating portion (54) and the second buried conductive layer (42) and that contacts the first impurity region (8) on the side surface (34) of the trench (31).

[0273] [Appendix 1-6] The semiconductor device (1) according to appendix 1-5, wherein the well region (50) includes a well side portion (56) covering the insulating lower portion (54) from the side surface (34) of the trench (31), and a well bottom portion (57) covering the insulating lower portion (54) from the bottom surface (35) of the trench (31), and the well bottom portion (57) has a thickness greater than that of the well side portion (56).

[0274] [Supplementary Note 1-7] The semiconductor device (1) according to any one of Supplementary Note 1-3 to Supplementary Note 1-6, wherein a two-layer structure of the first buried insulating layer (43) and the second buried conductive layer (42) stacked in order from a bottom surface (35) of the trench (31) along a side surface (34) thereof is formed within the trench (31), the isolation insulating film (44) covers an upper surface of the second buried conductive layer (42) and is integrally connected to the trench insulating film (32) at the side surface (34) of the trench (31), and the first buried insulating layer (43) has a thickness greater than that of the isolation insulating film (44).

[0275] [Appendix 1-8] The semiconductor device (1) according to Appendix 1-2, wherein the separation layer (43, 81, 91, 93) extends integrally from the trench insulating film (32) along both side surfaces (34) of the trench (31) and includes a sidewall insulating layer (91) covering the first impurity region (8) exposed from both side surfaces (34) of the trench (31), and the second buried conductive layer (42) is buried in a bottom of the trench (31) surrounded by the sidewall insulating layer (91) and forms a Schottky junction or a heterojunction with the first impurity region (8) at a bottom surface (35) of the trench (31).

[0276] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-2, wherein the separation layer (43, 81, 91, 93) is formed in a portion of the first impurity region (8) around the trench (31), and includes, at the bottom of the trench (31), a second conductivity type separation well region (81) that covers at least the bottom surface (35) of the trench (31) from the outside of the trench (31) out of the side surface (34) and bottom surface (35) of the trench (31).

[0277] [Appendix 1-10] The semiconductor device (1) according to Appendix 1-9, wherein the second buried conductive layer (42) integrally includes a lower electrode portion (82) covered by the isolation well region (81) in the depth direction of the trench (31), and an upper electrode portion (83) located between the lower electrode portion (82) and the isolation insulating film (44) and in contact with the first impurity region (8) on the side surface (34) of the trench (31).

[0278] [Appendix 1-11] The semiconductor device (1) according to appendix 1-10, wherein the isolation well region (81) integrally includes an isolation well side portion (84) covering the lower electrode portion (82) from the side surface (34) of the trench (31), and an isolation well bottom portion (85) covering the lower electrode portion (82) from the bottom surface (35) of the trench (31), and the isolation well bottom portion (85) has a thickness greater than that of the isolation well side portion (84).

[0279] [Appendix 1-12] The semiconductor device (1) according to Appendix 1-2, wherein the separation layer (43, 81, 91, 93) is formed in a portion of the first impurity region (8) around the trench (31), and includes a second conductivity type separation well region (93) that covers one of the one and other side surfaces (34) of the trench (31) and the entire bottom surface (35) of the trench (31) from outside the trench (31).

[0280] [Appendix 1-13] The semiconductor device (1) according to Appendix 1-12, wherein the isolation well region (93) extends from a bottom of the trench (31) along one side surface (34) of the trench (31) and is connected to the second impurity region (30) at one side surface (34) of the trench (31).

[0281] [Appendix 1-14] The semiconductor device (1) according to Appendix 1-1, wherein the second buried conductive layer (42) forms a Schottky junction or a heterojunction with the first impurity region (8) exposed from the side surface (34) and the bottom surface (35) of the trench (31).

[0282] [Appendix 1-15] The semiconductor device (1) according to Appendix 1-14, wherein the second buried conductive layer (42) forms a Schottky junction or a heterojunction with the first impurity region (8) over the entire portion thereof contacting the side surface (34) and the bottom surface (35) of the trench (31).

[0283] [Appendix 1-16] The semiconductor device (1) according to Appendix 1-14 further includes a well region (97) of a second conductivity type formed in a portion of the first impurity region (8) around the trench (31) and covering one of the one and other side surfaces (34) of the trench (31) and a part of a bottom surface (35) of the trench (31) from outside the trench (31), wherein the second buried conductive layer (42) forms a Schottky junction or a heterojunction with the bottom surface (35) of the trench (31) and the first impurity region (8) exposed from the other side surface (34) of the trench (31).

[0284] [Appendix 1-17] The semiconductor device (1) according to Appendix 1-16, wherein the well region (97) extends from a bottom of the trench (31) along one side surface (34) of the trench (31) and is connected to the second impurity region (30) at one side surface (34) of the trench (31).

[0285] [Appendix 1-18] The semiconductor device (1) according to any one of Appendices 1-1 to 1-17, further comprising: a recess (40) formed in the trench (31) above the first buried conductive layer (33); and a second buried insulating layer (62) buried in the recess (40) and covering the first buried conductive layer (33).

[0286] [Appendix 1-19] The semiconductor device (1) according to any one of Appendices 1-1 to 1-18, further comprising: a plurality of the trenches (31) arranged in a stripe pattern at intervals; a second trench (101) between adjacent trenches (31); a third buried conductive layer (103) buried in the second trench (101) and electrically connected to the first electrode (20); a second isolation insulating film (102) between an inner surface of the second trench (101) and the third buried conductive layer (103); and a second well region (107) of a second conductivity type formed in a portion of the first impurity region (8) around the second trench (101), at the bottom of the second trench (101), covering the third buried conductive layer (103) from outside the second trench (101) via the second isolation insulating film (102).

[0287] [Appendix 1-20] The semiconductor device (1) according to any one of Appendices 1-1 to 1-19, wherein the second buried conductive layer (42) includes a Schottky metal made of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, a Ni layer, or a silicide thereof, or a heteroelectrode made of polysilicon.

[0288] [Appendix 1-21] The semiconductor device (1) according to any one of Appendices 1-1 to 1-20, wherein the chip (2) includes a SiC chip (2).

[0289] [Appendix 1-22] The semiconductor device (1) according to any one of Appendices 1-1 to 1-21, wherein the first electrode (20) includes a first principal surface electrode (20) arranged on the first principal surface (3), and the second electrode (29) includes a second principal surface electrode (29) arranged on the second principal surface (4).

[0290] [Appendix 1-23] The semiconductor device (1) according to any one of Appendices 1-1 to 1-22, wherein the first impurity region (8) includes an n-type drift region (8), the second impurity region (30) includes a p-type body region (30), and the third impurity region (45) includes an n-type source region (45).

[0291] [Supplementary Note 2-1] A chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (8) of a first conductivity type in a surface layer portion of the first main surface (3); a plurality of trenches (31) in the first main surface (3); a first buried conductive layer (33) buried in the trench (31) and to which a first potential is applied; a trench insulating film (32) between an inner surface (34, 35) of the trench (31) and the first buried conductive layer (33); a second buried conductive layer (42) buried in the trench (31) closer to the bottom of the trench (31) than the first buried conductive layer (33), forming a Schottky junction or a heterojunction with the first impurity region (8) at the inner surface (34, 35) of the trench (31), and to which a second potential different from the first potential is applied; A semiconductor device (1) comprising: a first electrode (20) electrically connected to the second buried conductive layer (42); and a second electrode (29) electrically connected to the first impurity region (8).

[0292] [Supplementary Note 2-2] The semiconductor device (1) according to Supplementary Note 2-1, wherein the absolute value of the second potential is equal to the absolute value of the potential applied between the first electrode (20) and the second electrode (29).

[0293] [Supplementary Note 2-3] The semiconductor device (1) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the first potential includes a control potential applied to form a current path within the chip (2).

[0294] [Supplementary Note 2-4] The semiconductor device (1) according to any one of Supplementary Note 2-1 to Supplementary Note 2-3, wherein the second potential is greater than the first potential.

[0295] [Supplementary Note 2-5] The semiconductor device (1) according to any one of Supplementary Note 2-1 to Supplementary Note 2-4, wherein the first potential is a gate potential and the second potential is a source potential.

[0296] [Supplementary Note 3-1] A chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (8) of a first conductivity type in a surface layer portion of the first main surface (3); a plurality of trenches (31) in the first main surface (3), the plurality of trenches (31) having a first trench surface (35) and a second trench surface (34) having mutually different surface orientations; a first buried conductive layer (33) buried in the trench (31) and to which a first potential is applied; and a second buried conductive layer (42) buried in the trench (31) closer to the bottom of the trench (31) than the first buried conductive layer (33), forming a Schottky junction or a heterojunction with the first impurity region (8) at one of the first trench surface (35) and the second trench surface (34), and to which a second potential different from the first potential is applied. A semiconductor device (1) comprising: a first electrode (20) electrically connected to the second buried conductive layer (42); and a second electrode (29) electrically connected to the first impurity region (8).

[0297] [Supplementary Note 3-2] The semiconductor device (1) according to Supplementary Note 3-1, wherein the first trench surface (35) is a polar surface and the second trench surface (34) is a non-polar surface.

[0298] [Appendix 3-3] The semiconductor device (1) according to appendix 3-2, wherein the chip (2) includes a SiC chip (2), the first trench surface (35) is a c-plane, and the second trench surface (34) is an m-plane or an a-plane.

[0299] [Supplementary Note 3-4] The semiconductor device (1) according to Supplementary Note 3-1, wherein the first trench surface (35) is a non-polar surface and the second trench surface (34) is a polar surface.

[0300] [Appendix 3-5] The semiconductor device (1) according to appendix 3-4, wherein the chip (2) includes a SiC chip (2), the first trench surface (35) is an m-plane or an a-plane, and the second trench surface (34) is a c-plane.

[0301] REFERENCE SIGNS LIST 1...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor layer, 7...Second semiconductor layer, 8...Drift region, 9...Active region, 10...Peripheral region, 11...Gate structure, 12...Diode structure, 13...Outer well region, 14...Field region, 15...Surface insulating film, 16...Interlayer insulating layer, 17...Gate wiring, 18...Gate pad wiring, 19...Source opening, 20...Source pad electrode, 21...First pad portion, 22...Second pad portion, 23...Third pad portion, 24...Gate pad 1. A semiconductor device according to claim 1, further comprising: a source electrode, 25...gate finger electrode, 26...first slit portion, 27...source finger electrode, 28...second slit portion, 29...drain pad electrode, 30...body region, 31...trench, 32...trench insulating film, 33...first buried conductive layer, 34...side surface, 35...bottom surface, 36...mesa portion, 37...channel region, 38...upper surface, 39...step, 40...recess, 41...protrusion portion, 42...second buried conductive layer, 43...first buried insulating layer, 44...isolation insulating film, 45...source region, 46...channel section, 47...body contact region, 48...junction interface, 49...interface, 50... Well region, 52... boundary surface, 53... step, 54... lower insulating portion, 55... upper insulating portion, 56... well side portion, 57... well bottom portion, 58... step, 59... side surface, 60... upper surface, 61... lower surface, 62... second buried insulating layer, 63... upper edge, 64... upper surface, 65... silicide layer, 66... ​​non-silicide portion, 67... connecting insulating layer, 68... connecting conductive layer, 69... outer contact region, 70... first main surface electrode, 71... barrier layer, 72... main body layer, 73... second recess, 74... resin layer, 76... main surface insulating film, 77... gate opening, 80... outer opening, 81... isolation well region, 82... lower electrode , 83... upper part of electrode, 84... side part of isolation well, 85... bottom part of isolation well, 86... well contact region, 87... side surface, 88... upper surface, 89... lower surface, 90... step, 91... sidewall insulating layer, 92... junction interface, 93... isolation well region, 94... junction interface, 95... junction interface, 96... junction interface, 97... well region, 98... junction interface, 99... junction interface, 100... junction interface, 101... second trench, 102... second isolation insulating film, 103... third buried conductive layer, 104... upper surface, 105... step, 106... recess, 107... second well region, 108... lead film, 109... junction opening

Claims

a first impurity region of a first conductivity type in a surface layer portion of the first surface; a plurality of trenches in the first surface; a second impurity region of a second conductivity type and a third impurity region of the first conductivity type in a surface layer portion of the first impurity region and arranged in this order from the second surface side along a side surface of the trench; a first buried conductive layer buried in the trench and facing the second impurity region; a trench insulating film between an inner surface of the trench and the first buried conductive layer; a second buried conductive layer buried in the trench closer to the bottom of the trench than the first buried conductive layer and forming a Schottky junction or a heterojunction with the first impurity region on the inner surface of the trench; an isolation insulating film between the first buried conductive layer and the second buried conductive layer and isolating the first buried conductive layer from the second buried conductive layer; and a first electrode electrically connected to the third impurity region and the second buried conductive layer. a second electrode electrically connected to the first impurity region.

2. The semiconductor device according to claim 1, further comprising an isolation layer covering at least one of the side and bottom surfaces of the trench and physically isolating the first impurity region and the second buried conductive layer, wherein the second buried conductive layer forms a Schottky junction or a heterojunction with the first impurity region exposed from the other of the side and bottom surfaces of the trench.

3. The semiconductor device according to claim 2, wherein the isolation layer further includes a first buried insulating layer buried in the bottom of the trench and covering the first impurity region exposed at the bottom surface of the trench, and the second buried conductive layer forms a Schottky junction or a heterojunction with the first impurity region on the side surface of the trench.

4. The semiconductor device according to claim 3, further comprising a well region of a second conductivity type formed in a portion of the first impurity region surrounding the trench and covering the first buried insulating layer from outside the trench at the bottom of the trench.

5. The semiconductor device described in claim 4, wherein the first buried insulating layer includes, in the depth direction of the trench, a lower insulating portion covering the well region, and an upper insulating portion located between the lower insulating portion and the second buried conductive layer and in contact with the first impurity region on the side surface of the trench.

6. The semiconductor device according to claim 5, wherein the well region includes a well side portion covering the lower insulating portion from the side surface of the trench, and a well bottom portion covering the lower insulating portion from the bottom surface of the trench, and the well bottom portion has a thickness greater than that of the well side portion.

7. A semiconductor device according to any one of claims 3 to 6, wherein a two-layer structure of the first buried insulating layer and the second buried conductive layer is formed in the trench, stacked in order from the bottom surface of the trench along the side surface, the isolation insulating film covers the top surface of the second buried conductive layer and is integrally connected to the trench insulating film on the side surface of the trench, and the first buried insulating layer has a thickness greater than that of the isolation insulating film.

8. The semiconductor device according to claim 2, wherein the isolation layer includes a sidewall insulating layer that extends integrally from the trench insulating film along both side surfaces of the trench and covers the first impurity region exposed from both side surfaces of the trench, and the second buried conductive layer is buried in the bottom of the trench surrounded by the sidewall insulating layer and forms a Schottky junction or a heterojunction with the first impurity region at the bottom surface of the trench.

9. The semiconductor device according to claim 2, wherein the isolation layer is formed in a portion of the first impurity region surrounding the trench, and includes an isolation well region of the second conductivity type at the bottom of the trench, covering at least the bottom surface of the trench from outside the trench among the side and bottom surfaces of the trench.

10. The semiconductor device described in claim 9, wherein the second buried conductive layer integrally includes, in the depth direction of the trench, a lower electrode portion covering the isolation well region, and an upper electrode portion located between the lower electrode portion and the isolation insulating film and in contact with the first impurity region on the side surface of the trench.

11. The semiconductor device according to claim 10, wherein the isolation well region integrally includes an isolation well side portion covering the lower portion of the electrode from the side surface of the trench, and an isolation well bottom portion covering the lower portion of the electrode from the bottom surface of the trench, and the isolation well bottom portion has a thickness greater than that of the isolation well side portion.

12. The semiconductor device according to claim 2, wherein the isolation layer is formed in a portion of the first impurity region surrounding the trench and includes an isolation well region of a second conductivity type that covers one of the side surfaces of the trench and the entire bottom surface of the trench from outside the trench.

13. The semiconductor device according to claim 12, wherein said isolation well region extends from the bottom of said trench along one side surface of said trench and is connected to said second impurity region at said one side surface of said trench.

14. The semiconductor device according to claim 1, wherein said second buried conductive layer forms a Schottky junction or a heterojunction with said first impurity region exposed from the side and bottom surfaces of said trench.

15. The semiconductor device according to claim 14, wherein the second buried conductive layer forms a Schottky junction or a heterojunction with the first impurity region over the entire portion of the second buried conductive layer contacting the side and bottom surfaces of the trench.

16. The semiconductor device according to claim 14, further comprising a well region of a second conductivity type formed in a portion of the first impurity region surrounding the trench and covering one of the one and other side surfaces of the trench and a portion of the bottom surface of the trench from outside the trench, wherein the second buried conductive layer forms a Schottky junction or a heterojunction between the bottom surface of the trench and the first impurity region exposed from the other side surface of the trench.

17. The semiconductor device according to claim 16, wherein the well region extends from the bottom of the trench along one side surface of the trench and is connected to the second impurity region at the one side surface of the trench.

18. The semiconductor device according to any one of claims 1 to 17, further comprising: a recess formed in the trench above the first buried conductive layer; and a second buried insulating layer buried in the recess and covering the first buried conductive layer.

19. The semiconductor device according to any one of claims 1 to 18, wherein a plurality of the trenches are arranged in a striped pattern with spaces between them, and further comprising: a second trench between adjacent trenches; a third buried conductive layer buried in the second trench and electrically connected to the first electrode; a second isolation insulating film between the inner surface of the second trench and the third buried conductive layer; and a second well region of the second conductivity type formed in a portion of the first impurity region surrounding the second trench, at the bottom of the second trench, covering the third buried conductive layer from outside the second trench via the second isolation insulating film.

20. The semiconductor device according to any one of claims 1 to 19, wherein the second buried conductive layer includes a Schottky metal made of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, a Ni layer, or a silicide thereof, or a heteroelectrode made of polysilicon.

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