Ceramic substrate, ceramic joined body, and semiconductor device

Abstract

Provided are a ceramic substrate, a ceramic joined body, and a semiconductor device capable of suppressing arc discharge generation and further improving long-term reliability. In a ceramic substrate according to an embodiment, when an AC voltage of 50 Hz or 60 Hz is applied across the front surface and the back surface from 0 kV to 6 kV at a voltage ramp rate of 200 V / s, arc discharge is not detected. The dielectric breakdown voltage of the ceramic substrate is preferably 20 kV / mm or higher. In at least any observation region of 90 µm by 120 µm included in a given cross-section, the total number of first voids having a surface area of less than 0.1 µm2 and second voids having a surface area of 0.1 µm2 to less than 1 µm2 is preferably 29 or less, and the number of third voids having a surface area of 1 µm2 or more is preferably 0 to 3.

Description

Ceramic substrate, ceramic bonded body, and semiconductor device

[0001] The embodiments described below relate to a ceramic substrate, a ceramic bonded body, and a semiconductor device.

[0002] In recent years, as industrial equipment has become more sophisticated, the power modules mounted on them have become increasingly powerful. This has led to an increase in the power output of semiconductor elements. The guaranteed operating temperature for semiconductor elements is 125°C to 150°C, but this may rise to 175°C or higher in the future. Ceramic circuit boards are used as circuit boards on which semiconductor elements are mounted. Examples of ceramic substrates include silicon nitride substrates, aluminum nitride substrates, and aluminum oxide substrates.

[0003] For example, Japanese Patent No. 6293772 (Patent Document 1) discloses a silicon nitride substrate having a thermal conductivity of 50 W / m·K or more and a three-point bending strength of 600 MPa or more. In Patent Document 1, the distribution of grain boundary phases in the thickness direction of the substrate is controlled. In Japanese Patent No. 5928896 (Patent Document 2), the area ratio of voids with a circle equivalent diameter of 0.5 μm or more is controlled.

[0004] The silicon nitride substrates described in Patent Documents 1 and 2 both have excellent insulating properties. However, there is still room for improvement in terms of long-term reliability. Conventional insulation tests measure dielectric strength, which is a breakdown test. In a dielectric strength test, electrodes are placed on the front and back surfaces of a ceramic substrate, and the voltage at which dielectric breakdown occurs is measured. Despite having high dielectric strength, ceramic substrates have sometimes been found to lack long-term reliability. Investigation into the cause of this has revealed that the conditions used in dielectric strength tests deviate significantly from practical electric fields, and that the measured dielectric strength may not be an appropriate indicator of long-term reliability.

[0005] Japanese Patent No. 6293772 Japanese Patent No. 5928896 International Publication No. 2024 / 062832

[0006] For example, International Publication No. 2024 / 062832 (Patent Document 3) uses arc discharge voltage to ensure the long-term reliability of a ceramic substrate. The arc discharge voltage is an effective indicator for measuring the long-term reliability of a ceramic substrate. However, according to Patent Document 3, arc discharge itself in the ceramic substrate is detected, and no further improvement can be achieved.

[0007] An object of the present invention is to provide a ceramic substrate, a ceramic joined body, and a semiconductor device that are capable of suppressing the occurrence of arc discharge and further improving long-term reliability.

[0008] With the ceramic substrate according to the embodiment, no arc discharge is detected when a 50 Hz or 60 Hz AC voltage is applied between the front and back surfaces from 0 kV to 6 kV at a voltage increase rate of 200 V / s.

[0009] 1 is a perspective view showing an example of a ceramic substrate according to an embodiment; FIG. 2 is a graph showing an example of measurement results of the amount of accumulated charge; FIG. 3 is a schematic view showing an example of a cross-sectional structure of a ceramic substrate according to an embodiment; FIG. 4 is a schematic view showing an example of the shortest distance between voids; FIG. 5 is a side view showing an example of a ceramic bonded body according to an embodiment; and FIG. 6 is a side view showing an example of a semiconductor device according to an embodiment.

[0010] With the ceramic substrate according to the embodiment, no arc discharge is detected when a 50 Hz or 60 Hz AC voltage is applied between the front and back surfaces from 0 kV to 6 kV at a voltage increase rate of 200 V / s.

[0011] Fig. 1 is a perspective view showing an example of a ceramic substrate according to an embodiment. In Fig. 1, reference numeral 1 denotes a ceramic substrate. Fig. 1 illustrates a ceramic substrate 1 having a rectangular (cuboid) upper surface, but the shape of the ceramic substrate 1 may be various shapes such as a circle (including an ellipse), a polygon, an L-shape, or a U-shape.

[0012] The presence or absence of arc discharge detection is confirmed using the following method. First, electrodes are placed on the front and back surfaces of the ceramic substrate 1, and the ceramic substrate 1 is sandwiched between the pair of electrodes. For example, spherical electrodes with a tip diameter of 10 mm, as specified in JIS-C-2110-1 (2013), are used as the electrodes. With the ceramic substrate 1 sandwiched between the pair of electrodes, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes. The voltage increase rate is set to 200 V / s. At the start of the AC voltage application, the potential is equal to ground and is considered to be essentially 0 V. The voltage when arc discharge is detected between the electrodes is measured as the arc discharge voltage (kV). Once the arc discharge voltage is measured, the voltage application is stopped without further increase. If no arc discharge is detected when a voltage of up to 6 kV is applied, the voltage is maintained at 6 kV for 2 seconds, and then the measurement is terminated. The measurement device used is an AC Withstand Voltage Tester-7473 manufactured by Keisoku Giken Kenkyusho, or a device with an arc discharge detection function equivalent to or better than that.

[0013] In the ceramic substrate 1 according to the embodiment, no arc discharge is detected even when an AC voltage of up to 6 kV is applied between the front and back surfaces. In other words, the ceramic substrate 1 according to the embodiment has an arc discharge voltage of at least 6 kV.

[0014] Arc discharge is detected as a pulse current that occurs periodically when an AC electric field of a constant frequency is applied to the ceramic substrate 1. The AC Withstand Voltage Tester -7473 can automatically detect arc discharge from changes in the measured current value. For example, arc discharge is likely to occur in a structure where electric field concentration occurs. The absence of detection of arc discharge indicates that the ceramic substrate 1 has a structure in which electric field concentration is suppressed.

[0015] The AC voltage of 6 kV is several times higher than the voltage that can be applied to a ceramic substrate in an actual semiconductor device. Therefore, even when the ceramic substrate 1 is applied to an actual semiconductor device and the semiconductor device is operated, arc deterioration in the ceramic substrate 1 can be suppressed. This can improve the long-term reliability of the semiconductor device.

[0016] For example, according to an embodiment, the dielectric breakdown voltage of the ceramic substrate 1 is 20 kV / mm or more. The dielectric breakdown voltage is measured in accordance with the dielectric breakdown strength test of JIS-C-2141 (1992). JIS-C-2141 corresponds to IEC 672-2 (1980). The latest IEC 60672-2 (1999) may also be referenced as necessary. The test is performed using a two-terminal method. Electrodes are placed on the front and back surfaces of the ceramic substrate 1, and the ceramic substrate 1 is sandwiched between the pair of electrodes. The electrodes are spherical electrodes as specified in JIS-C-2110-1 (2013). The electrode conditions for measuring the dielectric breakdown voltage are the same as those for measuring the arc discharge voltage described above. With the ceramic substrate 1 sandwiched between the pair of electrodes, a 50 Hz or 60 Hz AC voltage is applied between the electrodes, and the voltage is increased. At the start of application, the AC voltage is at the same potential as ground and is considered to be substantially 0 V. The voltage ramp rate is set to 200 V / s. The voltage at which the ceramic substrate 1 experiences dielectric breakdown is measured as the dielectric breakdown voltage (kV). The dielectric breakdown voltage is the voltage at which the ceramic substrate 1 loses its insulating properties when a voltage is applied to the ceramic substrate 1. The dielectric breakdown voltage is used as an index for measuring the insulating properties of a ceramic substrate.

[0017] In measuring the breakdown voltage, the applied voltage may be DC. The conditions for measuring with DC are also as described above. That is, the voltage value at the start of application of the DC voltage is set to 0 V, and the voltage is increased at a rate of 200 V / s, and the voltage at which the ceramic substrate 1 breaks down is measured. The breakdown voltage (kV / mm) is calculated by dividing the voltage at which breakdown occurs by the thickness of the substrate.

[0018] Alternatively, after checking whether or not an arc discharge is detected when a voltage up to 6 kV is applied as described above and measuring the ratio of the accumulated charge amounts described below, the breakdown voltage may be measured for the same ceramic substrate 1. In this case, after each measurement, the application of voltage to the ceramic substrate 1 is stopped and the next measurement is performed.

[0019] When measuring the breakdown voltage, a voltage of up to 20 kV is applied for both AC and DC. The breakdown voltage is calculated by dividing the voltage (V) at which breakdown occurs by the thickness of the ceramic substrate 1, so the unit of breakdown voltage is "kV / mm." The breakdown voltage measured by applying an AC voltage is expressed as V. ＡＣ , the breakdown voltage measured by applying a DC voltage is V ＤＣ The dielectric breakdown voltage of the ceramic substrate 1 being 20 kV / mm or more means that the dielectric breakdown voltage measured with either AC or DC is 20 kV / mm or more.

[0020] For the ceramic substrate 1 according to the embodiment, it is preferable that the breakdown voltage is 20 kV / mm or more, regardless of whether the applied voltage is AC or DC. When an AC voltage or DC voltage is applied to the ceramic substrate 1, an AC electric field or a DC electric field is generated in the ceramic substrate 1. When an AC electric field is applied, the direction of the electric field between the electrodes changes periodically. As a result, a current depending on the capacitance of the ceramic substrate 1 flows continuously. On the other hand, when a DC electric field is applied, the direction of the electric field between the electrodes is constant, and after the capacitance of the ceramic substrate 1 is saturated, only a weak current depending on the volume resistance flows. Because the electric field direction and current flow are different in this way, it is expected that the mechanisms of breakdown will also be different between AC electric fields and DC electric fields.

[0021] Semiconductor elements included in the electrical circuits of modules are often driven by a unipolar pulse waveform voltage. This can be considered as driving by a pseudo-DC electric field. On the other hand, due to complex circuit designs, ceramic substrates 1 used as insulating substrates may be subjected to electric fields with not only "DC components" but also "AC components." The fact that the breakdown voltage is 20 kV / mm or higher, whether measured with a DC electric field or an AC electric field, indicates that the ceramic substrate 1 has good insulating properties, regardless of whether a DC electric field or an AC electric field acts on the ceramic substrate 1.

[0022] When a DC electric field of 5 kV / mm is applied to the ceramic substrate 1 at 25° C., the ratio Q25(600) / Q25(5) of the amount of accumulated charge Q25(600) after 600 seconds to the amount of accumulated charge Q25(5) after 5 seconds is preferably 1.0 or more and 3.0 or less. Hereinafter, the ratio Q25(600) / Q25(5) will be referred to as the “accumulated charge ratio.”

[0023] The method for measuring the accumulated charge ratio is as follows. The measurement device used is an A&D Q(t) meter (model AD-9832A) or a device with equivalent or better performance. A 40 mm diameter measurement electrode is used as the standard. A 30 mm diameter electrode can also be used as long as it is large enough to prevent creepage leakage from the ceramic substrate 1. A measurement electrode size that ensures a creepage distance of 1 mm or more from the ceramic substrate 1 is a good guideline for preventing creepage leakage. Because the accumulated charge is also affected by the size of the measurement electrode, it is preferable to use a 40 mm diameter measurement electrode. Measurement electrodes are placed on the front and back surfaces of the ceramic substrate 1. A voltage corresponding to the thickness of the ceramic substrate 1 is applied between the electrodes to achieve an applied voltage of 5 kV / mm. The room in which the ceramic substrate 1 is placed is set to 25°C and held for at least 5 minutes before measurement.

[0024] After a voltage of 5 kV / mm is applied to the ceramic substrate 1, the measuring device measures the amount of charge accumulated between the electrodes at predetermined measurement intervals. By plotting the change in capacitance over time, a graph showing the relationship between time and the amount of accumulated charge is obtained. From the graph, the amount of accumulated charge 5 seconds after the voltage application (Q25(5)) and the amount of accumulated charge 600 seconds after the voltage application (Q25(600)) are read, and the ratio of the accumulated charge amounts Q25(600) / Q25(5) is calculated.

[0025] The accumulated charge amount is the amount of charge accumulated in the ceramic substrate 1 when a certain voltage is applied. A Q25(600) / Q25(5) ratio of 1.0 to 3.0 indicates that the accumulated charge amount after 600 seconds is within a range of 1.0 to 3.0 times the accumulated charge amount after 5 seconds. This indicates that the amount of charge accumulated over time is small. The closer Q25(600) / Q25(5) is to 1.0, the smaller the amount of charge accumulated over time. A DC electric field of 5 kV / mm is a condition assumed to be the driving voltage of a typical semiconductor device. Note that the lower limit of Q25(600) / Q25(5) is 1.0. Because the accumulated charge amount is the amount of charge accumulated over time, Q25(600) / Q25(5) cannot be less than 1.0.

[0026] For example, the drive voltage of a power card for an electric vehicle (including a hybrid vehicle) is designed to be around 1 kV. A power card is a power module that controls the power of the electric vehicle's motor, and is a card-type module on which multiple semiconductor elements are mounted.

[0027] The ceramic substrate 1 is preferably a silicon nitride substrate. As an example, when a voltage of 1 kV is applied to a silicon nitride substrate having a thickness of 0.32 mm, the DC electric field is 1 / 0.32 = 3.1 kV / mm. When the silicon nitride substrate has a thickness of 0.25 mm, the DC electric field is 1 / 0.25 = 4 kV / mm. A DC electric field of 5 kV / mm is a suitable condition for practical judgment. When the silicon nitride substrate has a thickness of 0.32 mm, a DC voltage of 1.6 kV (5 kV / mm x 0.32 mm) is applied to apply a DC electric field of 5 kV / mm to the silicon nitride substrate. When the silicon nitride substrate has a thickness of 0.25 mm, a DC voltage of 1.25 kV is applied to apply a DC electric field of 5 kV / mm to the silicon nitride substrate.

[0028] The ratio of the accumulated charge amount Q25(600) / Q25(5) when a DC electric field of 5 kV / mm is applied at 25°C is a parameter that estimates the amount of charge accumulated in a silicon nitride substrate at the driving voltage of a typical semiconductor device. Q25(5) is the amount of accumulated charge in the initial stage after voltage application. Q25(600) is the amount of accumulated charge 600 seconds after voltage application, and is a value measured after the behavior of charge accumulation in the ceramic substrate 1 has stabilized. For example, when a DC voltage is applied to the ceramic substrate 1, the current decreases as the charge accumulates. The period 600 seconds from the start of voltage application is included in the period during which the current is sufficiently reduced and leakage current flows.

[0029] When the ceramic substrate 1 is a silicon nitride substrate, Q25(5) is preferably 0.500 μC (microcoulomb) or less. Q25(5) is the amount of charge that is primarily dependent on the capacitance. Therefore, the smaller Q25(5) is, the better the insulating properties are. There is no particular limit to the lower limit of Q25(5), but a value of 0.300 μC or more is preferred. If the measurement result is less than 0.300 μC, the amount of charge may not have been measured properly.

[0030] The value of the accumulated charge is affected by the size of the measurement electrode. In other words, the accumulated charge can vary depending on the contact area between the ceramic substrate 1 and the measurement electrode. A Q25(5) of 0.500 μC or less is the value when a silicon nitride substrate is measured using a measurement electrode with a diameter of 40 mm. If the size of the measurement electrode is larger or smaller than 40 mm, the value of "0.500 μC" is corrected according to the change in contact area. For example, when the measurement electrode is 30 mm in diameter, Q25(5) is preferably 0.300 μC or less.

[0031] FIG. 2 is a graph showing an example of the measurement results of the amount of accumulated charge. In FIG. 2, the horizontal axis represents time (seconds) and the vertical axis represents the amount of accumulated charge Q(t). Immediately after voltage application, the amount of accumulated charge increases significantly. After 5 seconds, the amount of accumulated charge saturates and the change becomes gradual. Thereafter, the amount of accumulated charge gradually increases over time. In the example shown in FIG. 2, the amount of accumulated charge Q25(5) is approximately 330 nC (= 0.33 μC), and the amount of accumulated charge Q25(600) is approximately 510 nC (= 0.51 μC). Therefore, the ratio of the amount of accumulated charge Q25(600) / Q25(5) is approximately 1.55.

[0032] The ceramic substrate 1 according to the embodiment exhibits excellent insulation properties in terms of breakdown voltage, accumulated charge ratio, and arc discharge voltage. With regard to breakdown voltage, the ceramic substrate 1 exhibits excellent insulation properties in both DC and AC electric fields.

[0033] Semiconductor elements include insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field effect transistors (MOSFETs), metal semiconductor FETs (MESFETs), and high electron mobility transistors (HEMTs). Generally, the switching frequency of a Si-IGBT element, which is a type of Si element, is approximately 100 Hz to 50 kHz. The switching frequency of a SiC-MOSFET element is approximately 8 kHz to 1 MHz. As the switching frequency increases, the output power and power density increase. For example, a Si-IGBT element with a switching frequency of 25 kHz has an output power of 3.3 kW and a power density of 0.3 W / cm. ３ For a SiC-MOSFET device with a switching frequency of 160 kHz, the output power is 5 kW and the power density is 1.8 W / cm. ３ There are devices with switching operating frequencies of about 1 GHz to 10 GHz for GaAs-MESFETs and HEMTs. An increase in switching frequency leads to an increase in output voltage or power density.

[0034] The ceramic substrate 1 according to the embodiment exhibits excellent insulation properties even when the switching frequency is as high as 8 kHz or more. ３ Even when the above semiconductor elements are mounted, the ceramic substrate 1 exhibits excellent insulation. In other words, for ceramic substrates 1 used in semiconductor devices including high-performance semiconductor elements, the insulation cannot be properly evaluated by the breakdown voltage alone. In addition, IGBT elements and the like are called power semiconductor elements. Power semiconductor elements convert voltage and frequency. Power semiconductor elements also convert AC and DC. As mentioned above, the insulation properties for both AC and DC are improved, making it suitable for mounting power semiconductor elements.

[0035] The ceramic substrate 1 is one selected from a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, and a zirconium oxide substrate. Ceramic substrates 1 are classified according to the component they contain most abundantly. For example, a substrate containing the most silicon nitride is called a silicon nitride substrate. Among ceramic substrates 1, a silicon nitride substrate is preferred. The thermal conductivity of a silicon nitride substrate is 40 W / m·K or more, and even 80 W / m·K or more. The three-point bending strength of a silicon nitride substrate is 600 MPa or more, and even 700 MPa or more. The thermal conductivity of an aluminum nitride substrate is 160 W / m·K or more, and even 200 W / m·K or more. The three-point bending strength of an aluminum nitride substrate is approximately 300 to 450 MPa. The three-point bending strength of an aluminum oxide substrate is approximately 300 to 450 MPa, but aluminum oxide substrates are less expensive than other substrates. The thermal conductivity of an aluminum oxide substrate is approximately 20 to 30 W / m·K. The three-point bending strength of a zirconium oxide substrate is high at approximately 550 MPa, but the thermal conductivity is approximately 30 to 50 W / m·K.

[0036] The thickness of the ceramic substrate 1 is preferably in the range of 0.1 mm to 3 mm. If the thickness is less than 0.1 mm, the insulating properties of the ceramic substrate 1 may be insufficient. If the thickness exceeds 3 mm, the insulating properties of the ceramic substrate 1 are good, but the heat dissipation properties are reduced. Silicon nitride substrates have high insulating properties and strength. Therefore, the thickness of the silicon nitride substrate may be in the range of 0.15 mm to 0.8 mm, or may be in the range of 0.2 mm to 0.4 mm.

[0037] When observing an arbitrary cross section of the ceramic substrate 1, it is preferable that the total number of first voids and second voids is 29 or less, and the number of third voids is 0 to 3 in at least one observation area of ​​90 μm × 120 μm. Here, the "first void" is defined as a void having an area of ​​0.1 μm ２ A "secondary void" is a void with an area of ​​0.1 μm or less. ２ 1 μm or more ２ A "third void" is a void with an area of ​​1 μm or less. ２ That's all there is to it.

[0038] Figure 3 is a schematic diagram showing an example of the cross-sectional structure of a ceramic substrate 1 according to an embodiment. In Figure 3, reference numeral 2 denotes a cross section, reference numeral 3a denotes a first void, reference numeral 3b denotes a second void, and reference numeral 3c denotes a third void. Figure 3 illustrates an observation area of ​​90 μm × 120 μm on cross section 2. Hereinafter, the observation area of ​​90 μm × 120 μm may be simply referred to as the "observation area."

[0039] A method for observing a cross section will be described. First, an arbitrary cross section of the ceramic substrate 1 is prepared. A polished surface with a surface roughness Ra of 1 μm or less is used as the cross section. The cross section is observed with a scanning electron microscope (SEM), and a 1000x magnification photograph is taken. The SEM used is a JEOL JCM-7000 or JSM-7200F, or a device with equivalent or higher performance. From the enlarged photograph taken, a 0.1 μm area is observed. ２ and a first void 3a having an area of ​​less than 0.1 μm ２ 1 μm or more ２ Second void 3b, area less than 1 μm ２ The third void 3c described above will be observed.

[0040] To observe voids, SEM photographs are analyzed using image analysis software. Image J or equivalent software is used as the image analysis software. In cross-sectional SEM photographs, contrast occurs between voids and other parts. For example, the color of voids appears darker and more intense than the color of parts other than voids. By utilizing this contrast and binarizing the SEM photograph, it is possible to distinguish between voids and other parts. ２ Voids smaller than 0.01 μm in area are difficult to distinguish in a 1000x magnification photograph. ２ Therefore, the first void is counted as a void having an area of ​​0.01 μm or more. ２ 0.1 μm or more ２ It is a void less than.

[0041] The threshold value for binarization is obtained using the "mode method" or "discriminant analysis binarization method." If the image analysis software has the function of discriminant analysis binarization, the discriminant analysis binarization method of that image analysis software is used. With discriminant analysis binarization, the threshold value is uniquely determined by the analysis software. This makes it easy to identify voids. For example, in an SEM photograph, the white area around a void is the boundary between the void and the silicon nitride sintered body. Therefore, the white area around a void should not be counted as a void. For example, in an SEM photograph, the silicon nitride sintered body is gray. By using the threshold value obtained by the "mode method" or "discriminant analysis binarization method," voids can be displayed in black, and the white area around the void and the silicon nitride sintered body can be displayed in white. Using the binarized image, it is possible to distinguish between voids and other areas in the SEM photograph.

[0042] In the observation area, the total number of first voids 3a and second voids 3b is preferably 29 or less. ２These are small voids of less than 100 microns in size. By limiting the total number of first voids 3 a and second voids 3 b in the observation area to 29 or less, the insulation properties of the ceramic substrate 1 can be improved. In particular, it is possible to obtain a ceramic substrate 1 in which no arc discharge is detected even when an AC voltage of up to 6 kV is applied. More preferably, in any observation area included in the 1000x magnified photograph, the total number of first voids 3 a and second voids 3 b is 29 or less.

[0043] There is no particular limitation on the lower limit of the total number of first voids 3 a and second voids 3 b. However, in order to make the total number zero, it is necessary to extremely reduce the amount of impurities, as described below, and to strictly control the manufacturing process. Therefore, the lower limit of the total number of first voids 3 a and second voids 3 b may be 1 or more, 3 or more, or 5 or more.

[0044] In addition, in any observation region in the cross section, an area of ​​1 μm ２ The number of the third voids 3c is preferably 0 to 3. The third voids 3c have an area of ​​1 μm ２ By limiting the number of third voids 3c to three or less, the insulating properties of the ceramic substrate 1 can be improved. More preferably, in any observation region in the cross section, a void with an area of ​​1 μm or less is ２ The above third voids 3c are not present. More preferably, the number of third voids 3c is 3 or less in any observation area included in the 1000x magnification photograph. Most preferably, the number of third voids 3c is 0 in any observation area included in the 1000x magnification photograph.

[0045] Arc discharge is detected as a pulse current that periodically occurs when an AC electric field of a constant frequency is applied between electrodes. Initial arc discharge phenomena occur in voids within the ceramic substrate 1. Repeated arc discharges lead to a phenomenon known as arc degradation. As arc degradation progresses, dielectric breakdown occurs. In other words, arc discharge is a precursor to dielectric breakdown. Therefore, measuring the voltage at which arc discharge occurs can confirm the long-term reliability of the ceramic substrate 1. When voltage is applied to the ceramic substrate 1, a shared voltage is applied to the voids. When the shared voltage reaches the discharge voltage, partial discharge occurs. When partial discharge occurs, a pulse current flows. The magnitude of the shared voltage varies depending on the size and shape of the voids. According to the embodiment, the voids are small and few in number, resulting in small partial discharges. By limiting the total number of first voids 3a and second voids 3b to 29 or less and limiting the number of third voids 3c to 0 or more and 3 or less, as in the embodiment, partial discharges can be suppressed, and arc discharges are not detected up to 6 kV.

[0046] In particular, as the switching frequency of the semiconductor element increases, the number of periodically generated pulse currents increases. As the output voltage and power density increase, arc discharge becomes more likely to occur inside the ceramic substrate 1. Therefore, the higher the switching frequency, output voltage, and power density, the more likely the insulation inside the ceramic substrate 1 is to be degraded by arc discharge, even if the ceramic substrate 1 does not experience dielectric breakdown. As a result, long-term reliability problems may arise.

[0047] According to the embodiment, as described above, the number of first voids 3 a, second voids 3 b, and third voids 3 c in the observation area is controlled, thereby reducing the causes of arc discharge.

[0048] In addition, in any observation region of the cross section, an area of ​​0.1 μm ２ 1 μm or more ２ The number of second voids 3b with an area of ​​less than 0.01 μm is preferably 15 or less, and more preferably 10 or less. As mentioned above, arc discharge is likely to occur in the voids. ２0.1 μm or more ２ The first voids 3a having a size of less than 1 μm are minute voids and therefore unlikely to cause arc discharge. The number of first voids 3a may be three times or less the number of second voids 3b. If the number of first voids 3a exceeds three times the number of second voids 3b, the total area of ​​the first voids 3a also increases. If the total area increases, the insulating properties of the ceramic substrate 1 may be reduced. For this reason, it is preferable that the number of first voids 3a does not exceed three times the number of second voids 3b. More preferably, it is two times or less, and even more preferably, it is 1.7 times or less. For this reason, it is preferable that the number of first voids 3a does not exceed three times the number of second voids 3b. ２ 1 μm or more ２ It is preferable to control the number of second voids 3b to less than 1 / 2.

[0049] According to the embodiment, the number of first voids 3a and the number of second voids 3b are controlled in a well-balanced manner, thereby making it possible to reduce the causes of arc discharge.

[0050] Area 0.1μm ２ 1 μm or more ２ The shortest distance between the second voids 3b is preferably 5 μm or more, where the shortest distance between the second voids 3b is less than 5 μm. Fig. 4 is a schematic diagram showing an example of the shortest distance between the voids. In Fig. 4, reference numeral 3b denotes the second voids, reference numeral 5 denotes ceramic crystal grains, and reference numeral 6 denotes the shortest distance between the voids. The ceramic crystal grains 5 are crystal grains of the base material of the ceramic substrate 1. For example, when the ceramic substrate 1 is a silicon nitride substrate, the ceramic crystal grains 5 are silicon nitride crystal grains.

[0051] The SEM photograph used to measure the number of voids is used to measure the shortest distance 6 between the second voids 3b. In the SEM photograph, the shortest distance 6 between the second voids 3b is measured. Specifically, after identifying the second voids 3b shown in the SEM photograph, a pair of second voids 3b that are closest to each other is extracted. The distance between that pair of second voids 3b is measured as the shortest distance 6.

[0052] Preferably, the area is 0.1 μm ２For the above voids, the shortest distance between adjacent voids is preferably 5 μm or more. In other words, in the SEM photograph, the shortest distance between adjacent second voids 3 b, the shortest distance between adjacent second voids 3 b and third voids 3 c, and the shortest distance between adjacent third voids 3 c are all preferably 5 μm or more.

[0053] The fact that the shortest distance 6 between voids is 5 μm or more means that ceramic crystal grains 5 exist between the second voids 3 b. In addition to the ceramic crystal grains 5, a grain boundary phase (not shown) may also exist between the second voids 3 b. The ceramic crystal grains 5 that form the base material of the ceramic substrate 1 are insulators. By positioning the second voids 3 b apart and having the insulator ceramic crystal grains 5 exist between them, excessive electric field concentration can be avoided, leading to the suppression of discharge phenomena. As a result, the occurrence of arc discharge can be suppressed even when an AC voltage of up to 6 kV is applied.

[0054] It is preferable that three or more ceramic crystal particles 5 exist on a straight line along the shortest distance 6 between the second voids 3b. ２ Three or more ceramic crystal particles 5 may be present on the line along the shortest distance between the third voids 3c. In the example shown in Fig. 4, when a line is drawn connecting adjacent voids, four ceramic crystal particles 5 are present on the line.

[0055] Furthermore, in the example shown in Figure 4, ceramic crystal particles 5-1 and 5-2 are present. These ceramic crystal particles are located behind other ceramic crystal particles, and only part of their outlines can be observed. For these ceramic crystal particles, if their outlines are tangent to a straight line, they are counted. If their outlines are not tangent to a straight line, they are not counted. For example, the outline of ceramic crystal particle 5-1 is tangent to a straight line, but the outline of ceramic crystal particle 5-2 is not tangent to a straight line. Therefore, ceramic crystal particle 5-1 is counted, but ceramic crystal particle 5-2 is not counted.

[0056] The ceramic substrate 1 according to the embodiment may contain 1% by mass or more and 20% by mass or less of the grain boundary phase. When the relative density of the ceramic substrate 1 is 97% or more, the ceramic substrate 1 has a structure in which ceramic crystal grains 5 and the grain boundary phase are mixed. When measuring the proportion of the grain boundary phase in the ceramic substrate 1, if the relative density is 97% or more, the mass percentage of the grain boundary phase may be calculated by subtracting the total mass percentage of the ceramic crystal grains that form the matrix from 100%. In other words, if the relative density is 97% or more, it can be considered a sufficiently dense structure that includes the ceramic crystal grains that form the matrix and a grain boundary phase composed of a sintering aid composition.

[0057] The occurrence of partial discharge can be suppressed by having ceramic crystal grains 5 and a grain boundary phase present within the shortest distance 6 between the second voids 3b. As a result, even when an AC voltage of up to 6 kV is applied, the occurrence of arc discharge can be suppressed.

[0058] When the ceramic substrate 1 is a silicon nitride substrate, the base material of the ceramic substrate 1 is silicon nitride crystal grains. Most silicon nitride crystal grains have an aspect ratio of 2 or more. Therefore, it is easy for three or more silicon nitride crystal grains to exist on a line along the shortest distance 6 between the second voids 3b. In other words, a silicon nitride substrate is suitable for suppressing the occurrence of arc discharge.

[0059] When two adjacent observation regions of 90 μm × 120 μm are set in a cross section of the ceramic substrate 1, the difference in the total number of first voids 3 a, second voids 3 b, and third voids 3 c between those observation regions is preferably 5 or less. This indicates that there is little variation in the number of voids between adjacent observation regions. By suppressing the variation in the number of voids, good insulation can be obtained even when the ceramic substrate 1 is enlarged. Therefore, according to the embodiment, good insulation can be obtained even when the long side of the ceramic substrate 1 is 100 mm or more, or even 150 mm or more.

[0060] Although there is no particular limitation on the upper limit of the long side of the ceramic substrate 1, it is preferably 300 mm or less. If the long side exceeds 300 mm, the productivity of the ceramic substrate 1 may decrease. Therefore, the length of the long side of the ceramic substrate 1 is preferably within a range of 100 mm or more and 300 mm or less, and more preferably within a range of 120 mm or more and 250 mm or less.

[0061] The large ceramic substrate 1 is suitable for multi-cavity production. Multi-cavity production is a method of dividing a large ceramic substrate into pieces of the required size to obtain a plurality of ceramic substrates. By performing multi-cavity production, mass productivity can be improved. The length of the long side of each divided ceramic substrate 1 may be less than 100 mm.

[0062] The ceramic substrate 1 described above can be used for a ceramic bonded body. The ceramic bonded body according to the embodiment includes the ceramic substrate 1 according to the embodiment and a metal portion provided thereon.

[0063] FIG. 5 is a side view showing an example of a ceramic bonded body according to an embodiment. In FIG. 5, reference numeral 1 denotes a ceramic substrate, reference numeral 7 denotes a metal portion, reference numeral 8 denotes a bonding layer, and reference numeral 9 denotes a ceramic bonded body. In the example shown in FIG. 5, two metal portions 7 are bonded to the front side of the ceramic substrate 1, and one metal portion 7 is bonded to the back side of the ceramic substrate 1. The ceramic bonded body 9 according to the embodiment is not limited to this configuration. For example, one metal portion 7 may be provided on the front side of the ceramic substrate 1, or three or more metal portions 7 may be provided. Furthermore, by providing a circuit shape to the metal portion 7 on the front side, it can be used as a circuit portion. The metal portion 7 on the back side can be used as a heat sink. Alternatively, the metal portion 7 on the back side of the ceramic substrate 1 may be used as a circuit portion.

[0064] The metal portion 7 is preferably a metal plate. The metal plate is, for example, a copper plate (including a copper alloy plate) or an aluminum plate (including an aluminum alloy plate). The thickness of the metal plate is preferably 0.2 mm or more, and more preferably 0.8 mm or more. Increasing the thickness of the metal plate can improve heat dissipation and current-carrying capacity. In particular, when a power semiconductor element is mounted, a thick metal plate is preferable. There is no particular upper limit to the thickness of the metal plate, but 3 mm or less is preferable. If the thickness of the metal plate exceeds 3 mm, it may be difficult to impart an inclined shape to the side surface of the metal plate by etching. For this reason, the thickness of the metal plate is preferably 0.2 mm or more and 3 mm or less, and more preferably 0.8 mm or more and 2 mm or less.

[0065] When the ceramic bonded body 9 is used as a circuit board, the metal portion 7 may be provided with a circuit shape by etching after being bonded to the ceramic substrate 1. Alternatively, the metal portion 7 may be pre-processed into a circuit shape and then bonded to the ceramic substrate 1.

[0066] The bonding layer 8 may be, for example, an active metal bonding layer. When the metal plate is a copper plate, the active metal bonding layer contains titanium (Ti). The active metal bonding layer contains, as a component other than Ti, one or more selected from silver (Ag), copper (Cu), tin (Sn), and indium (In). When the metal plate is an aluminum plate, the active metal bonding layer contains, for example, one or more selected from aluminum (Al), silicon (Si), and magnesium (Mg).

[0067] By mounting a semiconductor element on the ceramic bonded body according to the embodiment, a semiconductor device can be obtained.

[0068] Fig. 6 is a side view showing an example of a semiconductor device according to an embodiment. In Fig. 6, reference numeral 10 denotes a semiconductor element. Reference numeral 11 denotes a semiconductor device. In the example shown in Fig. 6, the semiconductor element 10 is mounted on one of the plurality of metal parts 7 on the front side. A semiconductor element 10 may be mounted on each of the metal parts 7 on the front side. The semiconductor element 10 may be mounted on one of the metal parts 7, and a lead frame or a metal terminal may be mounted on another metal part 7.

[0069] According to the embodiment, the ratio of the accumulated charge amount Q25(600) / Q25(5) of the ceramic bonded body can be set within a range of 1.0 to 3.0. The value of the accumulated charge amount Q25(5) varies depending on the size of the metal part 7. As described above, a φ40 mm electrode is used to measure the accumulated charge amount of the ceramic substrate 1. When the electrode size is φ40 mm, the accumulated charge amount Q25(5) is 0.5 μC or less. This value is calculated proportionally depending on the size (bonding area) of the metal part 7 when measuring the accumulated charge amount of the ceramic bonded body. For example, if metal parts 7 of 30 mm × 50 mm are provided on both sides of the ceramic substrate 1, the bonding area of ​​the metal parts 7 is 30 mm × 50 mm = 1500 mm. ２ When a φ40 mm electrode is brought into contact with the ceramic substrate 1, the contact area is 20 mm × 20 mm × 3.14 = 1256 mm ２ From the calculation of 1500:X=1256:0.5, X=0.597 is obtained. That is, when a metal portion 7 of 30 mm×50 mm is provided, the amount of accumulated charge Q25(5) is 0.597 μC or less.

[0070] If the sizes of the metal portions 7 on the front and back sides of the ceramic substrate 1 are different, the accumulated charge amount Q25(5) is calculated based on the size of the metal portion 7 with the smaller area. For example, if a 30 mm x 50 mm metal portion 7 is provided on the front side of the ceramic substrate 1 and an 80 mm x 100 mm metal portion 7 is provided on the back side, the accumulated charge amount Q25(5) is calculated based on the 30 mm x 50 mm metal portion 7. As a result, as in the above example, the accumulated charge amount Q25(5) is calculated to be 0.597 μC or less.

[0071] According to the embodiment, the ratio of the amount of stored charge at the driving voltage of the semiconductor element is controlled. Therefore, the ceramic substrate 1 according to the embodiment has excellent long-term reliability. As described above, the driving voltage of the power card is designed to be around 1 kV. Generally, the driving voltage of the power card is designed to be 0.6 kV or more and 1.4 kV or less (rounded to 1 kV). The DC electric field of 5 kV / mm is a condition assuming the driving voltage of the semiconductor element. Therefore, the ratio of stored charge is suitable as an indicator of long-term reliability under practical conditions.

[0072] Next, a method for manufacturing the ceramic substrate 1 according to the embodiment will be described. The method for manufacturing the ceramic substrate 1 according to the embodiment is not particularly limited as long as it has the above-described configuration. Here, a method for obtaining the ceramic substrate 1 with a high yield will be described.

[0073] First, silicon nitride powder and sintering aid powder are prepared as raw materials. Silicon nitride powder produced by imide decomposition or direct nitridation is used. The average particle size of the silicon nitride powder is preferably in the range of 0.1 μm to 4 μm. The sintering aid is one or more selected from rare earth elements, titanium (Ti), hafnium (Hf), magnesium (Mg), calcium (Ca), tungsten (W), and molybdenum (Mo). Compounds of these elements may also be used. Examples of compounds include oxides, nitrides, oxynitrides, and silicon nitrides. Examples of rare earth elements include yttrium (Y) and lanthanoid elements. Examples of lanthanoid elements include ytterbium (Yb), erbium (Er), europium (Eu), lutetium (Lu), lanthanum (La), cerium (Ce), and dysprosium (Dy). The average particle size of the sintering aid powder is preferably in the range of 0.1 μm to 4 μm.

[0074] It is preferable to control the amounts of impurities contained in the silicon nitride powder and the sintering aid powder. Examples of impurities to be controlled include Fe and carbon. The mixed silicon nitride powder and sintering aid powder are called the raw material mixed powder. The Fe content of the raw material mixed powder is preferably 0% by mass or more and 0.05% by mass or less. The carbon content of the raw material mixed powder is preferably 0% by mass or more and 0.5% by mass or less.

[0075] Fe and carbon present as impurities in the raw material powder mixture can lead to the formation of structural defects in the sintered body. For example, Fe dissolves into the liquid phase during sintering, significantly reducing the liquid phase viscosity of the dissolved area. In liquid phase sintering, densification progresses through grain boundary diffusion. In areas where the liquid phase viscosity is reduced, the rate of grain boundary diffusion changes, making it more likely that defects such as voids will form. Iron contained as an impurity is particularly likely to cause voids. Carbon also has a strong reducing effect, making it more likely that defects such as voids will form.

[0076] In order to control the Fe and carbon contents of the raw material mixed powder, it is effective to use silicon nitride powder and sintering aid powder with low Fe and carbon contents. Methods to prevent the incorporation of impurities during the manufacturing process are also effective. When the raw material mixed powder contains a large amount of Fe, it is also effective to remove the Fe using a magnet. By controlling the Fe and carbon contents, a void distribution that has little effect on arc discharge characteristics and stored charge can be obtained.

[0077] It is also effective to control the fluorine (F) or chlorine (Cl) present as impurities in the raw material mixed powder. The total content of fluorine and chlorine in the raw material mixed powder is preferably 0 wtppm or more and 1000 wtppm or less. The total content of fluorine or chlorine in the sintered body is preferably 0 wtppm or more and 1000 wtppm or less.

[0078] Fluorine and chlorine are elements that are easily contained in silicon nitride powder. Silicon nitride powder is mainly produced by the imide decomposition method or the direct nitridation method. In the imide decomposition method, silicon halide is used as the raw material. In the direct nitridation method, a fluorine compound is used as a catalyst to nitride metallic silicon. For this reason, fluorine or chlorine tends to remain in the silicon nitride powder.

[0079] Furthermore, due to the high electronegativity of fluorine or chlorine, anion defects are likely to occur in the sintered body. Therefore, these elements may have a significant impact on arc discharge characteristics and stored charge. Therefore, the total fluorine or chlorine content in the raw material mixed powder is preferably in the range of 0 wtppm to 1000 wtppm, more preferably in the range of 0 wtppm to 400 wtppm. This allows the fluorine or chlorine content in the silicon nitride sintered body to be 1000 wtppm or less, and even 0 wtppm to 400 wtppm.

[0080] The total sodium content of the silicon nitride powder and the sintering aid powder is preferably 0 wtppm or more and 500 wtppm or less. Sodium is easily mixed in during processes using water. Examples of processes using water include water washing processes for raw materials or substrates and cleaning processes for manufacturing equipment.

[0081] When producing an aluminum nitride substrate, an aluminum oxide substrate, or a zirconium oxide substrate, it is also preferable to control the amounts of iron, carbon, fluorine, chlorine, and sodium in the raw material powder.

[0082] A mixing process is performed in which the raw material powder mixture, consisting of silicon nitride powder and sintering aid powder, is further mixed using a mill. Examples of mills include a ball mill or a bead mill. In the mixing process, a binder and a solvent are added to the raw material powder mixture to produce a raw material powder slurry. It is also preferable to suppress the hysteresis of the raw material powder slurry. Controlling the thixotropy is an effective way to suppress the hysteresis of the slurry. Thixotropy is the property in which the apparent viscosity decreases over time when a constant shear stress is applied, and gradually recovers when the force is removed. The apparent viscosity is thought to reflect the internal structure of the slurry, such as its aggregation state. JIS-R-1665 (2005) specifies the evaluation of thixotropy by measuring the hysteresis of the flow curve.

[0083] To suppress the hysteresis of the slurry, it is effective to bring the thixotropy index (TI value), which is an index of thixotropy, closer to 1. To bring the thixotropy index closer to 1, for example, it is preferable to lower the particle concentration in the slurry and use a good solvent for particle dispersibility. A good solvent has a high affinity with the particle surface, making it possible to stably disperse particles. Therefore, it is easy to achieve a state in which particles are uniformly dispersed in the slurry. Furthermore, a low particle concentration in the slurry reduces the interaction between particles, allowing for uniform particle dispersion. As a result, the particle distribution in the compact can be made relatively uniform and dense. Voids are less likely to occur during sintering densification, and the void distribution can be controlled. The thixotropy index (TI value) is preferably less than 1.5.

[0084] The TI value is measured using a rotational viscometer in accordance with JIS-R-1665 (2005). When the shear rate is continuously increased using a rotational viscometer, the viscosity of a fluid with aggregation generally decreases. In this case, the ratio of the viscosity η at shear rate a to the viscosity η at shear rate b is the TI value. In other words, the TI value is expressed by the following formula: TI value = ηa / ηb

[0085] The viscosity η is measured with the shear rate a set to 4 (1 / s), and the viscosity η is measured with the shear rate b set to 40 (1 / s). The TI value is calculated from ηa / ηb. The closer the TI value is to 1, the closer it is to the behavior of a Newtonian fluid, meaning that it is a highly dispersed slurry with no or very weak aggregation. The shear rates a and b can be any value within the range of a<b, but it is preferable that b is 10 times or more greater than a.

[0086] A TI value of less than 1.5 indicates that the slurry has low cohesion. By suppressing cohesion, it is possible to reduce voids in the molded body and control the void distribution. The lower limit of the TI value is not particularly limited, but a value of 1.0 or more is preferable. If the TI value is less than 1.0, a strong cohesion state called dilatant may be present, which may have an adverse effect on sheet molding. For this reason, the TI value of the slurry is preferably in the range of 1.0 or more and less than 1.5, and more preferably in the range of 1.0 or more and 1.2 or less. The TI value of the slurry is the average value of three measurements. Three measurement samples are randomly taken from the same slurry.

[0087] A molded body is produced using a slurry with a controlled TI value. For the molding process, known molding methods such as doctor blade molding and metal molding can be used. The production of a sheet-shaped molded body is called sheet molding.

[0088] Next, a drying step is performed to dry the compact. For example, the drying step is performed within a range of room temperature to 150° C. Regarding the drying step, it is preferable to derive the constant rate drying period and the falling rate drying period from the weight loss behavior of the solvent, and set the temperature and time of the drying step based on the constant rate drying period and the falling rate drying period.

[0089] At the beginning of drying, there is a sufficient amount of solvent in the ceramic compact. Therefore, the solvent is connected at the interface of the ceramic particles that make up the compact, forming a continuous layer. The constant rate drying period is the process in which drying progresses from the continuous layer state mentioned above. The constant rate drying period is the period in which the solvent in the ceramic compact evaporates at an almost constant rate through the continuous layer.

[0090] On the other hand, the falling-rate drying period is the process in which drying progresses after the constant-rate drying period. Because there is little solvent, there are areas around the ceramic particles where there is no solvent. The falling-rate drying period is a period in which the continuous solvent layer is broken and the solvent inside the ceramic compact evaporates. During the transition period from the constant-rate drying period to the falling-rate drying period, the shrinkage stress on the compact is at its maximum. For this reason, controlling the constant-rate drying period, falling-rate drying period, and transition period leads to the control of voids.

[0091] The weight loss rate of the solvent during the constant rate drying period is preferably 0.2% by mass / min or more. The upper limit of the weight loss rate of the solvent during the constant rate drying period is not particularly limited, but is preferably 2% by mass / min or less. If the weight loss rate exceeds 2% by mass / min, voids may become large. Therefore, the weight loss rate of the solvent during the constant rate drying period is preferably in the range of 0.2% by mass / min or more and 2% by mass / min or less, and more preferably in the range of 0.3% by mass / min or more and 1.2% by mass / min or less.

[0092] The weight loss rate of the solvent during the falling-rate drying period is preferably slower than the weight loss rate of the solvent during the constant-rate drying period. Furthermore, the ratio of the weight loss rates (weight loss rate of the solvent during the constant-rate drying period / weight loss rate of the solvent during the falling-rate drying period) is preferably greater than 1 and less than 10. This allows the solvent inside the ceramic molded body to evaporate during the falling-rate drying period using the solvent evaporation route formed during the constant-rate drying period. A weight loss rate ratio (weight loss rate of the solvent during the constant-rate drying period / weight loss rate of the solvent during the falling-rate drying period) exceeding 10 can lead to an excessively fast drying rate, potentially resulting in large voids. A slow weight loss rate during the falling-rate drying period reduces production efficiency. The weight loss rate of the solvent during the falling-rate drying period is preferably less than 0.2 mass% / min.

[0093] The constant rate drying period is the period during which the solvent evaporates from the surface of the ceramic compact. The falling rate drying period is the period during which the solvent evaporates from the interior of the ceramic compact. Therefore, it is possible to distinguish between the constant rate drying period and the falling rate drying period. The weight loss rate can be calculated, for example, by measuring the mass of the compact before the drying process and then measuring the mass every 2 to 5 minutes. The compact may be placed on a mass meter and the change in mass may be measured during the drying process.

[0094] The green body that has been subjected to the drying process is then subjected to a degreasing process. The degreasing process is preferably carried out at a temperature in the range of 400°C to 800°C. The degreasing process can remove organic substances such as binders. Any remaining solvent is also removed.

[0095] Next, a sintering step is carried out. In the sintering step, the compact is heated in a non-oxidizing atmosphere within a temperature range of 1650°C to 1950°C for a period of 4 hours to 24 hours. The non-oxidizing atmosphere is preferably a nitrogen gas atmosphere or a reducing atmosphere containing nitrogen gas. The pressure inside the sintering furnace is preferably a pressurized atmosphere. If the compact is sintered at a sintering temperature below 1650°C, it is difficult to obtain a dense sintered body. On the other hand, if the compact is sintered at a sintering temperature higher than 1950°C, Si ３ N ４ Therefore, it is preferable to control the sintering temperature within the above range.

[0096] In the sintering step, it is preferable that the compact is held within a temperature range of 1400° C. to 1650° C. for 1 hour to 8 hours before being held within a temperature range of 1650° C. to 1950° C. This treatment promotes and controls the diffusion of the liquid phase consisting of the sintering aid, leading to the control of voids in the sintered compact.

[0097] In the sintering process, pressure is preferably applied. In particular, by gradually increasing the applied pressure above the liquid phase generation temperature, densification accompanied by the diffusion of the liquid phase can be effectively controlled. For example, from 1400°C to the sintering temperature, the pressure is increased in the range of 0.1 MPa to 0.5 MPa in increments of 50 to 150°C.

[0098] The ceramic substrate 1 according to the embodiment can be obtained through the above steps. According to the embodiment, the ceramic substrate 1 with reduced voids can be obtained without performing hot isostatic pressing (HIP).

[0099] A ceramic bonded body 9 can be manufactured by providing a metal portion on the obtained ceramic substrate 1. The metal portion 7 is, for example, a metal plate, a metallized layer, or a thin film layer. The metal plate is bonded using an active metal bonding method. The metallized layer is formed by applying and firing a metal paste. The main component of the metallized layer is, for example, tungsten, molybdenum, titanium, or silver. The thin film layer is formed by plating or sputtering. The main component of the thin film layer is, for example, gold, silver, or titanium.

[0100] A semiconductor device is obtained by mounting a semiconductor element on the ceramic bonded body 9. The semiconductor device may be provided with a lead frame, wire bonding, sealing resin, etc., as required.

[0101] (Examples 1 to 5, Comparative Examples 1 and 2) A silicon nitride substrate or an aluminum nitride substrate is produced as the ceramic substrate 1. The mixing ratio of the raw material powder (silicon nitride powder or aluminum nitride powder) and the sintering aid powder is as shown in Table 1. The mixing ratio is a value when the total of the raw material powder (silicon nitride powder or aluminum nitride powder) and the sintering aid powder is taken as 100 mass%. In all of the examples and comparative examples, the Fe content in the raw material mixed powder is 0.05 mass% or less, and the carbon content is 0.5 mass% or less. Furthermore, the fluorine content and chlorine content in the raw material mixed powder are each 400 wtppm or less, and the sodium content is 500 wtppm or less.

[0102]

[0103] A raw material powder and a sintering aid powder were mixed to prepare a slurry. In the examples, the TI value of the slurry was controlled to be in the range of 1.0 or more and less than 1.5. In the comparative examples, the TI value of the slurry was set to be greater than 1.5. The TI value was measured in accordance with JIS-R-1665 (2005). The details of the measurement conditions are as described above.

[0104] The obtained sheet molded body was subjected to a drying process. In the examples, the weight loss rate of the solvent during the constant rate drying period was set to a range of 0.2 mass% / min to 2 mass% / min. In addition, in the examples, the ratio of the weight loss rates (weight loss rate of the solvent during the constant rate drying period / weight loss rate of the solvent during the falling rate drying period) was set to a range of more than 1 to 10. The TI value of the slurry, the weight loss rate of the solvent during the constant rate drying period in the drying process, and the weight loss rate ratio (weight loss rate of the solvent during the constant rate drying period / weight loss rate of the solvent during the falling rate drying period) are as shown in Table 2.

[0105]

[0106] The sheet-shaped compact after the drying process was subjected to a degreasing process. The degreasing process was carried out in the air at a temperature range of 400°C to 800°C. The obtained degreasing body was then subjected to a sintering process. During the temperature increase process up to the maximum temperature in the sintering process, the temperature was maintained in a non-oxidizing atmosphere at a temperature range of 1400°C to 1650°C for 1 hour to 8 hours. Thereafter, the temperature was maintained at a temperature range of 1650°C to 1950°C for 4 hours to 24 hours. In the sintering process, the pressure was increased in accordance with the increase in temperature. The relationship between temperature and pressure in the sintering process is as shown in Table 3. In Table 3, the TOP temperature refers to the maximum temperature in the sintering process. In the examples, the TOP temperature was set within a range of 1700°C to 1950°C.

[0107]

[0108] In Examples 1 to 5, the pressure was increased in 100°C increments from 1400°C to the TOP temperature. Table 3 lists the pressure values ​​after the increase. For example, in Example 1, the pressure was increased by 0.18 MPa from 1500 to 1600°C, and set to 0.30 MPa. From 1600 to 1700°C, the pressure was increased by 0.20 MPa, and set to 0.50 MPa. In Comparative Examples 1 and 2, the pressure was increased in 200°C increments.

[0109] Ceramic substrates 1 were fabricated through the above steps. The silicon nitride substrates of Examples 1 to 4 and Comparative Example 1 measured 200 mm long, 150 mm wide, and 0.32 mm thick. The aluminum nitride substrates of Example 5 and Comparative Example 2 measured 150 mm long, 100 mm wide, and 0.635 mm thick. The iron, carbon, fluorine, chlorine, and sodium contents of the resulting ceramic substrates 1 are shown in Table 4.

[0110]

[0111] As can be seen from Table 4, the contents of Fe, F, Cl, Na, and C are reduced to a small amount in both the Examples and Comparative Examples. For example, in Examples 2 and 4, the total content of fluorine and chlorine is 1000 wtppm or less. In Examples 1, 3, and 5 and Comparative Example 2, the total content of fluorine and chlorine is 400 wtppm or less. In Comparative Example 1, the total content of fluorine and chlorine exceeds 1000 wtppm, but the excess amount is small.

[0112] For each ceramic substrate 1, the dielectric breakdown voltage, the accumulated charge ratio Q25(600) / Q25(5), and the presence or absence of arc discharge up to the application of an AC voltage of 6 kV were measured. The measurement conditions were as described above. A measuring electrode with a diameter of 40 mm was used to measure the accumulated charge. The results are shown in Table 5.

[0113]

[0114] As can be seen from Table 5, in each example, the breakdown voltage was 20 kV / mm or higher regardless of whether DC or AC was applied. Furthermore, in each example, the ratio of the accumulated charge amount Q25(600) / Q25(5) was within the range of 1.0 or higher and 3.0 or lower. The accumulated charge amount Q25(5) was within the range of 0.300 μC or higher and 0.500 μC or lower. Furthermore, no arc discharge was detected even when AC voltages up to 6 kV were applied.

[0115] The dielectric breakdown voltage of the ceramic substrates 1 according to Comparative Examples 1 and 2 was equivalent to that of the ceramic substrates 1 according to Examples 1 to 5. However, in Comparative Examples 1 and 2, the ratio of the amount of accumulated charge was large, and arc discharge was also detected when AC voltages up to 6 kV were applied.

[0116] Next, an arbitrary observation area of ​​90 μm×120 μm was set on the cross section of each ceramic substrate 1, and the distribution of voids was measured. ２ The number of voids less than 10 ...

[0117]

[0118] As can be seen from Table 6, in Examples 1 to 5, in the observation area of ​​90 μm × 120 μm, ２ The number of voids smaller than 1 μm was 29 or less. ２ The number of voids was very small, ranging from 0 to 3. It can be seen that in Examples 1 to 5, voids were controlled without HIP treatment. Furthermore, in Examples 1 to 5, the difference in the number of voids between adjacent observation areas was kept to 5 or less. This shows that the variation in the number of voids between observation areas was also suppressed.

[0119] On the other hand, in Comparative Examples 1 and 2, the number of first to third voids was very large. Therefore, the shortest distance between the second voids was also less than 5 μm. There was also a large difference in the number of voids between adjacent observation areas.

[0120] These results show that controlling the amount of impurities and voids in the raw material mixed powder is effective in controlling the breakdown voltage, the accumulated charge ratio, and the arc discharge voltage. Furthermore, according to the example, no arc discharge occurs even when an AC voltage of 6 kV is applied, so deterioration of the ceramic substrate 1 due to arc discharge can be prevented. Therefore, by using the ceramic substrate 1 according to the example in a semiconductor device, the long-term reliability of the semiconductor device can be improved.

[0121] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0122] DESCRIPTION OF SYMBOLS 1... Ceramic substrate 2... Cross section 3a... First void 3b... Second void 3c... Third void 5... Ceramic crystal particle 6... Shortest distance between voids 7... Metal part 8... Bonding layer 9... Ceramic bonded body 10... Semiconductor element 11... Semiconductor device

Claims

1. A ceramic substrate in which no arc discharge is detected when a 50 Hz or 60 Hz AC voltage is applied between the front and back surfaces from 0 kV to 6 kV at a voltage increase rate of 200 V / s.

2. The ceramic substrate according to claim 1, having a dielectric breakdown voltage of 20 kV / mm or more.

3. The ceramic substrate according to claim 2, which has a breakdown voltage of 20 kV / mm or more when a DC electric field or an AC electric field is applied.

4. A ceramic substrate according to any one of claims 1 to 3, wherein when a DC electric field of 5 kV / mm is applied at 25°C, the ratio of the accumulated charge amount Q25(600) after 600 seconds to the accumulated charge amount Q25(5) after 5 seconds is 1.0 or more and 3.0 or less.

5. The ceramic substrate according to any one of claims 1 to 4, which is a silicon nitride substrate.

6. In at least one observation area of ​​90 μm × 120 μm included in any cross section of the ceramic substrate, an area of ​​0.1 μm ２ The number and area of ​​primary voids less than 0.1 μm ２ 1 μm or more ２ The total number of second voids that are less than 29 and have an area of ​​1 μm ２ The ceramic substrate according to any one of claims 1 to 5, wherein the number of the third voids is 0 or more and 3 or less.

7. In at least one observation area of ​​90 μm × 120 μm included in the cross section, an area of ​​1 μm ２ The ceramic substrate according to claim 6 , wherein the third void is not present.

8. The ceramic substrate according to claim 6 or 7, wherein the number of the second voids is 10 or less in at least any observation region of 90 μm×120 μm included in the cross section.

9. A ceramic substrate according to any one of claims 6 to 8, wherein the shortest distance between the second voids is 5 µm or more in at least one observation region of 90 µm x 120 µm included in the cross section.

10. The ceramic substrate according to any one of claims 6 to 9, wherein in at least one observation region of 90 μm × 120 μm included in the cross section, three or more ceramic crystal grains are present on a straight line connecting voids having an area of ​​1 μm or more along the shortest distance.

11. A ceramic substrate according to any one of claims 6 to 10, wherein when the total number of the first voids, the second voids, and the third voids is counted in each of two adjacent 90 μm x 120 μm observation regions in the cross section, the difference in the total number between the two 90 μm x 120 μm observation regions is 5 or less.

12. A ceramic bonded body comprising: a ceramic substrate according to any one of claims 1 to 11; and a metal part provided on the ceramic substrate.

13. A semiconductor device comprising: the ceramic bonded body according to claim 12; and a semiconductor element mounted on the metal part.

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