Data driving device of display device and method for driving data driving device

Abstract

A method for driving a data driving device of the present specification may comprise the steps of: mapping various image data for displaying a result obtained by interfacing with a CFG; storing CFG information including CDR BW configuration information and EQ configuration information; generating a CDR error signal and an EQ error signal by using the CFG information; when at least one error signal among the CDR error signal and the EQ error signal is generated, displaying, on a display panel, image data corresponding to the at least one generated error signal among the mapped various image data; and when no error signal is generated, displaying, on the display panel, image data indicating that no error has occurred among the mapped various image data.

Description

Data driving device of display device and driving method of data driving device

[0001] This specification relates to a display device, and more specifically, to a data driving device and a data driving method of the display device.

[0002] Video display devices, which display a variety of information on a screen, are a core technology of the information and communication age. They are evolving toward thinner, lighter, more portable, and higher performance. Accordingly, display devices that can be manufactured in a lightweight and thin form factor are attracting attention.

[0003] Specific examples of such display devices include a liquid crystal display apparatus (LCD), a quantum dot display apparatus (QD), a field emission display apparatus (FED), and an organic light emitting diode (OLED).

[0004] Such a display device may include a data processing device, referred to as a timing controller, and a data driving device, referred to as a source driver. Image data may be transmitted from the data processing device to the data driving device. The image data is transmitted as a digital signal, and the data driving device converts the image data received as a digital signal into an analog voltage to drive each pixel of the display panel. Accordingly, the data processing device and the data driving device may exchange signals with each other through a communication line.

[0005] Recently, as display panels have become larger and have higher resolutions, both the number of pixels placed on the display panel and the frame rate have increased. In order to process the increased amount of image data due to larger and higher resolutions, data communication in the display device needs to be accelerated.

[0006] This type of high-speed data communication can result in a higher data loss rate than low-speed data communication. Therefore, the data processing device transmits various configuration data required for high-speed data communication to the data drive device via low-speed data communication.

[0007] However, errors may occur in the communication between the data processing device and the data driving device.

[0008] The problem to be solved by this specification is to provide a data driving device of a display device and a driving method of the data driving device that can display setting data and interface operation results on a display panel so that they can be visually confirmed without a separate protocol.

[0009] The tasks of this specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0010] According to one embodiment of the present specification, a data driving device of a display device may include an auto-tuning unit that receives data from a data processing device, restores a clock signal, compares the restored clock signal with a plurality of set CDR BWs, outputs a CDR error signal, receives an EQ tuning signal from the data processing device, tunes it, compares the restored clock signal with a plurality of set EQ information, and outputs an EQ error signal; a high-speed communication unit that processes and outputs image data received from the data processing device using the restored clock signal; a low-speed communication unit that receives a setting data signal for a high-speed communication environment from the data processing device; a first register that stores and selectively outputs the CDR error signal or the EQ error signal output from the auto-tuning unit; a color mapping unit that stores image data for displaying an interface result with the data processing device on a display panel and outputs at least one image data from the stored image data according to a signal output from the first register; and a multiplexer that selects and outputs one of the image data output from the high-speed communication unit or the image data output from the color mapping unit.

[0011] A driving method of a data driving device according to one embodiment of the present specification may include a step of mapping various image data for displaying an interface result with a data processing device, a step of storing CFG information including CDR BW setting information and EQ setting information, a step of generating a CDR error signal and an EQ error signal using the CFG information, a step of displaying corresponding image data among the various mapped image data on a display panel when at least one error signal among the CDR error signal and the EQ error signal is generated, and a step of displaying image data indicating that no error has occurred among the various mapped image data on the display panel when no error signal is generated.

[0012] Specific details of other embodiments are included in the detailed description and drawings.

[0013] According to this specification, without a separate protocol, after setting output options within Configuration or Display Mode, information from the receiver, rather than input RGB data, can be output to the panel for visual confirmation during the Pixel Data period of Display Mode. This can be expected to improve readability and shorten evaluation time during evaluation.

[0014] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0015] FIG. 1 is a block diagram illustrating a display device according to one embodiment of the present specification.

[0016] FIG. 2 is a configuration diagram of a data processing device and a plurality of data driving devices of a display device according to one embodiment of the present specification.

[0017] FIG. 3 is an example diagram of a signal sequence between a data processing device and a data driving device for explaining an Overall Timing Sequence according to one embodiment of the present specification.

[0018] FIG. 4 is a block diagram of a data drive device according to one embodiment of the present specification.

[0019] FIG. 5 is an example diagram of a signal sequence specifically indicating the Vertical Blank Region and Vertical Active Region of the Display Mode according to one embodiment of the present specification.

[0020] FIG. 6 is an operational flowchart for explaining the operation of a data driving device according to one embodiment of the present specification.

[0021] FIG. 7 is an explanatory diagram of a state in which CFG and interface operation results are displayed on a display panel according to one embodiment of the present specification.

[0022] Hereinafter, preferred embodiments of the present disclosure will be described with reference to the attached drawings. Throughout the specification, the same reference numbers denote substantially identical components.

[0023] In the following description, if a detailed description of a technology or configuration related to this specification is deemed to unnecessarily obscure the gist of this specification, such detailed description will be omitted. Furthermore, the component names used in the following description have been selected for ease of specification writing and may differ from the names of actual product components.

[0024] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining various embodiments of this specification are merely examples, and thus this specification is not limited to the matters depicted in the drawings. Like reference numerals throughout this specification denote like components.

[0025] In addition, in describing this specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of this specification, the detailed description is omitted.

[0026] In the specification, when "includes," "has," and "consists of" are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes cases where the plural is included unless there is a special explicit description.

[0027] In interpreting the components included in various embodiments of this specification, they are interpreted to include a range of errors even if there is no separate explicit description.

[0028] In describing various embodiments of this specification, when describing a positional relationship, for example, when the positional relationship between two parts is described as ‘on’, ‘above’, ‘below’, ‘next to’, etc., one or more other parts may be located between the two parts unless ‘right’ or ‘directly’ is used.

[0029] In describing various embodiments of this specification, when describing a temporal relationship, for example, when a temporal relationship is described as ‘after’, ‘following’, ‘next to’, ‘before’, etc., cases where it is not continuous may also be included, unless ‘immediately’ or ‘directly’ is used.

[0030] In describing various embodiments of this specification, terms such as 'first~', 'second~', etc. may be used to describe various components, but these terms are only used to distinguish between identical or similar components. Accordingly, unless otherwise stated, components described as 'first~' in this specification may be identical to components described as 'second~' within the technical spirit of this specification.

[0031] Each of the features within the various embodiments of this specification may be partially or wholly combined or combined with one another, and may be technically capable of various interconnections and operations, and each of the various embodiments may be implemented independently of one another or may be implemented together in a related relationship.

[0032] Hereinafter, a display device according to an embodiment of the present specification will be described with reference to the drawings.

[0033] FIG. 1 is a block diagram illustrating a display device according to one embodiment of the present specification.

[0034] A display device according to one embodiment of the present specification may include a display panel (110), a data driving device (120), a gate driving device (130), and a data processing device (140; or timing controller), as illustrated in FIG. 1.

[0035] The display panel (110) may be provided with a plurality of gate lines (GL) and a plurality of data lines (DL) intersecting the plurality of gate lines (GL). A plurality of pixels may be arranged in a matrix form in an area where the plurality of gate lines (GL) and the plurality of data lines (DL) intersect.

[0036] Each pixel can be composed of multiple sub-pixels (SP). For example, the sub-pixels can include R (red), G (green), B (blue), W (white), etc. One pixel can be composed of three sub-pixels (SP) of R, G, and B, or four sub-pixels (SP) of R, G, B, and G, or four sub-pixels (SP) of R, G, B, and W, etc. In the following, for convenience of explanation, one unit pixel is described as being composed of three sub-pixels of R, G, and B.

[0037] The data driving device (120), the gate driving device (130), and the data processing device (140) are devices that generate signals for displaying an image on the display panel (110).

[0038] The gate driving device (130) can sequentially supply a gate driving signal of a turn-on voltage or a turn-off voltage to a plurality of gate lines (GL). When the gate driving signal of the turn-on voltage is supplied to the sub-pixel (SP), the sub-pixel (SP) can receive the data voltage supplied through the data line (DL). In addition, when the gate driving signal of the turn-off voltage is supplied to the sub-pixel (SP), the sub-pixel (SP) blocks reception of the data voltage supplied to the data line (DL). The gate driving device (130) may be referred to as a gate driver.

[0039] The data driving device (120) can supply a data voltage (Vp) to a sub-pixel (SP) through a data line (DL) in synchronization with a gate driving signal. The data driving device (120) may be referred to as a source driver.

[0040] The data driving device (120) may include at least one integrated circuit. The at least one integrated circuit may be connected to a bonding pad of the display panel (110) as a tape automated bonding (TAB) type or a chip on glass (COG) type, or may be formed directly on the display panel (110), and may be formed by being integrated into the display panel (110) according to an embodiment. In addition, the data driving device (120) may be implemented as a chip on film (COF) type.

[0041] The data processing device (140) can supply control signals to the gate driving device (130) and the data driving device (120). For example, the data processing device (140) can transmit a gate control signal (GCS) to the gate driving device (130) to initiate scanning.

[0042] The data processing device (140) can output image data to the data driving device (120). In addition, the data processing device (140) can transmit a data control signal that controls the data driving device (120) to supply a data voltage (Vp) to each sub-pixel (SP). The data processing device (140) may be referred to as a timing controller.

[0043] The data processing device (140) can transmit image data and data control signals to the data driving device (120) using a first protocol signal (PS1) having a built-in clock.

[0044] The data processing device (140) and the data driving device (120) can perform high-speed data communication using the first protocol signal (PS1). Such high-speed data communication may result in a higher data loss rate compared to low-speed data communication. Accordingly, the data processing device (140) can transmit various configuration data of the data driving device (120) required for high-speed data communication to the data driving device (120) through low-speed data communication.

[0045] In other words, the data processing device (140) transmits the setting data of the data driving device (120) to the data driving device (120) through low-speed data communication with a low data loss rate, so that the data driving device (120) can accurately receive the setting data.

[0046] The setting data of the data driving device (120) as described above may include the basic gain level of the equalizer included in the data driving device (120), scramble information, line polarity information, etc. Here, the scramble information may include information on whether the data processing device (140) transmits the data as is or scrambles the data when transmitting the data to the data driving device (120), and the line polarity information may include information indicating the polarity of each line of the pixel.

[0047] The data processing device (140) can perform such low-speed data communication via the second protocol signal (PS2). The data processing device (140) can transmit the first protocol signal (PS1) and the second protocol signal (PS2) to the data driving device (120) via the first communication line (LN1).

[0048] The data processing device (140) can transmit signals to the data driving device (120) via the first communication line (LN1) to optimize high-speed data communication. For example, the data processing device (140) can transmit a tuning signal to an equalizer of the data driving device (120), and the data driving device (120) can use this tuning signal to optimally tune the gain, etc., of the equalizer.

[0049] The data driving device (120) can generate status data on the reception status of specific information transmitted through the first protocol signal (PS1) and / or the second protocol signal (PS2), and display the status data on the display panel (110) using the same.

[0050] The data processing device (140) and the data driving device (120) can perform one-to-one communication through the first communication line (LN1).

[0051] When a plurality of data driving devices (120) are configured, the data driving devices may be connected in a cascade configuration by connecting a second communication line (LN2) between adjacent data driving devices. However, this is not limited to this and the data driving devices may be connected in an open drain configuration.

[0052] FIG. 2 is a configuration diagram of a data processing device and a plurality of data driving devices of a display device according to one embodiment of the present specification.

[0053] A display device according to one embodiment of the present specification may include at least one data processing device (140) and a plurality of data driving devices (120a, 120b, 120c, 120d), as illustrated in FIG. 2.

[0054] The data processing device (140) may be placed on a first PCB (PCB1, printed circuit board). In addition, the data processing device (140) may be connected to a plurality of data driving devices (120a, 120b, 120c, 120d) via a communication line (LN1) and a second communication line (LN2).

[0055] A first communication line (LN1) and a second communication line (LN2) can be connected to a plurality of data driving devices (120a, 120b, 120c, 120d) via a first PCB (PCB1) and a second PCB (PCB2). The first PCB (PCB1) and the second PCB (PCB2) can be connected via a first film (FL1) made of a flexible material. The first communication line (LN1) and the second communication line (LN2) can be extended from the first PCB (PCB1) to the second PCB (PCB2) via the first film (FL1).

[0056] Each data driving device (120a, 120b, 120c, 120d) may be placed on a second film (FL2) in the form of a chip-on-film (COF). The second film (FL2) may be a flexible material support substrate connecting the second PCB (PCB2) and the display panel (110). The first communication line (LN1) and the second communication line (LN2) may extend from the second PCB (PCB2) to each data driving device (120a, 120b, 120c, 120d) via the second film (FL2).

[0057] The first communication line (LN1) can be connected one-to-one between the data processing device (140) and the data driving devices (120a, 120b, 120c, 120d).

[0058] The second communication line (LN2) may be connected between each data driving device (120a, 120b, 120c, 120d) or between the data driving device (120d) and the data processing device (140) without overlapping the first communication line (LN1) in a plane. For example, the first data driving device (120a) may be connected to the second data driving device (120b) via the second communication line (LN2), and the second data driving device (120b) may be connected to the third data driving device (120c) via the second communication line (LN2). At this time, the second data driving device (120b) and the third data driving device (120c) may be connected to different second PCBs (PCB2). Accordingly, the second communication line (LN2) arranged therebetween can connect the second data driving device (120b) and the third data driving device (120c) via the second PCB (PCB2), the first film (FL1), and the first PCB (PCB1). The third data driving device (120c) can be connected to the fourth data driving device (120d) via the second communication line (LN2), and the fourth data driving device (120d) can be connected to the data processing device (140) via the second communication line (LN2).

[0059] As described above, the data processing device (140) and the data driving device (120a, 120b, 120c, 120d) can communicate with each other through the first communication line (LN1) and the second communication line (LN2).

[0060] Here, the communication frequency between the data processing device (140) and the data driving devices (120a, 120b, 120c, 120d) may not be predetermined. In other words, the communication circuit of the data driving devices (120a, 120b, 120c, 120d) may not be adjusted to the communication frequency of the data processing device (140).

[0061] In Fig. 2, the data processing device (140) and the data driving devices (120a, 120b, 120c, 120d) are shown to be connected in a cascade manner, but this is not limited thereto. The data processing device (140) and each data driving device (120a, 120b, 120c, 120d) may be connected in a multi-drop manner in which the first communication line (LN1) and the second communication line (LN2) are independently connected.

[0062] FIG. 3 is an example diagram of a signal sequence between a data processing device and a data driving device for explaining an Overall Timing Sequence according to one embodiment of the present specification.

[0063] Referring to FIG. 3, the display device can operate in Configuration Mode, Auto Compensation Mode, and Display Mode. Configuration Mode is a low-speed communication mode, and Auto Compensation Mode and Display Mode can be high-speed communication modes.

[0064] Configuration Mode is a standby mode in which the display device can prepare to transmit and receive image data. In Configuration Mode, the display device can transmit setting data for high-speed data communication via low-speed data communication.

[0065] The data drive device (120) can enter Configuration Mode after power-on. The data drive device (120) can receive Configuration Option (CFG) information of the data drive device (120), which is essential for stabilizing high-speed data communication operation.

[0066] The section corresponding to the low-speed communication mode of the data processing device (140) and the data driving device (120) in the configuration mode may include a preamble section and a CFG phase section.

[0067] In the preamble section, the data processing device (140) can transmit a low-speed communication clock signal to the data driving device (120). The data driving device (120) can perform low-speed clock training using the low-speed communication clock signal and receive low-speed data using the trained low-speed communication clock.

[0068] In the CFG Phase section, the data processing device (140) can transmit a setup data (CFG) signal to the data driving device (120). In the CFG Phase section, the data driving device (120) can receive the setup data (CFG) signal using the aforementioned low-speed communication clock, and set a circuit part for high-speed data communication using the setup data included in the setup data signal.

[0069] The data processing device (140) can transmit active setup data (Active CFG) and check setup data (Check CFG) signals to the data driving device (120) during the CFG Phase section. Here, the check setup data (Check CFG) is data retransmitted to check whether the active setup data (Active CFG) has been received correctly.

[0070] Here, the setting data (CFG) may include basic gain level, scramble information, and line polarity information of the equalizer included in the data driving device (120). In addition, it may further include a plurality of CDR (clock data recovery) BW (bandwith) setting information used in the CDR tuning section described later, a plurality of EQ (equalizer) setting information used in the equalizer tuning section, and BERT setting information for a bit error rate test.

[0071] In Auto Compensation Mode, the data driving device (120) can perform evaluation and tuning for multiple CDR BWs set in Configuration Mode (Auto CDR BW Tuning). In addition, it can perform evaluation and tuning for multiple EQ (Equalizer) DC / AC Gains (N*N levels) set in Configuration Mode (Auto EQ BW Tuning).

[0072] In Display Mode, the display device can set the internal circuit of the data driving device (120) to operate at a frequency that enables high-speed data communication between the data processing device (140) and the data driving device (120).

[0073] That is, when entering the Vertical Blank Region, a frame control packet (FCP) can be transmitted. When entering the Active Region, line configuration and active data can be transmitted. In addition, in Display Mode, the display device can optimize the operation and characteristics of the CDR (clock data recovery) and equalizer (EQ) to improve signal quality.

[0074] In Display Mode, you can use the Line / Frame Control Packet to set display-related options for the receiver and output video data.

[0075] As illustrated in Fig. 1, when a driving voltage (VCC) is supplied to the data processing device (140) and the data driving device (120), the data processing device (140) can transmit a second protocol signal (PS2) to the data driving device (120) in the Configuration Mode. Thereafter, the data processing device (120) can transmit a first protocol signal (PS1) in the AUTO Compensation Mode and the Display Mode. The first protocol signal (PS1) and the second protocol signal (PS2) can be transmitted through the communication line (LN1).

[0076] Here, the second protocol signal (PS2) may be a signal based on a second protocol agreed upon between the data processing device (140) and the data driving device (120), and may be a signal according to a low-speed data communication protocol. The first protocol signal (PS1) may be a signal based on a first protocol agreed upon between the data processing device (140) and the data driving device (120), and may be a signal according to a high-speed data communication protocol.

[0077] The communication frequency of the first protocol signal (PS1) may be at least 10 times higher than the communication frequency of the second protocol signal (PS2). Based on this characteristic, the first protocol signal (PS1) may be classified as a high-speed data communication protocol, and the second protocol signal (PS2) may be classified as a low-speed data communication protocol.

[0078] Meanwhile, in high-speed data communication, the data loss rate may vary significantly depending on the settings of the data drive device (120) on the receiving side. Alternatively, in high-speed data communication, communication may not proceed smoothly depending on the settings on the receiving side.

[0079] In one embodiment of the present specification, before the data processing device (140) and the data driving device (120) perform high-speed data communication, setting data for smoothly performing high-speed data communication can be transmitted to the data driving device (120) via a second protocol signal (PS2) corresponding to low-speed data communication. This is because low-speed data communication does not have a large difference in data loss rate according to the setting of the data driving device (120), and thus the setting data can be transmitted to the data driving device (120) relatively accurately.

[0080] In high-speed data communications such as AUTO Compensation Mode and Display Mode, the data loss rate may vary significantly depending on the settings of the receiver. Alternatively, communication may not proceed smoothly depending on the settings of the receiver in high-speed data communications. Therefore, a display device according to an embodiment of the present disclosure may transmit configuration data from the transmitter to the receiver for smooth high-speed data communications before performing high-speed data communications. This configuration data may be transmitted and received via low-speed data communications such as Configuration Mode. Since low-speed data communications do not have a significant difference in data loss rate depending on the settings of the receiver, the configuration values ​​can be transmitted to the receiver relatively accurately.

[0081] The data processing device (140) can transmit setting data required for high-speed data communication by transmitting a second protocol signal (PS2) corresponding to low-speed data communication before transmitting a first protocol signal (PS1) corresponding to high-speed data communication.

[0082] When the display device is in Display Mode, the Clock Training section, Link Training section, VB section, and Frame section included in the second protocol signal (PS2) can be used. Specifically, the data driving device (120) can perform clock training for the Clock Training section to restore the clock and synchronize transmission and reception between the data processing device (140) and the data driving device (120). The data driving device (120) can perform link training for the Link Training section to check whether data is processed by meaning or link. The data driving device (120) can output image data included in the Frame section and wait for output of image data in the VB section.

[0083] FIG. 4 is a block diagram of a data drive device according to one embodiment of the present specification.

[0084] A data driving device (120) according to one embodiment of the present specification may include an auto-tuning unit (510), a high-speed communication unit (520), a low-speed communication unit (530), a first register (540), an RX control unit (550), a selection unit (560), a configuration comparison unit (570), a second register (580), a color mapping unit (590), a multiplexer (600), and a display logic unit (610), as illustrated in FIG. 4.

[0085] The auto tuning unit (510) can be operated by EQ options, CDR options, and tuning options from the RX control unit (550). The auto tuning unit (510) may include an amplifier unit (511) that receives and amplifies data from the data processing device (140), a clock recovery unit (CDR) (512) that samples a signal from the amplifier unit (511) and restores a clock signal while changing the setting value of an oscillator included therein at regular intervals (Ts), and an EQ / CDR Controller / Cheker unit (513) that selects EQ and CDR hardware options, compares the restored clock signal with a plurality of CDR BWs set in the Configuration Mode, and outputs the number of CDR errors, and receives an EQ tuning signal from the data processing device (140) through the amplifier unit (511), performs tuning, and compares the EQ (Equalizer) information set in the Configuration Mode to output the number of EQ errors.

[0086] The EQ / CDR Controller / Cheker unit (513) compares the number of CDR errors or EQ errors with a threshold value, determines that the number of CDR errors or EQ errors is normal if the number of CDR errors or EQ errors is less than the threshold value, and outputs a CDR error signal or an EQ error signal if the number of CDR errors or EQ errors is greater than the threshold value.

[0087] The EQ / CDR Controller / Cheker unit (513) can compare the number of CDR errors or the number of EQ errors with at least two threshold values, output a first CDR error signal or a first EQ error signal if the number of CDR errors or the number of EQ errors is between the at least two threshold values, and output a second CDR error signal or a second EQ error signal if the number of CDR errors or the number of EQ errors is greater than or equal to at least two threshold values.

[0088] The high-speed communication unit (520) may include an image processing unit (521) that processes image data (RGB) received from a data processing device (140) using a clock signal recovered from a clock recovery unit (CDR) (512), and a BERT unit (522) that performs a bit error rate test (BERT) according to a value set in the Configuration Mode, receives a PRBS12 bit stream for error check, performs an error check, and then determines that an error exists if the number of errors exceeds a preset threshold value and outputs a BERT error presence / absence signal.

[0089] The low-speed communication unit (530) can perform low-speed clock training using the low-speed communication clock signal received from the data processing device (140) in the preamble section (see FIG. 3) of the low-speed communication mode. The low-speed communication unit (530) can receive a setting data signal for a high-speed communication environment from the data processing device (140). The low-speed communication unit (510) can process the setting data signal as setting data and transfer the setting data to the first register (540) to be described later. Here, the low-speed communication unit (530) can receive the setting data signal in the CFG Phase section of FIG. 3 and set a circuit portion for high-speed data communication using the setting data included in the setting data signal.

[0090] Here, the setting data may include basic gain level, scramble information, and line polarity information of the equalizer included in the data driving device (120). In addition, it may further include a plurality of CDR BW setting information used in the CDR tuning section described below, a plurality of EQ (Equalizer) setting information used in the equalizer tuning section, and BERT information for BERT.

[0091] The first register (540) can store CFG configuration information including CDR BW information, EQ configuration information, and BERT information received from the low-speed communication unit (510). The first register (540) can include an RX Configuration register.

[0092] The RX control unit (550) can output various control signals.

[0093] FIG. 5 is an example diagram of a signal sequence specifically indicating a Vertical Blank Region of a Display Mode according to one embodiment of the present specification.

[0094] As illustrated in FIG. 5, the data processing device (140) can transmit a Frame Control Packet (FCP) when entering the Vertical Blank Region in Display Mode. In addition, when transmitting the Frame Control Packet, check setting data (Check CFG) can be transmitted at high speed.

[0095] In addition, as described above, the data processing device (140) can transmit active setting data (Active CFG) and check setting data (Check CFG) signals to the data driving device (120) during the CFG Phase section.

[0096] Accordingly, according to the control signal (selection signal (Sel)) of the RX control unit (550), the selection unit (560) can select one of the check configuration data (Check CFG) signal transmitted in the CFG Phase section of the Configuration Mode and the check configuration data (Check CFG) transmitted at high speed during Frame Control Packet (FCP) transmission of the Display Mode.

[0097] The configuration comparison unit (570) can compare the check configuration data (Check CFG) signal transmitted in the CFG Phase section of the configuration mode output from the selection unit (560) with one of the configuration data (CFG) transmitted at high speed during Frame Control Packet (FCP) transmission of the display mode and the active configuration data (Active CFG) signal transmitted in the CFG Phase section of the configuration mode to output a CFG error presence / absence signal indicating whether an error has occurred.

[0098] The second register (580) can receive and store information on the operation status and results of the interface. For example, the second register (580) stores the number of CDR errors and the number of EQ errors output from the EQ / CDR Controller / Cheker unit (513), the BERT error presence / absence signal output from the BERT unit (522), and the CFG error presence / absence signal of the Configuration comparison unit (570). The second register (580) can output the number of CDR errors and the number of EQ errors, the BERT error presence / absence signal, and the CFG error presence / absence signal under the control of the RX control unit (550). The second register (580) may include an RX status register. The first register (540) and the second register (580) may be configured as one register.

[0099] The color mapping unit (590) can store various image data for displaying the setting data and the interface operation result on the display panel. The color mapping unit (590) can output one image data among various image data for displaying the setting data and the interface operation result on the display panel according to a signal output from the second register (580) and the control of the RX control unit (550). However, the present invention is not limited thereto, and the color mapping unit (590) can output one or more image data among various image data for displaying the setting data and the interface operation result on the display panel according to a signal output from the second register (580) and the control of the RX control unit (550).

[0100] Various image data for displaying the CFG and interface operation results may include image data when a CFG error occurs, image data when a BERT error occurs, image data when a CDR and EQ error occur, and image data when no error occurs. The image data when a CFG error occurs, the image data when a BERT error occurs, and the image data when a CDR and EQ error occur may be the same or different. The image data when a CDR and EQ error occur may be mapped differently depending on the number of CDR errors or the number of EQ errors. For example, the image data may be distinguished by color or color tone. In addition, the image data may be distinguished by color or color tone, and a set time or panel area may be allocated.

[0101] The multiplexer (600) can select and output one of the image data (RGB) processed in the image processing unit (521) and the image data output from the color mapping unit (590) according to the control signal (selection signal (Sel)) of the RX control unit (550).

[0102] The display logic unit (610) can convert image data (RGB) or setting data processed by the image processing unit (521) output from the multiplexer (600) and image data for displaying the interface operation result on the display panel into an analog signal and supply the signal to the data lines of the display panel (110).

[0103] The operation of a data drive device according to one embodiment of the present specification configured as described above is described as follows.

[0104] FIG. 6 is an operational flowchart for explaining the operation of a data driving device according to one embodiment of the present specification.

[0105] Various image data for displaying the CFG and interface operation results are mapped to the color mapping unit (590) (S1). The various image data for displaying the CFG and interface operation results may include first image data for displaying a CFG error when it occurs, second image data for displaying a BERT error when it occurs, third image data for displaying a CDR or EQ error when it occurs, and fourth image data for displaying when no error occurs. The first to third image data may be the same or different. The third image data may be mapped to different image data depending on the number of CDR errors or the number of EQ errors. For example, the third image data may be mapped differently to 3-1 image data, 3-2 image data, 3-4 image data, … ., etc. depending on the number of CDR errors or the number of EQ errors.

[0106] The low-speed communication unit (530) stores CFG information including CDR BW setting information, EQ setting information, and BERT setting information in the first register (540) in Configuration Mode (S2).

[0107] The configuration comparison unit (570) can generate a CFG error signal by comparing the check configuration data (Check CFG) signal transmitted in the CFG Phase section of the configuration mode output from the selection unit (560) with one of the configuration data (CFG) transmitted at high speed during the Frame Control Packet (FCP) transmission of the display mode and the active configuration data (Active CFG) signal transmitted in the CFG Phase section of the configuration mode (S3).

[0108] And, by determining whether a CFG error signal has been generated (S6), if a CFG error signal has been generated, the first image data for displaying a CFG error among the image data for displaying the interface operation result and the CFG mapped to the color mapping unit (590) is output to the display panel to display the CFG error result (S9).

[0109] It is determined whether a CFG error signal is generated (S6), and if a CFG error signal is not generated, the fourth image data for displaying the CFG mapped to the color mapping unit (590) and the interface operation result when no error has occurred is output to the display panel to display that the CFG and the interface operation result are normal (S10).

[0110] In addition, the EQ / CDR Controller / Cheker unit (513) can output the number of CDR errors by comparing the restored clock signal with a plurality of CDR BWs set in the Configuration Mode, receive an EQ tuning signal to tune, and output the number of EQ errors by comparing the restored clock signal with a plurality of EQ (Equalizer) information set in the Configuration Mode (S4).

[0111] The EQ / CDR Controller / Cheker unit (513) compares the number of CDR errors or EQ errors with a threshold value, determines that the number of CDR errors or EQ errors is normal if the number of CDR errors or EQ errors is less than the threshold value, and outputs a CDR error signal or an EQ error signal if the number of CDR errors or EQ errors is greater than the threshold value.

[0112] The EQ / CDR Controller / Cheker unit (513) can compare the number of CDR errors or the number of EQ errors with at least two threshold values, output a first CDR error signal or a first EQ error signal if the number of CDR errors or the number of EQ errors is between the at least two threshold values, and output a second CDR error signal or a second EQ error signal if the number of CDR errors or the number of EQ errors is greater than or equal to at least two threshold values.

[0113] And, by determining whether a CDR or EQ error signal has been generated (S7), if a CDR or EQ error signal has been generated, the CFG mapped to the color mapping unit (590) and the third image data for displaying the interface operation result when a CDR or EQ error occurs among the corresponding image data are output to the display panel to display the CDR or EQ error result (S9).

[0114] In the above step (S9), one of the 3-1 image data, the 3-2 image data, the 3-4 image data, … can be output to the display panel according to the 1st CDR error signal, the 1st EQ error signal, the 2nd CDR error signal, the 2nd EQ error signal, or the number of CDR errors or the number of EQ errors, to display the CDR or EQ error result.

[0115] It is determined whether a CDR or EQ error signal is generated (S7), and if a CDR or EQ error signal is not generated, when no error occurs among the corresponding image data for displaying the CFG mapped to the color mapping unit (590) and the interface operation result, the fourth image data for displaying this is output to the display panel to display that the CFG and the interface operation result are normal (S10).

[0116] In addition, the BERT unit (522) performs a bit error rate test (BERT) according to the value set in the Configuration Mode, receives a PRBS12 bit stream for error check, performs an error check, and if the number of errors exceeds a preset threshold value, it determines it to be an error and outputs a BERT error signal (S5).

[0117] And, by determining whether a BERT error signal has been generated (S8), if a BERT error signal has been generated, the second image data for displaying the BERT error signal among the corresponding image data for displaying the CFG mapped to the color mapping unit (590) and the interface operation result is output to the display panel to display the BERT error result (S9).

[0118] It is determined whether a BERT error signal is generated (S8), and if a BERT error signal is not generated, the fourth image data for displaying the CFG mapped to the color mapping unit (590) and the interface operation result when no error has occurred is output to the display panel to display that the CFG and the interface operation result are normal (S10).

[0119] FIG. 7 is an explanatory diagram of a state in which CFG and interface operation results are displayed on a display panel according to one embodiment of the present specification.

[0120] As described in FIG. 2, the data driving device (120) may include a plurality of data driving devices (120a, 120b, 120c, 120d). Accordingly, in the steps (Sd1-S9), each data driving device (120a, 120b, 120c, 120d) is operated individually.

[0121] Among the multiple data driving devices, the unevaluation data driving device can display black data on the display panel.

[0122] Data driven devices that have errors below a threshold or have not yet occurred may display a blue color on the display panel.

[0123] Additionally, data drive devices that have errors exceeding the threshold value may display a red light on the display panel.

[0124] According to the data driving device and the driving method of the data driving device of the display device according to the embodiment of the present specification described above, after setting the output option in the Configuration or Display Mode without a separate protocol, error information of the receiving end, not input RGB data, can be displayed on the display panel in the Pixel Data period of the Display Mode so that it can be visually confirmed. Through this, improved readability and shortened evaluation time can be expected during evaluation. Since the bezel area can be reduced, the display area on the display panel can be maximized.

[0125] The present specification described above is not limited to the above-described embodiments and attached drawings, and it will be apparent to a person having ordinary skill in the technical field to which the present specification pertains that various substitutions, modifications, and changes are possible within the scope that does not depart from the technical spirit of the present specification.

[0126] This specification is a technology applicable to display devices.

Claims

1. An auto tuning unit that receives data from a data processing device, restores a clock signal, compares the restored clock signal with a plurality of set CDR BWs, and outputs a CDR error signal, and receives an EQ tuning signal from the data processing device, tunes the signal, and compares the received signal with a plurality of set EQ information to output an EQ error signal; A high-speed communication unit that processes and outputs image data received from the data processing device using the restored clock signal; A low-speed communication unit that receives a setting data signal for a high-speed communication environment from the above data processing device; A first register that stores and selectively outputs the CDR error signal or the EQ error signal output from the auto tuning unit; A color mapping unit that stores image data for displaying the interface result with the data processing device on a display panel and outputs at least one image data among the stored image data according to a signal output from the first register; and A data driving device of a display device including a multiplexer that selects and outputs either image data output from the high-speed communication unit or image data output from the color mapping unit.

2. In paragraph 1, A second register that stores CFG setting information including the CDR BW information, the EQ setting information, and BERT information from the low-speed communication unit, and outputs setting data signals to each unit; and Further comprising a configuration comparison unit that compares the check configuration data signal and the active configuration data signal and outputs a CFG error signal indicating whether an error has occurred; The above first register is a data driving device of a display device that further stores and outputs the CFG error signal.

3. In paragraph 2, The above high-speed communication unit performs a bit error rate test (BERT) according to the above setting data, performs an error check, and if the number of errors exceeds a preset threshold, it judges it as an error and outputs a BERT error signal. The above first register is a data driving device of a display device that further stores and outputs the BERT error signal.

4. In paragraph 3, A selection unit that selects one of the check setting data signals transmitted in the configuration mode section and the check setting data transmitted at high speed and outputs the selection to the configuration comparison unit, A data driving device of a display device further comprising a display logic unit that converts the image data output from the multiplexer into an analog signal and supplies the signal to data lines of a display panel.

5. In paragraph 4, The above configuration comparison unit is a data drive device of a display device that compares the check configuration data signal transmitted in the configuration mode section with one of the check configuration data transmitted at high speed and the active configuration data signal to output a CFG error signal indicating whether an error has occurred.

6. In paragraph 1, The above auto tuning section, An amplifier that receives data from the data processing device and amplifies it, A clock restoration unit that restores a clock signal by sampling a signal from the amplification unit while changing the setting value of the oscillator included therein at regular intervals, A data driving device of a display device including an EQ / CDR Controller / Cheker that selects EQ and CDR hardware options, outputs a CDR error signal by comparing a restored clock signal with a plurality of set CDR BWs, receives an EQ tuning signal from the data processing device through the amplifier, tunes the signal, and outputs an EQ error signal by comparing the signal with a plurality of set EQ information.

7. In paragraph 6, The EQ / CDR Controller / Cheker unit is a data driving device of a display device that compares the number of CDR errors or the number of EQ errors with a threshold value, determines that the number of CDR errors or the number of EQ errors is normal if the number of CDR errors or the number of EQ errors is less than the threshold value, and outputs the CDR error signal or the EQ error signal if the number of CDR errors or the number of EQ errors is greater than the threshold value.

8. In paragraph 6, A data driving device of a display device, wherein the EQ / CDR Controller / Cheker unit compares the number of CDR errors or the number of EQ errors with at least two threshold values, outputs a first CDR error signal or a first EQ error signal if the number of CDR errors or the number of EQ errors is between the at least two threshold values, and outputs a second CDR error signal or a second EQ error signal if the number of CDR errors or the number of EQ errors is greater than or equal to at least two threshold values.

9. In paragraph 6, The above high-speed communication unit, An image processing unit that processes image data received from the data processing device using the clock signal restored by the clock restoration unit; A data drive device of a display device including a BERT unit that performs a bit error rate test (BERT) according to the above setting data, receives a PRBS12 bit stream for error checking, performs an error check, and outputs the BERT error signal when the number of errors exceeds a threshold value.

10. In any one of paragraphs 1 to 9, A data driving device of a display device including the above setting data, a basic gain level of an equalizer included in the data driving device, scramble information, line polarity information, a plurality of CDR BW setting information used in a CDR tuning section, a plurality of EQ setting information used in an equalizer tuning section, or BERT information for BERT.

11. A step of mapping various image data to display the interface results with the data processing device; A step of storing CFG information including CDR BW setting information and EQ setting information; A step of generating a CDR error signal and an EQ error signal using the above CFG information; When at least one error signal among the above CDR error signal and the above EQ error signal is generated, a step of displaying the corresponding image data among the various mapped image data on a display panel; and A method for driving a data drive device of a display device, comprising: a step of displaying image data indicating that no error has occurred among the various mapped image data on a display panel if an error signal is not generated; 12. In paragraph 11, Using the above CFG information, further generate a CFG error signal, A driving method of a data driving device of a display device, further comprising the step of displaying image data corresponding to the CFG error signal among the various mapped image data on the display panel when the CFG error signal is generated.

13. In paragraph 12, The above CFG error signal is a driving method of a data driving device of a display device generated by comparing a check setting data signal and an active setting data signal.

14. In paragraph 11, The above CDR error signal is, A driving method of a data driving device of a display device including a CDR error number obtained by comparing a restored clock signal with a plurality of set CDR BWs, or a signal when the CDR error number is greater than a threshold value.

15. In paragraph 11, The above EQ error signal is, A method for driving a data driving device of a display device including tuning an EQ tuning signal and comparing it with a plurality of set EQ information, and obtaining an EQ error number, or a signal when the EQ error number is greater than a threshold value.

16. In paragraph 11, The above CFG information further includes BERT setting information, and further generates a BERT error signal using the BERT setting information. A driving method of a data driving device of a display device, further comprising the step of displaying image data corresponding to the BERT error signal among the various mapped image data on the display panel when the BERT error signal is generated.

17. In paragraph 16, The above BERT error signal is, A method for driving a data drive device of a display device that performs a bit error rate test (BERT) according to the above BERT setting information, receives a PRBS12 bit stream, performs an error check, and then generates a data drive device when the number of errors exceeds a threshold value.

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