Stacked semiconductor device having hybrid channel, and manufacturing method therefor

Abstract

A stacked semiconductor device manufacturing method is provided. The stacked semiconductor device manufacturing method may comprise the steps of: preparing a base structure in which first material layers and second material layers having different etch sensitivities are alternately and repeatedly stacked; forming a trench by etching the base structure in the direction in which the first material layers and the second material layers are stacked; forming, on an inner wall of the trench, a first channel layer extending in the direction in which the first material layers and the second material layers are stacked and including silicon (Si); forming, on the first channel layer, a second channel layer extending in the direction in which the first material layers and the second material layers are stacked and including a semiconductor oxide; forming a recess region between the first material layers adjacent to each other in the base structure by selectively etching the second material layers from among the first material layers and the second material layers; forming a charge storage layer in the recess region such that contact is made with the first channel layer; and forming a gate in the recess region such that contact is made with the charge storage layer.

Description

Layered semiconductor device having a hybrid channel and method for manufacturing the same

[0001] The present invention relates to a stacked semiconductor device and a method for manufacturing the same, and more particularly, to a stacked semiconductor device having a hybrid channel in which a silicon channel and a semiconductor oxide channel are mixed, and a method for manufacturing the same.

[0002] Basically, the existing commercialized V-NAND manufacturing technology uses silicon (Si) as a channel material. Among them, the mobility is 10 cm 2 / Vs, very low polycrystalline silicon (Poly-Si) is used as a channel layer. This is because it is impossible to deposit high-mobility single-crystal Si as a channel layer in the V-NAND manufacturing process flow. Since V-NAND has a structure in which multiple transistors are connected in series, the channel length increases as the number of stacked cells increases, which has the characteristic of reducing the driving current. Therefore, in the case of stacked V-NAND using existing Poly-Si as a channel layer, it is difficult to apply it to high integration of more than 500 layers. This is because it is difficult to distinguish information due to the characteristics of NAND memory that distinguishes information between 0 and 1 through the size of the current when the driving current falls below a certain level. To improve this problem, research has been actively conducted to use a semiconductor oxide that has higher mobility than the existing channel material, Poly-Si, excellent step coverage under high aspect ratio conditions, and excellent large-area uniformity.

[0003] However, research on applying semiconductor oxides as channel materials for NAND has a critical problem: the erase operation is limited. For normal memory operation, both write and erase operations must be performed repeatedly. Existing silicon nitride (SiN) x) as a charge storage layer (charge trap layer, CTL), a write operation is performed by injecting electrons into the CTL, and an erase operation is performed by putting holes into the CTL and reacting with the already injected electrons to eliminate them. In the case of semiconductor oxides, they generally have N-type semiconductor characteristics and have a very large band gap, so electrons can be excited, but holes cannot move through the excitation, which limits the erase operation.

[0004] Furthermore, semiconductor oxides present challenges when incorporated into existing semiconductor manufacturing processes, including NAND. Specifically, semiconductor oxides are exposed to extremely high temperatures, ranging from 800°C to 1000°C, during the memory manufacturing process, typically the BEOL process. This is because semiconductor oxides exhibit deteriorating electrical properties at temperatures above 400°C due to dehydrogenation and unstable crystallization.

[0005] Accordingly, the present invention aims to provide a layered semiconductor device and a method for manufacturing the same, which uses a semiconductor oxide, but allows both writing and erasing operations to be easily performed, and can operate stably even in a high-temperature environment of 400°C or higher.

[0006] The technical problem to be solved by the present invention is to provide a stacked semiconductor device and a method for manufacturing the same.

[0007] Another technical problem to be solved by the present invention is to provide a layered semiconductor device using a semiconductor oxide as a channel and a method for manufacturing the same.

[0008] Another technical problem to be solved by the present invention is to provide a stacked semiconductor device having a hybrid channel and a method for manufacturing the same.

[0009] Another technical problem to be solved by the present invention is to provide a stacked semiconductor device that is easy to erase and a method for manufacturing the same.

[0010] Another technical problem to be solved by the present invention is to provide a layered semiconductor device with improved high-temperature stability and a method for manufacturing the same.

[0011] The technical problems to be solved by the present invention are not limited to those described above.

[0012] To solve the above-described technical problems, the present invention provides a method for manufacturing a layered semiconductor device.

[0013] According to one embodiment, the method for manufacturing the stacked semiconductor device may include the steps of: preparing a base structure in which first material layers and second material layers having different etching selectivities are alternately and repeatedly stacked; etching the base structure in a direction in which the first material layer and the second material layer are stacked to form a trench; forming a first channel layer including silicon (Si) on an inner wall of the trench, the first channel layer extending in the direction in which the first material layer and the second material layer are stacked, the second channel layer including a semiconductor oxide on the first channel layer; forming a recess region between the first material layers adjacent to each other in the base structure by selectively etching the second material layer among the first material layer and the second material layer; forming a charge storage layer in the recess region so as to be in contact with the first channel layer; and forming a gate in the recess region so as to be in contact with the charge storage layer.

[0014] According to one embodiment, the first channel layer and the second channel layer may be formed by different methods.

[0015] According to one embodiment, the first channel layer may be formed by chemical vapor deposition (CVD), and the second channel layer may be formed by atomic layer deposition (ALD).

[0016] According to one embodiment, the step of forming the second channel layer may include the steps of providing a first precursor including indium (In) on the first channel layer, providing a first reactant including oxygen on the first channel layer on which the first precursor is provided, providing a second precursor including gallium (Ga) on the first channel layer on which the first reactant is provided, and providing a second reactant including oxygen on the first channel layer on which the second precursor is provided.

[0017] According to one embodiment, the step of providing the first precursor and the step of providing the first reactant are defined as a first unit process, the step of providing the second precursor and the step of providing the second reactant are defined as a second unit process, and the first unit process and the second unit process may each be repeatedly performed multiple times.

[0018] According to one embodiment, the number of repetitions of the first unit process may be greater than the number of repetitions of the second unit process.

[0019] According to one embodiment, the method may further include forming a first oxide layer in the recessed region to be in contact with the first channel layer before forming the charge storage layer after forming the recessed region, and forming a second oxide layer in the recessed region to be in contact with the charge storage layer before forming the gate after forming the charge storage layer.

[0020] According to one embodiment, as the second channel layer is formed on the first channel layer, oxygen within the second channel layer may move from the second channel layer toward the first channel layer, thereby forming oxygen vacancies within the second channel layer.

[0021]

[0022] To solve the above-described technical problems, the present invention provides a stacked semiconductor device.

[0023] According to one embodiment, the stacked semiconductor device may include a stacked structure in which insulating layers and electrode layers are alternately and repeatedly stacked, and a trench is formed in the direction in which the insulating layers and the electrode layers are stacked; a first channel layer disposed on an inner wall of the trench, extending in the direction in which the insulating layers and the electrode layers are stacked, and including silicon (Si); and a second channel layer disposed on the first channel layer, extending in the direction in which the insulating layers and the electrode layers are stacked, and including a semiconductor oxide, wherein the electrode layer may include a gate disposed to be spaced apart from the first channel layer in a direction perpendicular to the direction in which the first channel layer extends; and a charge storage layer disposed between the gate and the first channel layer.

[0024] According to one embodiment, the stacked semiconductor device may be applied to a V-NAND, and may include a write operation performed through the second channel layer and an erase operation performed through the first channel layer.

[0025] According to one embodiment, the second channel layer may include IGO (Indium-Gallium-Oxide).

[0026] According to one embodiment, the thickness of the second channel layer may be 10 nm or more.

[0027] According to one embodiment, a silicon oxide layer may be formed between the first channel layer and the second channel layer.

[0028] According to another embodiment, the stacked semiconductor device may include a stacked structure in which insulating layers and electrode layers are alternately and repeatedly stacked, a trench formed in a direction in which the insulating layers and the electrode layers are stacked, a first channel layer disposed on an inner wall of the trench, extending in the direction in which the insulating layers and the electrode layers are stacked, and including silicon (Si), a second channel layer disposed on the first channel layer, extending in the direction in which the insulating layers and the electrode layers are stacked, and including a semiconductor oxide, and a tin oxide layer disposed between the first channel layer and the second channel layer, wherein the electrode layer may include a gate disposed to be spaced apart from the first channel layer in a direction perpendicular to a direction in which the first channel layer extends, and a charge storage layer disposed between the gate and the first channel layer.

[0029] A stacked semiconductor device according to an embodiment of the present invention includes a stacked structure in which insulating layers and electrode layers are alternately and repeatedly stacked, and a trench is formed in a direction in which the insulating layers and the electrode layers are stacked, a first channel layer disposed on an inner wall of the trench, extending in the direction in which the insulating layers and the electrode layers are stacked and including silicon, and a second channel layer disposed on the first channel layer, extending in the direction in which the insulating layers and the electrode layers are stacked and including a semiconductor oxide, wherein the electrode layer may include a gate disposed to be spaced apart from the first channel layer in a direction perpendicular to a direction in which the first channel layer extends, and a charge storage layer disposed between the gate and the first channel layer.

[0030] The above-described stacked semiconductor device is applied to V-NAND, and a write operation can be performed through the second channel layer and an erase operation can be performed through the first channel layer. Accordingly, an erase operation can be easily performed even though a semiconductor oxide is used as a channel.

[0031] In addition, the stacked semiconductor device may use IGO (Indium-Gallium-Oxide) as the semiconductor oxide. Accordingly, high-temperature stability can be improved, and thus, it can be easily applied to existing memory manufacturing processes that are exposed to high-temperature environments, such as BEOL (Back End Of Line).

[0032] FIG. 1 is a flowchart for explaining a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention.

[0033] FIG. 2 is a schematic diagram illustrating step S110 of a method for manufacturing a laminated semiconductor device according to a first embodiment of the present invention.

[0034] FIG. 3 is a schematic diagram illustrating step S120 of a method for manufacturing a laminated semiconductor device according to a first embodiment of the present invention.

[0035] FIG. 4 is a schematic diagram illustrating step S130 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention.

[0036] FIG. 5 is a schematic diagram illustrating step S140 of a method for manufacturing a laminated semiconductor device according to a first embodiment of the present invention.

[0037] FIG. 6 is a drawing for explaining the process flow of step S140 in the method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0038] FIG. 7 is a drawing for explaining an oxide film formed in step S140 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0039] FIG. 8 is a schematic diagram illustrating step S150 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0040] FIG. 9 is a schematic diagram illustrating step S160 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0041] Figure 10 is an enlarged view of area A of Figure 9.

[0042] FIG. 11 is a schematic diagram illustrating step S170 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0043] Figure 12 is an enlarged view of area A of Figure 11.

[0044] FIG. 13 is a schematic diagram illustrating step S180 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0045] Figure 14 is an enlarged view of area A of Figure 13.

[0046] FIG. 15 is a schematic diagram illustrating step S190 of a method for manufacturing a stacked semiconductor device according to the first embodiment of the present invention.

[0047] Figure 16 is an enlarged view of area A of Figure 15.

[0048] FIG. 17 is a schematic diagram illustrating step S230 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention.

[0049] FIG. 18 is a schematic diagram for explaining step S235 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention.

[0050] FIG. 19 is a schematic diagram illustrating step S240 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention.

[0051] Figure 20 is a drawing for explaining the electrical characteristics of a transistor according to Experimental Example 1 of the present invention.

[0052] Figures 21 to 24 are drawings for explaining the electrical characteristics of a transistor according to Experimental Example 2 of the present invention.

[0053] Figure 25 is an image of a V-NAND according to Experimental Example 3 of the present invention.

[0054] FIG. 26 and FIG. 27 are drawings for explaining the operation verification and mechanism simulation results of V-NAND according to Experimental Example 3 of the present invention.

[0055] Figure 28 is a schematic diagram of a transistor according to Experimental Example 4 of the present invention.

[0056] Figure 29 is a drawing comparing the electrical characteristics of transistors according to Experimental Example 4 of the present invention.

[0057] Figure 30 is a drawing for explaining the structural characteristics of a hybrid thin film according to Experimental Example 4 of the present invention.

[0058] Figure 31 is a schematic diagram and a drawing for explaining the electrical characteristics of a transistor having a hybrid channel.

[0059] Figure 32 is a drawing for explaining the 3D NAND flash memory structure, equivalent circuit, and timing diagram of the erase operation used in the TCAD simulation.

[0060] Figure 33 is a drawing for explaining the simulation results of the deletion operation.

[0061] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art.

[0062] In this specification, when a component is referred to as being on another component, it means that it can be formed directly on the other component, or a third component may be interposed between them. In addition, in the drawings, the thicknesses of films and regions are exaggerated for the purpose of effectively explaining the technical contents.

[0063] Also, although terms such as first, second, and third have been used to describe various components in various embodiments of this specification, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Also, the term "and / or" has been used herein to mean including at least one of the components listed before and after.

[0064] In the specification, singular expressions include plural expressions unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term "connection" is used in the present specification to mean both indirectly connecting multiple components and directly connecting them.

[0065] In addition, when describing the present invention below, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0066]

[0067] Method for manufacturing a stacked semiconductor device according to the first embodiment

[0068] FIG. 1 is a flowchart for explaining a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 2 is a schematic diagram for explaining step S110 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 3 is a schematic diagram for explaining step S120 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 4 is a schematic diagram for explaining step S130 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 5 is a schematic diagram for explaining step S140 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 6 is a diagram for explaining a process flow of step S140 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 7 is a diagram for explaining an oxide film formed in step S140 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, and FIG. 8 is a diagram for explaining a process flow of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention. FIG. 9 is a schematic diagram for explaining step S150, FIG. 9 is a schematic diagram for explaining step S160 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 10 is an enlarged view of area A of FIG. 9, FIG. 11 is a schematic diagram for explaining step S170 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 12 is an enlarged view of area A of FIG. 11, FIG. 13 is a schematic diagram for explaining step S180 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, FIG. 14 is an enlarged view of area A of FIG. 13, FIG. 15 is a schematic diagram for explaining step S190 of a method for manufacturing a stacked semiconductor device according to a first embodiment of the present invention, and FIG. 16 is an enlarged view of area A of FIG. 15.

[0069] Referring to FIGS. 1 and 2, a base structure (BS) in which a first material layer (110) and a second material layer (120) are alternately and repeatedly laminated may be prepared (S110). According to one embodiment, the first material layer (110) and the second material layer (120) may have different etching selectivities. For example, the first material layer (110) may have a relatively low etching rate by an etching material used in step S150, which will be described later. In contrast, the second material layer (120) may have a relatively high etching rate by an etching material used in step S150, which will be described later.

[0070] Referring to FIGS. 1 and 3, the base structure (BS) may be etched to form a trench (TC) (S120). According to one embodiment, the trench (TC) may be formed by etching the base structure (BS) in the direction in which the first material layer (110) and the second material layer (120) are stacked.

[0071] Referring to FIGS. 1 and 4, a first channel layer (210) may be formed on the inner wall of the trench (TC) (S130). According to one embodiment, the first channel layer (210) may be formed on the inner wall of the trench (TC) so as to extend in the direction in which the first material layer (110) and the second material layer (120) are stacked. According to one embodiment, the first channel layer (210) may include polycrystalline silicon (Poly-Si). In addition, the first channel layer (210) may be formed by a chemical vapor deposition (CVD) method. More specifically, the first channel layer (210) can be formed using a SiH4 precursor under conditions of a pressure of 0.98 Torr, a deposition temperature of 535°C, a subsequent heat treatment temperature of 800 to 900°C, a nitrogen (N2) atmosphere, and a 90 sec RTA.

[0072] Referring to FIGS. 1 and 5, a second channel layer (220) may be formed on the first channel layer (210) (S140). According to one embodiment, the second channel layer (220) may be formed on the first channel layer (210) so as to extend in the direction in which the first material layer (110) and the second material layer (120) are stacked. According to one embodiment, the second channel layer (220) may include IGO (Indium-Gallium-Oxide). In addition, the second channel layer (220) may be formed by atomic layer deposition (ALD).

[0073] More specifically, the step (S140) of forming the second channel layer (220) is as shown in FIG. 6, a first precursor (1) containing indium (In) is formed on the first channel layer (210). st Step (S141) of providing a Precursor, the first purge (1 st Purge) step (S142), the first reactant (1) containing oxygen is provided on the first channel layer (210) provided with the first precursor. st Step (S143) of providing a reactant, second purge (2 nd Purge) step (S144), a second precursor (2) containing gallium (Ga) is provided on the first channel layer to which the first reactant is provided. nd Step (S145) of providing a Precursor, 3rd fuzzy (3 rd Purge) step (S146), and the second reactant (2) containing oxygen is provided on the first channel layer (210) provided with the second precursor. nd Step (S147) of providing a reactant), and the fourth purge (4 th It may include a Purge step (S148).

[0074] For example, the first precursor may include (3-(dimethylamino)propyl)dimethylindium. For example, the second precursor may include Dimethyl[N-(2-methoxyethyl)-2-methylpropan-2-amine]gallium. For example, both the first reactant and the second reactant may include ozone (O3).

[0075] According to one embodiment, steps S141 to S144 are a first unit process (1 st Unit Process). In contrast, steps S145 to S148 may be defined as a second unit process (2 nd It can be defined as a Unit Process. In addition, the first unit process and the second unit process can be defined as a total process.

[0076] The above first unit process and the above second unit process can each be repeated multiple times, and the overall process can also be repeated multiple times. Depending on the number of repetitions of the first unit process, the second unit process, and the overall process, the thickness and composition of the second channel layer (220) can be controlled.

[0077] According to one embodiment, the number of repetitions of the first unit process may be greater than the number of repetitions of the second unit process. For example, the number of repetitions of the first unit process: the number of repetitions of the second unit process may be controlled at a ratio of 4:1, thereby forming the second channel layer (220).

[0078] According to one embodiment, the second channel layer (220) may have a thickness of 10 nm or more. Conversely, if the second channel layer (220) has a thickness of less than 10 nm, high-temperature stability may be deteriorated, resulting in deterioration problems in high-temperature environments.

[0079] According to one embodiment, an oxide film (230) of the first channel layer (210) may be formed between the first channel layer (210) and the second channel layer (220). For example, the oxide film (230) may include silicon oxide (SiO2). More specifically, the first channel layer (210) may be oxidized by ozone (O3) used in the process of forming the second channel layer (220), so that the oxide film (230) may be formed on the first channel layer (210). In addition, when the second channel layer (220) is formed on the first channel layer (210), oxygen in the second channel layer (220) moves from the second channel layer (220) toward the first channel layer (210), so that the oxide film (230) may be formed on the first channel layer (210). Meanwhile, as oxygen within the second channel layer (220) moves from the second channel layer (220) toward the first channel layer (210), oxygen vacancies may be formed within the second channel layer (220). Accordingly, the electrical characteristics of the second channel layer (220) may be improved by the oxygen vacancies.

[0080] Referring to FIGS. 1 and 8, among the first material layer (110) and the second material layer (120), the second material layer (120) may be selectively etched to form a recess area (RA) between adjacent first material layers (110) within the base structure (BS) (S150). According to one embodiment, the second material layer (120) may be selectively etched by an etching material. As described above, since the first material layer (110) and the second material layer (120) have different etching selectivities, the first material layer (110) may not be etched by the etching material, whereas the second material layer (120) may be etched by the etching material. Accordingly, an empty space is formed between the adjacent first material layers (110) where the second material layer (120) is removed, and the empty space can be defined as the recess area (RA).

[0081] Referring to FIGS. 1, 9, and 10, a first oxide layer (310) may be formed within the recess area (RA) (S160). More specifically, the first oxide layer (310) may be conformally formed along the surface profiles of the first channel layer (210) and the first material layer (110) so as to be in contact with the first channel layer (210) and the first material layer (110).

[0082] According to one embodiment, the first oxide layer (310) may include silicon oxide (SiO2) as a tunneling oxide. According to one embodiment, the first oxide layer (310) may be formed by low-pressure chemical vapor deposition (LP-CVD) using a TEOS precursor.

[0083] Referring to FIGS. 1, 11, and 12, a charge storage layer (charge trapping layer) 320 may be formed within the recess area (RA) (S170). More specifically, the charge storage layer (320) may be conformally formed along a surface profile of the first oxide layer (310) so as to be in contact with the first oxide layer (310). According to one embodiment, the charge storage layer (320) may include silicon nitride (Si3N4). According to one embodiment, the charge storage layer (320) may be formed by low-pressure chemical vapor deposition (LP-CVD). The charge storage layer (320) may be in contact with the first channel layer (210) through the first oxide layer (310).

[0084] Referring to FIGS. 1, 13, and 14, a second oxide layer (330) may be formed within the recess area (RA) (S180). More specifically, the second oxide layer (330) may be formed conformally along the surface profile of the charge storage layer (320) so as to be in contact with the charge storage layer (320).

[0085] According to one embodiment, the second oxide layer (330) may include silicon oxide (SiO2) as a blocking oxide. According to one embodiment, the second oxide layer (330) may be formed by low-pressure chemical vapor deposition (LP-CVD) using a TEOS precursor.

[0086] Referring to FIGS. 1, 15, and 16, a gate (400) may be formed within the recess area (RA) (S190). Accordingly, a stacked semiconductor device according to the embodiment may be manufactured. More specifically, the gate (400) may be formed to fill the interior of the recess area (RA) remaining after the first oxide layer (310), the charge storage layer (320), and the second oxide layer (330) are formed. According to one embodiment, the first oxide layer (310), the charge storage layer (320), the second oxide layer (330), and the gate (400) formed within the recess area (RA) may be defined as an electrode layer (100). In addition, the first material layer (110) may be defined as an insulating layer.

[0087] As a result, a stacked semiconductor device according to an embodiment of the present invention includes a stacked structure in which an insulating layer (110) and an electrode layer (100) are alternately and repeatedly stacked, and a trench (TC) is formed in the direction in which the insulating layer (110) and the electrode layer (100) are stacked, a first channel layer (210) disposed on the inner wall of the trench (TC) and extending in the direction in which the insulating layer (110) and the electrode layer (100) are stacked and containing silicon (Si), and a second channel layer (220) disposed on the first channel layer (210) and extending in the direction in which the insulating layer (110) and the electrode layer (100) are stacked and containing a semiconductor oxide, wherein the electrode layer (100) is spaced apart from the first channel layer (210) in a direction perpendicular to the direction in which the first channel layer (210) extends, and a gate (400) and the first It may include a charge storage layer (320) disposed between channel layers (210).

[0088] The above-described stacked semiconductor device is applied to V-NAND, and a write operation can be performed through the second channel layer (220) and an erase operation can be performed through the first channel layer (210). Accordingly, an erase operation can be easily performed even though a semiconductor oxide is used as a channel.

[0089] In addition, the stacked semiconductor device may use IGO (Indium-Gallium-Oxide) as the semiconductor oxide. Accordingly, high-temperature stability can be improved, and thus, it can be easily applied to existing memory manufacturing processes that are exposed to high-temperature environments, such as BEOL (Back End Of Line).

[0090]

[0091] Method for manufacturing a stacked semiconductor device according to the second embodiment

[0092] A method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention may include a step of preparing a base structure (S210), a step of etching the base structure to form a trench (S220), a step of forming a first channel layer on an inner wall of the trench (S230), a step of forming a tin oxide layer on the first channel layer (S235), a step of forming a second channel layer on the tin oxide layer (S240), a step of forming a recess region in the base structure (S250), a step of forming a first oxide layer in the recess region (S260), a step of forming a charge storage layer in the recess region (S270), a step of forming a second oxide layer in the recess region (S280), and a step of forming a gate in the recess region (S290).

[0093] According to one embodiment, steps S210, S220, S230, S250, S260, S270, S280, and S290 may be the same as steps S110, S120, S130, S150, S160, S170, S180, and S190, respectively, included in the method for manufacturing a stacked semiconductor device according to the first embodiment.

[0094] That is, the method for manufacturing a stacked semiconductor device according to the second embodiment has differences compared to the method for manufacturing a stacked semiconductor device according to the first embodiment in that step S235 is added and step S240 is different from step S140. Hereinafter, the method for manufacturing a stacked semiconductor device according to the second embodiment will be described with a focus on steps S235 and S240.

[0095] FIG. 17 is a schematic diagram for explaining step S230 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention, FIG. 18 is a schematic diagram for explaining step S235 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention, and FIG. 19 is a schematic diagram for explaining step S240 of a method for manufacturing a stacked semiconductor device according to a second embodiment of the present invention.

[0096] Referring to FIGS. 17 and 18, a tin oxide layer (240) may be formed on the first channel layer (210), and the second channel layer (220) may be formed on the tin oxide layer (240). According to one embodiment, the tin oxide layer (240) formed on the first channel layer (210) may include SnO. The SnO tin oxide layer (240) may be changed into a SnO2 tin oxide layer (240) by the formation of the second channel layer (220). That is, in the method for manufacturing a stacked semiconductor device according to the second embodiment, unlike the method for manufacturing a stacked semiconductor device according to the first embodiment, a sacrificial layer (SnO) may be formed on the first channel layer (210) in order to prevent a SiO2 oxide film from being formed on the first channel layer (210). When a SnO2 tin oxide layer (240) is formed instead of a SiO2 oxide film (230) between the first channel layer (210) and the second channel layer (220), the electrical characteristics of the second channel layer (220) can be relatively improved. More specifically, SnO2 is an n-type semiconductor oxide that has a cubic crystallinity like IGO and has very high conductivity, and thus can improve the electrical characteristics of IGO compared to SiO2.

[0097]

[0098] Experimental Example 1: Confirming the Thermal Stability of InOx Channels

[0099] InO x A bottom-gate structure transistor with a (x>0) channel was prepared. Afterwards, InO x (x>) After heat treatment of the channel at temperatures of 400°C and 800°C, the electrical characteristics of the transistor were measured.

[0100] Figure 20 is a drawing for explaining the electrical characteristics of a transistor according to Experimental Example 1 of the present invention.

[0101] Referring to (a) to (c) of Fig. 20, InO x Electrical characteristics are measured and presented for the state before heat treatment (As-deposited), the state after heat treatment at 400°C (400°C annealed), and the state after heat treatment at 800°C (800°C annealed). More specific measurement results are summarized in below.

[0102] InOx ChannelAs-deposited400℃ annealed800℃ annealedV th [V]-1.40 ± 0.10-0.31 ± 0.01N / Aμ FE [cm 2 / Vs](@V d =0.1V)64.63 ± 2.8555.51 ± 0.55N / Aμ FE [cm 2 / Vs](@V d =1.0V)66.54 ± 0.7154.91 ± 0.27N / AS.S. [mV / decade]85.7 ± 0.0064.7 ± 0.3N / AI on / I off 2.20 x 10 8 2.13 x 10 8 N / A

[0103] As can be seen in Fig. 20 and , InO x (x>0) In the case of the channel, it can be confirmed that the electrical characteristics do not appear due to deterioration caused by high-temperature heat treatment at 800℃.

[0104]

[0105] Experimental Example 2: Confirming the Thermal Stability of IGO Channels

[0106] A bottom-gate structure transistor having an IGO channel was prepared. More specifically, the IGO channel was formed by atomic layer deposition (ALD) using an indium precursor (3-(dimethylamino)propyl)dimethylindium), a gallium precursor (Dimethyl[N-(2-methoxyethyl)-2-methylpropan-2-amine]gallium), and ozone (O3), as described with reference to Fig. 6, and the number of repetitions of the first unit process: the second unit process was controlled at a ratio of 4:1. Thereafter, the IGO channel was heat-treated at temperatures of 400°C and 800°C, and the electrical characteristics of the transistor were measured.

[0107] Figures 21 to 24 are drawings for explaining the electrical characteristics of a transistor according to Experimental Example 2 of the present invention.

[0108] Referring to FIGS. 21 to 24, the electrical characteristics of transistors having IGO channels of different thicknesses are shown in the as-deposited state, the 400°C annealed state, and the 800°C annealed state. More specifically, FIG. 21 shows the results for an IGO channel having a thickness of 3 nm, FIG. 22 shows the results for an IGO channel having a thickness of 5 nm, FIG. 23 shows the results for an IGO channel having a thickness of 10 nm, and FIG. 24 shows the results for an IGO channel having a thickness of 20 nm. In addition, the specific results of FIG. 21 are summarized in , the specific results of FIG. 22 are summarized in , the specific results of FIG. 23 are summarized in , and the specific results of FIG. 24 are summarized in .

[0109] IGO channel (3 nm)As-deposited400℃ annealed800℃ annealedV th[V]-0.31 ± 0.04-0.08 ± 0.01N / Aμ FE [cm 2 / Vs](@V d =0.1V)36.84 ± 0.3439.32 ± 1.92N / Aμ FE [cm 2 / Vs](@V d =1.0V)35.84 ± 0.5036.94 ± 1.13N / AS.S. [mV / decade]108.5 ± 0.0363.5 ± 0.4N / AI on / I off 5.92 x 10 7 1.17 x 10 8 N / A

[0110] IGO 채널(5 nm)As-deposited400℃ annealed800℃ annealedV th [V]N / A-2.62 ± 0.160.87 ± 0.07μ FE [cm 2 / Vs](@V d =0.1V)N / A45.25 ± 1.9416.31 ± 1.87μ FE [cm 2 / Vs](@V d =1.0V)N / A44.37 ± 1.6415.65 ± 1.96S.S. [mV / decade]N / A75.1 ± 0.579.3 ± 0.8I on / I off N / A2.33 x 10 8 2.33 x 10 8

[0111] IGO 채널(10 nm)As-deposited400℃ annealed800℃ annealedV th [V]N / A-0.15 ± 0.010.40 ± 0.01μ FE [cm 2 / Vs](@V d =0.1V)N / A66.98 ± 4.6458.88 ± 1.21μ FE [cm 2 / Vs](@V d=1.0V)N / A65.07 ± 4.1056.95 ± 1.96SS [mV / decade]N / A65.4 ± 0.371.0 ± 0.1I on / I off N / A2.16 x 10 8 1.77 x 10 8

[0112] IGO channel (20 nm)As-deposited400℃ annealed800℃ annealedV th [V]N / A-0.08 ± 0.010.30 ± 0.03μ FE [cm 2 / Vs](@V d =0.1V)N / A64.36 ± 1.3468.71 ± 0.79μ FE [cm 2 / Vs](@V d =1.0V)N / A63.74 ± 1.4565.97 ± 0.77SS [mV / decade]N / A71.7 ± 0.470.4 ± 0.9I on / I off N / A2.16 x 10 8 1.94 x 10 8

[0113] As can be seen in Fig. 21 and , when the thickness of the IGO channel is 3 nm, it can be confirmed that the electrical characteristics do not appear due to deterioration caused by the high temperature heat treatment at 800°C. In addition, as can be seen in Fig. 22 and , when the thickness of the IGO channel is 5 nm, the electrical characteristics appear despite the high temperature heat treatment at 800°C, but it can be confirmed that the electrical characteristics are significantly reduced compared to the heat treatment at 400°C.

[0114] However, as can be seen in FIGS. 23 and 24, and , when the thickness of the IGO channel is 10 nm and 20 nm, there is no significant difference between the electrical characteristics exhibited by heat treatment at 400°C and those exhibited by heat treatment at 800°C. Consequently, when IGO is used as a channel material, it can be seen that it should be manufactured with a thickness of 10 nm or more in order to improve stability at high temperatures (over 800°C).

[0115]

[0116] Experimental Example 3: Fabrication and Operational Verification of V-NAND with p-Si / IGO Hybrid Channel

[0117] A three-layer stacked V-NAND having a p-Si / IGO hybrid channel in which a 10 nm thick IGO ​​channel is stacked on a p-Si channel was fabricated.

[0118] Figure 25 is an image of a V-NAND according to Experimental Example 3 of the present invention.

[0119] Referring to Fig. 25, the HRTEM (High-Resolution Transmission Electron Microscopy) image and EDX (Energy Dispersive X-ray Spectroscopy) measurement results for the V-NAND according to Experimental Example 3 are shown. As can be seen in Fig. 25, it can be confirmed that the target material was fabricated as intended in layers.

[0120] FIG. 26 and FIG. 27 are drawings for explaining the operation verification and mechanism simulation results of V-NAND according to Experimental Example 3 of the present invention.

[0121] As can be confirmed in FIGS. 26 and 27, regardless of the channel type, the semiconductor characteristics were stably implemented, and in the case of memory operation, it can be confirmed that the threshold voltage shifted in the positive direction in proportion to the voltage applied when the program operation was performed in the initial state. In particular, while the erase operation was impossible in the semiconductor oxide channel V-NAND as described above, the erase operation was possible in the hybrid channel V-NAND, and it can be confirmed that the threshold voltage shifted in the negative direction by 2.5 V through the operation. This means that the erase operation, which is a problem in NAND memory using the existing semiconductor oxide as a channel layer, can be improved by introducing the p-Si / IGO hybrid channel structure. In addition, the results of the TCAD simulation showed that when the write operation is performed, electrons mainly flow through the relatively high-mobility IGO, enabling the write operation with a high operating current, and the erase operation was possible because holes were injected due to the GIDL operation of the poly-Si.

[0122]

[0123] Experimental Example 4: Comparison of IGO Single Channel and p-Si / IGO Hybrid Channel

[0124] A bottom-gate structure transistor with an IGO single channel and a bottom-gate structure transistor with a p-Si / IGO hybrid channel were prepared.

[0125] Figure 28 is a schematic diagram of a transistor according to Experimental Example 4 of the present invention.

[0126] Referring to FIG. 28, the structure and manufacturing process of the transistor used for comparison between the IGO single channel and the p-Si / IGO hybrid channel can be confirmed.

[0127] Figure 29 is a drawing comparing the electrical characteristics of transistors according to Experimental Example 4 of the present invention.

[0128] Referring to (a) of FIG. 29, an IV curve of a transistor having a 20 nm thick IGO ​​single channel is shown, referencing (b) of FIG. 29, an IV curve of a transistor having a 10 nm thick IGO ​​single channel is shown, referencing (c) of FIG. 29, an IV curve of a transistor having a p-Si / IGO hybrid channel in which a 10 nm thick IGO ​​channel is stacked on a 10 nm thick p-Si channel is shown, and referencing (d) of FIG. 29, field effect mobility and SS values ​​extracted from (a) to (c) of FIG. 29 are shown together with data values ​​of a p-Si channel reported previously.

[0129] As can be seen in (a) and (b) of Fig. 29, the transistor with the IGO single channel has a drain voltage (V) due to the characteristics of the semiconductor oxide. D ) has excellent off-leakage current and SS characteristics over the entire range, while the drain current decreases as the IGO channel thickness becomes thinner.

[0130] As can be seen in (c) of Fig. 29, the transistor with the p-Si / IGO hybrid channel has a larger off-leakage current as the drain voltage increases compared to the transistor with the IGO single channel, and V D It can be seen that the maximum current reaches about 15 nA at 1.1. This maximum value is similar to that of the p-Si channel due to the GIDL characteristic. Here, it can be seen that the p-Si channel generates hole current due to band-to-band tunneling (BTBT) caused by a strong electric field, even though it is an undoped channel without source / drain doping. In addition, it was observed that the proposed hybrid transistor exhibits a higher drain current than the transistor with an IGO single channel, despite the deterioration of the SS characteristic.

[0131] As can be seen in (d) of Fig. 29, the transistor (10 / 10) with a p-Si / IGO hybrid channel has a significantly higher mobility (p-Si / IGO: 63.78 cm) than the transistor (0 / 55) with a p-Si single channel reported previously. 2 / V·s, p-Si: 14.33 cm 2 / V·s) as well as a transistor with an IGO single channel (20 / 0: 57.14 cm 2 / V·s, 10 / 0: 43.15 cm 2 It can be confirmed that it exhibits higher mobility than / V·s).

[0132] Figure 30 is a drawing for explaining the structural characteristics of a hybrid thin film according to Experimental Example 4 of the present invention.

[0133] Referring to (a) and (b) of Fig. 30, depth profiles through TOFSIM analysis of a p-Si / IGO (20 nm / 20 nm) hybrid thin film are shown. More specifically, (a) of Fig. 30 shows the state before subsequent heat treatment, and (b) of Fig. 30 shows the state after subsequent heat treatment.

[0134] As can be seen in (a) and (b) of Fig. 30, silicon oxide (SiO) at the interface between IGO and p-Si x ) can be confirmed that p-Si is oxidized to form IGO. That is, it can be seen that p-Si is oxidized during the process of depositing IGO on p-Si.

[0135] Figure 30 (c) shows the XPS analysis results of a p-Si / IGO (20 nm / 20 nm) hybrid thin film after subsequent heat treatment, and Figure 30 (d) shows the area percentage of O 1s binding states. A shown in Figure 30 (d) means indium-O binding, B means oxygen deficiency, and C means OH and SiO binding.

[0136] More specifically, Fig. 30(c) shows the atomic percentages corresponding to the etching time of the post-annealed hybrid thin film through XPS spectrum analysis. Four etchings were performed: (1) etching time for the surface of the IGO thin film, (2) etching time for the bulk of the IGO thin film, (3) etching time for the interface between IGO and SiOx, and (4) etching time for SiOx.

[0137] To investigate the oxidation effect of p-Si at the interface between etching times (3) and (4), the O 1s spectra were deconvoluted into three different bonding states with corresponding binding energy values: state A (indium-O bond at 529.8 ± 0.1 eV), state B (oxygen deficiency at 531.1 ± 0.1 eV), and state C (OH and Si-O bond at 532.1 ± 0.1 eV).

[0138] This analysis is illustrated in Fig. 30(d), which shows the comparative area ratios of the deconvoluted O 1s spectra for IGO and SiO xThe interface between the IGO thin film and the SiO thin film corresponds to the intersection of states A and C, which are located between etching times (3) and (4), which is consistent with the results shown in (c) of Fig. 30. The area ratio of state B increases from 12.6% at etching time (1), 15.3% at etching time (2), and 30.0% at etching time (3) with the depth of the IGO thin film. These results indicate that the IGO and SiO thin film are interrelated. x This implies that an oxygen reduction reaction occurs in IGO due to the oxidation of p-Si at the interface between the two. This phenomenon is mainly attributed to state B, which occurs due to the formation of oxygen vacancies that generate electron carriers in the semiconductor oxide.

[0139] In particular, the increase in the area percentage of state B at etching time (3) is closely related to the high mobility of the proposed hybrid thin film, known as the percolation effect. However, the area percentage of state B at etching time (4) (12.5%) is similar to that at etching time (1), and as shown in (c) of Fig. 30, the O / Si ratio is 1.7, indicating an unstable oxidation state internally.

[0140]

[0141] Experimental Example 5: Verification of GIDL Erase Operation in 3D NAND Flash with p-Si / IGO Hybrid Channel

[0142] Figure 31 is a schematic diagram and a drawing for explaining the electrical characteristics of a transistor having a hybrid channel.

[0143] To verify the GIDL erase operation characteristics in 3D NAND flash memory structures, the IV curves of transistors with p-Si / IGO hybrid channels were initially examined, and model verification using physical models of p-Si and IGO channels was performed.

[0144] Figure 31 (a) shows a schematic diagram of a transistor with a hybrid channel and the physical parameter values ​​used in the TCAD simulation, Figure 31 (b) shows the BTBT model simulation results for confirming the IV curve of the p-Si channel, and Figure 31 (c) shows the results of various V GS The BTBT generation rate and electron / hole current density are shown in .

[0145] As can be seen in (a) of Fig. 31, the model parameters were set as follows to represent the general characteristics of the p-Si channel: trap model of p-Si (volume defect density), band gap (1.12 eV), electron affinity (4.05 eV), constant electron and hole mobility (14.33 cm cm 2 / V·s and 7.5 cm 2 / V·s). For the IGO channel, the volume defect density model of a typical n-type semiconductor oxide was set as follows: band gap (3.1 eV), electron affinity (4.35 eV), and constant electron and hole mobilities (63 and 0.1 cm 2 / V·s). Both p-Si and IGO channels used mobility and recombination models, which are general models of semiconductor materials: mobility models (doping-dependent and high-field saturation models) and recombination models (Shockley-Read-Hall, Auger, and interband BTBT models). Finally, the silicon gate was a p-type 1×10 21 cm -3 , and the work function of the source / drain contacts was set to 4.5 eV. In addition, no source / drain doping was applied to the p-Si channel.

[0146] Figure 31(b) shows the simulation results of the IV curve using the BTBT model for the p-Si channel, which indicates that the GIDL current is generated by the activation of the BTBT model. In addition, the V of -10 V is generated due to the high electric field-induced GIDL current. GSIt was confirmed that the GIDL current was the largest in the IGO, and since IGO has a greater electron affinity than poly-Si, the drain current was 10 V at V as shown in (c) of Figure 31. GS It can be confirmed that the dominant GIDL current flows most prominently in the drain region of the p-Si channel, while the dominant electron current originates from the IGO channel. These results indicate that the TCAD setup effectively replicates the IV curve characteristics of a transistor with a hybrid channel, while verifying the proper GIDL erase behavior in a 3D NAND flash memory structure based on the same physical model of the p-Si and IGO channels.

[0147] Figure 32 is a drawing for explaining the 3D NAND flash memory structure, equivalent circuit, and timing diagram of the erase operation used in the TCAD simulation.

[0148] Referring to (a) of Fig. 32, a 16-WL layer 3D NAND flash memory structure used in TAD simulation is shown, referencing (b) of Fig. 32, an equivalent circuit of a 3D NAND flash memory showing a GIDL erase mechanism is shown, and referencing (c) of Fig. 32, a timing diagram of an erase operation is shown.

[0149] More specifically, all structures include a BL, a select string line (SSL), a ground select line (GSL), a common source line (CSL), and 16 word lines (WL). The gate length and space length were both set to 30 nm, and the SiO2 / Si3N4 / SiO2 (ONO) thicknesses were set to 4 nm / 5 nm / 6 nm, respectively. The thicknesses of the p-Si channel and the IGO channel were both set to 10 nm, and the thickness of the p-Si / IGO channel was set to 2 nm (10 nm + 10 nm). Since the channel hole size was set to be the same (110 nm) for all three structures, the diameter of the oxide pillar was set to 30 nm for the p-Si and IGO single-channel structures, and 20 nm for the p-Si / IGO hybrid-channel structure.

[0150] The hybrid channel structure is n-type heavily doped (1 × 10 21 cm -3 ) connected the p-Si channel and IGO channel to the BL and CSL contacts through p-Si. In addition, the non-local tunneling model was activated for the erase operation of 3D NAND flash memory. Since 3D NAND flash memory has the structural characteristic of a floating channel in which only the SSL and GSL transistors are directly connected to the BL and CSL contacts, respectively, the memory cell cannot directly control the channel potential. In addition, since the existing 3D NAND flash memory technology adopts an n+ doped source p-Si channel, an erase operation using the GIDL mechanism is essential to increase the channel potential.

[0151] Referring to Fig. 32 (b), an equivalent circuit of a 3D NAND flash memory demonstrating the GIDL erasure mechanism is shown. To satisfy the GIDL generation condition, the erase voltage (V ) applied to BL and CSL ERS) must be sufficiently higher than the voltage applied to the GSL and SSL transistors. Under these GIDL conditions, the electron current (Ielectron) generated by BTBT flows in the BL direction, and the hole current (Ihole) flows in the channel direction at a relatively low potential. Afterwards, when the channel is sufficiently charged, holes are injected into the trap layer by the electric field caused by the difference between the channel potential and the WL bias, resulting in an erasure operation.

[0152] Referring to Fig. 32(c), a timing diagram of an erase operation is shown to verify the GIDL erase mechanism in a 3D NAND flash memory structure through TCAD simulation. Here, SSL and GSL transistors are connected to ground (GND) along with all WLs, and BL and CSL are connected to V ERS The rise time (t) is 5 μs. r ) was applied in the range of 0 to 15 V and the deletion pulse time (t er ) is 2ms.

[0153] Figure 33 is a drawing for explaining the simulation results of the deletion operation.

[0154] (a) of Figure 33 shows V during tr during the deletion operation. ERS We present simulation results for the variation of BL current (IBL) and average string channel potential (VB) of a 3D NAND channel as a function of V ERS As the V increases, there is no change in the IBL of the IGO channel, and consequently, there is no change in the VB, which means that no GIDL current occurs. On the other hand, both the conventional p-Si and hybrid structures have a V of 4 V. ERS Sufficient GIDL current is generated simultaneously, causing a rapid increase in IBL and a corresponding increase in VB. In addition, V of 7 V ERS In V ERS As V increases, IBL decreases until it reaches saturation, while ΔVB decreases until V ERS You can see that it follows.

[0155] Figure 33 (b) shows V of 4, 7 and 15 V. ERS We verify the GIDL operation mechanism by showing the hole density in the BL region of p-Si and hybrid structures in . Here, I holes is the V of 4V where the GIDL current is generated. ERS It occurs in the p-Si channel of both structures. On the other hand, in the IGO channel of the hybrid structure, I hole There is no path. After V ERS When it reaches 7V, the channel area of ​​the memory cell is I hole This is sufficiently supplied, and holes are accumulated in the p-Si channel. V ERS When the voltage is 15 V, the SSL transistor is also in the hole accumulation state and is strongly coupled with VERS due to the decrease in depletion capacitance. Therefore, due to this strong coupling, ΔVB is V as shown in (a) of Fig. 33. ERS will follow.

[0156] Figure 33 (c) shows ΔV during the full deletion operation in the conventional p-Si channel and hybrid channel (HC) structures. B and ΔV th It shows t r ΔV due to GIDL current in B Go V ERS After reaching V B Due to the high potential difference between t and WL er During this time, holes in the accumulated state of the p-Si channel are injected into the trap layer. These results demonstrate that the removal performance of the p-Si channel structure and the hybrid channel structure exhibit similar characteristics.

[0157] Also, t ersWe confirmed that sufficient holes were trapped in the nitride layer of the hybrid channel structure when the time was 2 ms. This indicates that the GIDL erase operation is normally observed in the 3D NAND flash memory structure. Therefore, the p-Si / IGO hybrid channel structure can implement an appropriate erase operation by appropriately using the p-Si channel, which proves that the proposed p-Si / IGO hybrid channel structure has GIDL erase compatibility characteristics.

[0158]

[0159] While the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to the specific embodiments described above, and should be interpreted in accordance with the appended claims. Furthermore, those skilled in the art will appreciate that numerous modifications and variations are possible without departing from the scope of the present invention.

[0160]

[0161] The present invention can be used in the semiconductor industry.

Claims

1. A step of preparing a base structure in which first and second material layers having different etching selectivities are alternately and repeatedly laminated; A step of forming a trench by etching the base structure in the direction in which the first material layer and the second material layer are laminated; A step of forming a first channel layer including silicon (Si) and extending in the direction in which the first material layer and the second material layer are laminated on the inner wall of the trench; A step of forming a second channel layer extending in the direction in which the first material layer and the second material layer are laminated on the first channel layer and including a semiconductor oxide; A step of selectively etching the second material layer among the first material layer and the second material layer to form a recess region between the adjacent first material layers in the base structure; A step of forming a charge storage layer so as to be in contact with the first channel layer within the recess region; and A method for manufacturing a stacked semiconductor device, comprising the step of forming a gate so as to be in contact with the charge storage layer within the recess region.

2. In paragraph 1, A method for manufacturing a stacked semiconductor device, comprising forming the first channel layer and the second channel layer using different methods.

3. In paragraph 1, A method for manufacturing a stacked semiconductor device, comprising: forming the first channel layer by chemical vapor deposition (CVD) and forming the second channel layer by atomic layer deposition (ALD).

4. In paragraph 1, The step of forming the second channel layer is: A step of providing a first precursor containing indium (In) on the first channel layer; A step of providing a first reactant containing oxygen on the first channel layer on which the first precursor is provided; A step of providing a second precursor including gallium (Ga) on the first channel layer provided with the first reactant; and A method for manufacturing a layered semiconductor device, comprising the step of providing a second reactant containing oxygen on the first channel layer on which the second precursor is provided.

5. In paragraph 4, The step of providing the first precursor and the step of providing the first reactant are defined as a first unit process, and the step of providing the second precursor and the step of providing the second reactant are defined as a second unit process. A method for manufacturing a stacked semiconductor device, wherein the first unit process and the second unit process are each performed repeatedly multiple times.

6. In paragraph 5, A method for manufacturing a stacked semiconductor device, wherein the number of repetitions of the first unit process is greater than the number of repetitions of the second unit process.

7. In paragraph 1, A step of forming a first oxide layer within the recessed region so as to be in contact with the first channel layer before the step of forming the charge storage layer after the step of forming the recessed region; and A method for manufacturing a stacked semiconductor device, further comprising a step of forming a second oxide layer within the recess region so as to be in contact with the charge storage layer before the step of forming the gate after the step of forming the charge storage layer.

8. In paragraph 1, A method for manufacturing a stacked semiconductor device, comprising forming the second channel layer on the first channel layer, thereby causing oxygen in the second channel layer to move from the second channel layer toward the first channel layer, thereby forming oxygen vacancies in the second channel layer.

9. A laminated structure in which an insulating layer and an electrode layer are alternately and repeatedly laminated, and a trench is formed in the direction in which the insulating layer and the electrode layer are laminated; A first channel layer disposed on the inner wall of the trench, extending in the direction in which the insulating layer and the electrode layer are laminated, and including silicon (Si); and A second channel layer is disposed on the first channel layer, extends in the direction in which the insulating layer and the electrode layer are laminated, and includes a semiconductor oxide. A stacked semiconductor device, wherein the electrode layer includes a gate arranged to be spaced apart from the first channel layer in a direction perpendicular to the direction in which the first channel layer extends, and a charge storage layer arranged between the gate and the first channel layer.

10. In paragraph 9, A stacked semiconductor device applied to V-NAND, wherein a write operation is performed through the second channel layer and an erase operation is performed through the first channel layer.

11. In paragraph 9, A stacked semiconductor device, wherein the second channel layer comprises IGO (Indium-Gallium-Oxide).

12. In paragraph 9, A stacked semiconductor device, comprising a second channel layer having a thickness of 10 nm or more.

13. In paragraph 9, A stacked semiconductor device comprising a silicon oxide layer formed between the first channel layer and the second channel layer.

14. A laminated structure in which an insulating layer and an electrode layer are alternately and repeatedly laminated, and a trench is formed in the direction in which the insulating layer and the electrode layer are laminated; A first channel layer disposed on the inner wall of the trench, extending in the direction in which the insulating layer and the electrode layer are laminated, and including silicon (Si); A second channel layer disposed on the first channel layer, extending in the direction in which the insulating layer and the electrode layer are laminated, and including a semiconductor oxide; and Including a tin oxide layer disposed between the first channel layer and the second channel layer, A stacked semiconductor device, wherein the electrode layer includes a gate arranged to be spaced apart from the first channel layer in a direction perpendicular to the direction in which the first channel layer extends, and a charge storage layer arranged between the gate and the first channel layer.

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