Method for optimizing junctionless transistor

Abstract

The present application provides a method for optimizing a junctionless transistor. The junctionless transistor comprises a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate on the shell layer, and a source and a drain on two sides of the gate, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer, and the value of a back bias can be determined for the junctionless transistor on the basis of the type of the junctionless transistor, wherein if the type of the junctionless transistor is an N-type device, the value of the back bias is a negative value, and if the type of the junctionless transistor is a P-type device, the value of the back bias is a positive value. When the junctionless transistor is in a working state, the back bias can be applied to the substrate, the electric field generated by the back bias is transmitted to the core layer and the shell layer by means of the buried oxide layer, and the generated electrostatic doping effect can flexibly control the carrier concentration distribution inside the source / drain and a channel, so as to reduce the source-drain series resistance of the junctionless transistor. Therefore, the conductivity of a device can be increased without changing the internal structure of the device, thereby increasing the output current.

Description

A junction-less transistor optimization method

[0001] This application claims priority to the Chinese patent application No. 202411012001.8, filed on July 25, 2024, and entitled "A junction-less transistor optimization method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor, in particular to a junction-less transistor optimization method. BACKGROUND

[0003] Fully Depleted Silicon on Insulator (FDSOI) uses a special structure to improve the performance and power consumption of semiconductor devices, which forms an insulating layer on the substrate and a thin layer of single-crystal silicon in the insulating layer, the insulating layer is usually silicon dioxide, known as a buried oxide (BOX), and the thin layer of single-crystal silicon is known as a top silicon or SOI layer, realizing a silicon on insulator (SOI) structure of top silicon-BOX-bottom silicon. And by thinning the thickness of the top silicon to make the depletion layer fill the entire channel region, i.e. fully depleted, to realize fully depleted silicon on insulator.

[0004] Junction-less (JL) transistors are of great interest due to their simple manufacturing process and potential in three-dimensional integration requiring low thermal budget. The source and drain of the JL transistor are uniformly doped, so the JL transistor has no junction, and it is turned off by depleting the carriers in the channel, has strong ability to suppress short channel effect, and has complete CMOS function. In addition, JL transistors also have the advantages of simple process, multi-threshold adjustment, low noise, etc. However, JL transistors also have some fundamental weaknesses: lower mobility, higher contact resistance, negative threshold voltage, etc. Therefore, in order to solve these problems, a Core-Shell Junction-less (CS-JL) transistor is proposed.

[0005] Core-Shell Junction-less transistor is a new type of junction-less transistor based on FDSOI technology. Compared with traditional junction-less transistors, the Core-Shell structure of the Core-Shell Junction-less transistor re-dopes the top silicon of the traditional FDSOI wafer as the Core layer, and adds a layer of ultra-thin lightly doped or undoped Shell layer on it, which can achieve positive threshold voltage and high on-state current, retains the advantages of JL transistor, and avoids its shortcomings. However, CS-JL transistors also have the demand to improve device performance. SUMMARY

[0006] Therefore, the present application aims to provide a method for optimizing a junctionless transistor, by applying a back bias to the junctionless transistor to reduce the source-drain series resistance of the junctionless transistor, and optimize the performance of the junctionless transistor.

[0007] The present application provides a method for optimizing a junctionless transistor, the junctionless transistor comprising a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate on the shell layer, a source and a drain on both sides of the gate; the doping concentration of the shell layer is less than the doping concentration of the core layer; the method comprising:

[0008] determining a value of a back bias for the junctionless transistor according to the type of the junctionless transistor; wherein, if the type of the junctionless transistor is an N-type device, the back bias is a positive value; if the type of the junctionless transistor is a P-type device, the back bias is a negative value;

[0009] applying the back bias to the substrate when the junctionless transistor is in a working state, to reduce the source-drain series resistance of the junctionless transistor.

[0010] Optionally, the doping concentration of the core layer is less than or equal to 1e20.

[0011] Optionally, the method further comprises:

[0012] determining a sign of the back bias for the junctionless transistor according to the type of the junctionless transistor, the sign of the back bias being positive or negative;

[0013] determining an absolute value of the back bias for the junctionless transistor according to the doping concentration of the core layer; the absolute value of the back bias is positively correlated with the doping concentration of the core layer.

[0014] Optionally, the method further comprises:

[0015] determining a sign of the back bias for the junctionless transistor according to the type of the junctionless transistor, the sign of the back bias being positive or negative;

[0016] determining an absolute value of the back bias for the junctionless transistor according to at least one of the thickness of the substrate, the thickness of the buried oxide layer, the thickness of the core layer and the thickness of the shell layer; the absolute value of the back bias is positively correlated with the thickness of the substrate, the thickness of the buried oxide layer, the thickness of the core layer and the thickness of the shell layer, respectively.

[0017] Optionally, the range of the back bias is -2V-2V.

[0018] Optionally, the absolute value of the back bias is determined as a first value when the amorphous transistor is a first device of P type, and the absolute value of the back bias is determined as a second value when the amorphous transistor is a second device of N type; if the device parameters of the first device and the second device are the same except for the doping elements, the first value is greater than the second value.

[0019] Optionally, a high-k dielectric layer is formed between the shell layer and the gate electrode, and a sidewall is arranged on the sidewall of the gate electrode.

[0020] Optionally, the material of the high-k dielectric layer is HfO2, and the thickness range is [1 nm, 1.5 nm].

[0021] Optionally, the thickness of the core layer is 3-10 nm, and the thickness of the shell layer is 3-10 nm.

[0022] Optionally, the thickness of the buried oxide layer is 15 nm, and the materials of the core layer and the shell layer are silicon.

[0023] The application provides an optimization method of an amorphous transistor, the amorphous transistor comprising a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate electrode on the shell layer, a source electrode and a drain electrode on both sides of the gate electrode, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer, and the value of a back bias of the amorphous transistor can be determined according to the type of the amorphous transistor, wherein the back bias is a negative value when the type of the amorphous transistor is an N type device, and the back bias is a positive value when the type of the amorphous transistor is a P type device, and the back bias can be applied to the substrate when the amorphous transistor is in a working state, an electric field generated by the back bias is transmitted to the core layer and the shell layer through the buried oxide layer, and the electrostatic doping effect can flexibly control the carrier concentration distribution in the source-drain and the channel, so as to reduce the source-drain series resistance of the amorphous transistor, thereby increasing the conductive capacity of the device without changing the internal structure of the device, and improving the output current. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0025] FIG. 1 shows a flowchart of an optimization method of an amorphous transistor according to an embodiment of the application;

[0026] FIG. 2 is a structural schematic diagram of an amorphous transistor according to an embodiment of the application;

[0027] FIG. 3 is a schematic diagram of applying a back bias according to an embodiment of the application;

[0028] FIG. 4 is a schematic diagram of a carrier density between a gate dielectric layer and a buried oxide layer according to an embodiment of the present application;

[0029] FIG. 5 is a schematic diagram of a band between a source and a shell according to an embodiment of the present application;

[0030] FIG. 6 is a schematic diagram of an electrical conductivity according to an embodiment of the present application;

[0031] FIG. 7 is a schematic diagram of a source-drain series resistance according to an embodiment of the present application;

[0032] FIG. 8 is a schematic diagram of another source-drain series resistance according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the personnel in the technical field better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0034] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0035] The present application is described in detail in conjunction with the schematic diagram, and when the embodiments of the present application are described, in order to facilitate the description, the cross-sectional view showing the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacture.

[0036] Core-shell devices, as a special kind of nanodevices, have great significance for the increasing demand of subsequent market in advanced nodes, especially in the fields of energy, sensors, optics, etc., they provide more efficient, more flexible, more environmentally friendly solutions, which benefits from their advantages in performance, scalability, design flexibility, suitable for harsh environments, etc.

[0037] The advantages of the Core-Shell structure coreless transistor are as follows: first, the traditional coreless device has a serious influence of Coulomb scattering on the carriers in the channel due to the uniform doping between the source and the drain, and the mobility is very poor, while the Core-Shell coreless transistor mainly contributes to the current from the undoped shell, which can greatly improve the overall carrier mobility; second, it has a positive and easy-to-adjust threshold voltage, which is controlled by the doping concentration and size (thickness) of the core, overcoming the always-on characteristics of the traditional coreless device due to high doping; third, the variability problem caused by random dopant fluctuation (RDF) in the coreless device can be alleviated by the presence of the shell, which not only effectively suppresses some common shortcomings of the traditional coreless device, but also retains the fundamental advantages of the coreless device, further optimizing the performance of the device.

[0038] With the reduction of device size, the performance of semiconductor devices and circuits will be degraded due to the existence of source-drain series resistance (also known as parasitic source-drain resistance), which is manifested in the transistor as a decrease in the voltage driving capability of the device, heat generated by current passing through the resistance and increased power consumption, and as the research and industrial demand deepens, the size of the transistor is gradually reduced, and the channel length and junction depth are also shortened in proportion, which causes the source-drain series resistance to occupy a larger proportion in the total resistance value. The CS device also inevitably has problems such as degradation of driving current caused by source-drain series resistance, so in order to effectively alleviate the difficulties and challenges faced by Core-Shell coreless transistors for advanced nodes, it is particularly important to study how to reduce the source-drain series resistance, a technical difficulty.

[0039] At present, this demand can be achieved by optimizing the process flow, changing the doping concentration, etc., but these methods still have many unstable factors. For example, the most common operation is to heavily dope the source and drain, but from the process point of view, this step requires source and drain doping and activation (high-temperature rapid annealing step), and such 3D sequential integration has high requirements for thermal budget, so it is difficult to control in the actual manufacturing process, and changing the internal doping of the device may cause degradation of other performance, which is contrary to the original intention of optimizing device performance by reducing source-drain series resistance.

[0040] Based on the above technical problems, the embodiment of the present application provides an optimization method of a junctionless transistor, the junctionless transistor comprising a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate on the shell layer, a source and a drain on both sides of the gate, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer, and the value of back bias of the junctionless transistor is determined according to the type of the junctionless transistor, wherein the back bias is negative if the type of the junctionless transistor is an N-type device, and the back bias is positive if the type of the junctionless transistor is a P-type device, and the back bias is applied to the substrate when the junctionless transistor is in a working state, an electric field generated by the back bias is transmitted to the core layer and the shell layer through the buried oxide layer, and the electrostatic doping effect generated can flexibly control the carrier concentration distribution in the source, the drain and the channel, so as to reduce the source-drain series resistance of the junctionless transistor, thereby increasing the conductive capacity of the device without changing the internal structure of the device, and improving the output current.

[0041] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0042] Referring to FIG. 1, which is a flowchart of an optimization method of a junctionless transistor provided by the embodiment of the present application, the method can comprise:

[0043] S101, determining the value of back bias of the junctionless transistor according to the type of the junctionless transistor.

[0044] S102, applying the back bias to the substrate when the junctionless transistor is in a working state, so as to reduce the source-drain series resistance of the junctionless transistor.

[0045] Referring to FIG. 2, which is a structural schematic diagram of a junctionless transistor provided by the embodiment of the present application, the junctionless transistor comprises a substrate 100, a buried oxide layer 110 on the substrate, a core layer 150 on the buried oxide layer 110, a shell layer 160 on the core layer 150, a gate 170 on the shell layer 160, a source 130 and a drain 140 on both sides of the gate 170.

[0046] In the embodiment of the present application, the substrate 100 can be a semiconductor substrate for providing support for the film layer thereon, for example, a silicon substrate, a germanium substrate, etc., and the substrate 100 can be circular in the manufacturing process, for example, a silicon wafer, on which a plurality of chips can form an array to realize the same batch manufacturing of a plurality of chips and improve the manufacturing efficiency.

[0047] A buried oxide layer (BOX) 110, a core layer 150 and a shell layer 160 can be formed on the substrate 100. The materials of the core layer 150 and the shell layer 160 can be the same. When the materials of the core layer 150 and the shell layer 160 are silicon, the substrate 100, the buried oxide layer 110, the core layer 150 and the shell layer 160 constitute an SOI substrate.

[0048] The buried oxide layer 110 is an insulating layer, which is used to isolate the core layer and the substrate 100, and avoid the leakage of the carriers in the core layer from the substrate 100 during the operation of the device. The buried oxide layer 110 can be silicon oxide, germanium oxide, etc. The thickness of the buried oxide layer can be 15 nm, for example.

[0049] The core layer 150 is part of the channel layer, and the material thereof can be silicon or germanium, etc. The thickness of the core layer 150 can range from 3 nm to 10 nm, specifically from 3 nm to 5 nm, for example, 3 nm. The doping concentration of the core layer 150 is greater than or equal to 1018cm-3. 19 cm -3 .

[0050] The shell layer 160 is part of the channel layer, and the material thereof can be silicon or germanium, etc. The thickness of the shell layer 160 can range from 3 nm to 10 nm, specifically from 3 nm to 5 nm, for example, 4 nm. The doping concentration of the shell layer 160 is less than that of the core layer 150, and the shell layer 160 can be lightly doped or undoped, for example, the shell layer 160 is an undoped film layer. When the materials of the core layer 150 and the shell layer 160 are both silicon, the two constitute a floating silicon layer.

[0051] The shell layer 160 has a gate (G) 170 thereon, which is used to be applied with a gate voltage. In addition, a gate dielectric layer 171 can be further formed between the gate 170 and the shell layer 160, which is used to isolate the gate 170 and the shell layer 160. The gate dielectric layer 171 can be a high-k dielectric layer, or silicon oxide, HfO2, etc., and the thickness thereof ranges from 1 nm to 1.5 nm.

[0052] A source (S) 130 can be formed on one side of the gate 170, and a drain (D) 140 can be formed on the other side of the gate 170. The gate 170 can have a side wall on the side wall facing the source 130 and the side wall facing the drain 140, and the side wall includes a first side wall 172 and a second side wall 173, which are respectively used to isolate the gate 170 and the source 130 and the drain 140. A source contact 131 can be formed on the source 130, and a drain contact 141 can be formed on the drain 140. The source contact 131 and the drain contact 141 can be metal silicide, which is used to reduce the series resistance of the source and the drain.

[0053] In a core-shell junctionless transistor, the core initially operates in a fully depleted state. As the gate voltage increases, the core begins to conduct, and the shell, activated by the gate voltage, also begins to conduct. Although the shell is undoped, the electric field provided by the gate voltage provides a high concentration of charge carriers to continuously fill its interior. Because it is undoped, it is almost unaffected by Coulomb scattering at room temperature. Simultaneously, due to the extremely high carrier concentration gradient between the source and the shell, source carriers more easily enter the channel region. These factors lead to a sharp increase in carrier mobility within the channel. Therefore, unlike traditional junctionless devices, the current contribution of a core-shell junctionless transistor largely comes from the gate-biased carriers in the shell, with a smaller portion originating from the core. Its electron distribution is remarkably similar to that of a crystalless material with the same thickness and doping information. The gate voltage not only opens the core from a fully depleted state to a near-flat band state but also, due to the activation of the shell, provides carriers with extremely high mobility and expands the effective width of the device, further enhancing its conductivity.

[0054] In this embodiment, a back-gate bias voltage (referred to as back bias) can be applied to the junctionless transistor during its operation. The electric field provided by the back-gate bias voltage is transmitted to the floating silicon layer (i.e., the core layer and the shell layer) through the buried oxide layer. The carrier concentration distribution inside the source, drain, and channel is flexibly controlled by the electrostatic doping effect. Ultimately, the goal of effectively reducing the source-drain series resistance is achieved without changing the internal structure and doping information of the device. This can further optimize the device performance, greatly improve the switching speed, driving capability, and other performance indicators of the device, and reduce power consumption and heat dissipation of the product.

[0055] Furthermore, reducing the source-drain series resistance by applying an external voltage eliminates the need for complex manufacturing processes and offers excellent stability and reliability. This technology can significantly reduce overall product operating costs and improve system efficiency, resulting in substantial economic benefits. It also holds significant value and importance for future research into advanced nodes in junctionless devices.

[0056] The back gate bias can be applied directly to the substrate or to the back gate connected to the substrate. The back bias can be set on the substrate and is independently set from the source, drain, gate, shell, and core layers, and can be isolated from these components by an insulating layer.

[0057] Back bias can be continuously applied while the device is in the working state (the device is in the working state when the circuit it is in is powered on). When the gate voltage is greater than the threshold voltage, the device is in the open state. At this time, the back bias has a more significant effect on reducing the source-drain series resistance.

[0058] The essence of applying back bias is actually the electrostatic doping inside the semiconductor device, which provides an ultra-shallow junction with good quality through the electrostatic interaction between different materials at the semiconductor and interface. Unlike the traditional method of changing the source-drain and channel doping concentration or doping type, electrostatic doping does not need to be realized from the process, but only needs to apply a voltage to the back gate to make the free carriers gather or dilute at the interface, thereby realizing the same effect of the traditional impurity doping. The advantage of electrostatic doping is to generate a simulated junction in the initially undoped or even completely depleted body, where the polarity and concentration of the internal carriers can be controlled by the gate bias. The minority carriers diffuse from the gate interface to the bottom interface, filling the entire space charge region, thereby improving the conductivity of the channel.

[0059] Referring to FIG. 3, a schematic diagram of applying a back bias provided by an embodiment of the present application is shown. The drain of the device applies a drain voltage V d , the gate applies a gate voltage V g , and when a voltage V bg is applied to the back gate of the device, additional charges are introduced in the floating body silicon layer to compensate for the potential of the back gate, reducing the effective electron (hole) concentration in the channel region. At this time, a built-in electric field is superimposed in the channel, which is based on the principle of electrostatic doping and can intensify the drift of carriers in the shell and core.

[0060] Specifically, if the amorphous transistor is an N-type device, the core layer is N-type doped, and the back bias is positive; if the amorphous transistor is a P-type device, the core is P-type doped, and the back bias is negative. To provide the corresponding electrostatic doping effect, intensify the drift of carriers in the shell and core, and reduce the source-drain series resistance of the device.

[0061] The doping concentration of the core layer can be less than or equal to 1e20, because when the doping concentration is small, the effect of back bias modulation will be more obvious. Of course, in the case where the doping concentration of the core layer is greater than 1e20, a back bias can also be applied to the amorphous transistor, but the effect of back bias modulation is relatively weak. The range of the back bias is approximately -2V ~ 2V.

[0062] Specifically, the sign of the back bias can be determined according to the type of the amorphous transistor, and the sign of the back bias is positive or negative. Then, the absolute value of the back bias can be determined according to the doping concentration of the core layer. In actual operation, the absolute value of the back bias is positively correlated with the doping concentration of the core layer, because the larger the absolute value of the back bias is, the more obvious the modulation effect is under the same doping concentration, and the larger the doping concentration of the core layer is, the less obvious the modulation effect is under the same back bias. Therefore, the larger the doping concentration of the core layer is, the larger the absolute value of the back bias can be set to achieve a better modulation effect. Specifically, a corresponding relationship between the doping concentration range and the absolute value of the back bias can be established. When the doping concentration of the core layer is within a certain range, the absolute value of the back bias corresponding to the range can be determined. The larger the doping concentration in the doping concentration range is, the larger the corresponding absolute value of the back bias is. For example, when the doping concentration of the core layer is within the range of 1e18-1e20, the absolute value of the back bias can be 1-2V.

[0063] Specifically, the sign of the back bias can be determined according to the type of the amorphous transistor, and the sign of the back bias is positive or negative. Then, the absolute value of the back bias can be determined according to the doping concentration of the core layer. In actual operation, the absolute value of the back bias is positively correlated with the doping concentration of the core layer, because the larger the absolute value of the back bias is, the more obvious the modulation effect is under the same doping concentration, and the larger the doping concentration of the core layer is, the less obvious the modulation effect is under the same back bias. Therefore, the larger the doping concentration of the core layer is, the larger the absolute value of the back bias can be set to achieve a better modulation effect. Specifically, a corresponding relationship between the doping concentration range and the absolute value of the back bias can be established. When the doping concentration of the core layer is within a certain range, the absolute value of the back bias corresponding to the range can be determined. The larger the doping concentration in the doping concentration range is, the larger the corresponding absolute value of the back bias is. For example, when the doping concentration of the core layer is within the range of 1e18-1e20, the absolute value of the back bias can be 1-2V.

[0064] In the embodiments of the present application, the absolute value of the back bias is determined as a first value when the amorphous transistor is a first device of P type, and the absolute value of the back bias is determined as a second value when the amorphous transistor is a second device of N type; if the device parameters of the first device and the second device are the same except for the doping elements, the first value is greater than the second value. That is, if the amorphous transistor of P type and the amorphous transistor of N type are the same except for the doping elements, a larger back gate can be provided for the amorphous transistor of P type, because the current of the P tube is usually smaller than that of the N tube under the same size, and therefore the current of the P tube can be greatly improved under the condition of a larger back gate. In this way, in the case where the currents of the N tube and the P tube need to be matched in a basic gate circuit such as a difference circuit, a difference amplifier or an inverter, the current matching of the two devices of the same size can be achieved by applying different back biases or only applying a back bias to the P tube.

[0065] Of course, the absolute value of the back bias can also be determined in combination with multiple of the doping concentration of the core layer, the type of the amorphous transistor, the thickness of the substrate, the thickness of the buried oxygen layer, the thickness of the core layer and the thickness of the shell layer.

[0066] Taking the amorphous transistor of N type as an example, referring to FIG. 4, a schematic diagram of the carrier density between the gate dielectric layer and the buried oxygen layer is provided, the horizontal coordinate is the position in the longitudinal direction of the device, the left side is the gate dielectric layer, the right side is the buried oxygen layer, the left half of the middle gray part is the shell, the right half is the core, the vertical coordinate is the electron density (eDensity), the curve in the middle gray part indicates the carrier density at this position under different back biases, and referring to FIG. 5, a band diagram between the source and the shell is provided, the horizontal coordinate is the position in the transverse direction of the device, the left side is the source, the right side is the shell, and the middle gray part is the intermediate position between the source and the shell, the vertical coordinate is the energy level, and the curve in the middle gray part indicates the energy level at this position under different back biases.

[0067] As can be seen from FIGS. 4 and 5, under the condition of applying different back biases V bg , in the core-shell, when a negative back bias is applied, the carriers (holes) in the core enter the shell and accumulate in the shell, the electron concentration in the shell decreases, the potential barrier at the shell is lifted, and the difficulty of the carriers crossing the potential barrier into the channel is increased, as shown in the band diagram of the source to the shell under different back biases in FIG. 5, which is manifested as an increase in the series resistance of the source and the drain. When a positive back bias is applied, the carriers (holes) in the shell enter the core under the action of the electric field, the hole concentration in the shell decreases, the electron concentration increases, the potential barrier at the shell is lower than that when no back bias is applied, and therefore the carriers (holes) in the source can more easily enter the channel, reducing the junction resistance.

[0068] Referring to FIG. 6, a schematic diagram of electrical conductivity is provided for an embodiment of the present application, the horizontal coordinate is the position of the longitudinal direction of the device, the left white area is the source edge position, the right is the buried oxygen layer, the vertical coordinate is the electrical conductivity σ, the unit is Siemens per meter (S / cm), by observing the change of the electrical conductivity of the source end under the application of different back bias, the influence of back bias on the source-drain series resistance of the source and drain can be intuitively reflected, when the positive back bias is applied, the electrical conductivity of the source end can be obviously improved, so from the principle level, when the positive back bias is applied to the Core-Shell amorphous transistor, the source-drain series resistance of the source and drain can be reduced as a whole.

[0069] Referring to FIG. 7, a schematic diagram of the source-drain series resistance is provided for an embodiment of the present application, the horizontal coordinate is the gate voltage (Overdrive Voltage), the unit is V, the vertical coordinate is the source-drain series resistance R sd *W, the unit is Ω*cm, referring to FIG. 8, another schematic diagram of the source-drain series resistance is provided for an embodiment of the present application, the horizontal coordinate is the back bias, the unit is V, the vertical coordinate is the source-drain series resistance R sd *W, the unit is Ω*cm, wherein W is the channel width.

[0070] Specifically, a Core-Shell amorphous transistor can be selected by using TCAD simulation to apply different back bias values, and by observing the electrical performance of the transistor under different channel lengths, the transfer characteristic curve can be drawn, and then the threshold voltage can be obtained by first derivative of the capacitance, and finally the source-drain series resistance of the device, i.e. the series resistance between the source and drain, can be extracted. The Modified-TLM method is used to extract the source-drain series resistance under different bias, and by observing the curve change in the figure, it can be observed that when the positive back bias V BG (i.e. V bg ) is applied, the source-drain series resistance of the device has a significant downward trend, and when other conditions remain unchanged, the greater the value of the applied positive back bias V BG , the more obvious the improvement of the source-drain series resistance, which effectively proves that the scheme of applying back bias to the Core-Shell amorphous transistor to reduce the source-drain series resistance is feasible.

[0071] The application provides an optimization method of a junctionless transistor, the junctionless transistor comprising a substrate, a buried oxygen layer on the substrate, a core layer on the buried oxygen layer, a shell layer on the core layer, a gate on the shell layer, a source and a drain on both sides of the gate, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer, and the value of back bias of the junctionless transistor is determined according to the type of the junctionless transistor, wherein the back bias is negative if the type of the junctionless transistor is an N-type device, and the back bias is positive if the type of the junctionless transistor is a P-type device, and the back bias is applied to the substrate when the junctionless transistor is in a working state, an electric field generated by the back bias is transmitted to the core layer and the shell layer through the buried oxygen layer, and the electrostatic doping effect generated can flexibly control the carrier concentration distribution in the source, the drain and the channel, so as to reduce the series resistance of the source and the drain of the junctionless transistor, and therefore the conductive capacity of the device can be increased without changing the internal structure of the device, and the output current is improved.

[0072] The above only describes the preferred embodiments of the application, and the application is disclosed as above with the preferred embodiments, but is not used to limit the application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the application or modify equivalent embodiments with the disclosed methods and technical contents without departing from the scope of the technical solutions of the application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application without departing from the content of the technical solutions of the application still belongs to the protection scope of the technical solutions of the application.

Claims

1. An optimization method of a junctionless transistor, characterized in that, the junctionless transistor comprises a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate on the shell layer, a source and a drain on both sides of the gate; a doping concentration of the shell layer is less than a doping concentration of the core layer; the method comprises: determining a value of a back bias for the junctionless transistor according to a type of the junctionless transistor; wherein, if the type of the junctionless transistor is an N-type device, the back bias is a positive value; if the type of the junctionless transistor is a P-type device, the back bias is a negative value; applying the back bias to the substrate when the junctionless transistor is in a working state to reduce a source-drain series resistance of the junctionless transistor.

2. The method of claim 1, wherein, the doping concentration of the core layer is less than or equal to 1e20.

3. The method of claim 2, wherein, the determining of the value of the back bias for the junctionless transistor according to the type of the junctionless transistor comprises: determining a sign of the back bias for the junctionless transistor according to the type of the junctionless transistor, the sign of the back bias being positive or negative; determining an absolute value of the back bias for the junctionless transistor according to the doping concentration of the core layer; the absolute value of the back bias being positively correlated with the doping concentration of the core layer.

4. The method of claim 1, wherein, the determining of the value of the back bias for the junctionless transistor according to the type of the junctionless transistor comprises: determining a sign of the back bias for the junctionless transistor according to the type of the junctionless transistor, the sign of the back bias being positive or negative; determining an absolute value of the back bias for the junctionless transistor according to at least one of a thickness of the substrate, a thickness of the buried oxide layer, a thickness of the core layer and a thickness of the shell layer; the absolute value of the back bias being positively correlated with the thickness of the substrate, the thickness of the buried oxide layer, the thickness of the core layer and the thickness of the shell layer respectively.

5. The method according to any one of claims 1 to 4, characterized in that, the range of the back bias is -2V-2V.

6. The method according to any one of claims 1 to 5, characterized in that, an absolute value of the back bias is determined as a first value when the junctionless transistor is a first device of a P-type, and an absolute value of the back bias is determined as a second value when the junctionless transistor is a second device of an N-type; if device parameters of the first device and the second device are the same except for a doping element, the first value is greater than the second value.

7. The method according to any one of claims 1 to 6, characterized in that, a high-k dielectric layer is formed between the shell layer and the gate, and a sidewall is arranged on a sidewall of the gate.

8. The method of claim 7, wherein, a material of the high-k dielectric layer is HfO2, and a thickness range of the high-k dielectric layer is [1nm, 1.5nm].

9. The method according to any one of claims 1 to 8, characterized in that, a thickness range of the core layer is 3-10nm, and a thickness range of the shell layer is 3-10nm.

10. The method according to any one of claims 1 to 9, characterized in that, a thickness of the buried oxide layer is 15nm, and materials of the core layer and the shell layer are silicon.

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