Small-sized oxide semiconductor etching method

Abstract

A small-sized oxide semiconductor etching method, which belongs to the technical field of information materials and devices. Firstly, a nanowire material is obtained by means of a low-temperature process, and the diameter of a nanowire is then further miniaturized by using a method of auto-oxidation combined with self-limiting etching, thereby realizing self-alignment and high-precision etching of an oxide semiconductor in a small size. Compared with other conventional mask etching methods relying on the exposure accuracy of devices such as DUV and EUV, the method solves the problem of size miniaturization of existing oxide semiconductor devices, can improve the density of an integrated circuit, can greatly reduce the requirements for photolithography devices, and can effectively reduce process costs.

Description

Method for etching oxide semiconductor with small size TECHNICAL FIELD

[0001] The present application relates to a method for etching oxide semiconductor with small size, belonging to the technical field of information materials and devices. BACKGROUND

[0002] Oxide semiconductor material has great advantages in the field of thin film transistor of flat panel display due to its unique high mobility, high light transmittance and large-area uniformity, and the characteristic of this application is that the device size is micron level. In recent years, with the in-depth study of oxide semiconductor material and device, it is found that the ultra-low off-state current caused by wide band gap, low mechanical stress caused by amorphous characteristics and low process thermal budget for realizing the compatibility of the later stage make oxide semiconductor become one of the most potential materials for realizing high-density and high-energy efficiency three-dimensional integrated circuit.

[0003] At present, oxide semiconductor devices with channel length and width within hundreds of nanometers can be realized by optimizing exposure and etching process, and good device performance is shown, which shows the application potential of oxide semiconductor in integrated circuit field. However, the realization of small size device requires high requirements for photolithography and etching equipment, and it is difficult to realize high yield and large area preparation. SUMMARY

[0004] In order to solve the problem of size miniaturization existing in the existing oxide semiconductor device and improve the integrated circuit density, the present application provides a method for etching oxide semiconductor with small size.

[0005] The technical scheme provided by the present application is as follows:

[0006] A method for etching oxide semiconductor with small size, comprising the following steps:

[0007] Step 1) preparing an amorphous silicon layer on the oxide semiconductor material to be etched;

[0008] Step 2) annealing at low temperature, using the metal in the oxide semiconductor material to induce lateral crystallization of the amorphous silicon layer to form polycrystalline silicon;

[0009] Step 3) oxidizing the surface layer of polycrystalline silicon to SiO2 by thermal oxidation and oxygen plasma treatment, and then removing the surface layer SiO2 by high-selectivity dry etching method, repeating several times to reduce to the required diameter to form silicon nanowire;

[0010] Step 4) using the silicon nanowire obtained in step 3) as a hard mask, and using wet etching or dry etching method to etch the oxide semiconductor material;

[0011] Step 5) removing the silicon nanowire hard mask without damaging the oxide semiconductor material by ion beam etching with a shaping function.

[0012] Further, step 1) is prepared by an amorphous silicon layer by a process of plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, pulsed vapor deposition or atomic layer deposition.

[0013] Further, step 1) is that the thickness of the amorphous silicon layer ranges from 20 nanometers to 200 nanometers.

[0014] Further, step 2) is that the temperature ranges from 150 ℃ to 400 ℃.

[0015] Further, step 3) is that the dry etching method is specifically a reactive ion etching, a reactive coupled plasma etching or an atomic layer etching.

[0016] Further, step 3) is that the diameter of the silicon nanowire ranges from 10 nanometers to 200 nanometers. The length ranges from about 50 nanometers to 2000 nanometers.

[0017] Further, the oxide semiconductor is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO and the like, as well as all oxide semiconductor single-layer thin films and multi-layer oxide thin film stacks of various doping components and proportions. The thickness ranges from about 0.5 nanometers to 50 nanometers.

[0018] The beneficial effects of the present application are as follows:

[0019] The present application proposes to use nanowire material as a self-aligned hard mask for etching, to realize small size etching by self-oxidation and self-limiting etching of nanowires, while reducing the demand for exposure equipment. The present application has great potential in improving the integration density of oxide semiconductor transistors. BRIEF DESCRIPTION OF DRAWINGS

[0020] Fig. 1-8 is a process flow chart of a specific embodiment of the present application;

[0021] Fig. 9 is an example illustration of Fig. 1-8. Specific implementation method

[0022] The embodiments of the present application will be described in detail below by means of implementation examples, which are shown in the accompanying drawings. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be explained as a limitation of the present application.

[0023] The implementation example is to etch an indium oxide film. Specifically, it includes the following steps:

[0024] S001, preparing an indium oxide thin film on a substrate, with a thickness ranging from about 0.5 nm to 50 nm, as shown in FIG. 1.

[0025] S002, preparing an amorphous silicon layer by plasma enhanced chemical vapor deposition, as shown in FIG. 2.

[0026] S003, heating the sample in an annealing furnace, and the amorphous silicon on the surface of the indium oxide crystallizes into polycrystalline silicon under the induction of indium metal. In this example, the temperature is 350°C, and the atmosphere is nitrogen, as shown in FIG. 3.

[0027] S004, oxidizing the polycrystalline silicon and the surface layer of residual amorphous silicon by thermal oxidation, as shown in FIG. 4.

[0028] S005, removing the SiO2 on the surface layer without affecting the internal polycrystalline silicon by dry etching based on CHF3 gas and oxygen, as shown in FIG. 5.

[0029] S006, repeating the S004 and S005 steps until the polycrystalline silicon is reduced to the desired size, forming a silicon nanowire, as shown in FIG. 6.

[0030] S007, using the silicon nanowire as a self-aligned mask, removing the uncovered indium oxide material by atomic layer etching based on methane gas. In this example, the temperature is 120°C, and each cycle of atomic layer etching is divided into a reaction and an etching step. In the reaction step, 100 sccm of argon and 10 sccm of methane are introduced, the ICP power is 400 W, and the duration is 5 s. In the etching step, 100 sccm of Ar is introduced, the RF power is 15 W, the ICP power is 250 W, and the duration is 8 s. As shown in FIG. 7.

[0031] S008, removing the silicon nanowire mask by ion beam sculpting dry etching. The ion beam sculpting (IBS) can remove the protrusions by adjusting the etching angle, as shown in FIG. 8.

[0032] Compared with the prior art, the above technical solution of the present application significantly reduces the requirement for exposure accuracy in the case of small size, reduces the impact of etching on the oxide semiconductor layer, and is not limited by the equipment and gas for etching.

[0033] The present application can be used to prepare planar transistors, vertical transistors, and logic and memory devices based on the above transistors. Any technical solution formed by equivalent transformation or equivalent transformation falls within the scope of protection of the present application.

[0034] It should be noted that the above examples illustrate the present application rather than limit it, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A small-sized oxide semiconductor etching method, characterized by, The steps include: Step 1) preparing an amorphous silicon layer on the oxide semiconductor material to be etched; Step 2) annealing at a low temperature to induce lateral crystallization of the amorphous silicon layer using the metal in the oxide semiconductor material to form polycrystalline silicon; Step 3) oxidizing the surface layer of the polycrystalline silicon to SiO2 using thermal oxidation or oxygen plasma treatment, and then removing the surface layer of SiO2 using a high-selectivity dry etching method, repeating several times to reduce to the desired diameter to form a silicon nanowire; Step 4) using the silicon nanowire obtained in step 3) as a hard mask, and using a wet or dry etching method to etch the oxide semiconductor material; Step 5) using an ion beam etching method with a shaping function to remove the silicon nanowire hard mask without damaging the oxide semiconductor material.

2. The small-size oxide semiconductor etching method according to claim 1, wherein Step 1) using a plasma-enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, pulsed vapor deposition, or atomic layer deposition process to prepare the amorphous silicon layer.

3. The small-size oxide semiconductor etching method according to claim 1, wherein The thickness of the amorphous silicon layer in step 1) ranges from 20 nm to 200 nm.

4. The small-size oxide semiconductor etching method according to claim 1, wherein The temperature in step 2) ranges from 150°C to 400°C.

5. The small-size oxide semiconductor etching method according to claim 1, wherein The dry etching method in step 3) is specifically a reactive ion etching, reactive coupled plasma etching, or atomic layer etching.

6. The small-size oxide semiconductor etching method according to claim 1, wherein The diameter of the silicon nanowire in step 3) ranges from 10 nm to 200 nm.

7. The small-size oxide semiconductor etching method according to claim 1, wherein The length of the silicon nanowire in step 3) ranges from 50 nm to 2000 nm.

8. The small-size oxide semiconductor etching method according to claim 1, wherein The oxide semiconductor material is selected from one or more of In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, or ITWO.

9. The small-size oxide semiconductor etching method according to claim 8, wherein The oxide semiconductor material is a single-layer thin film or a composite thin film stacked by multiple thin films.

10. The small-size oxide semiconductor etching method according to claim 1, wherein The thickness of the oxide semiconductor material ranges from 0.5 nm to 50 nm.

Images