Network-on-chip building method and apparatus, device, storage medium, and program

Abstract

The present application provides a network-on-chip building method and apparatus, an electronic device, and a computer-readable storage medium. The method comprises: in response to a connection operation between at least some of target interface elements among interface elements displayed in a building interface, acquiring a network-on-chip structure, wherein each target interface element comprised in the network-on-chip structure is associated with a corresponding code snippet, the at least some of target interface elements are associated with corresponding verification stimulus components, and each interface element corresponds to a constituent unit in the network-on-chip; and on the basis of the network-on-chip structure, and code snippets and verification stimulus components associated with target interface elements in the network-on-chip structure, performing code conversion to obtain a network-on-chip code file and a verification file. In the process of the present application, the step of manually writing codes and scripts is omitted, thereby greatly reducing the dependency on labor resources, and the verification file can also be synchronously and automatically updated when the network-on-chip structure changes, thereby reducing the costs of synchronous update.

Description

Methods, devices, equipment, storage media, and programs for building on-chip networks

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410998784.5, filed on July 24, 2024, entitled “Method, Apparatus, Device and Storage Medium for Building a Network on a Chip”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, computer-readable storage medium, and computer program for building an on-chip network. Background Technology

[0004] Network-on-chip (NOC) is a key technology in multiprocessor architectures. It serves as the interconnect and communication network within the processor, responsible for message passing and forming the basis for processor collaboration. Furthermore, to ensure the stability of NOC operation, its design needs to be verified.

[0005] Currently, Method 1 involves manually developing on-chip network files and then manually building a verification platform based on those files. Method 2, on the other hand, involves constructing on-chip network script files and then manually building a verification platform based on those scripts. In this method, functions related to consistency and peripheral interfaces are implemented through parameter passing within the script.

[0006] However, the current solution is highly dependent on human resources, resulting in high labor costs. Furthermore, the on-chip network files and verification platform cannot be updated synchronously, and the parameter transmission overhead in Method 2 is enormous. All of these factors further increase the cost of on-chip network design and verification. Summary of the Invention

[0007] This application provides a method, apparatus, electronic device, computer-readable storage medium, and computer program for building an on-chip network to solve problems in related technologies.

[0008] In a first aspect, embodiments of this application provide a method for constructing an on-chip network, the method comprising:

[0009] In response to a connection operation between at least some target interface elements in the interface elements of the constructed interface display, an on-chip network structure is obtained, wherein each target interface element in the on-chip network structure is associated with a corresponding code snippet, at least some of the target interface elements are associated with a corresponding verification stimulus component, and each interface element corresponds to a constituent unit in the on-chip network.

[0010] Based on the on-chip network structure, and the code snippets and verification stimulus components associated with the target interface elements in the on-chip network structure, code conversion is performed to obtain on-chip network code files and verification files. The verification files are used to build a verification platform to verify the on-chip network.

[0011] Secondly, embodiments of this application provide an apparatus for building an on-chip network, the apparatus comprising:

[0012] The identification module is used to identify the first data row in the storage array of the dynamic random access memory; the first data row is the data row that has been attacked.

[0013] The generation module is used to generate an exchange request for the second data row when it is determined that the data in the second data row associated with the first data row meets preset conditions;

[0014] A switching module is configured to respond to the switching request via a memory controller to transfer data in the second data row to a secure segment in the storage array.

[0015] Thirdly, embodiments of this application also provide an electronic device, including a processor;

[0016] Memory used to store the processor's executable instructions;

[0017] The processor is configured to execute the instructions to implement the method of the first aspect.

[0018] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0019] Fifthly, embodiments of this application provide a computer program including computer-readable code, which, when executed on a computing processing device, causes the computing processing device to perform the method of the first aspect.

[0020] In this embodiment, each component of the on-chip network can be converted into a displayable interface element. Users can select the corresponding interface element to position and connect them, thus enabling rapid construction of the on-chip network topology. Furthermore, each interface element can be associated with a corresponding code snippet and a corresponding verification stimulus component. Therefore, after the on-chip network topology is built, the on-chip network code file and verification file can be generated with a single click based on the on-chip network structure and the code snippets and verification stimulus components associated with the target interface elements within the on-chip network structure. This process eliminates the need for manual code and script writing, significantly reducing reliance on human resources. Moreover, when the on-chip network structure is changed, the target interface elements in the changed on-chip network structure still retain their associated code snippets and verification stimulus components. Therefore, the verification file can also be automatically updated synchronously when the on-chip network structure changes, reducing the cost of synchronous updates.

[0021] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a flowchart of the steps of a method for building an on-chip network according to an embodiment of this application;

[0024] Figure 2 is a diagram of the interface for building an on-chip network provided in an embodiment of this application;

[0025] Figure 3 is a code fragment mapping diagram provided in an embodiment of this application;

[0026] Figure 4 is a mapping diagram of an excitation component provided in an embodiment of this application;

[0027] Figure 5 is a flowchart of the specific steps of a method for building an on-chip network provided in an embodiment of this application;

[0028] Figure 6 is a schematic diagram of a component library and a code library provided in an embodiment of this application;

[0029] Figure 7 is an architecture diagram of a method for building an on-chip network according to an embodiment of this application;

[0030] Figure 8 is a verification platform architecture diagram provided in an embodiment of this application;

[0031] Figure 9 is a block diagram of an on-chip network construction device provided in an embodiment of this application;

[0032] Figure 10 is a block diagram of an electronic device provided in an embodiment of the present invention;

[0033] Figure 11 is a block diagram of another electronic device according to another embodiment of the present invention. Specific Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0036] Figure 1 is a flowchart of the steps of a method for building an on-chip network according to an embodiment of this application. As shown in Figure 1, the method may include:

[0037] Step 101: In response to connection operations between at least some of the target interface elements in the interface elements displayed on the construction interface, obtain the on-chip network structure.

[0038] In this on-chip network structure, each target interface element is associated with a corresponding code snippet, and at least some of the target interface elements are associated with a corresponding verification stimulus component. Each interface element corresponds to a constituent unit in the on-chip network.

[0039] In practical applications, although the multiple processor cores on a multi-core processor chip execute their own code, the processor cores need to share and synchronize data. Therefore, the hardware architecture of a multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication architecture will directly affect the performance of the processor.

[0040] Therefore, on-chip networking (BCN) aims to solve communication problems within multi-core processors. BCN is an integrated circuit built on a network-based communication subsystem, and it's a router-based packet-switching network between on-chip systems. BCN technology borrows from the interconnect network architecture of parallel computers, integrating a large number of computing resources and the on-chip communication network connecting these resources onto a single chip. Each processor core has an independent router and its private cache, connected together via the on-chip communication network. The processor cores communicate using a message-based mechanism, replacing the on-chip bus of related technologies with routers and packet switching to complete communication tasks, thus solving various bottleneck problems caused by bus interconnection in related technologies.

[0041] Among these technologies, the design and development of on-chip networks (BTCs) rely heavily on human resources, requiring extensive manual compilation. Furthermore, to ensure the operational stability of BTCs, a verification platform corresponding to the BTC design needs to be built for stability verification. This involves manually writing verification files based on the BTC design, a tedious and time-consuming process. When the BTC design changes, the verification files also need to be manually updated, further increasing labor costs.

[0042] In this embodiment of the application, in order to reduce the manpower cost of on-chip network design, verification and synchronous update process, as well as to reduce the complexity of the design, verification and synchronous update process, this embodiment of the application can develop a way to construct on-chip network design and verification documents using flowchart design ideas based on a simple and intuitive interface design.

[0043] The specific idea behind this application is to convert each component of the on-chip network into a displayable interface element. Users can then select the corresponding interface elements in the construction interface to perform operations such as placement and interconnection, thereby realizing the construction of the on-chip network topology. In addition, each interface element can be associated with a corresponding code snippet and a corresponding verification stimulus component. Thus, after the on-chip network topology is completed, the on-chip network code file and verification file can be generated with one click based on the on-chip network structure and the code snippets and verification stimulus components associated with the target interface elements in the on-chip network structure.

[0044] In this step, the on-chip network setup interface shown in Figure 2 can be displayed first. The setup interface can include a material selection area. Generally, an on-chip network can include external devices, routing modules, consistency modules, processor cores, and other constituent units (more constituent units are not shown one by one). In this embodiment, each constituent unit can be configured with a corresponding shape of interface element, and the interface elements of different constituent units are different. In Figure 2, the interface element of the routing module can be configured as a rounded rectangle, the interface element of the consistency module can be configured as an ellipse, the interface element of the processor core can be configured as a circle, and the interface element of the external device can be configured as a rectangular box.

[0045] Furthermore, referring to Figure 2, users can select at least some of the target interface elements from the interface elements for building the interface display according to actual design requirements, and place and connect the target interface elements in the design area to obtain the designed on-chip network structure. As shown in Figure 2, four routing module interface elements, one consistency module interface element, one processor core interface element, and one external device interface element are selected to construct an on-chip network topology. The four routing module interface elements are connected to each other in sequence, the consistency module interface element is connected to the interface element of routing module 1, the processor core interface element is connected to the interface element of routing module 4, and the external device interface element is connected to the interface element of routing module 2.

[0046] In addition, each interface element is associated with a corresponding code snippet, which is used to implement the function of the corresponding constituent unit of the interface element. Referring to Figure 3, the routing module interface element can be associated with a routing module code snippet, the consistency module interface element can be associated with a consistency module code snippet, the processor core interface element can be associated with a processor core code snippet, and the external device interface element can be associated with an external device code snippet. In the process of generating the final on-chip network code file, the on-chip network code file is generated by instantiating and connecting the code snippets layer by layer.

[0047] Furthermore, at least some interface elements are associated with corresponding verification stimulus components. These components are related to the on-chip network verification and are used to implement the interface configuration, model, comparison function, and corresponding signal timing definition required to initiate the verification function. Referring to Figure 4, external device interface elements can be associated with external interface stimulus components, and processor core interface elements can be associated with processor core interface stimulus components. The external interface stimulus components are used to implement the interaction interface between the verification platform and the external device, while the processor core interface stimulus components are used to implement the interaction interface between the verification platform and the processor core. Of course, there can be many other types of verification stimulus components, which are not all shown here.

[0048] Step 102: Based on the on-chip network structure, and the code snippets and verification stimulus components associated with the target interface elements in the on-chip network structure, perform code conversion to obtain the on-chip network code file and verification file.

[0049] The verification file is used to build a verification platform to verify the on-chip network.

[0050] In this embodiment of the application, after the on-chip network structure is constructed by building an interface in the form of a flowchart, the code can be automatically converted using a one-click conversion function based on the on-chip network structure and the code snippets and verification stimulus components associated with the target interface elements in the on-chip network structure, to obtain the on-chip network code file and verification file.

[0051] Meanwhile, when the design of the on-chip network structure is changed, the target interface elements, their positions, and connections in the changed on-chip network structure may change. However, since the target interface elements in the changed on-chip network structure are still associated with corresponding code snippets and verification stimulus components, the verification file can also be automatically updated synchronously when the on-chip network structure changes, achieving quick synchronous updates of the verification file and the on-chip network code file.

[0052] In summary, in this embodiment, each component of the on-chip network can be converted into a displayable interface element. Users can then select and arrange these elements, connecting them to each other, thus enabling rapid construction of the on-chip network topology. Furthermore, each interface element can be associated with a corresponding code snippet and a corresponding verification stimulus component. After the on-chip network topology is built, the on-chip network code file and verification file can be generated with a single click based on the on-chip network structure and the associated code snippets and verification stimulus components of the target interface elements within that structure. This process eliminates the need for manual code and script writing, significantly reducing reliance on human resources. Moreover, when the on-chip network structure is changed, the target interface elements in the revised structure still retain their associated code snippets and verification stimulus components. Therefore, the verification file can be automatically updated synchronously when the on-chip network structure changes, reducing the cost of synchronous updates.

[0053] Figure 5 is a flowchart illustrating the specific steps of a method for building an on-chip network according to an embodiment of this application. As shown in Figure 5, the method may include:

[0054] Step 201: Display the setup interface, which includes multiple interface elements to be selected.

[0055] Step 202: Select the target interface elements in the construction interface, and set the position of the target interface elements by dragging and dropping, and connect multiple target interface elements to obtain the on-chip network structure.

[0056] In this embodiment of the application, for steps 201-202, each constituent unit of the on-chip network can be converted into a displayable interface element, and the user can select the corresponding interface element in the building interface to perform operations such as placement and interconnection, thereby realizing the construction of the topology structure of the on-chip network.

[0057] For example, referring to Figure 2, in the material selection area, the interface element for configuring the routing module can be a rounded rectangle, the interface element for configuring the consistency module can be an ellipse, the interface element for configuring the processor core can be a circle, and the interface element for configuring external devices can be a rectangle. Users can select at least some of the target interface elements in the material selection area according to their actual needs, and then arrange and connect these target interface elements in the design area to obtain the designed on-chip network structure.

[0058] As shown in Figure 2, the user selected four routing module interface elements, one consistency module interface element, one processor core interface element, and one external device interface element to construct an on-chip network topology. The four routing module interface elements are connected to each other in sequence. The consistency module interface element is connected to the interface element of routing module 1, the processor core interface element is connected to the interface element of routing module 4, and the external device interface element is connected to the interface element of routing module 2.

[0059] Step 203: Based on the on-chip network structure and the code fragments associated with the target interface elements in the on-chip network structure, perform code conversion to obtain the on-chip network code file and intermediate file. The intermediate file is used to record the topology information and interface information of the on-chip network.

[0060] In this embodiment of the application, the on-chip network code file and intermediate file can be obtained by automatically converting the code based on the on-chip network structure and the code fragments associated with the target interface elements in the on-chip network structure using a one-click conversion function.

[0061] In this process, the code snippets associated with each target interface element in the on-chip network structure can be instantiated and linked layer by layer to obtain the on-chip network code file and intermediate files. The on-chip network code file reflects the basic functional information of the on-chip network, while the intermediate files contain the topology and interface information of the on-chip network. The intermediate files can be in .yml format, which is a file used to describe configuration information.

[0062] Optionally, the constituent units in the on-chip network include one or more of the following: processor core, consistency module, external device, and routing module; the shapes of the interface elements corresponding to different constituent units are different.

[0063] Optionally, the verification stimulus components include one or more of the following: processor core interface stimulus components, external interface stimulus components, verification comparison stimulus components, verification reference models, and connection components.

[0064] Optionally, step 203 may specifically include:

[0065] Sub-step 2031: Based on the target interface elements included in the on-chip network structure, search for the code snippets corresponding to the target interface elements from a preset code library, wherein the code library stores the correspondence between interface elements and code snippets.

[0066] Sub-step 2032: Based on the on-chip network structure and the code fragments associated with the target interface elements, perform code conversion to obtain the on-chip network code file and intermediate file.

[0067] In this embodiment, referring to sub-steps 2031-2032, Figure 6 illustrates a schematic diagram of a code library and component library. The code library includes code snippets such as routing module code snippets, consistency module code snippets, processor core code snippets, and external device code snippets. These code snippets are invoked during one-click conversion. Further referring to Figure 7, the on-chip network architecture of this embodiment may include input components, a conversion system, and an output and testing system. The conversion system includes a code conversion module and a verification conversion module. Regarding the code conversion module, in response to one-click conversion, it can match code snippets corresponding to the target interface elements in the code library based on the target interface elements included in the on-chip network structure. Then, it instantiates and connects the matched code snippets layer by layer to obtain the on-chip network code file and intermediate files.

[0068] Optionally, step 203 may specifically include:

[0069] Sub-step 2033: Convert the on-chip network structure into a recognizable standard format file.

[0070] Sub-step 2034: Based on the standard format file and the code fragments associated with the target interface elements in the on-chip network structure, perform code conversion to obtain the on-chip network code file and intermediate file.

[0071] In this embodiment, referring to Figure 7, for sub-steps 2033-2034, to improve the standardization and stability of the conversion process, the input to the code conversion module can be standardized, i.e., the code conversion module is required to use a file in a preset format as input. Therefore, in this embodiment, the on-chip network structure constructed in the setup interface of Figure 2 can first be converted into a recognizable standard format file, and then the standard format file can be input into the code conversion module to obtain the on-chip network code file and intermediate file. The recognizable standard format file can be a .sml or .yml file.

[0072] Step 204: Based on the intermediate file and the verification incentive component associated with the target interface element, perform code conversion to obtain the verification file.

[0073] In this embodiment of the application, referring to FIG7, the intermediate file serves as a file carrying the topology information and interface information of the on-chip network, and can provide intermediate variables for the construction of the verification platform. Therefore, in this embodiment of the application, the verification file can be instantiated and constructed based on the topology information and interface information of the on-chip network described in the intermediate file, and the verification platform can be built by running the verification file.

[0074] Optionally, step 204 may specifically include:

[0075] Sub-step 2041: Based on the target interface elements included in the on-chip network structure, search for the verification stimulus component corresponding to the target interface element from a preset component library. The component library stores the correspondence between interface elements and verification stimulus components.

[0076] Sub-step 2042: Based on the on-chip network structure and the verification stimulus component associated with the target interface element, perform code conversion to obtain the verification file.

[0077] In this embodiment, referring to sub-steps 2041-2042, Figure 6 illustrates a schematic diagram of a code library and a component library. The component library includes processor core stimulus components, external interface stimulus components, verification comparison stimulus components, verification reference models, connection components, etc. These stimulus components are used when building a verification platform. Further referring to Figure 7, in the on-chip network architecture of this embodiment, for the verification conversion module, in response to one-click conversion, it can use an intermediate file as input, match the stimulus component corresponding to the target interface element in the component library, and then instantiate and convert the matched stimulus component to obtain the verification file.

[0078] Referring to Figure 8, a schematic diagram of a verification architecture is shown, including: a verification platform and code under test. The verification platform includes a verification comparison module, a processor core interface, an external device interface, and a verification reference model; the code under test includes on-chip network code files.

[0079] Specifically, during the on-chip network simulation run corresponding to the on-chip network code file, data for the processor core and external devices can be transferred between the verification platform and the on-chip network by the bridging module. The processor core data can be passed to the verification comparison module through the processor core interface implemented by the verification platform, and the external device data can be passed to the verification comparison module through the external device interface implemented by the verification platform. The verification comparison module is used to compare the processor core data, the external device data, and the verification reference model data to obtain the verification result.

[0080] In summary, in this embodiment, each component of the on-chip network can be converted into a displayable interface element. Users can then select and arrange these elements, connecting them to each other, thus enabling rapid construction of the on-chip network topology. Furthermore, each interface element can be associated with a corresponding code snippet and a corresponding verification stimulus component. After the on-chip network topology is built, the on-chip network code file and verification file can be generated with a single click based on the on-chip network structure and the associated code snippets and verification stimulus components of the target interface elements within that structure. This process eliminates the need for manual code and script writing, significantly reducing reliance on human resources. Moreover, when the on-chip network structure is changed, the target interface elements in the revised structure still retain their associated code snippets and verification stimulus components. Therefore, the verification file can be automatically updated synchronously when the on-chip network structure changes, reducing the cost of synchronous updates.

[0081] Figure 9 is a block diagram of an on-chip network construction device provided in an embodiment of this application. The device includes:

[0082] The construction module 301 is used to obtain an on-chip network structure in response to a connection operation between at least some of the target interface elements in the interface elements of the construction interface display. Each target interface element in the on-chip network structure is associated with a corresponding code snippet, and at least some of the target interface elements are associated with a corresponding verification stimulus component. Each interface element corresponds to a constituent unit in the on-chip network.

[0083] The conversion module 302 is used to perform code conversion based on the on-chip network structure, the code snippets associated with the target interface elements in the on-chip network structure, and the verification stimulus components to obtain on-chip network code files and verification files. The verification files are used to build a verification platform to verify the on-chip network.

[0084] Optionally, the building module 301 includes:

[0085] The display submodule is used to display the building interface, which includes multiple interface elements to be selected;

[0086] The construction submodule is used to select target interface elements in the construction interface, set the position of the target interface elements by dragging, and connect multiple target interface elements to obtain the on-chip network structure.

[0087] Optionally, the conversion module 302 includes:

[0088] The first conversion submodule is used to perform code conversion based on the on-chip network structure and the code fragments associated with the target interface elements in the on-chip network structure to obtain the on-chip network code file and intermediate file. The intermediate file is used to record the topology information and interface information of the on-chip network.

[0089] The second conversion submodule is used to perform code conversion based on the intermediate file and the verification incentive component associated with the target interface element to obtain the verification file.

[0090] Optionally, the first conversion submodule includes:

[0091] The first lookup unit is used to look up code snippets corresponding to the target interface elements from a preset code library based on the target interface elements included in the on-chip network structure. The code library stores the correspondence between interface elements and code snippets.

[0092] The first conversion unit is used to perform code conversion based on the on-chip network structure and the code fragments associated with the target interface elements to obtain the on-chip network code file and intermediate file.

[0093] Optionally, the first conversion submodule includes:

[0094] A conversion unit is used to convert the on-chip network structure into a recognizable standard format file;

[0095] The second conversion unit is used to perform code conversion based on the standard format file and the code fragments associated with the target interface elements in the on-chip network structure to obtain the on-chip network code file and intermediate file.

[0096] Optionally, the second conversion submodule includes:

[0097] The second lookup unit is used to look up a verification stimulus component corresponding to the target interface element from a preset component library based on the target interface element included in the on-chip network structure. The component library stores the correspondence between interface elements and verification stimulus components.

[0098] The third conversion unit is used to perform code conversion based on the on-chip network structure and the verification stimulus component associated with the target interface element to obtain the verification file.

[0099] Optionally, the constituent units in the on-chip network include one or more of the following: processor core, consistency module, external device, and routing module; the shapes of the interface elements corresponding to different constituent units are different.

[0100] Optionally, the verification stimulus component includes one or more of the following: processor core interface stimulus component, external interface stimulus component, verification comparison stimulus component, verification reference model, and connection component.

[0101] Optionally, the interface elements of the routing module can be configured as rounded rectangles, the interface elements of the consistency module can be configured as ellipses, the interface elements of the processor core can be configured as circles, and the interface elements of the external devices can be configured as rectangular boxes.

[0102] Optionally, the intermediate file is a file in .yml format.

[0103] Optionally, the standard format file is a .sml or .yml file.

[0104] Optionally, the verification platform includes: a verification comparison module, a processor core interface, an external device interface, and a verification reference model;

[0105] The verification comparison module is connected to the verification reference model, the external device interface, and the processor core interface, respectively; the verification reference model is connected to the processor core interface and the external device interface, respectively.

[0106] The verification comparison module is used to compare the data sent by the external device interface, the data sent by the external device interface, and the data of the verification reference model to obtain the verification result.

[0107] Optionally, the intermediate file is used to record the topology and interface information of the on-chip network.

[0108] Optionally, the interactive operation is a drag-and-drop operation.

[0109] Optionally, the on-chip network code file reflects the basic functional information of the on-chip network.

[0110] Optionally, the shapes of the interface elements corresponding to different constituent units may be different.

[0111] In summary, in this embodiment, each component of the on-chip network can be converted into a displayable interface element. Users can then select and arrange these elements, connecting them to each other, thus enabling rapid construction of the on-chip network topology. Furthermore, each interface element can be associated with a corresponding code snippet and a corresponding verification stimulus component. After the on-chip network topology is built, the on-chip network code file and verification file can be generated with a single click based on the on-chip network structure and the associated code snippets and verification stimulus components of the target interface elements within that structure. This process eliminates the need for manual code and script writing, significantly reducing reliance on human resources. Moreover, when the on-chip network structure is changed, the target interface elements in the revised structure still retain their associated code snippets and verification stimulus components. Therefore, the verification file can be automatically updated synchronously when the on-chip network structure changes, reducing the cost of synchronous updates.

[0112] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0113] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0114] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0115] This application provides an apparatus for building an on-chip network, including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs include methods for performing the methods described in one or more of the above embodiments.

[0116] Figure 10 is a block diagram illustrating an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0117] Referring to FIG10, the electronic device 600 may include one or more of the following components: processing component 602, memory 604, power supply component 606, multimedia component 608, audio component 610, input / output (I / O) interface 612, sensor component 614, and communication component 616.

[0118] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0119] Memory 604 is used to store various types of data to support the operation of electronic device 600. Examples of such data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0120] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0121] Multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0122] Audio component 610 is used to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) used to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0123] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0124] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 can detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0125] Communication component 616 facilitates wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 4G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0126] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of this application.

[0127] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of an electronic device 600 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0128] Figure 11 is a block diagram illustrating an electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Referring to Figure 11, the electronic device 700 includes a processing component 722, which further includes one or more processors, and memory resources represented by memory 732 for storing instructions executable by the processing component 722, such as application programs. The application programs stored in memory 732 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 722 is configured to execute instructions to perform the methods provided in the embodiments of this application.

[0129] Electronic device 700 may also include a power supply component 726 configured to perform power management of electronic device 700, a wired or wireless network interface 750 configured to connect electronic device 700 to a network, and an input / output (I / O) interface 758. Electronic device 700 can operate on an operating system, such as Windows Server, stored in memory 732. TM MacOSX TMUnix TM Linux TM FreeBSD TM Or similar.

[0130] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described in the above embodiments.

[0131] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0132] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0133] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0134] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0135] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0136] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0137] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0138] The foregoing has provided a detailed description of the method, apparatus, electronic device, computer-readable storage medium, and computer program for building an on-chip network provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method of building a network-on-chip, wherein, The method comprises: obtaining a network-on-chip structure in response to a connection operation between at least part of target interface elements in interface elements displayed on a design interface, each target interface element in the network-on-chip structure being associated with a corresponding code segment, at least part of the target interface elements being associated with corresponding verification incentive components, each interface element corresponding to a constituent unit in the network-on-chip; performing code conversion according to the network-on-chip structure, the code segments associated with the target interface elements in the network-on-chip structure, and the verification incentive components to obtain a network-on-chip code file and a verification file, the verification file being used for verifying the network-on-chip on a verification platform.

2. The method of claim 1, wherein, The method comprises: displaying a design interface, the design interface comprising a plurality of interface elements to be selected; selecting target interface elements in the design interface and setting positions of the target interface elements through an interactive operation, and connecting the target interface elements to each other to obtain the network-on-chip structure.

3. The method of claim 1, wherein, The method comprises: performing code conversion according to the network-on-chip structure and the code segments associated with the target interface elements in the network-on-chip structure to obtain the network-on-chip code file and an intermediate file; performing code conversion according to the intermediate file and the verification incentive components associated with the target interface elements to obtain the verification file.

4. The method of claim 3, wherein, The method comprises: finding, from a preset code library, a code segment corresponding to a target interface element in the network-on-chip structure, the code library storing a correspondence between interface elements and code segments; performing code conversion according to the network-on-chip structure and the code segment associated with the target interface element to obtain the network-on-chip code file and the intermediate file.

5. The method of claim 3, wherein, The method comprises: converting the network-on-chip structure into a standard format file that can be recognized; performing code conversion according to the standard format file, the code segment associated with the target interface element in the network-on-chip structure to obtain the network-on-chip code file and the intermediate file.

6. The method of building a network-on-chip of claim 3, wherein, The method comprises: finding, from a preset component library, a verification incentive component corresponding to a target interface element in the network-on-chip structure, the component library storing a correspondence between interface elements and verification incentive components; performing code conversion according to the network-on-chip structure and the verification incentive component associated with the target interface element to obtain the verification file. According to the on-chip network structure and the verification incentive component associated with the target interface element, code conversion is performed to obtain the verification file.

7. The method of building a network-on-chip according to any of claims 1-6, wherein, The constituent units in the on-chip network include one or more of a processor core, a coherence module, an external device, and a routing module.

8. The method of building a network-on-chip according to any of claims 1-6, wherein, The verification incentive component includes one or more of a processor core interface incentive component, an external interface incentive component, a verification comparison incentive component, a verification reference model, and a connection component.

9. The method of building a network-on-chip of claim 7, wherein, The interface element of the routing module is configured as a rounded square, the interface element of the coherence module is configured as an ellipse, the interface element of the processor core is configured as a circle, and the interface element of the external device is configured as a rectangular square.

10. The method of building a network-on-chip of claim 3, wherein, The intermediate file is a.yml format file.

11. The method of building a network-on-chip of claim 5, wherein, The standard format file is a.sml or.yml format file.

12. The method of building a network-on-chip of claim 1, wherein, The verification platform includes a verification comparison module, a processor core interface, an external device interface, and a verification reference model. The verification comparison module is connected with the verification reference model, the external device interface, and the processor core interface, respectively; and the verification reference model is connected with the processor core interface and the external device interface, respectively. The verification comparison module is used to compare the data sent by the external device interface, the data sent by the external device interface, and the data of the verification reference model, so as to obtain a verification result.

13. The method of building a network-on-chip of claim 1, wherein, The intermediate file is used to record the topology information and the interface information of the on-chip network.

14. The method of building a network-on-chip of claim 2, wherein, The interactive operation is a drag operation.

15. The method of building a network-on-chip of claim 1, wherein, The on-chip network code file reflects the basic function information of the on-chip network.

16. The method of building a network-on-chip of claim 7, wherein, The shapes of the interface elements corresponding to different constituent units are different.

17. A building device of a network-on-chip, wherein, The device includes: A construction module is configured to, in response to a connection operation between at least some target interface elements displayed on a building interface, obtain an on-chip network structure, each target interface element included in the on-chip network structure being associated with a corresponding code segment, and at least some of the target interface elements being associated with a corresponding verification incentive component, each interface element corresponding to a constituent unit in an on-chip network. A conversion module is configured to, according to the on-chip network structure, and the code segments and verification incentive components associated with the target interface elements in the on-chip network structure, perform code conversion to obtain an on-chip network code file and a verification file, the verification file being used to build a verification platform to verify the on-chip network.

18. An electronic device, comprising: It includes: A processor; A memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of any one of claims 1-16.

19. A computer readable storage medium, wherein, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1-16.

20. A computer program comprising computer readable code which, when run on a computing processing device, causes the computing processing device to perform the method of any one of claims 1-16.

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