Semiconductor device and preparation method therefor, power module, conversion circuit and vehicle

Abstract

A semiconductor device and a preparation method therefor, a power module, a conversion circuit and a vehicle. The semiconductor device comprises: a substrate (10); a semiconductor epitaxial layer (20), which is located on one side of the substrate (10); a gate trench (01), which is located on the surface of the side of the semiconductor epitaxial layer (20) away from the substrate (10); a trench gate structure (60), which is located in the gate trench (01); a first electrode (30), which is located on the side of the substrate (10) away from the semiconductor epitaxial layer (20); a second electrode (40), which is located on the surface of the side of the semiconductor epitaxial layer (20) away from the substrate (10) and is located on at least one side of the trench gate structure (60); and a third electrode (50), which is disposed inside the semiconductor epitaxial layer (20) and is located at the bottom of the trench gate structure (60), wherein the semiconductor epitaxial layer (20) comprises a first body region (22) and a second body region (25), which are in contact with the trench gate structure (60), the first body region (22) being configured to form a first channel (L1) that brings the first electrode (30) into communication with the second electrode (40), and the second body region (25) being configured to form a second channel (L2) that brings the first electrode (30) into communication with the third electrode (50).

Description

Semiconductor device, manufacturing method, power module, conversion circuit and vehicle

[0001] This application claims priority to the Chinese patent application No. 202410991924.6, filed on July 23, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor technology, for example to a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle. BACKGROUND

[0003] As a representative of the third generation semiconductor material, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, high thermal conductivity, high electron saturation velocity, strong radiation resistance and other advantages, so the semiconductor device prepared by using SiC material can not only operate stably at a higher temperature, but also is suitable for high voltage and high frequency scenarios.

[0004] However, the SiC semiconductor device still has the problem of large on-resistance. At present, the multi-channel method or the method of setting a trench gate is usually used to reduce the on-resistance of the power device. FIG. 1 is a structural schematic diagram of a semiconductor device provided in the related art. Referring to FIG. 1, the semiconductor device includes a semiconductor epitaxial layer and source and drain electrodes S and D located on opposite sides of the semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N-type drift region (n-drift), an n+ region at the bottom of a gate G, and a P-type base region (p-base) and an n+ region and a p-base region at the side of the gate G. The semiconductor device shown in FIG. 1 is a non-trench type semiconductor device including multiple channels (lateral channels and vertical channels). However, for the non-trench type multi-channel on structure, since the cell unit area is large, the effect of improving the current density (reducing the on-resistance) is not good. The trench type semiconductor device has the advantages of small cell size and large current density. However, in the trench type semiconductor device, the high electric field at the bottom of the trench and the slot angle can increase the electric field on the gate insulating layer, thereby causing the gate insulating layer to be easily broken down.

[0005] FIG. 2 is a structural schematic diagram of another semiconductor device provided in the related art. Referring to FIG. 2, the semiconductor device shown in FIG. 2 is a trench type semiconductor device including a shield gate structure. By providing the shield gate structure 1 below the trench gate, the problem that the gate insulating layer is easily broken down can be improved, and the breakdown voltage of the device is increased. In addition, deepening the depth of the trench also helps to reduce the on-resistance. However, the provision of the shield gate structure 1 requires the provision of a trench with a relatively deep depth, and the deeper the depth of the trench, the more difficult the preparation of the device. FIG. 3 is a structural schematic diagram of another semiconductor device provided in the related art. Referring to FIG. 3, a P+ region 2 can also be formed at the bottom and sidewall of the gate trench as an electric field shielding structure by means of ion implantation. However, the P+ region 2 at the bottom of the gate can easily cause the shielding effect to decrease and fail due to the accumulation of electric charges. SUMMARY

[0006] Embodiments of the present application provide a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle to reduce the on-resistance while increasing the breakdown voltage of the device.

[0007] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0008] a substrate;

[0009] a semiconductor epitaxial layer located on one side of the substrate;

[0010] a gate trench located on the surface of the semiconductor epitaxial layer away from the substrate;

[0011] a trench gate structure located in the gate trench;

[0012] a first electrode located on the side of the substrate away from the semiconductor epitaxial layer;

[0013] a second electrode located on the surface of the semiconductor epitaxial layer away from the substrate and located on at least one side of the trench gate structure;

[0014] a third electrode provided in the semiconductor epitaxial layer and located at the bottom of the trench gate structure;

[0015] wherein the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is configured to form a first channel for conducting the first electrode and the second electrode; and the second body region is configured to form a second channel for conducting the first electrode and the third electrode.

[0016] According to another aspect of the present application, a preparation method of a semiconductor device is provided, comprising:

[0017] providing a substrate;

[0018] forming a semiconductor epitaxial layer on one side of the substrate;

[0019] forming a gate trench on the surface of the semiconductor epitaxial layer away from the substrate;

[0020] forming a third electrode on the bottom of the gate trench and forming a trench gate structure in the gate trench;

[0021] forming a second electrode on the surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure;

[0022] forming a first electrode on the surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer comprises a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel for conducting the first electrode and the second electrode; the second body region is used to form a second channel for conducting the first electrode and the third electrode.

[0023] According to another aspect of the present application, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present application, the substrate is configured to carry the semiconductor device.

[0024] According to another aspect of the present application, a power conversion circuit is provided, the power conversion circuit is configured to perform one or more of current conversion, voltage conversion, and power factor correction.

[0025] The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of the embodiments of the present application, the semiconductor device is electrically connected to the circuit board.

[0026] According to another aspect of the present application, a vehicle is provided, comprising a load and a power conversion circuit according to any one of the embodiments of the present application, the power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input to the load. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 is a structural schematic diagram of a semiconductor device provided in the related art;

[0028] FIG. 2 is a structural schematic diagram of another semiconductor device provided in the related art;

[0029] FIG. 3 is a structural schematic diagram of another semiconductor device provided in the related art;

[0030] FIG. 4 is a structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0031] FIG. 5 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0032] FIG. 6 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0033] FIG. 7 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0034] FIG. 8 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0035] FIG. 9 is a structural schematic diagram corresponding to step S120 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0036] FIG. 10 is a structural schematic diagram corresponding to step S130 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0037] FIG. 11 is a structural schematic diagram corresponding to step S411 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0038] FIGS. 12-14 are structural schematic diagrams corresponding to step S412 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0039] FIG. 15 is a structural schematic diagram corresponding to step S413 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0040] FIGS. 16-18 are structural schematic diagrams corresponding to steps S414-S416 in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0041] FIGS. 19-24 are structural schematic diagrams corresponding to steps S421-S426 in the method for manufacturing a semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application will be described below in detail with reference to the accompanying drawings. The embodiments described are partial or complete embodiments of the present application. Any other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort shall fall within the scope of the present application.

[0043] The terms "first", "second", and the like, as used in the specification and claims of the application and the above figures, are used for distinguishing between similar objects and are not necessarily used to describe a particular sequential or chronological order. The use of such terms in the specification and claims of the application is only to distinguish one claimed or described embodiment from another, and the use of such terms is not an attempt to limit the application to a given order in which the steps or intervening steps are performed. The use of the terms "include," "includes," "including," "have," "has," or "having" and variations thereof herein are intended to be broad and encompass the presence of a step, a unit, a component, a feature, an object, an action, an operation, an element, an apparatus, an item, or the like, but do not exclude the presence of one or more other steps, units, components, features, objects, actions, operations, elements, apparatuses, items, or the like.

[0044] The embodiments of the application provide a semiconductor device, and Fig. 4 is a structural schematic diagram of a semiconductor device provided by the embodiments of the application. Referring to Fig. 4, the semiconductor device comprises:

[0045] a substrate 10;

[0046] a semiconductor epitaxial layer 20 located on one side of the substrate 10;

[0047] a gate trench located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10;

[0048] a trench gate structure 60 located in the gate trench;

[0049] a first electrode 30 located on a side of the substrate 10 away from the semiconductor epitaxial layer 20;

[0050] a second electrode 40 located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 and located on at least one side of the trench gate structure 60; Fig. 4 exemplarily shows that the second electrode 40 is located on opposite sides of the trench gate structure 60;

[0051] a third electrode 50 arranged in the semiconductor epitaxial layer 20 and located at the bottom of the trench gate structure 60;

[0052] The first electrode 30 and the second electrode 40 are connected through a first channel L1 extending along the sidewall of the gate trench; the first electrode 30 and the third electrode 50 are connected through a second channel L2 extending along the sidewall of the gate trench and / or the bottom surface of the gate trench. The semiconductor epitaxial layer 20 comprises a first body region 22 and a second body region 25 in contact with the trench gate structure 60; the first body region 22 is arranged to form the first channel L1 connecting the first electrode 30 and the second electrode 40; and the second body region 25 is arranged to form the second channel L2 connecting the first electrode 30 and the third electrode 50.

[0053] Optionally, the material of the substrate 10 can be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiments of the present application, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both can be SiC. That is, the trench-type power device in the embodiments of the present application can be a trench-type SiC power device. SiC has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, a high breakdown field, a high thermal conductivity, a high electron saturation velocity, a strong anti-radiation capability, and the like, so that the semiconductor device prepared by using SiC material can not only stably operate at a higher temperature, but also is suitable for high-voltage and high-frequency scenarios. In some embodiments of the present application, the substrate 10 and the semiconductor epitaxial layer 20 can be integrally arranged. The substrate 10 and the semiconductor epitaxial layer 20 being integrally arranged can be understood as that the substrate 10 and the semiconductor epitaxial layer 20 are a whole piece of SiC film layer structure formed in the same preparation process. After a front process is performed on the whole piece of SiC film layer structure, a thinning treatment is performed on the back of the SiC film layer structure, and the back of the SiC film layer structure is heavily doped with ions to form the substrate 10.

[0054] The trench gate structure 60 includes a polysilicon gate 61 and a gate insulating layer 62 between the polysilicon gate 61 and the gate trench. The material of the gate insulating layer 62 can include at least one of aluminum oxide and silicon oxide. The materials of the first electrode 30, the second electrode 40 and the third electrode 50 can all include metal materials. Among them, the first electrode 30 can be a drain electrode, and the second electrode 40 and the third electrode 50 are both source electrodes; or the first electrode 30 can be a source electrode, and the second electrode 40 and the third electrode 50 are both drain electrodes. The first electrode 30 and the second electrode 40 are conductive through the first channel L1 extending along the side wall of the gate trench; the first electrode 30 and the third electrode 50 are conductive through the second channel L2 extending along the side wall of the gate trench and / or the bottom surface of the gate trench, thereby forming a multi-channel semiconductor device.

[0055] The semiconductor device provided by the embodiments of the present application forms a trench-type semiconductor device with multiple channels by arranging the third electrode at the bottom of the trench gate structure, can reduce the on-resistance by using multiple channels, and can also reduce the cell unit area by arranging the semiconductor device as a trench-type, which has a better effect on improving the current density (reducing the on-resistance); in addition, the body region and the contact region formed by the third electrode and ion implantation around the third electrode can reduce the electric field at the bottom and the bottom corner of the gate trench, thereby improving the problem that the gate insulating layer is easily broken down and improving the breakdown voltage of the device; compared with the shielding gate structure scheme, it is not necessary to etch a deep trench, which can reduce the preparation difficulty of the semiconductor device; compared with the scheme of simply arranging a P+ region, the third electrode can improve the problem of the decline and failure of the electric field shielding effect caused by the accumulation of charges. Thus, the on-resistance is reduced while the breakdown voltage of the device is improved.

[0056] The semiconductor device with multiple channels is described below in conjunction with the accompanying drawings.

[0057] Referring to FIG. 4, the semiconductor epitaxial layer 20 includes a drift region 21, a first body region 22, and a first contact region 23 in contact with the second electrode 40, which are sequentially away from the substrate 10.

[0058] The first body region 22 and the first contact region 23 are both on the same side of the trench gate structure 60 as the second electrode 40. FIG. 4 exemplarily shows that the first body region 22 and the first contact region 23 are both on opposite sides of the trench gate structure 60; the first contact region 23 includes a first-doping-type first contact region 231 and a second-doping-type first contact region 232; the first-doping-type first contact region 231 is between the gate trench and the second-doping-type first contact region 232; the first body region 22 is of the second-doping-type, and the drift region 21 is of the first-doping-type; the first body region 22 is in contact with the sidewall of the trench gate structure 60, and the first channel L1 is in the first body region 22 between the first-doping-type first contact region 231 and the drift region 21.

[0059] Optionally, the first-doping-type first contact region 231 can be of N-type, and the second-doping-type first contact region 232 can be of P-type. Alternatively, the first-doping-type first contact region 231 can be of P-type, and the second-doping-type first contact region 232 can be of N-type. In this case, the drift region 21 is of the same doping type as the first-doping-type first contact region 231, and the ion doping concentration of the drift region 21 is lower than that of the first-doping-type first contact region 231. The first body region 22 is of the same doping type as the second-doping-type first contact region 232, and the ion doping concentration of the first body region 22 is lower than that of the second-doping-type first contact region 232.

[0060] In FIG. 4, the first-doping-type first contact region 231 and the drift region 21 are exemplarily doped with N-type doping ions; the second-doping-type first contact region 232 and the body region are doped with P-type doping ions. In the drawings, P+ and N+ represent that the ion doping concentration of the region is high, and P- and N- represent that the ion doping concentration of the region is low. In this case, the N-type doping ions can be phosphorus (P) or nitrogen (N) ions, and the P-type doping ions can be aluminum (Al) or boron (B) ions. The first channel L1 is in the first body region 22 between the first-doping-type first contact region 231 and the drift region 21, and extends along the sidewall of the gate trench. The current flows upward from the first electrode 30 to the second electrode 40, the first channel L1 forms an upper channel, and the first channel L1 is a vertical channel.

[0061] Please continue to refer to Figure 4, optionally, the semiconductor epitaxial layer 20 further comprises a second contact region 24 covering the sidewall and bottom of the third electrode 50 and a second body region 25 between the second contact region 24 and the drift region 21;

[0062] The second contact region comprises a first-doped-type second contact region 241 and a second-doped-type second contact region 242; the first-doped-type second contact region 241 is located at the sidewall of the third electrode 50; the second-doped-type second contact region 242 is located at the bottom of the third electrode 50; the second body region 25 contacts at least one of the sidewall and the bottom of the trench gate structure 60; and the second channel L2 is located in the second body region 25 between the first-doped-type first contact region 231 and the drift region 21.

[0063] The first body region 22 and the second body region 25 are of the same doping type; the first-doped-type second contact region 241 and the first-doped-type first contact region 231 are of the same doping type; and the second-doped-type second contact region 242 and the second-doped-type first contact region 232 are of the same doping type.

[0064] The bottom of the trench gate structure 60 is added with a conduction path, so that the current is increased (the on-resistance is reduced) without increasing the device area; the source metal (the third electrode 50) at the bottom of the trench gate structure 60 has the function of isolating the drain (the first electrode) and the gate insulating layer 62, so as to protect the bottom edge of the relatively fragile gate oxide and increase the reliability of the device. The P+ region and the P- region formed at the bottom of the trench gate structure 60 can form a body diode with a large contact area, so as to increase the maximum instantaneous current and the surge current that the body diode can withstand, thereby improving the reliability of the device.

[0065] Optionally, referring to Figure 4, in an embodiment of the present application, the width of the third electrode 50 is smaller than the width of the gate trench; the first-doped-type second contact region 241 and the second body region 25 are both located at the bottom of the gate trench, and the width of the second body region 25 is smaller than or equal to the width of the gate trench (Figure 4 exemplarily shows that the width of the second body region 25 is smaller than the width of the gate trench); the second body region 25 contacts the bottom of the trench gate structure 60, and the second channel L2 extends along the bottom surface of the gate trench.

[0066] Optionally, Figure 5 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application. Referring to Figure 5, in another embodiment of the present application, the width of the third electrode 50 is smaller than the width of the gate trench; the first-doped-type second contact region 241 is located at the bottom of the gate trench; the second body region 25 is located at the bottom of the gate trench and extends from the bottom of the gate trench to the sidewall of the gate trench along the bottom corner of the gate trench; the second body region 25 contacts the bottom and the sidewall of the trench gate structure 60; and the second channel L2 extends along the sidewall at the bottom corner of the gate trench and the bottom of the gate trench.

[0067] Optionally, FIG. 6 is a structure diagram of another semiconductor device according to an embodiment of the present application. Referring to FIG. 6, in another embodiment of the present application, the width of the third electrode 50 is less than the width of the gate trench; the first doped type second contact region 241 is located at the bottom of the gate trench and extends from the bottom of the gate trench to the sidewall of the gate trench along the bottom corner of the gate trench; the second body region 25 extends from the bottom of the gate trench along the surface of the first doped type second contact region 241 away from the sidewall of the gate trench until covering the surface of the first doped type second contact region 241 away from the substrate 10; the second body region 25 contacts the sidewall of the trench gate structure 60, and the second channel L2 extends along the sidewall of the gate trench.

[0068] Optionally, FIG. 7 is a structure diagram of another semiconductor device according to an embodiment of the present application. Referring to FIG. 7, in another embodiment of the present application, the width of the third electrode 50 is equal to the width of the gate trench; the first doped type second contact region 241 extends from the sidewall of the third electrode 50 to the sidewall of the gate trench; the second body region 25 extends from the bottom of the gate trench along the surface of the first doped type second contact region 241 away from the sidewall of the gate trench until covering the surface of the first doped type second contact region 241 away from the substrate 10; the second body region 25 contacts the sidewall of the trench gate structure 60, and the second channel L2 extends along the sidewall of the gate trench.

[0069] Referring to FIGS. 4-7, optionally, the semiconductor device further comprises a dielectric isolation layer 70; the dielectric isolation layer 70 is located in the gate trench and between the third electrode 50 and the polysilicon gate 61. In the embodiments shown in FIGS. 4-6, the vertical projection of the dielectric isolation layer 70 on the substrate 10 is greater than the vertical projection of the third electrode 50 on the substrate 10, and in the embodiment shown in FIG. 7, the vertical projection of the dielectric isolation layer 70 on the substrate 10 is less than the vertical projection of the third electrode 50 on the substrate 10. In other embodiments of the present application, the vertical projection of the dielectric isolation layer 70 on the substrate 10 can be equal to the vertical projection of the third electrode 50 on the substrate 10.

[0070] Optionally, since the thickness of the gate insulating layer 62 is generally in the range of 4-5 nm, the thickness is thin, and the gate insulating layer 62 at the bottom of the gate trench is more difficult to grow than the gate insulating layer 62 at the sidewall of the gate trench, resulting in that the gate insulating layer 62 at the bottom is thinner, therefore, the dielectric isolation layer 70 with a relatively thick thickness is arranged between the third electrode 50 and the polysilicon gate 61, which can enhance the isolation effect of the third electrode 50 and the polysilicon gate 61. The thickness of the dielectric isolation layer 70 can be greater than or equal to the thickness of the gate insulating layer 62 at the bottom of the gate trench. The material of the dielectric isolation layer 70 can include at least one of SiO2 and Al2O3. The preparation method of the dielectric isolation layer 70 can be at least one of atomic layer deposition (ALD), thermal oxidation, and wet method.

[0071] The embodiment of the present application further provides a preparation method of a semiconductor device, which is used for preparing the semiconductor device in any of the above embodiments. FIG. 8 is a flowchart of the preparation method of the semiconductor device according to the embodiment of the present application. Referring to FIG. 8, the preparation method of the semiconductor device includes the following steps.

[0072] S110, providing a substrate.

[0073] S120, forming a semiconductor epitaxial layer on one side of the substrate.

[0074] Optionally, FIG. 9 is a structural schematic diagram corresponding to step S120 in the preparation method of the semiconductor device according to the embodiment of the present application. Referring to FIG. 9, the material of the substrate 10 can be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiment of the present application, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both can be SiC. In some embodiments of the present application, the substrate 10 and the semiconductor epitaxial layer 20 can be integrally arranged. The integration of the substrate 10 and the semiconductor epitaxial layer 20 can be understood as that the substrate 10 and the semiconductor epitaxial layer 20 are a whole piece of SiC film layer structure formed in the same preparation process. After the front process is performed on the whole piece of SiC film layer structure, the back of the SiC film layer structure is thinned, and the back of the SiC film layer structure is heavily doped with ions to form the substrate 10.

[0075] After forming the semiconductor epitaxial layer 20 on one side of the substrate 10, further comprising: forming, in the semiconductor epitaxial layer 20, a drift region 21, a first body region 22 and a first contact region 23 in contact with the second electrode 40 in sequence away from the substrate 10. Optionally, the drift region 21, the first body region 22 and the first contact region 23 in sequence away from the substrate 10 can be formed in the semiconductor epitaxial layer 20 by using a plasma enhanced chemical vapor deposition (PECVD) and a photolithography technology, transferring a pattern of a photo mask to a SiO2mask layer, then based on the patterned mask layer, performing a front ion implantation on the semiconductor epitaxial layer 20, and then removing the mask layer. Different patterned mask layers can be used when performing ion implantation on different regions. In FIG. 9, N-type doping ions are implanted in the first contact region 231 of the first doping type and the drift region 21; and P-type doping ions are implanted in the first contact region 232 of the second doping type and the first body region 22.

[0076] S130, forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate.

[0077] Optionally, FIG. 10 is a structure diagram corresponding to step S130 in the method for manufacturing a semiconductor device provided by the embodiment of the present application. As shown in FIG. 10, the gate trench 01 can be formed by a photolithography process, etching the first contact region 23 (the first contact region 231 of the first doping type), the first body region 22 and part of the drift region 21 in sequence from the surface of the first contact region 23 away from the substrate 10. After forming the gate trench 01, the first body region 22 and the first contact region 23 are located on opposite sides of the gate trench 01. The step of forming the gate trench 01 by the photolithography process can include: depositing SiO2as a mask layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 by a chemical vapor deposition (CVD) process, spin-coating a photoresist (PR) on the surface of the mask layer, forming a photoresist PR with a desired pattern by exposure and development, and then based on the patterned photoresist PR, etching the mask layer to pattern the mask layer. The patterned mask layer exposes a preset position of the gate trench. Based on the patterned mask layer, the first contact region 231 of the first doping type, the first body region 22 and part of the drift region 21 of the semiconductor epitaxial layer 20 are etched in sequence; and the etching process can use a plasma dry etching process, such as a reactive ion etching (RIE) or an inductively coupled plasma (ICP) etching process.

[0078] S140, forming a third electrode at the bottom of the gate trench, and forming a trench gate structure in the gate trench.

[0079] Optionally, the forming of the third electrode at the bottom of the gate trench comprises: forming an electrode recess at the bottom of the gate trench, and performing ion implantation at the bottom of the gate trench to form a second contact region on the sidewall and the bottom of the electrode recess and a second body region between the second contact region and the drift region. The first body region and the second body region have the same doping type. The second contact region comprises a first-doping-type second contact region and a second-doping-type second contact region. The first-doping-type second contact region is located on the sidewall of the electrode recess. The second-doping-type second contact region is located on the bottom of the electrode recess. The second channel is located in the second body region between the first-doping-type first contact region and the drift region. The third electrode is formed in the electrode recess.

[0080] In an embodiment of the present application, optionally, the width of the third electrode 50 is less than the width of the gate trench. The forming of the third electrode at the bottom of the gate trench in step S140 comprises:

[0081] S411, forming an electrode recess with a width less than the width of the gate trench at the bottom of the gate trench.

[0082] Optionally, FIG. 11 is a structural schematic diagram corresponding to step S411 in the method for manufacturing a semiconductor device provided in an embodiment of the present application. As shown in FIG. 11, the electrode recess 02 with a width less than the width of the gate trench can be formed by using a SiO2 mask layer and an accurate dry etching technology (such as Deep Reactive Ion Etching (DRIE) or ICP).

[0083] S412, performing ion implantation at the bottom of the gate trench to form a second contact region on the sidewall and the bottom of the electrode recess and a second body region 25 between the second contact region and the drift region.

[0084] For forming the semiconductor device shown in FIG. 4, after performing ion implantation at the bottom of the gate trench 01, as shown in FIG. 12, the first-doping-type second contact region 241 and the second body region 25 are both located at the bottom of the gate trench 01, and the width of the second body region 25 is less than or equal to the width of the gate trench 01 (for example, the width of the second body region 25 is less than the width of the gate trench 01 as shown in FIG. 12).

[0085] For forming the semiconductor device shown in FIG. 5, after performing ion implantation at the bottom of the gate trench 01, as shown in FIG. 13, the first-doping-type second contact region 241 is located at the bottom of the gate trench 01, and the second body region 25 is located at the bottom of the gate trench 01 and extends from the bottom of the gate trench 01 to the sidewall of the gate trench 01 along the bottom corner of the gate trench 01.

[0086] For forming the semiconductor device shown in Fig. 6, after ion implantation at the bottom of the gate trench 01, referring to Fig. 14, the first-doped-type second contact region 241 is located at the bottom of the gate trench 01 and extends from the bottom of the gate trench 01 along the bottom corner of the gate trench 01 to the sidewall of the gate trench 01; the second body region 25 extends from the bottom of the gate trench 01 along the surface of the first-doped-type second contact region 241 away from the side of the gate trench 01 until covering the surface of the first-doped-type second contact region 241 away from the substrate 10.

[0087] S413, depositing source metal, removing the source metal on the sidewall of the gate trench by wet etching and retaining the source metal in the electrode recess, and performing annealing process to form the third electrode in the electrode recess.

[0088] Optionally, taking forming the semiconductor device shown in Fig. 4 as an example, referring to Fig. 15, after depositing the metal material, the metal material on the sidewall of the gate trench 01 is removed by wet etching and the metal material in the electrode recess 02 is retained, and annealing process is performed to form the third electrode 50 in the electrode recess 02.

[0089] In some optional embodiments, after ion implantation at the bottom of the gate trench 01 (i.e. before depositing the source metal), further comprising:

[0090] forming a carbon film on the sidewall of the gate trench 01 and the sidewall of the electrode recess 02, and removing the carbon film after passivating the sidewall by argon and high-temperature annealing treatment.

[0091] forming a sacrificial oxide layer on the sidewall of the gate trench 01 and the sidewall of the electrode recess 02, and removing the sacrificial oxide layer.

[0092] Optionally, in order to activate the implanted doping ions and eliminate the lattice damage defects caused by the implantation of the doping ions, activation annealing at a high temperature is needed for the semiconductor epitaxial layer 20, and the temperature is generally as high as 1600-1800℃. However, at such a high activation annealing temperature, since the material of the semiconductor epitaxial layer 20 is silicon carbide, the silicon on the surface of the silicon carbide is easy to sublimate from the surface of the silicon carbide and re-deposit on the wafer surface in the form of Si, Si2C, SiC2, etc., forming step clusters, increasing the surface roughness of the SiC wafer and the interface state density, and seriously affecting the device performance. The commonly used method during high-temperature annealing is carbon film protection method, and the manufacturing method is generally to sputter a carbon film protection layer or form a carbon film protection layer by baking and curing photoresist. After high-temperature annealing is completed, the carbon film for protecting the surface of the silicon carbide needs to be removed, and if the carbon film is not removed completely, it will affect the ohmic contact and seriously affect the switching characteristics, conductive characteristics, voltage withstand characteristics and other performances of the device. The carbon film can be removed by chemical solution immersion, and the chemical solution is generally a certain concentration of hydrochloric acid plus a certain amount of nitric acid as a catalyst. In some optional embodiments, after the carbon film on the surface of the semiconductor epitaxial layer 20 is removed, further comprising: forming a sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 by a thermal oxidation process to repair the lattice on the surface of the semiconductor epitaxial layer 20; and removing the sacrificial oxide layer. The sacrificial oxide layer on the surface can be removed by buffered oxide etching (BOE) cleaning.

[0093] FIGS. 16-18 are structure schematic diagrams corresponding to steps S414-S416 in the preparation method of the semiconductor device provided in the embodiments of the present application, and referring to FIGS. 16-18, in step S140, forming the trench gate structure in the gate trench 01 includes:

[0094] S414, forming a gate insulating layer on the slot wall of the gate trench.

[0095] Referring to FIG. 16, at least one of SiO2 and Al2O3 can be deposited by ALD to form the gate insulating layer 62.

[0096] S415, forming a dielectric isolation layer on the bottom of the gate trench.

[0097] Referring to FIG. 17, the material of the dielectric isolation layer 70 can include at least one of SiO2and Al2O3, and the dielectric isolation layer 70 can be prepared by at least one of ALD, thermal oxidation, and wet method. Since the thickness of the gate insulating layer 62 is generally in the range of 4 nm to 5 nm, the thickness is relatively thin, and the gate insulating layer 62 at the bottom of the gate trench 01 is more difficult to grow than the gate insulating layer 62 at the sidewall of the gate trench 01, resulting in that the gate insulating layer 62 at the bottom is thinner, therefore, the dielectric isolation layer 70 with a relatively thick thickness is arranged between the third electrode 50 and the polysilicon gate 61, which can enhance the isolation effect of the third electrode 50 and the polysilicon gate 61. The thickness of the dielectric isolation layer 70 can be greater than or equal to the thickness of the gate insulating layer 62 at the bottom of the gate trench 01.

[0098] S416, forming a polysilicon gate on the surface of the gate insulating layer away from the gate trench.

[0099] Referring to FIG. 18, the polysilicon material can be deposited by using a low pressure chemical vapor deposition (LPCVD) process, and after the deposition, the polysilicon etching is performed to reserve the polysilicon material in the gate trench 01, thereby forming the polysilicon gate 61.

[0100] In another embodiment of the present application, the width of the third electrode 50 is equal to the width of the gate trench 01. FIGS. 19 to 24 are structure schematic diagrams corresponding to steps S421 to S426 in a preparation method of a semiconductor device provided in an embodiment of the present application, which is used to form the semiconductor device shown in FIG. 7. Referring to FIGS. 19 to 24, the step of forming the third electrode at the bottom of the gate trench in step S140 includes:

[0101] S421, forming the gate trench and the electrode recess in the same etching process, so that the width of the electrode recess is equal to the width of the gate trench.

[0102] Referring to FIG. 19, since the width of the third electrode 50 is equal to the width of the gate trench 01, the width of the electrode recess 02 for accommodating the third electrode 50 is equal to the width of the gate trench 01. After the gate trench 01 is etched, the semiconductor epitaxial layer 20 can be continuously etched in the same process, thereby forming the electrode recess 02 with the width equal to the width of the gate trench 01.

[0103] S422, performing ion implantation at the bottom of the gate trench to form a second contact region at the sidewall and the bottom of the electrode recess, and a second body region between the second contact region and the drift region.

[0104] Referring to FIG. 20, after ion implantation at the bottom of the gate trench 01, the first-doped-type second contact region 241 extends from the sidewall of the electrode recess 02 to the sidewall of the gate trench 01; the second body region 25 extends from the bottom of the gate trench 01 along the surface of the first-doped-type second contact region 241 away from the side of the gate trench 01 until the surface of the first-doped-type second contact region 241 away from the substrate 10.

[0105] S423, depositing a source metal, removing the source metal on the sidewall of the gate trench 01 by wet etching to retain the source metal in the electrode recess, and performing an annealing process to form a third electrode in the electrode recess. Please refer to FIG. 21.

[0106] In some optional embodiments, after forming the gate trench 01 and the electrode recess 02, and after ion implantation at the bottom of the gate trench 01 (i.e., before depositing the source metal), the method further comprises:

[0107] After forming a carbon film on the sidewall of the gate trench 01 and the sidewall of the electrode recess 02, and performing passivation on the sidewall by argon and high-temperature annealing treatment, the carbon film is removed; a sacrificial oxide layer is formed on the sidewall of the gate trench 01 and the sidewall of the electrode recess 02, and the sacrificial oxide layer is removed. For specific steps and effects, please refer to the above embodiments, which will not be repeated here.

[0108] In step S140, forming a trench gate structure in the gate trench 01 comprises:

[0109] S424, forming a gate insulating layer on the sidewall of the gate trench, and removing the gate insulating layer at the bottom of the gate trench 01 by dry etching. Please refer to FIG. 22.

[0110] S425, forming a dielectric isolation layer at the bottom of the gate trench. Please refer to FIG. 23.

[0111] S426, forming a polysilicon gate on the surface of the gate insulating layer away from the gate trench. Please refer to FIG. 24.

[0112] S150, forming a second electrode on the surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure. Optionally, the second electrode can be located on opposite sides of the trench gate structure, please refer to FIGS. 4-7.

[0113] S160, forming a first electrode on the surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is configured to form a first channel for conducting the first electrode and the second electrode; and the second body region is configured to form a second channel for conducting the first electrode and the third electrode.

[0114] The first electrode 30 and the second electrode 40 are electrically connected through the first channel L1 extending along the sidewall of the gate trench; the first electrode 30 and the third electrode 50 are electrically connected through the second channel L2 extending along the sidewall of the gate trench and / or the bottom surface of the gate trench. Please refer to FIG. 4-7.

[0115] Before forming the first electrode 30 on the surface of the substrate 10 far away from the semiconductor epitaxial layer 20, the substrate 10 can be thinned from the side far away from the semiconductor epitaxial layer 20.

[0116] The embodiment of the present application further provides a power module, which comprises a substrate and at least one semiconductor device as described in any of the embodiments of the present application, and the substrate is arranged to carry the semiconductor device. The power module has the same technical effects as the semiconductor device described in any of the embodiments of the present application, and thus the details are not described herein.

[0117] The embodiment of the present application further provides a power conversion circuit, which is arranged to perform one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as described in any of the embodiments of the present application, and the semiconductor device is electrically connected to the circuit board. The power conversion circuit has the same technical effects as the semiconductor device described in any of the embodiments of the present application, and thus the details are not described herein.

[0118] The embodiment of the present application further provides a vehicle, which comprises a load and a power conversion circuit as described in any of the embodiments of the present application, and the power conversion circuit is arranged to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current or convert direct current into alternating current, and then input to the load. The vehicle has the same technical effects as the semiconductor device described in any of the embodiments of the present application, and thus the details are not described herein.

Claims

1. A semiconductor device, comprising: a substrate; a semiconductor epitaxial layer on one side of the substrate; a gate trench on a surface of the semiconductor epitaxial layer away from the substrate; a trench gate structure in the gate trench; a first electrode on a side of the substrate away from the semiconductor epitaxial layer; a second electrode on a surface of the semiconductor epitaxial layer away from the substrate and on at least one side of the trench gate structure; and a third electrode in the semiconductor epitaxial layer and on a bottom of the trench gate structure; wherein the semiconductor epitaxial layer comprises a first body region and a second body region in contact with the trench gate structure; the first body region is configured to form a first channel for conducting between the first electrode and the second electrode; and the second body region is configured to form a second channel for conducting between the first electrode and the third electrode. 2.The semiconductor device of claim 1, wherein: the semiconductor epitaxial layer comprises, in order away from the substrate, a drift region, the first body region, and a first contact region in contact with the second electrode; the first body region and the first contact region are on the same side of the trench gate structure; the first contact region comprises a first-doping-type first contact region and a second-doping-type first contact region; the first-doping-type first contact region is between the gate trench and the second-doping-type first contact region; the first body region is of a second doping type, and the drift region is of a first doping type; and the first body region is in contact with a sidewall of the trench gate structure. 3.The semiconductor device of claim 2, wherein: the semiconductor epitaxial layer further comprises a second contact region covering a sidewall and a bottom of the third electrode, and a second body region between the second contact region and the drift region; the first body region and the second body region are of the same doping type; the second contact region comprises a first-doping-type second contact region and a second-doping-type second contact region; the first-doping-type second contact region is on the sidewall of the third electrode; and the second-doping-type second contact region is on the bottom of the third electrode; the second body region is in contact with at least one of a sidewall and a bottom of the trench gate structure; the third electrode has a width smaller than a width of the gate trench; the first-doping-type second contact region and the second body region are on the bottom of the gate trench, and the second body region has a width smaller than or equal to the width of the gate trench; the second body region is in contact with the bottom of the trench gate structure; or the first-doping-type second contact region is on the bottom of the gate trench, the second body region is on the bottom of the gate trench, and extends from the bottom of the gate trench to the sidewall of the gate trench along a bottom corner of the gate trench; and the second body region is in contact with the sidewall and the bottom of the trench gate structure. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 4. The semiconductor device of claim 3, wherein, ​ ​ Alternatively, the first-doped-type second contact region is located at the bottom of the gate trench and extends from the bottom of the gate trench to the sidewall of the gate trench along the bottom corner of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first-doped-type second contact region away from the sidewall of the gate trench until covering the surface of the first-doped-type second contact region away from the substrate. The second body region is in contact with the sidewall of the trench gate structure.

5. The semiconductor device of claim 3, wherein, The width of the third electrode is equal to the width of the gate trench. The first-doped-type second contact region extends from the sidewall of the third electrode to the sidewall of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first-doped-type second contact region away from the sidewall of the gate trench until covering the surface of the first-doped-type second contact region away from the substrate. The second body region is in contact with the sidewall of the trench gate structure.

6. The semiconductor device of claim 1, wherein, The trench gate structure comprises a polysilicon gate and a gate insulating layer between the polysilicon gate and the gate trench.

7. The semiconductor device of claim 6, further comprising a dielectric isolation layer; The dielectric isolation layer is located in the gate trench and between the third electrode and the polysilicon gate.

8. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor epitaxial layer on one side of the substrate; forming a gate trench on the surface of the semiconductor epitaxial layer away from the substrate; forming a third electrode on the bottom of the gate trench and forming a trench gate structure in the gate trench; forming a second electrode on the surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure; forming a first electrode on the surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer comprises a first body region and a second body region in contact with the trench gate structure; the first body region is configured to form a first channel for conducting the first electrode and the second electrode; the second body region is configured to form a second channel for conducting the first electrode and the third electrode.

9. The method for manufacturing a semiconductor device of claim 8, after forming a semiconductor epitaxial layer on one side of the substrate, the method further comprises: forming a drift region, the first body region and a first contact region in contact with the second electrode in the semiconductor epitaxial layer in sequence away from the substrate; wherein the forming a gate trench on the surface of the semiconductor epitaxial layer away from the substrate comprises: etching the first contact region, the first body region and part of the drift region in sequence away from the surface of the first contact region away from the substrate to form the gate trench; after forming the gate trench, the first body region and the first contact region are both located on the same side of the gate trench as the second electrode. The first contact region comprises a first-doping-type first contact region and a second-doping-type first contact region; the first-doping-type first contact region is located between the gate trench and the second-doping-type first contact region; the first body region is of a second doping type, and the drift region is of a first doping type; the first body region is in contact with the sidewall of the trench gate structure.

10. The method of producing a semiconductor device according to Claim 9, wherein A third electrode is formed at the bottom of the gate trench, comprising: An electrode recess is formed at the bottom of the gate trench, and ion implantation is performed at the bottom of the gate trench to form a second contact region located at the sidewall and the bottom of the electrode recess and a second body region located between the second contact region and the drift region; the first body region and the second body region are of the same doping type; the second contact region comprises a first-doping-type second contact region and a second-doping-type second contact region; the first-doping-type second contact region is located at the sidewall of the electrode recess; the second-doping-type second contact region is located at the bottom of the electrode recess, and the second body region is in contact with at least one of the sidewall and the bottom of the trench gate structure; The third electrode is formed in the electrode recess.

11. The method of producing a semiconductor device according to Claim 9, wherein In the case where the width of the third electrode is equal to the width of the gate trench, an electrode recess is formed at the bottom of the gate trench, comprising: The gate trench and the electrode recess are formed in the same etching process.

12. The method for manufacturing the semiconductor device according to claim 10, after the gate trench and the electrode recess are formed, the method further comprises: A carbon film is formed on the sidewall of the gate trench and the sidewall of the electrode recess, and the sidewall is passivated by argon and subjected to high-temperature annealing treatment, and then the carbon film is removed; A sacrificial oxide layer is formed on the sidewall of the gate trench and the sidewall of the electrode recess, and then the sacrificial oxide layer is removed.

13. The method of producing a semiconductor device according to Claim 8, wherein A trench gate structure is formed in the gate trench, comprising: A gate insulating layer is formed on the sidewall of the gate trench; A polysilicon gate is formed on the surface of the gate insulating layer away from the gate trench; Before the polysilicon gate is formed on the surface of the gate insulating layer away from the gate trench, the method further comprises: A dielectric isolation layer is formed at the bottom of the gate trench.

14. A power module, comprising a substrate and at least one semiconductor device according to any one of claims 1-7, wherein the substrate is configured to support the semiconductor device.

15. A power conversion circuit, configured to perform one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1-7, wherein the semiconductor device is electrically connected to the circuit board.

16. A vehicle, comprising a load and a power conversion circuit according to claim 15, wherein the power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input to the load.

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