Oscillator, phase-locked loop circuit, and communication apparatus

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide an oscillator, a phase-locked loop circuit, and a communication apparatus. The oscillator is used for achieving low power consumption and low phase noise. The oscillator comprises an adjustable capacitor, a differential amplifier, and an inductive element. The inductive element comprises: a first inductor, a second inductor and a third inductor. One end of the first inductor is coupled to a first node, one end of the third inductor is coupled to a second node, the other end of the first inductor and one end of the second inductor are coupled to a third node, and the other end of the second inductor and the other end of the third inductor are coupled to a fourth node. The adjustable capacitor is coupled between the first node and the second node. The differential amplifier comprises a differential first input end and second input end, and a differential first output end and second output end, the first input end and the second output end both being coupled to the first node, and the second input end and the first output end both being coupled to the second node. The second inductor further comprises a tap end, the tap end being used for coupling to a power supply end or a ground end.

Description

Oscillator, phase-locked loop circuit and communication device

[0001] The present application claims priority to the Chinese patent application No. 202410988271.6, filed on July 22, 2024, and entitled "Oscillator, phase-locked loop circuit and communication device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular, to an oscillator, a phase-locked loop circuit and a communication device. BACKGROUND

[0003] Oscillators are widely used in various electronic systems. For example, an oscillator can be used in a clock circuit of a microprocessor to generate a stable clock signal. An oscillator can also be used in a phase-locked loop of a wireless transceiver to provide a stable local oscillation signal for the wireless transceiver to ensure the communication performance of the wireless transceiver. The power consumption and the phase noise of an oscillator are the main parameters for measuring the performance of the oscillator. Therefore, it is desirable to have an oscillator with low power consumption and low phase noise, which has been a long-term research topic. SUMMARY

[0004] Embodiments of the present application provide an oscillator, a phase-locked loop circuit and a communication device, which can be used to achieve low power consumption and low phase noise.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an oscillator is provided, comprising: an adjustable capacitor, a differential amplifier and an inductive element; the inductive element comprises: a first inductor, a second inductor and a third inductor; one end of the first inductor is coupled to a first node, one end of the third inductor is coupled to a second node, the other end of the first inductor and one end of the second inductor are coupled to a third node, the other end of the second inductor and the other end of the third inductor are coupled to a fourth node, and the adjustable capacitor is coupled between the first node and the second node; the differential amplifier comprises a differential first input and a differential second input, and a differential first output and a differential second output, the first input and the second input are both coupled to the first node, and the second input and the first output are both coupled to the second node; the second inductor further comprises a tap end, and the tap end is configured to be coupled to a power supply end or a ground end.

[0007] In the above technical solution, the oscillator uses a differential amplifier and an adjustable capacitor to form a resonant cavity, generating a resonant frequency. Under ideal conditions (i.e., when a stable resonance is generated in the resonant cavity), this resonant frequency is the oscillation frequency of the LC oscillator. The resonant cavity is connected in parallel with the negative resistance formed by the differential amplifier to supplement the energy consumed by the resonant cavity due to resonance, so that the oscillator generates a stable and continuous resonance. The oscillator with this structure has low phase noise and low power consumption. The phase noise of the oscillator directly affects the performance of the oscillator, and this oscillator has good performance.

[0008] In one possible implementation of the first aspect, the differential amplifier includes: a first transistor and a second transistor; the gate of the first transistor is a first input terminal, and the drain of the first transistor is a second output terminal; the gate of the second transistor is a second input terminal, and the drain of the second transistor is a first output terminal. In the above possible implementation, a resonant cavity is formed using the first transistor, the second transistor, and an adjustable capacitor to generate a resonant frequency. Ideally (i.e., when a stable resonance is generated within the resonant cavity), this resonant frequency is the oscillation frequency of the LC oscillator. The resonant cavity is connected in parallel with the negative resistance formed by the active first and second transistors to compensate for the energy consumed by the resonant cavity due to resonance, enabling the oscillator to generate a stable and continuous resonance. This differential amplifier structure includes a small number of transistors, resulting in less phase noise generated during oscillation, thus the oscillator has low phase noise. The phase noise of the oscillator directly affects the performance of the oscillator, and this oscillator has good performance. On the other hand, the transistors in this differential amplifier structure are equivalent to Class B power amplifiers, exhibiting low power consumption when the transistors are operating.

[0009] In one possible implementation of the first aspect, when the first transistor and the second transistor are NMOS transistors, the sources of both transistors are coupled to ground, and the first voltage terminal is the power supply terminal. The above possible implementations improve the variety of implementation options and increase selectivity.

[0010] In one possible implementation of the first aspect, when the first transistor and the second transistor are PMOS transistors, the sources of both transistors are coupled to the power supply terminal, and the first voltage terminal is grounded. The above possible implementations improve the variety of implementation options and increase selectivity.

[0011] In one possible implementation of the first aspect, the differential amplifier further includes a third transistor and a fourth transistor. The gate of the third transistor is coupled to the first node, the gate of the fourth transistor is coupled to the second node, the drain of the third transistor is coupled to the drain of the first transistor, and the drain of the fourth transistor is coupled to the drain of the second transistor. In the above possible implementations, increasing the number of transistors is equivalent to increasing the number of negative resistors, which improves the efficiency of supplementing the energy consumed by the resonant cavity due to resonance, thereby improving the performance of the oscillator.

[0012] In one possible implementation of the first aspect, the oscillator further includes a first set of switches and a second set of switches. The first set of switches includes a first switch and a second switch, and the second set of switches includes a third switch and a fourth switch. The first switch is coupled between the third node and the drain of the second transistor. One end of the first switch and the drain of the second transistor are coupled to a fifth node. The second switch is coupled between the fourth node and the drain of the first transistor. One end of the second switch and the drain of the first transistor are coupled to a sixth node. The third switch is coupled between the first node and the fifth node, and the fourth switch is coupled between the second node and the sixth node. In the above possible implementations, switching different switches allows the oscillator to operate in different states, satisfying different requirements.

[0013] In one possible implementation of the first aspect, when the first set of switches is open and the second set of switches is closed, the oscillator is in a low-power state. Specifically, when the first set of switches is open and the second set of switches is closed, the power consumption of the oscillator is less than when the first set of switches is closed and the second set of switches is open, and the phase noise is greater than when the first set of switches is closed and the second set of switches is open. When the first set of switches is closed and the second set of switches is open, the oscillator is in a low-phase-noise state. Specifically, when the first set of switches is closed and the second set of switches is open, the phase noise of the oscillator is less than when the first set of switches is open and the second set of switches is closed, and the power consumption is greater than when the first set of switches is open and the second set of switches is closed. In the above-mentioned possible solutions, the oscillator can operate in different states by switching different switches to meet different scenario requirements. For example, when the first set of switches is turned off and the second set of switches is turned on, the transistor is equivalent to a Class B power amplifier, and the oscillator is in a low-power state, which meets the requirements of low-power scenarios and reduces the power consumption of the oscillator. When the first set of switches is turned on and the second set of switches is turned off, the conversion time of device noise to phase noise within one frequency cycle is reduced, and the phase noise of the device itself is also reduced. The oscillator is in a low-phase noise state, which meets the requirements of low-phase noise (i.e., high-performance) scenarios and improves the performance of the oscillator.

[0014] In one possible implementation of the first aspect, the oscillator further includes a third set of switches, comprising a fifth switch and a sixth switch; one end of the fifth switch is coupled to a fifth node, and the other end of the fifth switch is coupled to a first inductor; one end of the sixth switch is coupled to a sixth node, and the other end of the sixth switch is coupled to a third inductor. In the above possible implementations, switching different switches allows the oscillator to handle low-power states or different phase noise states, meeting the requirements of low-power and different phase noise scenarios.

[0015] In one possible implementation of the first aspect, when the first and third sets of switches are open and the second set of switches is closed, the oscillator is in a low-power state; when the first set of switches is closed and the second and third sets of switches are open, the oscillator is in a first-phase-noise state; when the third set of switches is closed and the first and second sets of switches are open, the oscillator is in a second-phase-noise state, where the first-phase-noise is less than the second-phase-noise. In the above possible implementations, switching different switches allows the oscillator to handle either a low-power state or a different-phase-noise state, satisfying the requirements of both low power consumption and different-phase-noise scenarios.

[0016] In one possible implementation of the first aspect, the oscillator further includes a first set of switches and a second set of switches. The first set of switches includes a first switch and a second switch, and the second set of switches includes a third switch and a fourth switch. The first switch is coupled between a third node and the drain of a second transistor. One end of the first switch and the drain of the second transistor are coupled to a fifth node. The second switch is coupled between the fourth node and the drain of the first transistor. One end of the second switch and the drain of the first transistor are coupled to a sixth node. One end of the third switch is coupled to the fifth node, and the other end of the third switch is coupled to a first inductor. One end of the fourth switch is coupled to the sixth node, and the other end of the fourth switch is coupled to the third inductor. In the above possible implementation, connecting the switches to different positions on the inductor results in oscillators with different phase noises. During the design phase, the phase noise of the oscillator can be adjusted by changing the position of the switches connected to the inductor, thereby determining the required phase noise based on the position of the switches connected to the inductor.

[0017] In one possible implementation of the first aspect, when the first set of switches is closed and the second set of switches is open, the phase noise of the oscillator is the first phase noise; when the first set of switches is open and the second set of switches is closed, the phase noise of the oscillator is the third phase noise, and the first phase noise is greater than the third phase noise. In the above possible implementations, different phase noises are obtained by switching different switches, satisfying scenarios requiring different phase noises.

[0018] In one possible implementation of the first aspect, the oscillator further includes a shielding ring, with the oscillator located inside the shielding ring; the shielding ring includes a fourth inductor and a seventh switch, with the first and second ends of the fourth inductor coupled to the first and second ends of the seventh switch, respectively. In the above possible implementations, the shielding ring shields the oscillator from external circuitry, protecting the inductors in the oscillator from interference from other interference signals in the external circuitry, thereby improving the stability and anti-interference capability of the oscillator.

[0019] In one possible implementation of the first aspect, the shielding ring further includes: at least one capacitor; the at least one capacitor is connected in series between the first end of the fourth inductor and one end of the seventh switch. In the above possible implementations, the shielding ring shields the oscillator from external circuits, protecting the inductor in the oscillator from interference from other interference signals in the external circuit, improving the stability and anti-interference capability of the oscillator. Furthermore, by connecting different capacitors, the inductor can generate different induced currents and different magnetic fields, thereby changing the inductance value of the oscillator and achieving broadband frequency coverage, thus meeting broadband frequency coverage requirements.

[0020] In one possible implementation of the first aspect, the oscillator includes multiple adjustable capacitors, which are connected in series between the first node and the second node. In the above possible implementation, the adjustable capacitors can be used to adjust the frequency of the oscillator, achieving broadband frequency coverage and meeting broadband frequency coverage requirements.

[0021] In a second aspect, a phase-locked loop (PLL) circuit is provided, which includes a phase detector, a filter, and an oscillator. The oscillator is the same as that provided in the first aspect or any possible implementation thereof. The phase detector is used to obtain a phase difference signal and convert the phase difference signal into a voltage signal. The filter is used to filter the voltage signal. The oscillator is used to output a local oscillation signal based on the filtered voltage signal.

[0022] Thirdly, a communication device is provided, comprising a radio frequency transceiver, wherein a mixer and a phase-locked loop circuit as provided in the second aspect above are integrated in the radio frequency transceiver, the phase-locked loop circuit being used to provide a local oscillation signal for the mixer.

[0023] Understandably, any of the phase-locked loop circuits and communication devices provided above include all the features of the oscillator described above, and their beneficial effects can be referred to the beneficial effects of the oscillator provided above, which will not be repeated here. Attached Figure Description

[0024] Figure 1 is a schematic diagram of a negative resistance oscillator provided in an embodiment of this application;

[0025] Figure 2 is a structural layout of a negative resistance oscillator provided in an embodiment of this application;

[0026] Figure 3 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0027] Figure 4 is a schematic diagram of a phase-locked loop circuit provided in an embodiment of this application;

[0028] Figure 5 is a schematic diagram of an oscillator provided in an embodiment of this application;

[0029] Figure 6 is a schematic diagram of another oscillator provided in an embodiment of this application;

[0030] Figure 7 is a schematic diagram of another oscillator provided in an embodiment of this application;

[0031] Figure 8 is a schematic diagram of another oscillator provided in an embodiment of this application;

[0032] Figure 9 is a schematic diagram of another oscillator provided in an embodiment of this application;

[0033] Figure 10 is a structural layout of an oscillator provided in an embodiment of this application;

[0034] Figure 11 is a structural layout of another oscillator provided in an embodiment of this application;

[0035] Figure 12 is a structural layout of another oscillator provided in an embodiment of this application;

[0036] Figure 13 is a structural layout of another oscillator provided in an embodiment of this application;

[0037] Figure 14 is a structural layout of another oscillator provided in an embodiment of this application;

[0038] Figure 15 is a structural layout of another oscillator provided in an embodiment of this application;

[0039] Figure 16 is a schematic diagram of another oscillator provided in an embodiment of this application;

[0040] Figure 17 is a structural layout of another oscillator provided in an embodiment of this application;

[0041] Figure 18 is a structural layout of another oscillator provided in an embodiment of this application. Detailed Implementation

[0042] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, embodiments of this application utilize terms such as "first" and "second" to distinguish identical or similar items with essentially the same function and effect. For example, a first threshold and a second threshold are merely for distinguishing different thresholds and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order.

[0043] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0044] Before introducing the embodiments of this application, we will first introduce and explain the relevant knowledge of oscillators.

[0045] Oscillators, as one of the essential components of electronic systems, have a wide range of applications. For example, oscillators can be used in the clock circuits of microprocessors to generate stable clock signals; they can also be used in the phase-locked loops (PLLs) of wireless transceivers to provide a stable local oscillation signal, ensuring the transceiver's communication performance. Power consumption and phase noise are the main parameters for evaluating oscillator performance. Generally, it is desirable for oscillators to have low power consumption and low phase noise; therefore, oscillators with low power consumption and low phase noise have been a long-standing research topic.

[0046] Among them, negative resistance oscillators are widely used in communication devices due to their advantages such as simple structure, mature circuit design, and strong stability. For example, Figure 1 is a schematic diagram of a negative resistance oscillator 100, which includes transistors Ma to Md, an inductor L101, and an adjustable capacitor Cs101. The inductor L101 and the adjustable capacitor Cs101 are coupled in parallel between nodes Pa and Pb. The drain Da of transistor Ma, the drain Dc of transistor Mc, the gate Gb of transistor Mb, and the gate Gd of transistor Md are coupled to node Pa. The drain Db of transistor Mb, the drain Dd of transistor Md, the gate Ga of transistor Ma, and the gate Gc of transistor Mc are coupled to node Pb. The source Sa of transistor Ma and the source Sb of transistor Mb are coupled to the ground terminal GND. The source Sc of transistor Mc and the source Sd of transistor Md are used to receive the power supply voltage VDD.

[0047] A negative resistance oscillator is an oscillator that uses a negative resistance device (also called a negative resistor) to offset the oscillation loss of a positive resistance device (also called a positive resistor) in the circuit, thereby generating self-excited oscillation. The larger the current in the positive resistance device, the larger the voltage across the device, and the greater the power consumption. For example, a positive resistance device can include a resistor; in Figure 1, the resonant cavity formed by inductor L101 and capacitor Cs101 can be considered a positive resistance device. Conversely, the larger the current in a negative resistance device, the smaller the voltage across it. Under certain conditions, a negative resistance device not only does not consume power but also outputs power. For example, negative resistance devices can include transistors, vacuum tubes, and diodes. In Figure 1, transistors Ma to Md are negative resistance devices.

[0048] Furthermore, the coupling method between transistors Ma and Mb, or between transistors Mc and Md, can also be referred to as cross-coupling. The transistors in this embodiment can refer to metal oxide semiconductors (MOS), and the types of transistors can include n-type metal oxide semiconductors (NMOS) and p-type metal oxide semiconductors (PMOS). The transistors can also be other types, such as gallium nitride transistors. Figure 1 uses transistors Ma and Mb as NMOS and the third transistor Mc and Md as PMOS as an example.

[0049] During operation, the inductor L101 and capacitor Cs101 form a resonant cavity and generate a resonant frequency. Under ideal conditions (i.e., when a stable resonance is generated in the resonant cavity), this resonant frequency is the oscillation frequency of the LC oscillator. The resonant cavity is connected in parallel with the negative resistance formed by the active transistors Ma to Md to supplement the energy consumed by the resonant cavity due to resonance, so that the negative resistance oscillator 100 generates a stable and continuous resonance, so that the negative resistance oscillator 100 continues to oscillate.

[0050] For example, Figure 2 is a structural layout of the negative resistance oscillator shown in Figure 1. As can be seen from Figure 2, the inductor L101 in the negative resistance oscillator is a passive device and occupies a large area on the structural layout.

[0051] However, the negative resistance oscillator of this structure has high phase noise, which cannot meet the requirements of low noise (i.e., high performance) scenarios. On the other hand, the inductor occupies a large area on the structural layout, and the exposed metal coil is easily affected by other magnetic fields, affecting the performance of the oscillator. In addition, the oscillation frequency of the oscillator is related to the inductor and the adjustable capacitor. When the inductor is constant, the oscillation frequency is related to the change in the adjustable capacitor. Since the adjustment range of the adjustable capacitor is small, the oscillation frequency range of the oscillator is small, making it difficult to meet the requirement of bandwidth frequency coverage.

[0052] Based on this, this application provides an oscillator that uses a differential amplifier and an adjustable capacitor to form a resonant cavity and generate a resonant frequency. Under ideal conditions (i.e., when a stable resonance is generated in the resonant cavity), the resonant frequency is the oscillation frequency of the LC oscillator. The resonant cavity is connected in parallel with the negative resistance formed by the active differential amplifier to supplement the energy consumed by the resonant cavity due to resonance, so that the oscillator generates a stable and continuous resonance. The oscillator with this structure has low phase noise and low power consumption. The phase noise of the oscillator directly affects the performance of the oscillator, and this oscillator has good performance.

[0053] The oscillator provided in this application embodiment can be applied to a communication device. The structure of the communication device will be described below.

[0054] Figure 3 is a schematic diagram of a communication device provided in an embodiment of this application. The communication device may include a radio frequency transceiver 001 and multiple sets of radio frequency circuits 002, with the transceiver 001 and the multiple sets of radio frequency circuits 002 sharing some components. The radio frequency transceiver 001 may include: a phase-locked loop (PLL) circuit 10, a local oscillator generator (LO) 11, a digital baseband (DBB) circuit 12, a transmit analog baseband (TX ABB) circuit 13 (schematically TXABB in the figure), and a mixer 14. Optionally, the communication device may also include a power amplifier (PA) 15 and an antenna 16. Each set of radio frequency circuits 002 may include the TX ABB circuit 13, the mixer 14, the PA 15, and the antenna 16.

[0055] The PLL circuit 10 may include the oscillator provided in the embodiments of this application. In one possible design, the DBB circuit 12 and the TX ABB circuit 13 are collectively referred to as the baseband circuit.

[0056] First, the connection relationships of the above-mentioned devices will be explained:

[0057] The output of PLL circuit 10 is connected to the input of LO 11. For each group of RF circuits 002, the output of LO 11 is connected to the first input of mixer 14. On the transmit link of each group of RF circuits 002, DBB circuit 12 is connected to the input of TX ABB circuit 13, the output of TX ABB circuit 13 is connected to the second input of mixer 14, the output of mixer 14 is connected to the input of PA 15, and the output of PA 15 is connected to antenna 16.

[0058] The functions of each of the above devices are described below:

[0059] PLL circuit 10 is used to output a first oscillation signal with a fixed clock frequency for each channel to LO 11. This first oscillation signal can also be called a local oscillation signal.

[0060] LO 11 is used to process the first oscillation signal and output multiple local oscillation signals to the mixer 14.

[0061] DBB circuit 12 is used to send digital signals to the transmit link of RF circuit 13.

[0062] The TX ABB circuit 13 is used to filter and amplify the digital signal from the DBB circuit 12.

[0063] Mixer 14 is used to mix the transmitted oscillation signal and the signal output from TX ABB circuit 13, and output the signal to PA15.

[0064] PA15 is used to amplify the signal after mixing.

[0065] Antenna 16 is used to transmit the signal amplified by PA15.

[0066] The specific structure of the phase-locked loop (PLL) will be described in detail below based on Figure 4. Figure 4 is a schematic diagram of a PLL circuit, which can be the PLL circuit shown in Figure 3. The PLL circuit includes: a phase detector 401, a filter 402, an oscillator 403, and a frequency divider 404. The phase detector 401 is used to compare a reference signal and the local oscillation signal fed back by the frequency divider 404 to obtain a phase difference signal, and converts the phase difference signal into a voltage signal for output. The reference signal can be a signal provided by a reference frequency source. The filter 402 filters the voltage signal. The oscillator 403 is used to output a local oscillation signal based on the filtered voltage signal. The local oscillation signal can be fed back to the phase detector 401 through the frequency divider 404 to form a closed-loop feedback circuit.

[0067] The specific structure of the oscillator provided in the embodiment of this application will be described below based on Figure 5.

[0068] For example, Figure 5 is a schematic diagram of an oscillator provided in an embodiment of this application. The oscillator can be the oscillator shown in Figure 4. The oscillator may include: an adjustable capacitor Cs1, a first inductor L1, a second inductor L2, a third inductor L3, and a differential amplifier 501. The first inductor L1, the second inductor L2, and the third inductor L3 are connected in series between a first node P1 and a second node P2. One end of the first inductor L1 is coupled to the first node P1, one end of the third inductor L3 is coupled to the second node P2, the other end of the first inductor L1 and one end of the second inductor L2 are coupled to the third node P3, and the other ends of the second inductor L2 and the third inductor L3 are coupled to a fourth node P4. The adjustable capacitor Cs1 is coupled between the first node P1 and the second node P2.

[0069] The differential amplifier 501 includes a differential first input terminal Vi1 and a differential second input terminal Vi2, as well as a differential first output terminal Vo1 and a differential second output terminal Vo2. The first input terminal Vi1 and the second output terminal Vo2 are both coupled to the first node P1, and the second input terminal Vi2 and the first output terminal Vo1 are both coupled to the second node P2. The tap Q2 of the second inductor L2 is used to couple to either the power supply terminal VDD or the ground terminal GND.

[0070] In one possible embodiment, continuing to refer to FIG5, the differential amplifier 501 includes: a first transistor M1 and a second transistor M2. The gate G1 of the first transistor M1 is coupled to the first node P1 as the first input terminal Vi1 of the differential amplifier 501. The gate G2 of the second transistor M2 is coupled to the second node P2 as the second input terminal Vi2 of the differential amplifier 501. The drain D1 of the first transistor M1 is coupled to the second node P2 as the first output terminal Vo1 of the differential amplifier 501. The drain D2 of the second transistor M2 is coupled to the first node P1 as the second output terminal Vo2 of the differential amplifier 501.

[0071] The coupling method between the first transistor M1 and the second transistor M2 can also be referred to as cross-coupling. In this embodiment, the transistor can be a metal oxide semiconductor (MOS), and the type of transistor can include n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS). The transistor can also be other types, such as gallium nitride transistors; this embodiment does not specifically limit the type.

[0072] Furthermore, the first transistor M1 and the second transistor M2 are transistors of the same type. For example, the first transistor M1 and the second transistor M2 can both be PMOS transistors, or the first transistor M1 and the second transistor M2 can both be NMOS transistors. This application embodiment does not specifically limit this.

[0073] In addition, the second inductor L2 also includes a tap, which is used to couple with the power supply or ground. The tap can be located anywhere on the second inductor L2; for example, the tap of the second inductor L2 can be the midpoint Q1. Figure 5 shows an example where the tap of the second inductor L2 is the midpoint Q1.

[0074] Optionally, the inductance value of the first inductor L1 is equal to the inductance value of the third inductor L3.

[0075] Since the first transistor M1 and the second transistor M2 can be any type of transistor, when the types of the first transistor M1 and the second transistor M2 are different, the tap of the second inductor L2 is coupled to different voltage terminals (including the power supply terminal VDD and the ground terminal GND). The coupling method of the tap Q2 of the second inductor L2 when the first transistor M1 and the second transistor M2 are different types will be explained below.

[0076] In one possible embodiment, as shown in FIG5, the first transistor and the second transistor are NMOS transistors, the source S1 of the first transistor M1 and the source S2 of the second transistor M2 are both coupled to the ground terminal GND, and the tap terminal Q2 of the second inductor L2 is used to couple to the power supply terminal VDD.

[0077] In another possible embodiment, as shown in FIG6, the first transistor M1 and the second transistor M2 are PMOS transistors. The source S1 of the first transistor M1 and the source S2 of the second transistor M2 are both coupled to the power supply terminal VDD, and the tap terminal Q2 of the second inductor L2 is used to be coupled to the ground terminal GND.

[0078] Since the working principle of the oscillator shown in Figure 5 is similar to that of the oscillator shown in Figure 6, the working process of the oscillator will be explained below using Figure 5 as an example.

[0079] During operation, the first inductor L1, the second inductor L2, the third inductor L3, and the adjustable capacitor Cs1 form a resonant cavity that generates a resonant frequency. Under ideal conditions (i.e., when a stable resonance is generated in the resonant cavity), this resonant frequency is the oscillation frequency of the LC oscillator formed by the first inductor L1, the second inductor L2, the third inductor L3, and the adjustable capacitor Cs1. This resonant cavity is connected in parallel with the negative resistance formed by the active first transistor M1 and the second transistor M2 to supplement the energy consumed by the resonant cavity due to resonance, so that the oscillator generates a stable and continuous resonance.

[0080] In the above embodiment, the oscillator includes a first transistor M1, a second transistor M2, a first inductor L1, a second inductor L2, and a third inductor L3. Compared with the negative resistance oscillator shown in FIG1, the number of transistors is reduced, and the phase noise of the oscillator is lowered. On the other hand, the number of inductors is increased. Since the inductors have a filtering effect, the quality of the oscillator output signal is improved. The phase noise of the oscillator with this structure is lower than that of the oscillator shown in FIG1, thus improving the performance of the oscillator.

[0081] In one possible embodiment, the oscillator further includes a first set of switches and a second set of switches. The first set of switches includes a first switch I1 and a second switch I2, and the second set of switches includes a third switch I3 and a fourth switch I4. The specific structure of the oscillator will be described below with reference to Figures 7 and 8.

[0082] In one possible embodiment, the structure of the oscillator in Figure 5 is shown in Figure 7. The first switch I1 is coupled between the third node P3 and the drain D2 of the second transistor M2. One end of the first switch I1 and the drain D2 of the second transistor M2 are coupled to the fifth node P5. The second switch I2 is coupled between the fourth node P4 and the drain D1 of the first transistor M1. One end of the second switch I2 and the drain D1 of the first transistor M1 are coupled to the sixth node P6. The third switch I3 is coupled between the first node P1 and the fifth node P5. The fourth switch I4 is coupled between the second node P2 and the sixth node P6.

[0083] The working principle of the oscillator shown in Figure 7 is similar to that of the oscillator shown in Figure 5, and will not be repeated here. The working process of the oscillator shown in Figure 7 will be explained below.

[0084] In a first possible embodiment: when the first set of switches is open (i.e., the first switch I1 and the second switch I2 are open respectively) and the second set of switches is closed (i.e., the third switch I3 and the fourth switch I4 are closed respectively), the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are coupled to the first node P1 and the second node P2 respectively, and the drain D1 of the first transistor M1 and the drain D2 of the second transistor M2 are coupled to the fourth node P4 and the third node P3 respectively.

[0085] At this time, the first transistor M1 and the second transistor M2 are in the first operating state. At this time, the first transistor M1 and the second transistor M2 are equivalent to a Class B power amplifier. The first state can also be called the Class B state. This oscillator has lower power consumption and higher phase noise compared to the oscillator provided in the second possible embodiment below, in which the oscillator is in a low power consumption state.

[0086] In the second possible embodiment: when the first set of switches is closed (i.e., the first switch I1 and the second switch I2 are closed respectively) and the second set of switches is open (i.e., the third switch I3 and the fourth switch I4 are open respectively), the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are coupled to the first node P1 and the second node P2 respectively, that is, the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are coupled to one end of the first inductor L1 and the other end of the third inductor L3 respectively. The drain D1 of the first transistor M1 and the drain D2 of the second transistor M2 are coupled to the fourth node P4 and the third node P3 respectively, that is, the drain D1 of the first transistor M1 and the drain D2 of the second transistor M2 are coupled to the two ends of the second inductor L2 respectively.

[0087] Due to the principle of inductive voltage division, the voltages of the gate G1 and drain D1 of the first transistor M1 are different, as are the voltages of the gate G2 and drain D2 of the second transistor M2. This shapes the voltage waveform. Theoretical research is conducted based on the impulse sensitivity function (ISF) of the phase noise conversion mechanism. By changing the phase noise conversion mechanism through circuit structure, the phase noise in the transistor is reduced, while the conversion time from device noise to phase noise within one frequency cycle is also reduced. The first transistor M1 and the second transistor M2 operate in the second operating state. At this time, the oscillator has lower phase noise performance and higher power consumption compared to the oscillator provided in the first possible embodiment. In this embodiment, the oscillator is in a low phase noise state (i.e., a high performance state).

[0088] The first operating state and the second operating state are different. For example, in the second possible embodiment, the first transistor M1 and the second transistor M2 are equivalent to a Class A power amplifier, and the second state can also be called the Class A state. Alternatively, the first transistor M1 and the second transistor M2 are equivalent to a Class C power amplifier, and the second state can also be called the Class C state. The comparison of the embodiments in this application does not make specific limitations.

[0089] In the above embodiments, by closing or opening different switches, the oscillator can operate in different states. For example, when the first set of switches is opened and the second set of switches is closed, the oscillator is in a low-power state, which reduces the power consumption of the oscillator compared to the second possible embodiment and meets the requirements of low-power scenarios. Alternatively, when the first set of switches is closed and the second set of switches is opened, the oscillator is in a low-phase-noise state, which reduces the phase noise of the oscillator compared to the first possible embodiment, meets the requirements of low-phase-noise scenarios, and improves the performance and utilization of the oscillator.

[0090] In one possible embodiment, the structure of the oscillator in Figure 6 is shown in Figure 8. The coupling relationship between the first group of switches and the second group of switches in Figure 8 is the same as that between the first group of switches and the second group of switches in the oscillator shown in Figure 7. The working process of the oscillator shown in Figure 8 is similar to that of the oscillator shown in Figure 7. The working principle of the oscillator shown in Figure 8 is similar to that of the oscillator shown in Figure 5, and will not be described again here.

[0091] Optionally, the differential amplifier 501 may also include more transistors. For example, the differential amplifier 501 may also include a third transistor and a fourth transistor. The following will describe the cases in which the differential amplifier 501 includes different numbers of transistors.

[0092] In one possible embodiment, referring to FIG8 and as shown in FIG9, the differential amplifier 501 further includes a third transistor M3 and a fourth transistor M4. The gate G3 of the third transistor M3 is coupled to the first node P1, the gate G4 of the fourth transistor M4 is coupled to the second node P2, the drain D3 of the third transistor M3 is coupled to the drain D1 of the first transistor M1, the drain D4 of the fourth transistor M4 is coupled to the drain D2 of the second transistor M2, and the source S3 of the third transistor M3 and the source S4 of the fourth transistor M4 are respectively coupled to GND.

[0093] In this embodiment, the tap of the second inductor L2 is in a floating state, meaning that the tap of the second inductor L2 is not coupled to the power supply terminal VDD and not coupled to the ground terminal GND. Because the tap of the second inductor L2 is in a floating state, it is not shown in Figure 9.

[0094] In this figure, the third transistor M3 and the fourth transistor M4 are transistors of the same type, while the first transistor M1 is a transistor of a different type than the third transistor M3 and the fourth transistor M4. For example, when the first transistor M1 is an NMOS transistor, the third transistor M3 and the fourth transistor M4 are both PMOS transistors, and when the first transistor M1 is a PMOS transistor, the third transistor M3 and the fourth transistor M4 are both NMOS transistors. Figure 9 illustrates an example where the first transistor M1 and the second transistor M2 are PMOS transistors, and the third transistor M3 and the fourth transistor M4 are NMOS transistors.

[0095] Optionally, the differential amplifier 501 provided in this embodiment may further include a fifth transistor and a sixth transistor, or even more transistors. When it includes a fifth transistor and a sixth transistor, or even more transistors, the coupling method of the transistors is similar to the coupling method of the transistors shown in FIG9, and will not be described again here. The structural layout corresponding to the oscillator shown in FIG9 is shown in FIG10. The adjustable capacitor Cs1 is not shown in FIG10.

[0096] When the differential amplifier 501 includes different numbers of transistors, the number of negative resistors used to provide the energy consumed by the oscillation is different. The working principle of the oscillator shown in Figure 9 will be explained below.

[0097] During operation, the first inductor L1, the second inductor L2, the third inductor L3, and the adjustable capacitor Cs1 form a resonant cavity, generating a resonant frequency. Ideally (i.e., when a stable resonance is achieved within the cavity), this resonant frequency is the oscillation frequency of the LC oscillator formed by the first inductor L1, the second inductor L2, the third inductor L3, and the adjustable capacitor Cs1. This resonant cavity is connected in parallel with the negative resistor formed by the active first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 to compensate for the energy consumed by the resonant cavity due to resonance, thus enabling the oscillator to produce a stable and continuous resonance. The more transistors included in the oscillator, the more negative resistors are used to provide energy to the LC oscillation circuit, and the more energy is provided.

[0098] In this embodiment, different switches are switched according to actual needs, so that the oscillator operates in a low-power state or a low-phase-noise state, to meet different scenario requirements and improve the utilization rate of the oscillator.

[0099] Because the group switches (including the first group of switches and the second group of switches) included in the oscillator can be connected to different positions of the inductors (including the first inductor L1, the second inductor L2, and the third inductor L3), the phase noise and power consumption of the oscillator are different when the group switches (including the first group of switches and the second group of switches) are connected to different positions. This will be explained below with reference to Figure 11.

[0100] In one possible embodiment, referring to FIG10, as shown in FIG11, the first switch I1 is coupled between the third node P3 and the drain D2 of the second transistor M2; one end of the first switch I1 and the drain D2 of the second transistor M2 are coupled to the fifth node P5; the second switch I2 is coupled between the fourth node P4 and the drain D1 of the first transistor M1; one end of the second switch I2 and the drain D1 of the first transistor M1 are coupled to the sixth node P6; one end of the third switch I3 is coupled to the fifth node P5; the other end of the third switch I3 is coupled to the first inductor L1; one end of the fourth switch I4 is coupled to the sixth node P6; the other end of the fourth switch I4 is coupled to the third inductor L3. The adjustable capacitor Cs1 is not shown in FIG11.

[0101] The other end of the third switch I3 can be coupled to any point of the first inductor L1, for example, the other end of the third switch I3 can be coupled to the midpoint of the first inductor L1. The other end of the fourth switch I4 can be coupled to any point of the third inductor L3, or the other end of the fourth switch I4 can be coupled to the midpoint of the third inductor L3. This application does not impose specific limitations on this comparison. Figure 11 shows an example where the third switch I3 and the fourth switch I4 are coupled to the midpoints of the first inductor L1 and the third inductor L3, respectively.

[0102] The working principle of the oscillator shown in Figure 11 is similar to that of the oscillator shown in Figure 9, and will not be described again here.

[0103] The working process of the oscillator shown in Figure 11 will be explained below.

[0104] In a first possible embodiment, when the first set of switches is closed and the second set of switches is open, the phase noise of the oscillator is the first phase noise.

[0105] In a second possible embodiment, when the first set of switches is open and the second set of switches is closed, the phase noise of the oscillator is the third phase noise, and the first phase noise is greater than the third phase noise.

[0106] In this embodiment, the third and fourth switches in the second set of switches can be connected to different positions of the first and third inductors, respectively. Since the phase noise of the oscillator is different when the inductors are connected to different positions, the phase noise of the oscillator can be adjusted by the connection position of the switches during the design phase, and the final connection position can be selected according to the actual phase noise requirements.

[0107] Optionally, the oscillator may include more sets of switches. For example, the oscillator may include a third set of switches or even more sets of switches. When the oscillator includes more sets of switches, switching different switches can make the oscillator operate in a low-power state or a different phase noise state.

[0108] In one possible embodiment, referring to FIG10 and as shown in FIG12, the oscillator further includes a third set of switches, which includes a fifth switch I5 and a sixth switch I6. One end of the fifth switch I5 is coupled to the fifth node P5, and the other end of the fifth switch I5 is coupled to the first inductor L1. One end of the sixth switch I6 is coupled to the sixth node P6, and the other end of the sixth switch I6 is coupled to the third inductor L3.

[0109] The other end of the fifth switch I5 can be coupled to any point of the first inductor L1, for example, the other end of the fifth switch I5 can be coupled to the midpoint of the first inductor L1. Similarly, the other end of the sixth switch I6 can be coupled to any point of the third inductor L3, for example, the other end of the sixth switch I6 can be coupled to the midpoint of the third inductor L3. This application does not impose specific limitations on these connections. Figure 10 illustrates this with examples where the fifth switch I5 and the sixth switch I6 are coupled to the midpoints of the first inductor L1 and the third inductor L3, respectively.

[0110] The working process of the oscillator shown in Figure 12 will be explained below.

[0111] In the first possible embodiment, when the first set of switches and the third set of switches are open and the second set of switches is closed, the oscillator is in a low-power state, that is, the power consumption of the oscillator is lower than the power consumption of the oscillator in the following two possible embodiments in Figure 12.

[0112] In a second possible embodiment, when the first set of switches is closed and the second and third sets of switches are open respectively, the oscillator is in a first phase noise state.

[0113] In a third possible embodiment, when the third set of switches is closed and the first set of switches and the second set of switches are respectively open, the oscillator is in a second phase noise state, and the first phase noise is less than the second phase noise.

[0114] In this embodiment, closing or opening different groups of switches allows the oscillator to be in a low-power state or a different phase noise state, thus meeting the requirements for low power consumption and different phase noise.

[0115] For example, Figure 13 is a structural layout of another oscillator provided in an embodiment of this application. The oscillator includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first inductor L1, a second inductor L2, a third inductor L3, an adjustable capacitor Cs1, and a shielding ring 120. The oscillator is located within the shielding ring 120, which includes the fourth inductor L4 and a seventh switch I7. The first and second ends of the fourth inductor L4 are coupled to the first and second ends of the seventh switch I7, respectively. The adjustable capacitor Cs1 is not shown in Figure 13.

[0116] The coupling relationships between the aforementioned devices are similar to those of the transistors (including the first transistor M1 to the fourth transistor M4), inductors (including the first inductor L1 to the third inductor L3), and adjustable capacitor Cs1 in the oscillator shown in Figure 7, and will not be described again here. The operating principle of the oscillator shown in Figure 13 is similar to that of the oscillator shown in Figure 7.

[0117] In this embodiment, when the seventh switch I7 is closed, the shielding ring is used to shield the interference of external signals, protect the oscillator from interference by other signals, and improve the anti-interference capability of the oscillator.

[0118] Optionally, referring to Figure 13 and as shown in Figure 14, the shielding ring 120 further includes: at least one capacitor C; at least one capacitor C is connected in series between the first end of the fourth inductor L4 and one end of the seventh switch I7. Figure 14 illustrates an example where at least one capacitor C includes two first capacitors C1 and a second capacitor C2. The fourth inductor L4 and the two metal layers of the first inductor L1, second inductor L2, and third inductor L3 can be on the same layer or different layers; this application does not specifically limit this.

[0119] In this embodiment, at least one capacitor C can be used to form a resonant cavity with the first inductor L1, the second inductor L2 / the third inductor L3 and the adjustable capacitor Cs1. By connecting at least one capacitor of different numbers, the fourth inductor L4 generates induced currents of different magnitudes and magnetic fields of different intensities, thereby changing the inductance value of the oscillator and achieving a wide frequency coverage range. Furthermore, a metal ring is covered on the inductors (including the first inductor L1, the second inductor L2 and the third inductor L3) to protect the inductors from interference from other interference signals.

[0120] In one possible embodiment, as shown in FIG15, the oscillator includes a shielding ring 120, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first inductor L1, a second inductor L2, and a third inductor L3 connected in series between a first node P1 and a second node P2. The gate G1 of the first transistor M1 and the gate G3 of the third transistor M3 are both coupled to the first node P1, the gate G2 of the second transistor M2 and the gate G4 of the fourth transistor M4 are both coupled to the second node P2, the source S1 of the first transistor M1 and the source S2 of the second transistor M2 are both coupled to VDD, the source S2 of the second transistor M2 and the source S4 of the fourth transistor M4 are both coupled to GND, the drain D1 of the first transistor M1 and the drain D3 of the third transistor M3 are both coupled to the fourth node P4, and the drain D2 of the second transistor M2 and the drain D4 of the fourth transistor M4 are both coupled to the third node P3. The adjustable capacitor Cs1 is not shown in FIG15.

[0121] In this embodiment, the gate G1 of the first transistor M1 and the gate G3 of the third transistor M3 are both coupled to the first node P1. The drain D1 of the first transistor M1 and the drain D2 of the third transistor M2 are both coupled to the fourth node P4. Due to the principle of inductor voltage division, the voltages of the gate G1 and drain D1 of the first transistor M1 are different, as are the voltages of the gate G2 and drain D2 of the second transistor M2. Similarly, the voltages of the gate G2 and drain D2 of the second transistor M2 are different, as are the voltages of the gate G4 and drain D4 of the fourth transistor M4. At this time, the first transistor M1 to the fourth transistor M4 are in the second operating state. In the second operating state, the oscillator has low phase noise, that is, the oscillator is in the phase noise state (i.e., high performance state).

[0122] In one possible embodiment, the oscillator includes multiple adjustable capacitors, which are sequentially coupled in series between the first node P1 and the second node P2. For example, referring to Figure 9, Figure 16 shows an oscillator comprising four transistors (transistors M1 to M4), two adjustable capacitors (adjustable capacitors Cs1 and Cs12), three inductors (first inductor L1 to third inductor L3), two sets of switches (first set of switches and second set of switches), and a shielding ring 120. The shielding ring 120 includes a first capacitor C1, a second capacitor C2, a seventh switch I7, and a fourth inductor L4. The fourth inductor L4 is not shown in Figure 16.

[0123] In this configuration, adjustable capacitors Cs1 and Cs12 are connected in series between the first node P1 and the second node P2. The first capacitor C1, the second capacitor C2, and the seventh switch I7 are also connected in series between the first node P1 and the second node P2. The coupling relationships of other components are shown in Figure 9 above. The structural layout of the oscillator shown in Figure 16 is shown in Figure 17. Adjustable capacitors Cs1 and Cs12 are not shown in Figure 17.

[0124] In this embodiment, three inductors (first inductor L1 to third inductor L3), two adjustable capacitors (adjustable capacitor Cs1 and adjustable capacitor Cs12), first capacitor C1 and second capacitor C2 form an LC resonant circuit, and four transistors (transistors M1 to M4) provide power to the LC resonant circuit.

[0125] During operation, the oscillator operates in a low-power state when the first set of switches is closed and the second set of switches is open; and in a low-phase-noise mode when the first set of switches is open and the second set of switches is closed.

[0126] In this embodiment, switching different switches allows the oscillator to operate in different modes to meet different needs; the shielding ring 120 protects the inductor from interference from other interference signals; by connecting different switched capacitors in the shielding ring, the fourth inductor L4 generates different induced currents and magnetic fields of different intensities, thereby changing the inductance value of the oscillator; and by combining this with the change in the adjustable capacitor, a wide frequency coverage range can be achieved.

[0127] The oscillator shown in Figure 17 was simulated, with the oscillator operating in low-power mode and low-phase-noise mode, respectively. The simulation results are shown in Tables 1 and 2.

[0128] Table 1

[0129] Table 2

[0130] Wherein, frequency is the oscillation frequency of the oscillator, current is the current flowing through the oscillator under different operating conditions, voltage is the power supply voltage received by the gate G1 of the first crystal M1 and the gate G2 of the second crystal M2, and PN@10K to PN@100M represent the power used to measure the phase noise of the oscillator.

[0131] As shown in Table 1, under both low-power and low-phase-noise conditions, the gate voltages G1 of the first crystal M1 and G2 of the second crystal M2 are essentially the same, around 1.2V. The oscillator frequency changes very little. However, the current in the oscillator is 5.2mA under low-power conditions and 10mA under low-phase-noise conditions, indicating a smaller current in the low-power state compared to the low-phase-noise state. The phase noise of the oscillator varies depending on the measurement power; the higher the measurement power, the lower the phase noise. However, at the same measurement power, for example, PN@100K, the phase noise of the oscillator is -89 in the low-power state and -94.3 in the low-phase-noise state, showing a smaller phase noise in the low-power state compared to the low-phase-noise state.

[0132] In Table 2, SW represents the number of switched capacitors connected to the oscillator. SW=0 means that the number of switched capacitors connected to the oscillator is 0, SW=1 means that the number of switched capacitors connected to the oscillator is 1, SW=2 means that the number of switched capacitors connected to the oscillator is 2, and SW=3 means that the number of switched capacitors connected to the oscillator is 3.

[0133] Table 2 shows that the oscillator frequency varies with the number of connected switched capacitors. A higher number of connected switched capacitors results in a higher oscillator frequency, a larger current in the oscillator, and a lower power supply voltage received by the gate G1 of the first crystal M1 and the gate G2 of the second crystal M2. However, at the same measurement power, a higher number of connected switched capacitors leads to higher oscillator phase noise. With a fixed number of switches, the phase noise of the oscillator varies at different measurement power levels; the higher the measurement power, the lower the oscillator phase noise.

[0134] In one possible embodiment, referring to Figure 17 above and as shown in Figure 18, the oscillator further includes a third set of switches, which includes a fifth switch I5 and a sixth switch I6. One end of the fifth switch I5 is coupled to the fifth node P5, and the other end of the fifth switch I5 is coupled to the first inductor L1. One end of the sixth switch I6 is coupled to the sixth node P6, and the other end of the sixth switch I6 is coupled to the third inductor L3.

[0135] The oscillator provided in this embodiment includes: an adjustable capacitor, a first transistor, a second transistor, a first inductor, a second inductor, and a third inductor; the first inductor, the second inductor, and the third inductor are connected in series between a first node and a second node, the first inductor and the second inductor are coupled to a third node, the second inductor and the third inductor are coupled to a fourth node, the adjustable capacitor is coupled between the first node and the second node, the gate of the first transistor and the gate of the second transistor are coupled to the first node and the second node respectively, the drain of the first transistor and the drain of the second transistor are coupled to the second node and the first node respectively; the other drain of the first transistor and the other drain of the second transistor are used to couple to a first voltage terminal, the tap of the second inductor is used to couple to a second voltage terminal, the first voltage terminal is one of a power supply terminal or a ground terminal, and the second voltage terminal is the other of a power supply terminal or a ground terminal. This oscillator utilizes a first transistor, a second transistor, and an adjustable capacitor to form a resonant cavity, generating a resonant frequency. Ideally (i.e., when a stable resonance is achieved within the resonant cavity), this resonant frequency is the oscillation frequency of the LC oscillator. The resonant cavity is connected in parallel with the negative resistance formed by the active first and second transistors to compensate for the energy consumed by the resonant cavity due to resonance, enabling the oscillator to generate a stable and continuous resonance. This oscillator structure includes a small number of transistors, resulting in less phase noise during oscillation, thus exhibiting low phase noise. The phase noise of the oscillator directly affects its performance, and this oscillator demonstrates good performance. Furthermore, the transistors in this oscillator structure are equivalent to Class B power amplifiers, exhibiting low power consumption when operating.

[0136] Optionally, the oscillator provided in this application embodiment can be applied to communication devices, such as the radio frequency transceiver of a communication device, to provide a stable local oscillation signal for the wireless transceiver, thereby ensuring the communication performance of the transceiver. The oscillator can also be applied to wireless terminal communication products, such as wireless mobile phone communication chips, to achieve power saving and provide superior phase noise. The oscillator can also be applied to wireless short-range communication products, such as Bluetooth and Wireless Fidelity (Wi-Fi), to achieve power saving and provide superior phase noise. The oscillator can also be applied to the clock circuit of a microprocessor to generate a stable (i.e., low-jitter) clock signal.

[0137] This application also provides a phase-locked loop (PLL) circuit, which may include a phase detector, a filter, and an oscillator, wherein the oscillator may be the oscillator shown in Figures 5 to 18. This application also provides a communication device, which may include a PLL circuit, which may include an oscillator, which may be the oscillator shown in Figures 5 to 18.

[0138] In one possible embodiment, the communication device may include a radio frequency transceiver, which integrates a mixer and a phase-locked loop (PLL) circuit. The PLL circuit provides a local oscillation signal to the mixer. It should be noted that the relevant description of the oscillator can be found above, and will not be repeated here.

[0139] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An oscillator characterized by, Comprising: a tunable capacitor, a differential amplifier and an inductive element; the inductive element comprises a first inductor, a second inductor and a third inductor; one end of the first inductor is coupled to a first node, one end of the third inductor is coupled to a second node, the other end of the first inductor and one end of the second inductor are coupled to a third node, the other end of the second inductor and the other end of the third inductor are coupled to a fourth node, the tunable capacitor is coupled between the first node and the second node; the differential amplifier comprises a differential first input and a differential second input, and a differential first output and a differential second output, the first input and the second output are both coupled to the first node, the second input and the first output are both coupled to the second node; the second inductor further comprises a tap end, the tap end is used to be coupled to a power supply end or a ground end.

2. The oscillator of claim 1, wherein the differential amplifier comprises a first transistor and a second transistor; the gate of the first transistor is the first input, the drain of the first transistor is the first output, the gate of the second transistor is the second input, and the drain of the second transistor is the second output.

3. The oscillator of claim 2, wherein: when the first transistor and the second transistor are NMOS transistors, the source of the first transistor and the source of the second transistor are both coupled to a ground end, and the tap end is used to be coupled to a power supply end.

4. The oscillator of claim 2, wherein: when the first transistor and the second transistor are PMOS transistors, the source of the first transistor and the source of the second transistor are both coupled to a power supply end, and the tap end is used to be coupled to a ground end.

5. The oscillator of any of claims 2-4, wherein, the differential amplifier further comprises a third transistor and a fourth transistor, the gate of the third transistor is coupled to the first node, the gate of the fourth transistor is coupled to the second node, the drain of the third transistor is coupled to the drain of the first transistor, and the drain of the fourth transistor is coupled to the drain of the second transistor.

6. The oscillator of any of claims 2-5, wherein, the oscillator further comprises a first group of switches and a second group of switches, the first group of switches comprises a first switch and a second switch, and the second group of switches comprises a third switch and a fourth switch; the first switch is coupled between the third node and the drain of the second transistor, one end of the first switch and the drain of the second transistor are coupled to a fifth node, the second switch is coupled between the fourth node and the drain of the first transistor, one end of the second switch and the drain of the first transistor are coupled to a sixth node, the third switch is coupled between the first node and the fifth node, and the fourth switch is coupled between the second node and the sixth node.

7. The oscillator of claim 6, wherein: when the first group of switches is turned off and the second group of switches is turned on, the oscillator is in a low power consumption state; when the first group of switches is turned on and the second group of switches is turned off, the oscillator is in a low phase noise state.

8. The oscillator of claim 6 or 7, wherein The oscillator further comprises a third group of switches, the third group of switches comprising a fifth switch and a sixth switch; one end of the fifth switch is coupled to the fifth node, the other end of the fifth switch is coupled to the first inductor, one end of the sixth switch is coupled to the sixth node, the other end of the sixth switch is coupled to the third inductor.

9. The oscillator of claim 8, wherein, when the first group of switches and the third group of switches are respectively turned off, and the second group of switches is turned on, the oscillator is in a low power consumption state; when the first group of switches is turned on, and the second group of switches and the third group of switches are respectively turned off, the oscillator is in a first phase noise state; when the third group of switches is turned on, and the first group of switches and the second group of switches are respectively turned off, the oscillator is in a second phase noise state, the first phase noise is less than the second phase noise.

10. The oscillator of any of claims 2-5, wherein, The oscillator further comprises a first group of switches and a second group of switches, the first group of switches comprising a first switch and a second switch, the second group of switches comprising a third switch and a fourth switch; the first switch is coupled between the third node and the drain of the second transistor, one end of the first switch and the drain of the second transistor are coupled to a fifth node, the second switch is coupled between the fourth node and the drain of the first transistor, one end of the second switch and the drain of the first transistor are coupled to a sixth node, one end of the third switch is coupled to the fifth node, the other end of the third switch is coupled to the first inductor, one end of the fourth switch is coupled to the sixth node, the other end of the fourth switch is coupled to the third inductor.

11. The oscillator of claim 10, wherein, when the first group of switches is turned on, and the second group of switches is turned off, the phase noise of the oscillator is a first phase noise; when the first group of switches is turned off, and the second group of switches is turned on, the phase noise of the oscillator is a third phase noise, the first phase noise is greater than the third phase noise.

12. The oscillator of any of claims 1-11, wherein, The oscillator further comprises a shield ring, the oscillator is located in the shield ring; the shield ring comprises a fourth inductor and a seventh switch, the first end and the second end of the fourth inductor are coupled to the first end and the second end of the seventh switch respectively.

13. The oscillator of claim 12, wherein, The shield ring further comprises at least one capacitor; the at least one capacitor is coupled in series between the first end of the fourth inductor and one end of the seventh switch.

14. The oscillator of any of claims 1-13, wherein, The oscillator comprises a plurality of the adjustable capacitors, the plurality of the adjustable capacitors are coupled in series between the first node and the second node.

15. A phase-locked loop circuit, characterized by comprising: comprising: a phase detector, a filter and an oscillator, the oscillator is the oscillator of any one of claims 1-14, the phase detector is used to obtain a phase difference signal and convert the phase difference signal into a voltage signal, the filter is used to filter the voltage signal, the oscillator is used to output a local oscillation signal according to the filtered voltage signal.

16. A communications device, characterized by The communication device comprises a radio frequency transceiver, in which a mixer and a phase-locked loop circuit as claimed in claim 15 are integrated, the phase-locked loop circuit being used to provide a local oscillation signal for the mixer.

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