Chip verification method and apparatus, device and medium

Abstract

The present disclosure relates to the technical field of computers, and in particular to the technical field of chip verification, and provides a chip verification method and apparatus, a device and a medium. An implementation solution comprises: determining a first dependency relationship between a plurality of processing cores of a chip; in response to determining that a random instruction is to be added to a first processing core, using a random instruction generator to generate a first newly added instruction, comprising: in response to determining that there is at least one first dependent core among the plurality of processing cores that is dependent on the first processing core, determining a constraint condition for the random instruction generator, such that a random instruction generation result of the random instruction generator does not depend on an instruction corresponding to the at least one first dependent core, and running the random instruction generator on the basis of the constraint condition, so as to generate the first newly added instruction; and using the chip to execute a plurality of initial instructions and the first newly added instruction, so as to determine a chip verification result.

Description

Chip verification method and device, equipment and medium

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410998995.9, filed on July 24, 2024, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the field of computer technology, in particular to the field of chip verification, and specifically to a chip verification method, device, electronic device, computer readable storage medium and computer program product. BACKGROUND

[0004] Artificial intelligence is a discipline that studies enabling computers to simulate some thinking processes and intelligent behaviors of humans (such as learning, reasoning, thinking, planning, etc.), which has both hardware and software technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing, etc.; artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, and machine learning / deep learning, big data processing technology, knowledge graph technology, etc.

[0005] In order to adapt to the development of artificial intelligence technology, the scale and process of chips for executing artificial intelligence-based algorithms are further improved, and more accurate and efficient chip verification technologies are needed.

[0006] The methods described in this section can not necessarily be the methods previously conceived or employed. Unless otherwise indicated, nothing in this section should be assumed to be prior art merely because of its inclusion in this section. Similarly, unless otherwise indicated, matters discussed in this section should not be assumed to be prior to their mention in this section. SUMMARY

[0007] The present disclosure provides a chip verification method, device, electronic device, computer readable storage medium and computer program product.

[0008] According to an aspect of the present disclosure, a chip verification method is provided, wherein the chip comprises a plurality of processing cores, and the method comprises: determining a first dependency relationship between the plurality of processing cores, wherein the first dependency relationship is determined based on a second dependency relationship between a plurality of initial instructions and a correspondence relationship between the plurality of initial instructions and the plurality of processing cores; in response to determining that a random instruction is to be added for a first processing core of the plurality of processing cores, generating a first added instruction by using a random instruction generator, wherein the generation process of the first added instruction comprises: in response to determining that the first dependency relationship indicates that there is at least one first dependent core dependent on the first processing core among the plurality of processing cores, determining a constraint condition for the random instruction generator, wherein according to the constraint condition, a random instruction generation result of the random instruction generator is independent of an instruction corresponding to the at least one first dependent core; and generating the first added instruction by running the random instruction generator based on the constraint condition; and determining a verification result for the chip by executing the plurality of initial instructions and the first added instruction by using the chip.

[0009] According to another aspect of the present disclosure, a chip verification apparatus is provided, wherein the chip comprises a plurality of processing cores, and the apparatus comprises: a first determination unit configured to determine a first dependency relationship between the plurality of processing cores, wherein the first dependency relationship is determined based on a second dependency relationship between a plurality of initial instructions and a correspondence relationship between the plurality of initial instructions and the plurality of processing cores; a generation unit configured to, in response to determining that a random instruction is to be added for a first processing core of the plurality of processing cores, generate a first added instruction by using a random instruction generator, wherein the generation unit comprises: a determination sub-unit configured to, in response to determining that the first dependency relationship indicates that there is at least one first dependent core dependent on the first processing core among the plurality of processing cores, determine a constraint condition for the random instruction generator, wherein according to the constraint condition, a random instruction generation result of the random instruction generator is independent of an instruction corresponding to the at least one first dependent core; and a generation sub-unit configured to generate the first added instruction by running the random instruction generator based on the constraint condition; and a verification unit configured to determine a verification result for the chip by executing the plurality of initial instructions and the first added instruction by using the chip.

[0010] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned chip verification method.

[0011] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the chip verification method.

[0012] According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, is capable of implementing the chip verification method.

[0013] According to one or more embodiments of the present disclosure, the chip verification efficiency can be improved, and more comprehensive chip verification can be achieved.

[0014] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments and together with the description serve to explain exemplary implementations of the application. The illustrated embodiments are exemplary only and not limiting of the scope of the application. In all the drawings, like reference numerals refer to like parts throughout the several views.

[0016] FIG. 1 shows a schematic diagram of an exemplary system in which various methods described herein can be implemented, according to an exemplary embodiment of the present disclosure;

[0017] FIG. 2 shows a flowchart of a chip verification method, according to an exemplary embodiment of the present disclosure;

[0018] FIG. 3 shows a schematic diagram of an instruction generation process, according to an exemplary embodiment of the present disclosure;

[0019] FIG. 4 shows a schematic diagram of a solving process of a first dependency relationship, according to an exemplary embodiment of the present disclosure;

[0020] FIG. 5 shows a structural block diagram of a chip verification apparatus, according to an exemplary embodiment of the present disclosure;

[0021] FIG. 6 shows a structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the present disclosure are described herein below with reference to the accompanying drawings, in which various specific details are set forth to assist in understanding the present disclosure. It will be apparent, however, to one of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0023] In the present disclosure, the terms "first", "second", and the like are used to describe various elements only for the purpose of distinguishing one element from another, and do not intend to limit the positions, sequence, or importance of the elements. In some examples, a first element and a second element can refer to the same instance of the element, and in some cases, they can refer to different instances of the element based on the context of the description.

[0024] The terms used in the description of various described examples in the present disclosure are only for the purpose of describing particular examples and are not intended to be limiting. Unless specifically defined otherwise, an element that is a singular can be plural and vice versa. Also, the term "and / or" used in the present disclosure encompasses any and all possible combinations of the listed items.

[0025] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0026] FIG. 1 illustrates a schematic diagram of an example system 100 in which various methods and apparatuses described herein can be implemented according to embodiments of the present disclosure. Referring to FIG. 1, the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 can be configured to execute one or more application programs.

[0027] In embodiments of the present disclosure, the server 120 can run one or more services or software applications that enable the execution of a chip verification method.

[0028] In certain embodiments, the server 120 can also provide other services or software applications, which can include non-virtual and virtual environments. In certain embodiments, these services can be provided as web-based services or cloud services, for example, to users of the client devices 101, 102, 103, 104, 105, and / or 106 under a software as a service (SaaS) model.

[0029] In the configuration shown in FIG. 1, server 120 can include one or more components that implement functionality performed by server 120. These components can include software components that are executable by one or more processors, hardware components, or combinations thereof. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can in turn utilize one or more client applications to interact with server 120 to utilize services provided by these components. It should be understood that various different system configurations are possible, which can differ from system 100. Thus, FIG. 1 is one example of a system for implementing the various methods described herein and is not intended to be limiting.

[0030] A user can use client device 101, 102, 103, 104, 105, and / or 106 to send a verification request. The client device can provide an interface that enables a user of the client device to interact with the client device. The client device can also output information to the user via the interface. Although FIG. 1 only depicts six client devices, one of skill in the art will appreciate that the present disclosure can support any number of client devices.

[0031] Client devices 101, 102, 103, 104, 105, and / or 106 can include various categories of computer devices, such as portable handheld devices, general purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service kiosk devices, service robots, gaming systems, thin clients, various messaging devices, sensors or other sensing devices, and the like. These computer devices can run various categories and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, Linux, or Linux-like operating systems (such as GOOGLE Chrome OS); or include various mobile operating systems, such as MICROSOFT Windows Mobile OS, iOS, Windows Phone, Android. Portable handheld devices can include cellular telephones, smartphones, tablet computers, personal digital assistants (PDAs), and the like. Wearable devices can include head-mounted displays (such as smart glasses) and other devices. Gaming systems can include various handheld gaming devices, Internet-enabled gaming devices, and the like. The client devices are capable of executing various different applications, such as various Internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and can use various communication protocols.

[0032] Network 110 can be any sort of network known to those skilled in the art, which can support data communications using any of a variety of available protocols, including without limitation TCP / IP, SNA, IPX, etc. By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0033] Server 120 can include one or more general purpose computers, special purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other appropriate arrangement and / or combination. Server 120 can include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 can run one or more services or software applications that provide the functionality described below.

[0034] Computing units in server 120 can run one or more operating systems including any of the operating systems described above, as well as any commercially available server operating systems. Server 120 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0035] In some implementations, server 120 can include one or more applications to analyze and consolidate data feeds and / or event updates from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 can also include one or more applications to display the data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0036] In some implementations, server 120 can be a server of a distributed system, or a server incorporating blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. The cloud server is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and virtual private server (VPS, Virtual Private Server) services.

[0037] The system 100 can also include one or more databases 130. In certain embodiments, these databases can be used to store data and other information. For example, one or more of the databases 130 can be used to store information such as audio files and video files. The databases 130 can reside at various locations. For example, databases used by the server 120 can be local to the server 120 or can be remote from the server 120 and can communicate with the server 120 via a network-based or dedicated connection. The databases 130 can be of different categories. In certain embodiments, databases used by the server 120 can be, for example, relational databases. One or more of these databases can store, update, and retrieve data to and from the databases in response to commands.

[0038] In certain embodiments, one or more of the databases 130 can also be used by applications to store application data. Databases used by applications can be databases of different categories, such as key-value stores, object stores, or regular stores supported by file systems.

[0039] The system 100 of FIG. 1 can be configured and operated in various ways to enable the application of various methods and apparatuses described in accordance with the present disclosure.

[0040] Deep learning algorithms have been increasingly widely applied recently. Based on the requirement of deep learning algorithms for larger scale computing power, domain-specific architecture (DSA) processors applied to specific fields are developed to accelerate hardware implementation of deep learning algorithms. For example, various processing cores with corresponding functions can be implemented according to various types of operators in deep learning algorithms, such as activation operators, convolution operators, pooling operators, data transfer operators, and the like. In this case, each processing core maps a different instruction execution flow, and since there can be data dependencies between different instructions, there can be complex synchronization relationships between instruction execution flows.

[0041] In actual application scenarios, the instruction set to be verified of a chip usually contains a large number of instructions, that is, corresponds to multiple different chip functions, or corresponds to different parameters in the same function mode, such as data processing of different data scales. Understandably, it is difficult to achieve complete verification due to the high cost of traversing the instruction set to be verified of the chip. Therefore, a specific random configuration instruction is usually executed to randomly select target instructions from the instruction set to be verified to form multiple random instruction streams corresponding to multiple processing cores, so that the multiple processing cores in the chip to be verified can execute the multiple random instruction streams respectively, and the verification result of the chip is determined based on the execution result of the random instruction streams. It should be understood that when verifying a chip, the more functions of the chip to be verified, that is, the higher the randomness of the random instruction streams, the more comprehensive and reliable the verification result.

[0042] In related technologies, in order to improve the verification effect, a random instruction generator can be used to randomly generate verification stimuli of multiple instruction streams. However, generating multiple instruction streams based on complete randomness can easily lead to a deadlock ring between the instruction streams. For example, when instruction a in instruction stream A depends on instruction b in instruction stream B, and instruction c in instruction stream B depends on instruction d in instruction stream A, the dependency deadlock between the two will cause instruction stream A and instruction stream B to be unable to continue execution. To avoid the occurrence of dependency deadlock, one way is to generate verification stimuli of multiple instruction streams based on relatively simple dependency relationships. However, this greatly reduces the randomness of the verification stimuli, cannot generate verification stimuli with complex dependency relationships, that is, cannot achieve comprehensive verification, and reduces the verification efficiency.

[0043] Based on this, the present disclosure provides a verification method for a multi-core chip, first determines a first dependency relationship between multiple processing cores, when it is necessary to add a random instruction for a first processing core, generates a constraint condition for a random instruction generator based on the dependency on the first dependency relationship to constrain the random generation result, and avoid forming a dependency deadlock between the processing cores, thereby improving the generation efficiency of the verification stimuli without affecting the randomness of the verification stimuli, and further improving the verification efficiency.

[0044] FIG. 2 shows a flowchart of a chip verification method 200 according to an exemplary embodiment of the present disclosure, the chip comprising multiple processing cores. As shown in FIG. 2, the method 200 comprises:

[0045] Step S210, determining a first dependency relationship between the multiple processing cores, wherein the first dependency relationship is determined based on a second dependency relationship between multiple initial instructions and a correspondence relationship between the multiple initial instructions and the multiple processing cores;

[0046] Step S220, in response to determining that a random instruction is to be added for the first processing core of the plurality of processing cores, generating a first added instruction by using a random instruction generator, wherein the generation process of the first added instruction comprises:

[0047] Step S221, in response to determining that the first dependency relationship indicates that there is at least one first dependent core in the plurality of processing cores that depends on the first processing core, determining a constraint condition for the random instruction generator, wherein according to the constraint condition, the random instruction generation result of the random instruction generator does not depend on the instruction corresponding to the at least one first dependent core; and

[0048] Step S222, generating the first added instruction by running the random instruction generator based on the constraint condition; and

[0049] Step S230, determining a verification result for the chip by executing the plurality of initial instructions and the first added instruction by using the chip.

[0050] When verification needs to be performed on a chip containing a plurality of processing cores, by applying the above method 200, the first dependency relationship between the plurality of processing cores can be determined first, when a random instruction needs to be added for the first processing core, a constraint condition for the random instruction generator is generated based on the dependent core information that depends on the first processing core, to constrain the random generation result, to avoid the added instruction depending on the dependent core, to form a mutual dependency deadlock between the first processing core and the dependent core, thereby improving the generation efficiency of the verification stimulus without affecting the randomness of the verification stimulus, and further improving the verification efficiency.

[0051] It can be understood that the correspondence between the plurality of initial instructions and the plurality of processing cores is the correspondence between each processing core and the initial instruction stream of the processing core. For example, when the initial instruction stream of processing core A contains initial instruction a, the initial instruction stream of processing core B contains initial instruction b, and initial instruction b depends on initial instruction a, it can be determined that processing core B depends on processing core A based on this.

[0052] In some examples, the chip to be verified can be various types of chips, in particular data processing chips, such as chips for executing deep learning algorithms, voice processing chips, image processing chips, etc.

[0053] In some examples, the initial instructions and the first added instructions can be randomly selected from a pre-configured set of instructions to be verified, and the set of instructions to be verified may, for example, include data processing instructions, data transmission instructions, data read / write instructions, etc. various types to ensure that the chip to be verified can normally perform data processing, data transmission, data read / write, etc. functions.

[0054] In some examples, the first processing core can be any one of the plurality of processing cores. After determining the first added instruction for the first processing core, the corresponding steps can be repeated for other processing cores to achieve comprehensive verification of the multi-core chip.

[0055] In some examples, the determination of the verification result for the chip by executing the plurality of initial instructions and the first added instruction by the chip in step S230 can be implemented in a software or hardware based manner. For example, a hardware description language such as Verilog, VHDL (Veri-High-Speed Integrate Circuit Hardware Description Language) can be used to design and configure the chip circuit in a software environment, and after compiling to generate the chip circuit netlist information that can be used for simulation, the simulation verification of the chip circuit is performed based thereon. In some examples, the RTL (Register Transfer Level) code of the chip circuit to be verified can be obtained in a software environment to describe the data flow of the chip circuit, and thus the RTL simulation for the chip is implemented. In some examples, the corresponding code of the hardware description language can be written by using other languages (for example, C language) to generate the chip circuit netlist information that can be used for simulation. For another example, the corresponding hardware circuit can be implemented according to the hardware description language or the circuit netlist information, and the verification is performed on the hardware circuit.

[0056] According to some embodiments, the at least one dependent core is determined by: determining, based on the first dependency relationship, a processing core that each processing core of the plurality of processing cores depends on; and determining at least one first dependent core that depends on the first processing core by recursively traversing the processing core that each processing core depends on. In this way, the dependent core corresponding to each processing core can be maintained respectively, and the dependency relationship can be checked by recursive traversal, so that the dependent core can be determined more conveniently.

[0057] In some examples, the map structure can be utilized to store the dependent cores corresponding to each processing core. For example, when the processor includes processing core A, processing core B, processing core C and processing core D, it can be recorded that processing core A depends on B, C, and processing core B depends on D. In this case, recursion can be performed based on the dependent relationship corresponding to each processing core, for example, when it is determined that A depends on B and C, the dependent information of B and C can be further traversed to determine that A also indirectly depends on D. Based on this, it can be determined that the processing cores dependent on D include processing core A and processing core B, and further, the constraint condition can be determined to make the random instruction generation result for D not include instructions dependent on A and B.

[0058] According to some embodiments, the processing cores dependent on each processing core are stored in the dependent core queue corresponding to the processing core. By utilizing the queue to manage the dependent core information, the data structure can be simplified, and the chip verification can be more convenient and efficient.

[0059] In some examples, the dependent core information can also be managed based on other forms, for example, other data structures can be applied to store the dependent cores, which are not limited in the present disclosure.

[0060] In some examples, when the queue is utilized to manage the dependent core information, it can also be convenient and fast to check whether the dependent core queue corresponding to each processing core is an empty queue, and further determine whether the instruction flow corresponding to the processing core can continue to execute. When the dependent core queue is not empty, it indicates that the instruction flow corresponding to the processing core needs to wait for the trigger of other processing cores. Therefore, the execution of the instruction flow can be more conveniently and efficiently managed to ensure that the instruction execution of the multi-core chip meets the specific synchronization relationship and ensures the correctness of the instruction execution order.

[0061] In actual application scenarios, when generating a random instruction flow for a multi-core chip, the instruction generation order of multiple processing cores is usually fixed. For example, when the processor includes processing core A, processing core B, processing core C and processing core D, the conventional random excitation generation order can be to generate new instructions for each processing core in the order of A-B-C-D. It can be seen that in this case, the initial generation process of processing core A does not need to consider the dependency relationship between processing cores, which limits the randomness of the verification excitation to some extent.

[0062] Based on this, according to some embodiments, the step S220 of generating, in response to determining that a random instruction is to be added for the first processing core of the plurality of processing cores, the first newly added instruction by using a random instruction generator comprises: in response to determining that a random instruction is to be added for the first processing core, and in response to determining that a first time interval has elapsed, generating the first newly added instruction by using the random instruction generator, wherein the first time interval is randomly determined. By randomly adding a delay in the instruction generation process, the randomness of the plurality of instruction streams can be improved to achieve more comprehensive verification and improve verification efficiency.

[0063] According to some embodiments, the method 200 further comprises: in response to determining that the at least one dependent instruction executed by the first processing core is completed, updating the first dependency relationship, wherein, according to the updated first dependency relationship, the at least one first dependent core no longer depends on the first processing core. Thus, the dependency relationship can be updated in real time during the instruction execution process, the first dependency relationship between the processing cores is recursively updated after the dependent instruction (trigger instruction) is executed, and more accurate and comprehensive multi-core chip verification can be achieved based on the more accurate first dependency relationship.

[0064] According to some embodiments, the method 200 further comprises: in response to determining that a preset trigger condition is reached, causing the first processing core to execute at least one target instruction of the at least one dependent instruction; and updating the first dependency relationship based on the at least one target instruction. Thus, the dependency relationship between the processing cores can be released by actively executing the dependent instruction, the complexity of the mutual dependency between the plurality of processing cores can be avoided, the complexity of the constraint condition can be reduced, the calculation amount of the random instruction generator can be simplified, and the verification result can be easily solved.

[0065] According to some embodiments, the step of causing the first processing core to execute at least one target instruction of the at least one dependent instruction in response to determining that a preset trigger condition is reached comprises: in response to determining that randomly generated trigger information meets a preset condition, causing the first processing core to execute at least one target instruction of the at least one dependent instruction. Thus, the generation of the dependent instruction can be actively controlled by randomly triggering, and the verification efficiency can be improved by improving the randomness.

[0066] In some examples, the trigger condition for actively generating the dependent instruction and releasing the dependency relationship can also be set in other ways, for example, a fixed threshold can be set to control the generation interval of adjacent dependent instructions, or the complexity of the first dependency relationship between the plurality of processing cores can be checked and compared with a preset threshold to determine whether the dependent instruction needs to be actively generated. The specific setting manner of the trigger condition is not limited in the present disclosure.

[0067] FIG. 3 shows a schematic diagram of an instruction generation process according to an exemplary embodiment of the present disclosure. As shown in FIG. 3, the operation of each processing core to add a new random instruction can include the following steps:

[0068] Step S31, recursively query the current first dependency relationship.

[0069] Step S32, determine whether to continue to execute step S33 or steps S34-S36 based on the randomly generated trigger information.

[0070] Step S33, based on the dependency relationship, cause the processing core to execute a target instruction that is depended on by any other processing core.

[0071] Step S34, determine a constraint condition based on the result of the recursive query.

[0072] Step S35, generate a new instruction by executing a random instruction generator based on the constraint condition.

[0073] Step S36, update the first dependency relationship based on the new instruction.

[0074] FIG. 4 shows a schematic diagram of a solving process of the first dependency relationship according to an exemplary embodiment of the present disclosure. In this example, each processing core can have a corresponding core id. As shown in FIG. 4, the solving process of the first dependency relationship can include the following steps:

[0075] Step S41, determine the source core id and the target core id that are currently being checked.

[0076] Step S42, check whether the source core id exists in the corresponding dependency core queue of the target core id. If the detection result is yes, execute step S43, and if the detection result is no, execute step S44.

[0077] Step S43, determine that a dependency deadlock will be formed between the source core id and the target core id.

[0078] Step S44, update the source core id and the target core id, and take the core id in the corresponding dependency core queue of the target core id as a new target core id.

[0079] Based on step S44, step S42 can be continued to be executed to implement traversal of the first dependency relationship between all of the plurality of processing cores.

[0080] By executing the above recursive solving process, the core id information capable of forming a dependency deadlock with the source core id can be conveniently and efficiently determined, and then the constraint condition of the random instruction generator is determined based on this. By running the random instruction generator based on the constraint condition, the random instruction generation result containing instructions capable of causing a dependency deadlock can be avoided, the randomness of the verification stimulus is improved under the premise of ensuring the smooth execution of the instruction flow, so as to improve the verification effect.

[0081] According to an aspect of the present disclosure, a chip verification apparatus is also provided. FIG. 5 shows a structural block diagram of a chip verification apparatus 500 according to an exemplary embodiment of the present disclosure, the chip comprising a plurality of processing cores. As shown in FIG. 5, the apparatus 500 comprises:

[0082] A first determination unit 510 configured to determine a first dependency relationship between the plurality of processing cores, wherein the first dependency relationship is determined based on a second dependency relationship between a plurality of initial instructions and a correspondence relationship between the plurality of initial instructions and the plurality of processing cores;

[0083] A generation unit 520 configured to, in response to determining that a random instruction is to be added for a first processing core of the plurality of processing cores, generate a first added instruction by using a random instruction generator, wherein the generation unit comprises:

[0084] A determination sub-unit 521 configured to, in response to determining that the first dependency relationship indicates that there is at least one first dependent core dependent on the first processing core among the plurality of processing cores, determine a constraint condition for the random instruction generator, wherein according to the constraint condition, a random instruction generation result of the random instruction generator does not depend on an instruction corresponding to the at least one first dependent core; and

[0085] A generation sub-unit 522 configured to generate the first added instruction by running the random instruction generator based on the constraint condition; and

[0086] A verification unit 530 configured to determine a verification result for the chip by executing the plurality of initial instructions and the first added instruction by using the chip.

[0087] According to some embodiments, the at least one dependent core is determined by: determining, based on the first dependency relationship, a processing core dependent on each processing core of the plurality of processing cores; and determining, by recursively traversing the processing core dependent on each processing core, at least one first dependent core dependent on the first processing core.

[0088] According to some embodiments, the processing core dependent on each processing core is stored in a corresponding dependent core queue of the processing core.

[0089] According to some embodiments, the generating unit 520 is configured to generate the first new instruction with the random instruction generator in response to determining that a random instruction is to be added for the first processing core, and in response to determining that a first time interval has elapsed, wherein the first time interval is determined randomly.

[0090] According to some embodiments, the apparatus 500 further comprises an updating unit configured to update the first dependency relationship in response to determining that the first processing core will be dependent on at least one dependent instruction executed by the at least one first dependent core, wherein according to the updated first dependency relationship, the at least one first dependent core is no longer dependent on the first processing core.

[0091] According to some embodiments, the apparatus 500 further comprises an executing unit configured to cause the first processing core to execute at least one target instruction in the at least one dependent instruction in response to determining that a preset triggering condition is reached, and the updating unit is further configured to update the first dependency relationship based on the at least one target instruction.

[0092] According to some embodiments, the executing unit is configured to cause the first processing core to execute at least one target instruction in the at least one dependent instruction in response to determining that randomly generated triggering information meets a preset condition.

[0093] It should be understood that the operations of each unit of the chip verification apparatus 500 shown in FIG. 5 can correspond to each step in the chip verification method 200 described in FIG. 2. Therefore, the operations, features and advantages described above for the method 200 are also applicable to the apparatus 500 and each unit included therein. For the sake of brevity, certain operations, features and advantages are not described again here.

[0094] According to another aspect of the present disclosure, an electronic device is also provided, comprising at least one processor, and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip verification method described above.

[0095] According to another aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause the computer to perform the chip verification method described above.

[0096] According to another aspect of the present disclosure, a computer program product is also provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the chip verification method described above.

[0097] Referring to FIG. 6, a block diagram of an electronic device 600, which can be a server or a client of the present disclosure, will now be described, which is an example of a hardware device that can be applied to aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present disclosure described and / or claimed in this document.

[0098] As shown in FIG. 6, the device 600 includes a computing unit 601 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded into a random access memory (RAM) 603 from a storage unit 608. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0099] Various components in the device 600 are connected to the I / O interface 605, including an input unit 606, an output unit 607, a storage unit 608, and a communication unit 609. The input unit 606 can be any kind of device that can input information to the device 600, can receive inputted digital or character information, and generate key signal inputs related to user settings and / or function controls of the electronic device, and can include, but is not limited to, a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and / or a remote controller. The output unit 607 can be any kind of device that can present information, and can include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 608 can include, but is not limited to, a magnetic disk, an optical disk. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0100] The computing unit 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs various methods and processes described above, such as the chip verification method. For example, in some embodiments, the chip verification method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded onto the RAM 603 and executed by the computing unit 601, one or more steps of the chip verification method described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the chip verification method by any other suitable means, such as by means of firmware.

[0101] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0102] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0103] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0104] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0105] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

[0106] The computer system can include clients and servers. This relationship can be. The servers are typically remote from the users who use clients to interact with these servers. These clients and servers are often interconnected via communica tion networks. The relationship of client and server arises by interplay of programs in their respective computers and the concomitant con nection of the computers by a communication network. The servers can be cloud servers, servers of a distributed system, or servers incorporating blockchain.

[0107] It should be understood that the various forms of flow shown above can be re-ordered, added to, or have steps deleted, using the flow. For example, the steps recited in the disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technology disclosed in the disclosure are achieved, which is not limited herein.

[0108] Although embodiments or examples of the present disclosure have been described with reference to the drawings, it will be understood that the above-described methods, systems, and devices are merely exemplary embodiments or examples, and the scope of the present disclosure is not limited by these embodiments or examples. Various elements in the embodiments or examples can be omitted or replaced by equivalent elements thereof. In addition, each step can be performed in an order different from that described in the present disclosure. Further, various elements in the embodiments or examples can be combined in various ways. It is important that many of the elements described herein can be replaced by equivalent elements that appear after the present disclosure as technology evolves.

Claims

1. A method of chip verification, wherein, The chip comprises a plurality of processing cores, and the method comprises: determining a first dependency relationship between the plurality of processing cores, wherein the first dependency relationship is determined based on a second dependency relationship between a plurality of initial instructions and a correspondence between the plurality of initial instructions and the plurality of processing cores; in response to determining that a random instruction is to be added for a first processing core of the plurality of processing cores, generating a first added instruction by using a random instruction generator, wherein the generation process of the first added instruction comprises: in response to determining that the first dependency relationship indicates that there is at least one first dependent core in the plurality of processing cores that depends on the first processing core, determining a constraint condition for the random instruction generator, wherein according to the constraint condition, the random instruction generation result of the random instruction generator does not depend on the instruction corresponding to the at least one first dependent core; and generating the first added instruction by running the random instruction generator based on the constraint condition; and determining a verification result for the chip by executing the plurality of initial instructions and the first added instruction by using the chip.

2. The method of claim 1, wherein, The at least one dependent core is determined by: based on the first dependency relationship, determining the processing core that each processing core of the plurality of processing cores depends on; by recursively traversing the processing core that each processing core depends on, determining at least one first dependent core that depends on the first processing core.

3. The method of claim 2, wherein, The processing core that each processing core depends on is stored in the corresponding dependent core queue of the processing core.

4. The method of any one of claims 1-3, wherein, The response to determining that a random instruction is to be added for a first processing core of the plurality of processing cores, generating a first added instruction by using a random instruction generator comprises: in response to determining that a random instruction is to be added for the first processing core, and in response to determining that a first time interval has elapsed, generating the first added instruction by using the random instruction generator, wherein the first time interval is randomly determined.

5. The method of any one of claims 1-4, further comprising: in response to determining that at least one dependent instruction that the first processing core is to be depended on by the at least one first dependent core is executed, updating the first dependency relationship, wherein according to the updated first dependency relationship, the at least one first dependent core no longer depends on the first processing core.

6. The method of claim 5, further comprising: in response to determining that a preset trigger condition is reached, causing the first processing core to execute at least one target instruction of the at least one dependent instruction; and based on the at least one target instruction, updating the first dependency relationship. The response to determining that a preset trigger condition is reached, causing the first processing core to execute at least one target instruction of the at least one dependent instruction comprises:

7. The method of claim 6, wherein, in response to determining that randomly generated trigger information meets a preset condition, causing the first processing core to execute at least one target instruction of the at least one dependent instruction. The chip comprises a plurality of processing cores, and the apparatus comprises:

8. A chip verification apparatus, wherein, ​ a first determining unit configured to determine a first dependency relationship among the plurality of processing cores, wherein the first dependency relationship is determined based on a second dependency relationship among a plurality of initial instructions and a correspondence relationship between the plurality of initial instructions and the plurality of processing cores; a generating unit configured to, in response to determining that a random instruction is to be added for a first processing core among the plurality of processing cores, generate a first newly-added instruction by using a random instruction generator, wherein the generating unit comprises: a determining sub-unit configured to, in response to determining that the first dependency relationship indicates that there is at least one first dependent core among the plurality of processing cores that depends on the first processing core, determine a constraint condition for the random instruction generator, wherein according to the constraint condition, a random instruction generation result of the random instruction generator does not depend on an instruction corresponding to the at least one first dependent core; and a generating sub-unit configured to generate the first newly-added instruction by running the random instruction generator based on the constraint condition; and a verifying unit configured to determine a verification result for the chip by executing the plurality of initial instructions and the first newly-added instruction by using the chip.

9. The apparatus of claim 8, wherein, The at least one dependent core is determined in the following manner: determining, based on the first dependency relationship, a processing core that each processing core among the plurality of processing cores depends on; determining, by recursively traversing the processing core that each processing core depends on, at least one first dependent core that depends on the first processing core.

10. The apparatus of claim 9, wherein, The processing core that each processing core depends on is stored in a dependent core queue corresponding to the processing core.

11. The apparatus of any one of claims 8-10, wherein, The generating unit is configured to: in response to determining that a random instruction is to be added for the first processing core, and in response to determining that a first time interval has elapsed, generate the first newly-added instruction by using the random instruction generator, wherein the first time interval is randomly determined.

12. The apparatus of any one of claims 8-11, further comprising: an updating unit configured to, in response to determining that at least one depended instruction that the first processing core is to be depended on by the at least one first dependent core is executed, update the first dependency relationship, wherein according to the updated first dependency relationship, the at least one first dependent core no longer depends on the first processing core.

13. The apparatus of claim 12, further comprising: an executing unit configured to, in response to determining that a preset triggering condition is reached, cause the first processing core to execute at least one target instruction among the at least one depended instruction, the updating unit is further configured to update the first dependency relationship based on the at least one target instruction.

14. The apparatus of claim 13, wherein, the executing unit is configured to: in response to determining that randomly generated triggering information meets a preset condition, cause the first processing core to execute at least one target instruction among the at least one depended instruction.

15. An electronic device, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

16. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing a computer to perform the method of any one of claims 1-7.

17. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-7.

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