Chip heat dissipation structure and packaging method

Abstract

A packaging structure having a heat dissipation function and a preparation method. The packaging structure comprises: a substrate (10); first metal columns (101), which pass through the substrate (10); a metal layer (102), which is exposed on the back surface of the substrate (10) and connected to first ends of the first metal columns (101); a first chip (30), wherein the back surface of the first chip (30) is coated with a heat dissipation adhesive to form a heat dissipation layer (20), and the back surface of the first chip (30) is arranged on the front surface of the substrate (10) and connected to the top ends of the first metal columns (101); a redistribution layer (60), wherein the first chip (30) and second metal columns (50) are provided on the front surface of the redistribution layer (60); first solder balls (105), which are used for mounting the front surface of the first chip (30) to the front surface of the redistribution layer (60); a plastic packaging layer (40), which plastically packages the first chip (30) and the second metal columns (50), but is exposed on the back surface of the first chip (30) and one end of the second metal columns (50); second solder balls (306), which fix the second metal columns (50) on the front surface of the substrate (10); and a second chip (70), which is fixed on the back surface of the redistribution layer (60) by means of third solder balls (706). The chip of the packaging structure is coated with a heat dissipation adhesive, and is directly connected to the first metal columns (101) in the substrate (10), and heat is conducted to the exposed metal layer (102) by means of the first metal columns (101), thereby improving the heat dissipation capability of the packaging structure.

Description

Chip heat dissipation structure and packaging method TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a chip heat dissipation structure and packaging method. BACKGROUND

[0002] With the development of today's packaging technology, today's packaging is increasingly miniaturized and integrated. Therefore, the problem of chip heat dissipation is increasingly important for the improvement of product stability and reliability, and how to achieve good heat dissipation is also a problem that needs to be considered in technical research and development. The current heat dissipation mode of WB (wire bonding, wire bonding) product mainly includes the following two kinds: (1) the heat dissipation on the upper side of the chip is realized by attaching a heat dissipation sheet on the upper side of the chip; (2) the heat dissipation on the lower side of the chip is realized by punching or relying on the large copper sheet exposed on the lower side of the chip.

[0003] For the prior art, the heat dissipation performance of the punching heat dissipation is poor, and the heat cannot be effectively conducted, and the other heat dissipation through the exposed large copper sheet also has limited heat dissipation effect. SUMMARY

[0004] The purpose of the present application is to provide a chip heat dissipation structure and packaging method to solve the problem of poor heat dissipation in the prior art. In the packaging structure, the chip and the substrate are connected by solder balls, which solves the problem of delamination, the metal column in the substrate and the solder pad on the front and back of the substrate are punched, and the metal column is used to connect the heat dissipation layer and the exposed metal layer, which improves the heat dissipation capacity of the packaging structure, so that the device can quickly dissipate heat during operation.

[0005] In the first aspect of the present application, in view of the problems in the prior art, the present application provides a manufacturing method of a packaging structure with heat dissipation function to solve the problem, comprising:

[0006] Performing redistribution layer and second metal column arrangement, the redistribution layer is disposed on the temporary carrier by the temporary bonding film, and the second metal column is disposed on the front surface of the redistribution layer;

[0007] Mounting the first chip on the front surface of the redistribution layer and performing underfilling to complete electrical connection;

[0008] Performing plastic packaging and thinning the plastic packaging layer to expose the back surface of the first chip and the end of the second metal column that is not connected;

[0009] Removing the temporary bonding film between the redistribution layer and the carrier;

[0010] The back surface of the first chip is coated with a heat dissipation glue to form a heat dissipation layer, the re-wiring layer is inverted to make the back surface of the first chip contact the front surface of the substrate, and the re-wiring layer is arranged on the front surface of the substrate.

[0011] A second chip is arranged on the back surface of the re-wiring layer.

[0012] The substrate is embedded with a first metal column, and a metal layer is exposed on the back surface of the substrate, a first end of the first metal column is connected to the metal layer, and a second end of the first metal column is connected to the heat dissipation layer.

[0013] Further, the temporary bonding film is a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, etc., which can be removed by heating, mechanical, chemical, laser, freezing, etc.

[0014] Further, the carrier is a glass slide, or an organic substrate, a metal substrate, a ceramic substrate, a composite substrate of an organic substrate and a metal substrate, or other similar materials.

[0015] Further, the underfill is a gap between the chip and the conductive interconnection structure filled with an underfill material.

[0016] Further, the substrate surface has a pre-generated circuit.

[0017] Further, the step of arranging the re-wiring layer on the substrate includes forming solder balls on the front surface of the substrate, making the heat dissipation layer contact the second end of the first metal column in the substrate, completing the electrical connection between the substrate and the second metal column through the solder balls, and performing underfilling; the process of forming solder balls includes wafer-level ball mounting, single-chip ball mounting and printing of tin paste; the composition of the solder balls is SnPb or SnAgCu.

[0018] Further, the step of arranging the second chip on the back surface of the re-wiring layer includes generating solder balls on the back surface of the re-wiring layer to complete the electrical connection between the second chip and the re-wiring layer.

[0019] In the second aspect of the present application, in order to solve the problems existing in the prior art, the present application provides a packaging structure with heat dissipation function, comprising:

[0020] a substrate;

[0021] a first metal column penetrating through the substrate;

[0022] a metal layer exposed on the back surface of the substrate and connected to the first end of the first metal column;

[0023] The first chip is coated with a heat dissipation medium on the back surface to form a heat dissipation layer, and the back surface is arranged on the front surface of the substrate and connected with the top end of the first metal column;

[0024] The first chip and the second metal column are arranged on the front surface of the redistribution layer.

[0025] The first solder ball is used to mount the front surface of the first chip on the front surface of the redistribution layer.

[0026] The plastic sealing layer seals the first chip and the second metal column, but exposes the back surface of the first chip and one end of the second metal column.

[0027] The second solder ball is used to fix the second metal column on the front surface of the substrate.

[0028] The second chip is fixed on the back surface of the redistribution layer by the third solder ball.

[0029] Further, the structure further comprises underfill material, which is filled in the gap between the solder ball, the chip and the conductive interconnection structure.

[0030] Further, the redistribution layer, the chip, the second metal column and the substrate are electrically connected.

[0031] The conventional heat dissipation scheme mainly improves the heat dissipation capacity of the chip and the outside of the package by directly attaching a heat dissipation cover and the like, for example, the heat dissipation between the WB chip and the substrate is mainly through the conductive adhesive coated on the exposed gold surface on the lower side of the chip, such heat dissipation scheme has limited heat dissipation effect, and is prone to cause problems such as delamination of the gold surface and the solder; for another example, the heat dissipation mode between the WB chip and the substrate is mainly to expose a large piece of copper skin on the lower side of the chip, and the exposed large piece of copper skin is gold-plated, which may cause poor combination with the solder, resulting in delamination of the lower side of the chip, and the contact area of the two is greatly reduced after delamination, which affects the heat dissipation effect.

[0032] Therefore, the present application provides a chip heat dissipation structure and a preparation method, which coats the chip with heat dissipation adhesive to form a heat dissipation layer, and then directly connects with the metal column embedded in the substrate, so as to transmit heat to the exposed metal layer on the back surface of the substrate, thereby achieving more effective heat dissipation. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to further illustrate the above and other advantages and features of the embodiments of the present application, more specific description of the embodiments of the present application will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present application, and therefore should not be considered as limiting the scope thereof. In the drawings, for the sake of clarity and conciseness, the same or corresponding parts will be denoted by the same or similar reference numerals.

[0034] FIG. 1 shows a schematic diagram of a package structure with heat dissipation function according to one embodiment of the present application.

[0035] FIG. 2 shows a flow chart of forming a heat dissipation substrate according to one embodiment of the present application.

[0036] FIGS. 3A to 3F show schematic diagrams of a process of forming a package structure with heat dissipation function according to one embodiment of the present application. DETAILED DESCRIPTION

[0037] It should be noted that the components in the various figures can be exaggerated for the purpose of illustration and are not necessarily to scale.

[0038] In the present application, each embodiment is merely intended to illustrate the scheme of the present application and should not be understood as limiting.

[0039] In the present application, the quantifier "one", "a" does not exclude the scenario of multiple elements unless specifically indicated.

[0040] It should also be noted herein that, in the embodiments of the present application, only a part of components or assemblies can be shown for the sake of clarity and simplicity, but those skilled in the art can understand that, under the teaching of the present application, the required components or assemblies can be added according to the specific scenario as needed.

[0041] It should also be noted herein that, within the scope of the present application, the phrases "same", "equal", "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the phrases also cover "substantially same", "substantially equal", "substantially equal to".

[0042] It should also be noted herein that, in the description of the present application, the orientations or positional relationships indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for description purposes and cannot be understood as indicating or implying relative importance.

[0043] In addition, the embodiments of the present application describe the process steps in a specific order, however this is only for the convenience of distinguishing the steps and is not intended to limit the order of the steps, and in different embodiments of the present application, the order of the steps can be adjusted according to the adjustment of the process.

[0044] Figure 1 shows a schematic diagram of a packaging structure with heat dissipation function according to an embodiment of the present application.

[0045] As shown in Figure 1, the packaging structure with heat dissipation function includes a substrate 10, a first metal pillar 101, a metal layer 102, a heat dissipation layer 20, a first chip 30, a plastic encapsulation layer 40, a second metal pillar 50, a redistribution layer 60, a second chip 70, and an underfill material 90.

[0046] The first metal pillar 101 penetrates the substrate 10, connects the heat dissipation layer 20 and the metal layer 102, and conducts heat to the exposed metal layer through the metal pillar, thereby achieving more efficient heat dissipation.

[0047] The redistribution layer 60 is electrically connected to the second metal pillar 50, and the front surface of the redistribution layer 60 is provided with the first chip 30, and the back surface is provided with the second chip 70.

[0048] The back surface of the first chip 30 is coated with a heat dissipation adhesive to form the heat dissipation layer 20, which is arranged on the front surface of the substrate 10 and in contact with the first metal pillar 101, thereby forming a heat conduction loop from the first chip 30 to the first metal pillar 101, and then to the metal layer 102, achieving the effect of heat dissipation.

[0049] The second metal pillar 50 is welded to the substrate 10 through a first solder ball 105, the first chip 30 is welded to the redistribution layer 60 through a second solder ball 306, and the second chip 70 is welded to the redistribution layer 60 through a third solder ball 706 after the welding is completed.

[0050] The plastic encapsulation layer 40 encapsulates the first chip 30 and the second metal pillar 50 on the redistribution layer 60, but exposes the back surface of the first chip 30 and one end of the second metal pillar 50, which facilitates the arrangement of the first chip 30 and the second metal pillar 50 on the front surface of the substrate 10.

[0051] Figure 2 shows a flowchart of forming a heat dissipation substrate according to an embodiment of the present application. Figures 3A to 3F show schematic diagrams of the process of forming a packaging structure with heat dissipation function according to an embodiment of the present application.

[0052] In an embodiment of the present application, the process of forming a packaging structure with heat dissipation function includes:

[0053] In step 201, as shown in Figure 3A and Figure 2, the redistribution layer and the second metal pillar 50 are wired. The redistribution layer 60 is arranged on the carrier 80 through a temporary bonding film 806.

[0054] In the embodiment of the present application, the carrier is generally a glass carrier, and the carrier can also be made of other materials, such as a single crystal silicon wafer, an organic substrate, a metal substrate, a ceramic substrate, a substrate made of a combination of an organic substrate and a metal substrate, or other similar materials. Those skilled in the art should understand that as long as the carrier has a flat surface with a certain strength, it can be used as the carrier of the present application.

[0055] In one embodiment of the present application, in step 201, a temporary bonding film 806 is first formed on the carrier 80, and then a redistribution layer RDL 60 and a second metal pillar 50 are formed on the temporary bonding film 806. The redistribution layer RDL is a structure composed of a metal layer and an insulating dielectric layer. The metal layer is used to form an electrical connection, and the insulating dielectric layer is used to isolate the conductive metal layer. In one embodiment of the present application, the insulating dielectric layer and the metal wiring layer can be prepared by physical vapor deposition (PVD) and etching process. Alternatively, the redistribution layer RDL wiring can be completed by photolithography, electroplating and etching process. In the embodiment of the present application, the redistribution layer RDL 60 can include one or more metal layers and one or more insulating dielectric layers disposed around the metal layer.

[0056] The second metal pillar 50 is disposed on the surface of the redistribution layer 60 and has a certain height.

[0057] In step 202, as shown in FIG. 3B and FIG. 2, the first chip 30 is soldered to the surface of the redistribution layer 60 by the second solder ball 306, and the underfill material is filled in the gap between the first chip 30 and the conductive interconnection structure disposed on the surface of the redistribution layer 60 by the underfill process.

[0058] In step 203, as shown in FIG. 3C and FIG. 2, the first chip 30 and the second metal pillar 50 are molded on the redistribution layer 60, and then thinned to expose the end of the first chip 30 and the second metal pillar 50 that are not connected.

[0059] In step 204, as shown in FIG. 3D and FIG. 2, the temporary bonding film 806 is disassembled by laser. The temporary bonding film is a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, etc. The temporary bonding film can be removed by heating, mechanical, chemical, laser, freezing, etc.

[0060] In step 205, the step of forming the heat dissipation substrate 10 includes:

[0061] Step 205.1, providing a substrate 10.

[0062] Step 205.2, forming the first metal pillar 101 through the substrate 10. Specifically, first etching the substrate 10 to form a substrate via, and then filling the metal to form the first metal pillar 101. Wherein the first metal pillar 101 is located in the middle of the substrate.

[0063] Step 205.3, forming the metal layer 102 at one end of the first metal pillar 101.

[0064] In step 206, as shown in FIG. 3E and FIG. 2, the redistribution layer 60 is inverted, the heat dissipation layer 20 is coated on the back of the first chip 30 to form an effective contact with the substrate 10, and the second metal pillar is welded to the substrate 10 through the first solder ball 105 and underfilling is performed.

[0065] In step 206, the first metal pillar 101 connects the heat dissipation layer 20, so as to achieve heat transfer from the first chip 30 to the metal layer 102.

[0066] In step 207, as shown in FIG. 3F and FIG. 2, the second chip 70 is welded to the back of the redistribution layer 60 through the third solder ball 706.

[0067] The present application has the following beneficial effects: the packaging structure disclosed in the present application has a heat dissipation function, the chip is directly coated with a heat dissipation material and placed on the substrate, the copper pillar is embedded in the substrate and connected to the exposed metal layer and the heat dissipation layer, the copper pillar connects the heat dissipation layer and the metal layer, and heat is transferred from the chip to the metal layer, thereby more effectively dissipating heat from the chip.

[0068] Although some embodiments of the present application have been described in the present application, those skilled in the art can understand that these embodiments are only shown as examples. Those skilled in the art can think of numerous variations, alternatives and improvements under the teaching of the present application without departing from the scope of the present application. The appended claims are intended to define the scope of the present application, and thereby cover the methods and structures within the scope of these claims themselves and their equivalent transformations.

Claims

1. A packaging method of a chip heat dissipation structure, characterized by, The method comprises the following steps: arranging a redistribution layer and a second metal column, the redistribution layer being arranged on a temporary carrier by a temporary bonding film, the second metal column being arranged on the front surface of the redistribution layer; mounting a first chip on the front surface of the redistribution layer and performing underfilling to complete electrical connection; performing plastic packaging and thinning the plastic packaging layer to expose the back surface of the first chip and the end of the second metal column not connected; removing the temporary bonding film between the redistribution layer and the carrier; applying a heat dissipation adhesive to the back surface of the first chip to form a heat dissipation layer, inverting the redistribution layer so that the back surface of the first chip is in contact with the front surface of the substrate and the redistribution layer is arranged on the front surface of the substrate; arranging a second chip on the back surface of the redistribution layer; the substrate is embedded with a first metal column, and the back surface of the substrate is exposed with a metal layer, the first end of the first metal column being connected to the metal layer, and the second end of the first metal column being connected to the heat dissipation layer.

2. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The temporary bonding film is a thermoplastic or thermosetting organic material or an inorganic material containing Cu, Ni, Cr or Co components, and the temporary bonding film is removed by heating, mechanical, chemical, laser or freezing.

3. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The carrier is a glass slide, an organic substrate, a metal substrate, a ceramic substrate, or a composite substrate of an organic substrate and a metal substrate.

4. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The underfilling is to fill an underfilling material in the gap between the chip and the conductive interconnection structure.

5. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The surface of the substrate has a pre-generated circuit.

6. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The step of arranging the redistribution layer on the substrate includes forming solder balls on the front surface of the substrate, making the heat dissipation layer contact the second end of the first metal column in the substrate, completing the electrical connection between the substrate and the second metal column through the solder balls, and performing underfilling; the process of forming the solder balls includes wafer-level ball mounting, single-chip ball mounting or printing of tin paste; the composition of the solder balls is SnPb or SnAgCu.

7. The packaging method of a chip heat dissipation structure according to claim 1, wherein, The step of arranging the second chip on the back surface of the redistribution layer includes generating solder balls on the back surface of the redistribution layer to complete the electrical connection between the second chip and the redistribution layer.

8. A chip heat dissipation structure, characterized by comprising: The structure further comprises an underfilling material filled in the gap between the solder balls, the chip and the conductive interconnection structure. The redistribution layer, the chip, the second metal column and the substrate are electrically connected. ​ ​ ​ ​ ​ ​ ​ ​ 9. The chip heat dissipation structure according to claim 8, wherein, ​ 10. The chip heat dissipation structure according to claim 8, wherein, ​

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